drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * RC6 is a special power stage which allows the GPU to enter an very
  36  * low-voltage mode when idle, using down to 0V while at this stage.  This
  37  * stage is entered automatically when the GPU is idle when RC6 support is
  38  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  39  *
  40  * There are different RC6 modes available in Intel GPU, which differentiate
  41  * among each other with the latency required to enter and leave RC6 and
  42  * voltage consumed by the GPU in different states.
  43  *
  44  * The combination of the following flags define which states GPU is allowed
  45  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  46  * RC6pp is deepest RC6. Their support by hardware varies according to the
  47  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  48  * which brings the most power savings; deeper states save more power, but
  49  * require higher latency to switch to and wake up.
  50  */
  51 #define INTEL_RC6_ENABLE                        (1<<0)
  52 #define INTEL_RC6p_ENABLE                       (1<<1)
  53 #define INTEL_RC6pp_ENABLE                      (1<<2)
  54
  55 static void bxt_init_clock_gating(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58
  59         /* WaDisableSDEUnitClockGating:bxt */
  60         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  61                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  62
  63         /*
  64          * FIXME:
  65          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  66          */
  67         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  68                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  69 }
  70
  71 static void i915_pineview_get_mem_freq(struct drm_device *dev)
  72 {
  73         struct drm_i915_private *dev_priv = dev->dev_private;
  74         u32 tmp;
  75
  76         tmp = I915_READ(CLKCFG);
  77
  78         switch (tmp & CLKCFG_FSB_MASK) {
  79         case CLKCFG_FSB_533:
  80                 dev_priv->fsb_freq = 533; /* 133*4 */
  81                 break;
  82         case CLKCFG_FSB_800:
  83                 dev_priv->fsb_freq = 800; /* 200*4 */
  84                 break;
  85         case CLKCFG_FSB_667:
  86                 dev_priv->fsb_freq =  667; /* 167*4 */
  87                 break;
  88         case CLKCFG_FSB_400:
  89                 dev_priv->fsb_freq = 400; /* 100*4 */
  90                 break;
  91         }
  92
  93         switch (tmp & CLKCFG_MEM_MASK) {
  94         case CLKCFG_MEM_533:
  95                 dev_priv->mem_freq = 533;
  96                 break;
  97         case CLKCFG_MEM_667:
  98                 dev_priv->mem_freq = 667;
  99                 break;
 100         case CLKCFG_MEM_800:
 101                 dev_priv->mem_freq = 800;
 102                 break;
 103         }
 104
 105         /* detect pineview DDR3 setting */
 106         tmp = I915_READ(CSHRDDR3CTL);
 107         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 108 }
 109
 110 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 111 {
 112         struct drm_i915_private *dev_priv = dev->dev_private;
 113         u16 ddrpll, csipll;
 114
 115         ddrpll = I915_READ16(DDRMPLL1);
 116         csipll = I915_READ16(CSIPLL0);
 117
 118         switch (ddrpll & 0xff) {
 119         case 0xc:
 120                 dev_priv->mem_freq = 800;
 121                 break;
 122         case 0x10:
 123                 dev_priv->mem_freq = 1066;
 124                 break;
 125         case 0x14:
 126                 dev_priv->mem_freq = 1333;
 127                 break;
 128         case 0x18:
 129                 dev_priv->mem_freq = 1600;
 130                 break;
 131         default:
 132                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 133                                  ddrpll & 0xff);
 134                 dev_priv->mem_freq = 0;
 135                 break;
 136         }
 137
 138         dev_priv->ips.r_t = dev_priv->mem_freq;
 139
 140         switch (csipll & 0x3ff) {
 141         case 0x00c:
 142                 dev_priv->fsb_freq = 3200;
 143                 break;
 144         case 0x00e:
 145                 dev_priv->fsb_freq = 3733;
 146                 break;
 147         case 0x010:
 148                 dev_priv->fsb_freq = 4266;
 149                 break;
 150         case 0x012:
 151                 dev_priv->fsb_freq = 4800;
 152                 break;
 153         case 0x014:
 154                 dev_priv->fsb_freq = 5333;
 155                 break;
 156         case 0x016:
 157                 dev_priv->fsb_freq = 5866;
 158                 break;
 159         case 0x018:
 160                 dev_priv->fsb_freq = 6400;
 161                 break;
 162         default:
 163                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 164                                  csipll & 0x3ff);
 165                 dev_priv->fsb_freq = 0;
 166                 break;
 167         }
 168
 169         if (dev_priv->fsb_freq == 3200) {
 170                 dev_priv->ips.c_m = 0;
 171         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 172                 dev_priv->ips.c_m = 1;
 173         } else {
 174                 dev_priv->ips.c_m = 2;
 175         }
 176 }
 177
 178 static const struct cxsr_latency cxsr_latency_table[] = {
 179         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 180         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 181         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 182         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 183         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 184
 185         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 186         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 187         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 188         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 189         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 190
 191         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 192         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 193         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 194         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 195         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 196
 197         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 198         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 199         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 200         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 201         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 202
 203         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 204         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 205         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 206         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 207         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 208
 209         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 210         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 211         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 212         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 213         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 214 };
 215
 216 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 217                                                          int is_ddr3,
 218                                                          int fsb,
 219                                                          int mem)
 220 {
 221         const struct cxsr_latency *latency;
 222         int i;
 223
 224         if (fsb == 0 || mem == 0)
 225                 return NULL;
 226
 227         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 228                 latency = &cxsr_latency_table[i];
 229                 if (is_desktop == latency->is_desktop &&
 230                     is_ddr3 == latency->is_ddr3 &&
 231                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 232                         return latency;
 233         }
 234
 235         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 236
 237         return NULL;
 238 }
 239
 240 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 241 {
 242         u32 val;
 243
 244         mutex_lock(&dev_priv->rps.hw_lock);
 245
 246         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 247         if (enable)
 248                 val &= ~FORCE_DDR_HIGH_FREQ;
 249         else
 250                 val |= FORCE_DDR_HIGH_FREQ;
 251         val &= ~FORCE_DDR_LOW_FREQ;
 252         val |= FORCE_DDR_FREQ_REQ_ACK;
 253         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 254
 255         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 256                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 257                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 258
 259         mutex_unlock(&dev_priv->rps.hw_lock);
 260 }
 261
 262 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 263 {
 264         u32 val;
 265
 266         mutex_lock(&dev_priv->rps.hw_lock);
 267
 268         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 269         if (enable)
 270                 val |= DSP_MAXFIFO_PM5_ENABLE;
 271         else
 272                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 273         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 274
 275         mutex_unlock(&dev_priv->rps.hw_lock);
 276 }
 277
 278 #define FW_WM(value, plane) \
 279         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 280
 281 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 282 {
 283         struct drm_device *dev = dev_priv->dev;
 284         u32 val;
 285
 286         if (IS_VALLEYVIEW(dev)) {
 287                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 288                 POSTING_READ(FW_BLC_SELF_VLV);
 289                 dev_priv->wm.vlv.cxsr = enable;
 290         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 291                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 292                 POSTING_READ(FW_BLC_SELF);
 293         } else if (IS_PINEVIEW(dev)) {
 294                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 295                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 296                 I915_WRITE(DSPFW3, val);
 297                 POSTING_READ(DSPFW3);
 298         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 299                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 300                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 301                 I915_WRITE(FW_BLC_SELF, val);
 302                 POSTING_READ(FW_BLC_SELF);
 303         } else if (IS_I915GM(dev)) {
 304                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 305                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 306                 I915_WRITE(INSTPM, val);
 307                 POSTING_READ(INSTPM);
 308         } else {
 309                 return;
 310         }
 311
 312         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 313                       enable ? "enabled" : "disabled");
 314 }
 315
 316
 317 /*
 318  * Latency for FIFO fetches is dependent on several factors:
 319  *   - memory configuration (speed, channels)
 320  *   - chipset
 321  *   - current MCH state
 322  * It can be fairly high in some situations, so here we assume a fairly
 323  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 324  * set this value too high, the FIFO will fetch frequently to stay full)
 325  * and power consumption (set it too low to save power and we might see
 326  * FIFO underruns and display "flicker").
 327  *
 328  * A value of 5us seems to be a good balance; safe for very low end
 329  * platforms but not overly aggressive on lower latency configs.
 330  */
 331 static const int pessimal_latency_ns = 5000;
 332
 333 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 334         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 335
 336 static int vlv_get_fifo_size(struct drm_device *dev,
 337                               enum pipe pipe, int plane)
 338 {
 339         struct drm_i915_private *dev_priv = dev->dev_private;
 340         int sprite0_start, sprite1_start, size;
 341
 342         switch (pipe) {
 343                 uint32_t dsparb, dsparb2, dsparb3;
 344         case PIPE_A:
 345                 dsparb = I915_READ(DSPARB);
 346                 dsparb2 = I915_READ(DSPARB2);
 347                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 348                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 349                 break;
 350         case PIPE_B:
 351                 dsparb = I915_READ(DSPARB);
 352                 dsparb2 = I915_READ(DSPARB2);
 353                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 354                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 355                 break;
 356         case PIPE_C:
 357                 dsparb2 = I915_READ(DSPARB2);
 358                 dsparb3 = I915_READ(DSPARB3);
 359                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 360                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 361                 break;
 362         default:
 363                 return 0;
 364         }
 365
 366         switch (plane) {
 367         case 0:
 368                 size = sprite0_start;
 369                 break;
 370         case 1:
 371                 size = sprite1_start - sprite0_start;
 372                 break;
 373         case 2:
 374                 size = 512 - 1 - sprite1_start;
 375                 break;
 376         default:
 377                 return 0;
 378         }
 379
 380         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 381                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 382                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 383                       size);
 384
 385         return size;
 386 }
 387
 388 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 389 {
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         uint32_t dsparb = I915_READ(DSPARB);
 392         int size;
 393
 394         size = dsparb & 0x7f;
 395         if (plane)
 396                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 397
 398         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 399                       plane ? "B" : "A", size);
 400
 401         return size;
 402 }
 403
 404 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 405 {
 406         struct drm_i915_private *dev_priv = dev->dev_private;
 407         uint32_t dsparb = I915_READ(DSPARB);
 408         int size;
 409
 410         size = dsparb & 0x1ff;
 411         if (plane)
 412                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 413         size >>= 1; /* Convert to cachelines */
 414
 415         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 416                       plane ? "B" : "A", size);
 417
 418         return size;
 419 }
 420
 421 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 422 {
 423         struct drm_i915_private *dev_priv = dev->dev_private;
 424         uint32_t dsparb = I915_READ(DSPARB);
 425         int size;
 426
 427         size = dsparb & 0x7f;
 428         size >>= 2; /* Convert to cachelines */
 429
 430         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 431                       plane ? "B" : "A",
 432                       size);
 433
 434         return size;
 435 }
 436
 437 /* Pineview has different values for various configs */
 438 static const struct intel_watermark_params pineview_display_wm = {
 439         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 440         .max_wm = PINEVIEW_MAX_WM,
 441         .default_wm = PINEVIEW_DFT_WM,
 442         .guard_size = PINEVIEW_GUARD_WM,
 443         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 444 };
 445 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 446         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 447         .max_wm = PINEVIEW_MAX_WM,
 448         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 449         .guard_size = PINEVIEW_GUARD_WM,
 450         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 451 };
 452 static const struct intel_watermark_params pineview_cursor_wm = {
 453         .fifo_size = PINEVIEW_CURSOR_FIFO,
 454         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 455         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 456         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 457         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 458 };
 459 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 460         .fifo_size = PINEVIEW_CURSOR_FIFO,
 461         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 462         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 463         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 464         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 465 };
 466 static const struct intel_watermark_params g4x_wm_info = {
 467         .fifo_size = G4X_FIFO_SIZE,
 468         .max_wm = G4X_MAX_WM,
 469         .default_wm = G4X_MAX_WM,
 470         .guard_size = 2,
 471         .cacheline_size = G4X_FIFO_LINE_SIZE,
 472 };
 473 static const struct intel_watermark_params g4x_cursor_wm_info = {
 474         .fifo_size = I965_CURSOR_FIFO,
 475         .max_wm = I965_CURSOR_MAX_WM,
 476         .default_wm = I965_CURSOR_DFT_WM,
 477         .guard_size = 2,
 478         .cacheline_size = G4X_FIFO_LINE_SIZE,
 479 };
 480 static const struct intel_watermark_params valleyview_wm_info = {
 481         .fifo_size = VALLEYVIEW_FIFO_SIZE,
 482         .max_wm = VALLEYVIEW_MAX_WM,
 483         .default_wm = VALLEYVIEW_MAX_WM,
 484         .guard_size = 2,
 485         .cacheline_size = G4X_FIFO_LINE_SIZE,
 486 };
 487 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 488         .fifo_size = I965_CURSOR_FIFO,
 489         .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 490         .default_wm = I965_CURSOR_DFT_WM,
 491         .guard_size = 2,
 492         .cacheline_size = G4X_FIFO_LINE_SIZE,
 493 };
 494 static const struct intel_watermark_params i965_cursor_wm_info = {
 495         .fifo_size = I965_CURSOR_FIFO,
 496         .max_wm = I965_CURSOR_MAX_WM,
 497         .default_wm = I965_CURSOR_DFT_WM,
 498         .guard_size = 2,
 499         .cacheline_size = I915_FIFO_LINE_SIZE,
 500 };
 501 static const struct intel_watermark_params i945_wm_info = {
 502         .fifo_size = I945_FIFO_SIZE,
 503         .max_wm = I915_MAX_WM,
 504         .default_wm = 1,
 505         .guard_size = 2,
 506         .cacheline_size = I915_FIFO_LINE_SIZE,
 507 };
 508 static const struct intel_watermark_params i915_wm_info = {
 509         .fifo_size = I915_FIFO_SIZE,
 510         .max_wm = I915_MAX_WM,
 511         .default_wm = 1,
 512         .guard_size = 2,
 513         .cacheline_size = I915_FIFO_LINE_SIZE,
 514 };
 515 static const struct intel_watermark_params i830_a_wm_info = {
 516         .fifo_size = I855GM_FIFO_SIZE,
 517         .max_wm = I915_MAX_WM,
 518         .default_wm = 1,
 519         .guard_size = 2,
 520         .cacheline_size = I830_FIFO_LINE_SIZE,
 521 };
 522 static const struct intel_watermark_params i830_bc_wm_info = {
 523         .fifo_size = I855GM_FIFO_SIZE,
 524         .max_wm = I915_MAX_WM/2,
 525         .default_wm = 1,
 526         .guard_size = 2,
 527         .cacheline_size = I830_FIFO_LINE_SIZE,
 528 };
 529 static const struct intel_watermark_params i845_wm_info = {
 530         .fifo_size = I830_FIFO_SIZE,
 531         .max_wm = I915_MAX_WM,
 532         .default_wm = 1,
 533         .guard_size = 2,
 534         .cacheline_size = I830_FIFO_LINE_SIZE,
 535 };
 536
 537 /**
 538  * intel_calculate_wm - calculate watermark level
 539  * @clock_in_khz: pixel clock
 540  * @wm: chip FIFO params
 541  * @pixel_size: display pixel size
 542  * @latency_ns: memory latency for the platform
 543  *
 544  * Calculate the watermark level (the level at which the display plane will
 545  * start fetching from memory again).  Each chip has a different display
 546  * FIFO size and allocation, so the caller needs to figure that out and pass
 547  * in the correct intel_watermark_params structure.
 548  *
 549  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 550  * on the pixel size.  When it reaches the watermark level, it'll start
 551  * fetching FIFO line sized based chunks from memory until the FIFO fills
 552  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 553  * will occur, and a display engine hang could result.
 554  */
 555 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 556                                         const struct intel_watermark_params *wm,
 557                                         int fifo_size,
 558                                         int pixel_size,
 559                                         unsigned long latency_ns)
 560 {
 561         long entries_required, wm_size;
 562
 563         /*
 564          * Note: we need to make sure we don't overflow for various clock &
 565          * latency values.
 566          * clocks go from a few thousand to several hundred thousand.
 567          * latency is usually a few thousand
 568          */
 569         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 570                 1000;
 571         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 572
 573         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 574
 575         wm_size = fifo_size - (entries_required + wm->guard_size);
 576
 577         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 578
 579         /* Don't promote wm_size to unsigned... */
 580         if (wm_size > (long)wm->max_wm)
 581                 wm_size = wm->max_wm;
 582         if (wm_size <= 0)
 583                 wm_size = wm->default_wm;
 584
 585         /*
 586          * Bspec seems to indicate that the value shouldn't be lower than
 587          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 588          * Lets go for 8 which is the burst size since certain platforms
 589          * already use a hardcoded 8 (which is what the spec says should be
 590          * done).
 591          */
 592         if (wm_size <= 8)
 593                 wm_size = 8;
 594
 595         return wm_size;
 596 }
 597
 598 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 599 {
 600         struct drm_crtc *crtc, *enabled = NULL;
 601
 602         for_each_crtc(dev, crtc) {
 603                 if (intel_crtc_active(crtc)) {
 604                         if (enabled)
 605                                 return NULL;
 606                         enabled = crtc;
 607                 }
 608         }
 609
 610         return enabled;
 611 }
 612
 613 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 614 {
 615         struct drm_device *dev = unused_crtc->dev;
 616         struct drm_i915_private *dev_priv = dev->dev_private;
 617         struct drm_crtc *crtc;
 618         const struct cxsr_latency *latency;
 619         u32 reg;
 620         unsigned long wm;
 621
 622         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 623                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 624         if (!latency) {
 625                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 626                 intel_set_memory_cxsr(dev_priv, false);
 627                 return;
 628         }
 629
 630         crtc = single_enabled_crtc(dev);
 631         if (crtc) {
 632                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 633                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 634                 int clock = adjusted_mode->crtc_clock;
 635
 636                 /* Display SR */
 637                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 638                                         pineview_display_wm.fifo_size,
 639                                         pixel_size, latency->display_sr);
 640                 reg = I915_READ(DSPFW1);
 641                 reg &= ~DSPFW_SR_MASK;
 642                 reg |= FW_WM(wm, SR);
 643                 I915_WRITE(DSPFW1, reg);
 644                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 645
 646                 /* cursor SR */
 647                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 648                                         pineview_display_wm.fifo_size,
 649                                         pixel_size, latency->cursor_sr);
 650                 reg = I915_READ(DSPFW3);
 651                 reg &= ~DSPFW_CURSOR_SR_MASK;
 652                 reg |= FW_WM(wm, CURSOR_SR);
 653                 I915_WRITE(DSPFW3, reg);
 654
 655                 /* Display HPLL off SR */
 656                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 657                                         pineview_display_hplloff_wm.fifo_size,
 658                                         pixel_size, latency->display_hpll_disable);
 659                 reg = I915_READ(DSPFW3);
 660                 reg &= ~DSPFW_HPLL_SR_MASK;
 661                 reg |= FW_WM(wm, HPLL_SR);
 662                 I915_WRITE(DSPFW3, reg);
 663
 664                 /* cursor HPLL off SR */
 665                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 666                                         pineview_display_hplloff_wm.fifo_size,
 667                                         pixel_size, latency->cursor_hpll_disable);
 668                 reg = I915_READ(DSPFW3);
 669                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 670                 reg |= FW_WM(wm, HPLL_CURSOR);
 671                 I915_WRITE(DSPFW3, reg);
 672                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 673
 674                 intel_set_memory_cxsr(dev_priv, true);
 675         } else {
 676                 intel_set_memory_cxsr(dev_priv, false);
 677         }
 678 }
 679
 680 static bool g4x_compute_wm0(struct drm_device *dev,
 681                             int plane,
 682                             const struct intel_watermark_params *display,
 683                             int display_latency_ns,
 684                             const struct intel_watermark_params *cursor,
 685                             int cursor_latency_ns,
 686                             int *plane_wm,
 687                             int *cursor_wm)
 688 {
 689         struct drm_crtc *crtc;
 690         const struct drm_display_mode *adjusted_mode;
 691         int htotal, hdisplay, clock, pixel_size;
 692         int line_time_us, line_count;
 693         int entries, tlb_miss;
 694
 695         crtc = intel_get_crtc_for_plane(dev, plane);
 696         if (!intel_crtc_active(crtc)) {
 697                 *cursor_wm = cursor->guard_size;
 698                 *plane_wm = display->guard_size;
 699                 return false;
 700         }
 701
 702         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 703         clock = adjusted_mode->crtc_clock;
 704         htotal = adjusted_mode->crtc_htotal;
 705         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 706         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 707
 708         /* Use the small buffer method to calculate plane watermark */
 709         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
 710         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 711         if (tlb_miss > 0)
 712                 entries += tlb_miss;
 713         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 714         *plane_wm = entries + display->guard_size;
 715         if (*plane_wm > (int)display->max_wm)
 716                 *plane_wm = display->max_wm;
 717
 718         /* Use the large buffer method to calculate cursor watermark */
 719         line_time_us = max(htotal * 1000 / clock, 1);
 720         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 721         entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
 722         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 723         if (tlb_miss > 0)
 724                 entries += tlb_miss;
 725         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 726         *cursor_wm = entries + cursor->guard_size;
 727         if (*cursor_wm > (int)cursor->max_wm)
 728                 *cursor_wm = (int)cursor->max_wm;
 729
 730         return true;
 731 }
 732
 733 /*
 734  * Check the wm result.
 735  *
 736  * If any calculated watermark values is larger than the maximum value that
 737  * can be programmed into the associated watermark register, that watermark
 738  * must be disabled.
 739  */
 740 static bool g4x_check_srwm(struct drm_device *dev,
 741                            int display_wm, int cursor_wm,
 742                            const struct intel_watermark_params *display,
 743                            const struct intel_watermark_params *cursor)
 744 {
 745         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 746                       display_wm, cursor_wm);
 747
 748         if (display_wm > display->max_wm) {
 749                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 750                               display_wm, display->max_wm);
 751                 return false;
 752         }
 753
 754         if (cursor_wm > cursor->max_wm) {
 755                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 756                               cursor_wm, cursor->max_wm);
 757                 return false;
 758         }
 759
 760         if (!(display_wm || cursor_wm)) {
 761                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 762                 return false;
 763         }
 764
 765         return true;
 766 }
 767
 768 static bool g4x_compute_srwm(struct drm_device *dev,
 769                              int plane,
 770                              int latency_ns,
 771                              const struct intel_watermark_params *display,
 772                              const struct intel_watermark_params *cursor,
 773                              int *display_wm, int *cursor_wm)
 774 {
 775         struct drm_crtc *crtc;
 776         const struct drm_display_mode *adjusted_mode;
 777         int hdisplay, htotal, pixel_size, clock;
 778         unsigned long line_time_us;
 779         int line_count, line_size;
 780         int small, large;
 781         int entries;
 782
 783         if (!latency_ns) {
 784                 *display_wm = *cursor_wm = 0;
 785                 return false;
 786         }
 787
 788         crtc = intel_get_crtc_for_plane(dev, plane);
 789         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 790         clock = adjusted_mode->crtc_clock;
 791         htotal = adjusted_mode->crtc_htotal;
 792         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 793         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 794
 795         line_time_us = max(htotal * 1000 / clock, 1);
 796         line_count = (latency_ns / line_time_us + 1000) / 1000;
 797         line_size = hdisplay * pixel_size;
 798
 799         /* Use the minimum of the small and large buffer method for primary */
 800         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
 801         large = line_count * line_size;
 802
 803         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 804         *display_wm = entries + display->guard_size;
 805
 806         /* calculate the self-refresh watermark for display cursor */
 807         entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
 808         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 809         *cursor_wm = entries + cursor->guard_size;
 810
 811         return g4x_check_srwm(dev,
 812                               *display_wm, *cursor_wm,
 813                               display, cursor);
 814 }
 815
 816 #define FW_WM_VLV(value, plane) \
 817         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 818
 819 static void vlv_write_wm_values(struct intel_crtc *crtc,
 820                                 const struct vlv_wm_values *wm)
 821 {
 822         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 823         enum pipe pipe = crtc->pipe;
 824
 825         I915_WRITE(VLV_DDL(pipe),
 826                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 827                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 828                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 829                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 830
 831         I915_WRITE(DSPFW1,
 832                    FW_WM(wm->sr.plane, SR) |
 833                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 834                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 835                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 836         I915_WRITE(DSPFW2,
 837                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 838                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 839                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 840         I915_WRITE(DSPFW3,
 841                    FW_WM(wm->sr.cursor, CURSOR_SR));
 842
 843         if (IS_CHERRYVIEW(dev_priv)) {
 844                 I915_WRITE(DSPFW7_CHV,
 845                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 846                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 847                 I915_WRITE(DSPFW8_CHV,
 848                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 849                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 850                 I915_WRITE(DSPFW9_CHV,
 851                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 852                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 853                 I915_WRITE(DSPHOWM,
 854                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 855                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 856                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 857                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 858                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 859                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 860                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 861                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 862                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 863                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 864         } else {
 865                 I915_WRITE(DSPFW7,
 866                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 867                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 868                 I915_WRITE(DSPHOWM,
 869                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 870                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 871                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 872                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 873                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 874                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 875                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 876         }
 877
 878         /* zero (unused) WM1 watermarks */
 879         I915_WRITE(DSPFW4, 0);
 880         I915_WRITE(DSPFW5, 0);
 881         I915_WRITE(DSPFW6, 0);
 882         I915_WRITE(DSPHOWM1, 0);
 883
 884         POSTING_READ(DSPFW1);
 885 }
 886
 887 #undef FW_WM_VLV
 888
 889 enum vlv_wm_level {
 890         VLV_WM_LEVEL_PM2,
 891         VLV_WM_LEVEL_PM5,
 892         VLV_WM_LEVEL_DDR_DVFS,
 893 };
 894
 895 /* latency must be in 0.1us units. */
 896 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 897                                    unsigned int pipe_htotal,
 898                                    unsigned int horiz_pixels,
 899                                    unsigned int bytes_per_pixel,
 900                                    unsigned int latency)
 901 {
 902         unsigned int ret;
 903
 904         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 905         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
 906         ret = DIV_ROUND_UP(ret, 64);
 907
 908         return ret;
 909 }
 910
 911 static void vlv_setup_wm_latency(struct drm_device *dev)
 912 {
 913         struct drm_i915_private *dev_priv = dev->dev_private;
 914
 915         /* all latencies in usec */
 916         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 917
 918         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 919
 920         if (IS_CHERRYVIEW(dev_priv)) {
 921                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 922                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 923
 924                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 925         }
 926 }
 927
 928 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 929                                      struct intel_crtc *crtc,
 930                                      const struct intel_plane_state *state,
 931                                      int level)
 932 {
 933         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 934         int clock, htotal, pixel_size, width, wm;
 935
 936         if (dev_priv->wm.pri_latency[level] == 0)
 937                 return USHRT_MAX;
 938
 939         if (!state->visible)
 940                 return 0;
 941
 942         pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 943         clock = crtc->config->base.adjusted_mode.crtc_clock;
 944         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 945         width = crtc->config->pipe_src_w;
 946         if (WARN_ON(htotal == 0))
 947                 htotal = 1;
 948
 949         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 950                 /*
 951                  * FIXME the formula gives values that are
 952                  * too big for the cursor FIFO, and hence we
 953                  * would never be able to use cursors. For
 954                  * now just hardcode the watermark.
 955                  */
 956                 wm = 63;
 957         } else {
 958                 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
 959                                     dev_priv->wm.pri_latency[level] * 10);
 960         }
 961
 962         return min_t(int, wm, USHRT_MAX);
 963 }
 964
 965 static void vlv_compute_fifo(struct intel_crtc *crtc)
 966 {
 967         struct drm_device *dev = crtc->base.dev;
 968         struct vlv_wm_state *wm_state = &crtc->wm_state;
 969         struct intel_plane *plane;
 970         unsigned int total_rate = 0;
 971         const int fifo_size = 512 - 1;
 972         int fifo_extra, fifo_left = fifo_size;
 973
 974         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 975                 struct intel_plane_state *state =
 976                         to_intel_plane_state(plane->base.state);
 977
 978                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
 979                         continue;
 980
 981                 if (state->visible) {
 982                         wm_state->num_active_planes++;
 983                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 984                 }
 985         }
 986
 987         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 988                 struct intel_plane_state *state =
 989                         to_intel_plane_state(plane->base.state);
 990                 unsigned int rate;
 991
 992                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 993                         plane->wm.fifo_size = 63;
 994                         continue;
 995                 }
 996
 997                 if (!state->visible) {
 998                         plane->wm.fifo_size = 0;
 999                         continue;
1000                 }
1001
1002                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1003                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1004                 fifo_left -= plane->wm.fifo_size;
1005         }
1006
1007         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1008
1009         /* spread the remainder evenly */
1010         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1011                 int plane_extra;
1012
1013                 if (fifo_left == 0)
1014                         break;
1015
1016                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1017                         continue;
1018
1019                 /* give it all to the first plane if none are active */
1020                 if (plane->wm.fifo_size == 0 &&
1021                     wm_state->num_active_planes)
1022                         continue;
1023
1024                 plane_extra = min(fifo_extra, fifo_left);
1025                 plane->wm.fifo_size += plane_extra;
1026                 fifo_left -= plane_extra;
1027         }
1028
1029         WARN_ON(fifo_left != 0);
1030 }
1031
1032 static void vlv_invert_wms(struct intel_crtc *crtc)
1033 {
1034         struct vlv_wm_state *wm_state = &crtc->wm_state;
1035         int level;
1036
1037         for (level = 0; level < wm_state->num_levels; level++) {
1038                 struct drm_device *dev = crtc->base.dev;
1039                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1040                 struct intel_plane *plane;
1041
1042                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1043                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1044
1045                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1046                         switch (plane->base.type) {
1047                                 int sprite;
1048                         case DRM_PLANE_TYPE_CURSOR:
1049                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1050                                         wm_state->wm[level].cursor;
1051                                 break;
1052                         case DRM_PLANE_TYPE_PRIMARY:
1053                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1054                                         wm_state->wm[level].primary;
1055                                 break;
1056                         case DRM_PLANE_TYPE_OVERLAY:
1057                                 sprite = plane->plane;
1058                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1059                                         wm_state->wm[level].sprite[sprite];
1060                                 break;
1061                         }
1062                 }
1063         }
1064 }
1065
1066 static void vlv_compute_wm(struct intel_crtc *crtc)
1067 {
1068         struct drm_device *dev = crtc->base.dev;
1069         struct vlv_wm_state *wm_state = &crtc->wm_state;
1070         struct intel_plane *plane;
1071         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1072         int level;
1073
1074         memset(wm_state, 0, sizeof(*wm_state));
1075
1076         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1077         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1078
1079         wm_state->num_active_planes = 0;
1080
1081         vlv_compute_fifo(crtc);
1082
1083         if (wm_state->num_active_planes != 1)
1084                 wm_state->cxsr = false;
1085
1086         if (wm_state->cxsr) {
1087                 for (level = 0; level < wm_state->num_levels; level++) {
1088                         wm_state->sr[level].plane = sr_fifo_size;
1089                         wm_state->sr[level].cursor = 63;
1090                 }
1091         }
1092
1093         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1094                 struct intel_plane_state *state =
1095                         to_intel_plane_state(plane->base.state);
1096
1097                 if (!state->visible)
1098                         continue;
1099
1100                 /* normal watermarks */
1101                 for (level = 0; level < wm_state->num_levels; level++) {
1102                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1103                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1104
1105                         /* hack */
1106                         if (WARN_ON(level == 0 && wm > max_wm))
1107                                 wm = max_wm;
1108
1109                         if (wm > plane->wm.fifo_size)
1110                                 break;
1111
1112                         switch (plane->base.type) {
1113                                 int sprite;
1114                         case DRM_PLANE_TYPE_CURSOR:
1115                                 wm_state->wm[level].cursor = wm;
1116                                 break;
1117                         case DRM_PLANE_TYPE_PRIMARY:
1118                                 wm_state->wm[level].primary = wm;
1119                                 break;
1120                         case DRM_PLANE_TYPE_OVERLAY:
1121                                 sprite = plane->plane;
1122                                 wm_state->wm[level].sprite[sprite] = wm;
1123                                 break;
1124                         }
1125                 }
1126
1127                 wm_state->num_levels = level;
1128
1129                 if (!wm_state->cxsr)
1130                         continue;
1131
1132                 /* maxfifo watermarks */
1133                 switch (plane->base.type) {
1134                         int sprite, level;
1135                 case DRM_PLANE_TYPE_CURSOR:
1136                         for (level = 0; level < wm_state->num_levels; level++)
1137                                 wm_state->sr[level].cursor =
1138                                         wm_state->wm[level].cursor;
1139                         break;
1140                 case DRM_PLANE_TYPE_PRIMARY:
1141                         for (level = 0; level < wm_state->num_levels; level++)
1142                                 wm_state->sr[level].plane =
1143                                         min(wm_state->sr[level].plane,
1144                                             wm_state->wm[level].primary);
1145                         break;
1146                 case DRM_PLANE_TYPE_OVERLAY:
1147                         sprite = plane->plane;
1148                         for (level = 0; level < wm_state->num_levels; level++)
1149                                 wm_state->sr[level].plane =
1150                                         min(wm_state->sr[level].plane,
1151                                             wm_state->wm[level].sprite[sprite]);
1152                         break;
1153                 }
1154         }
1155
1156         /* clear any (partially) filled invalid levels */
1157         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1158                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1159                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1160         }
1161
1162         vlv_invert_wms(crtc);
1163 }
1164
1165 #define VLV_FIFO(plane, value) \
1166         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1167
1168 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1169 {
1170         struct drm_device *dev = crtc->base.dev;
1171         struct drm_i915_private *dev_priv = to_i915(dev);
1172         struct intel_plane *plane;
1173         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1174
1175         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1176                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1177                         WARN_ON(plane->wm.fifo_size != 63);
1178                         continue;
1179                 }
1180
1181                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1182                         sprite0_start = plane->wm.fifo_size;
1183                 else if (plane->plane == 0)
1184                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1185                 else
1186                         fifo_size = sprite1_start + plane->wm.fifo_size;
1187         }
1188
1189         WARN_ON(fifo_size != 512 - 1);
1190
1191         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1192                       pipe_name(crtc->pipe), sprite0_start,
1193                       sprite1_start, fifo_size);
1194
1195         switch (crtc->pipe) {
1196                 uint32_t dsparb, dsparb2, dsparb3;
1197         case PIPE_A:
1198                 dsparb = I915_READ(DSPARB);
1199                 dsparb2 = I915_READ(DSPARB2);
1200
1201                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1202                             VLV_FIFO(SPRITEB, 0xff));
1203                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1204                            VLV_FIFO(SPRITEB, sprite1_start));
1205
1206                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1207                              VLV_FIFO(SPRITEB_HI, 0x1));
1208                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1209                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1210
1211                 I915_WRITE(DSPARB, dsparb);
1212                 I915_WRITE(DSPARB2, dsparb2);
1213                 break;
1214         case PIPE_B:
1215                 dsparb = I915_READ(DSPARB);
1216                 dsparb2 = I915_READ(DSPARB2);
1217
1218                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1219                             VLV_FIFO(SPRITED, 0xff));
1220                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1221                            VLV_FIFO(SPRITED, sprite1_start));
1222
1223                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1224                              VLV_FIFO(SPRITED_HI, 0xff));
1225                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1226                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1227
1228                 I915_WRITE(DSPARB, dsparb);
1229                 I915_WRITE(DSPARB2, dsparb2);
1230                 break;
1231         case PIPE_C:
1232                 dsparb3 = I915_READ(DSPARB3);
1233                 dsparb2 = I915_READ(DSPARB2);
1234
1235                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1236                              VLV_FIFO(SPRITEF, 0xff));
1237                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1238                             VLV_FIFO(SPRITEF, sprite1_start));
1239
1240                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1241                              VLV_FIFO(SPRITEF_HI, 0xff));
1242                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1243                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1244
1245                 I915_WRITE(DSPARB3, dsparb3);
1246                 I915_WRITE(DSPARB2, dsparb2);
1247                 break;
1248         default:
1249                 break;
1250         }
1251 }
1252
1253 #undef VLV_FIFO
1254
1255 static void vlv_merge_wm(struct drm_device *dev,
1256                          struct vlv_wm_values *wm)
1257 {
1258         struct intel_crtc *crtc;
1259         int num_active_crtcs = 0;
1260
1261         wm->level = to_i915(dev)->wm.max_level;
1262         wm->cxsr = true;
1263
1264         for_each_intel_crtc(dev, crtc) {
1265                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1266
1267                 if (!crtc->active)
1268                         continue;
1269
1270                 if (!wm_state->cxsr)
1271                         wm->cxsr = false;
1272
1273                 num_active_crtcs++;
1274                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1275         }
1276
1277         if (num_active_crtcs != 1)
1278                 wm->cxsr = false;
1279
1280         if (num_active_crtcs > 1)
1281                 wm->level = VLV_WM_LEVEL_PM2;
1282
1283         for_each_intel_crtc(dev, crtc) {
1284                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1285                 enum pipe pipe = crtc->pipe;
1286
1287                 if (!crtc->active)
1288                         continue;
1289
1290                 wm->pipe[pipe] = wm_state->wm[wm->level];
1291                 if (wm->cxsr)
1292                         wm->sr = wm_state->sr[wm->level];
1293
1294                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1295                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1296                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1297                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1298         }
1299 }
1300
1301 static void vlv_update_wm(struct drm_crtc *crtc)
1302 {
1303         struct drm_device *dev = crtc->dev;
1304         struct drm_i915_private *dev_priv = dev->dev_private;
1305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1306         enum pipe pipe = intel_crtc->pipe;
1307         struct vlv_wm_values wm = {};
1308
1309         vlv_compute_wm(intel_crtc);
1310         vlv_merge_wm(dev, &wm);
1311
1312         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1313                 /* FIXME should be part of crtc atomic commit */
1314                 vlv_pipe_set_fifo_size(intel_crtc);
1315                 return;
1316         }
1317
1318         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1319             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1320                 chv_set_memory_dvfs(dev_priv, false);
1321
1322         if (wm.level < VLV_WM_LEVEL_PM5 &&
1323             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1324                 chv_set_memory_pm5(dev_priv, false);
1325
1326         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1327                 intel_set_memory_cxsr(dev_priv, false);
1328
1329         /* FIXME should be part of crtc atomic commit */
1330         vlv_pipe_set_fifo_size(intel_crtc);
1331
1332         vlv_write_wm_values(intel_crtc, &wm);
1333
1334         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1335                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1336                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1337                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1338                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1339
1340         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1341                 intel_set_memory_cxsr(dev_priv, true);
1342
1343         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1344             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1345                 chv_set_memory_pm5(dev_priv, true);
1346
1347         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1348             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1349                 chv_set_memory_dvfs(dev_priv, true);
1350
1351         dev_priv->wm.vlv = wm;
1352 }
1353
1354 #define single_plane_enabled(mask) is_power_of_2(mask)
1355
1356 static void g4x_update_wm(struct drm_crtc *crtc)
1357 {
1358         struct drm_device *dev = crtc->dev;
1359         static const int sr_latency_ns = 12000;
1360         struct drm_i915_private *dev_priv = dev->dev_private;
1361         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1362         int plane_sr, cursor_sr;
1363         unsigned int enabled = 0;
1364         bool cxsr_enabled;
1365
1366         if (g4x_compute_wm0(dev, PIPE_A,
1367                             &g4x_wm_info, pessimal_latency_ns,
1368                             &g4x_cursor_wm_info, pessimal_latency_ns,
1369                             &planea_wm, &cursora_wm))
1370                 enabled |= 1 << PIPE_A;
1371
1372         if (g4x_compute_wm0(dev, PIPE_B,
1373                             &g4x_wm_info, pessimal_latency_ns,
1374                             &g4x_cursor_wm_info, pessimal_latency_ns,
1375                             &planeb_wm, &cursorb_wm))
1376                 enabled |= 1 << PIPE_B;
1377
1378         if (single_plane_enabled(enabled) &&
1379             g4x_compute_srwm(dev, ffs(enabled) - 1,
1380                              sr_latency_ns,
1381                              &g4x_wm_info,
1382                              &g4x_cursor_wm_info,
1383                              &plane_sr, &cursor_sr)) {
1384                 cxsr_enabled = true;
1385         } else {
1386                 cxsr_enabled = false;
1387                 intel_set_memory_cxsr(dev_priv, false);
1388                 plane_sr = cursor_sr = 0;
1389         }
1390
1391         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1392                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1393                       planea_wm, cursora_wm,
1394                       planeb_wm, cursorb_wm,
1395                       plane_sr, cursor_sr);
1396
1397         I915_WRITE(DSPFW1,
1398                    FW_WM(plane_sr, SR) |
1399                    FW_WM(cursorb_wm, CURSORB) |
1400                    FW_WM(planeb_wm, PLANEB) |
1401                    FW_WM(planea_wm, PLANEA));
1402         I915_WRITE(DSPFW2,
1403                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1404                    FW_WM(cursora_wm, CURSORA));
1405         /* HPLL off in SR has some issues on G4x... disable it */
1406         I915_WRITE(DSPFW3,
1407                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1408                    FW_WM(cursor_sr, CURSOR_SR));
1409
1410         if (cxsr_enabled)
1411                 intel_set_memory_cxsr(dev_priv, true);
1412 }
1413
1414 static void i965_update_wm(struct drm_crtc *unused_crtc)
1415 {
1416         struct drm_device *dev = unused_crtc->dev;
1417         struct drm_i915_private *dev_priv = dev->dev_private;
1418         struct drm_crtc *crtc;
1419         int srwm = 1;
1420         int cursor_sr = 16;
1421         bool cxsr_enabled;
1422
1423         /* Calc sr entries for one plane configs */
1424         crtc = single_enabled_crtc(dev);
1425         if (crtc) {
1426                 /* self-refresh has much higher latency */
1427                 static const int sr_latency_ns = 12000;
1428                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1429                 int clock = adjusted_mode->crtc_clock;
1430                 int htotal = adjusted_mode->crtc_htotal;
1431                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1432                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1433                 unsigned long line_time_us;
1434                 int entries;
1435
1436                 line_time_us = max(htotal * 1000 / clock, 1);
1437
1438                 /* Use ns/us then divide to preserve precision */
1439                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1440                         pixel_size * hdisplay;
1441                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1442                 srwm = I965_FIFO_SIZE - entries;
1443                 if (srwm < 0)
1444                         srwm = 1;
1445                 srwm &= 0x1ff;
1446                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1447                               entries, srwm);
1448
1449                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450                         pixel_size * crtc->cursor->state->crtc_w;
1451                 entries = DIV_ROUND_UP(entries,
1452                                           i965_cursor_wm_info.cacheline_size);
1453                 cursor_sr = i965_cursor_wm_info.fifo_size -
1454                         (entries + i965_cursor_wm_info.guard_size);
1455
1456                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1457                         cursor_sr = i965_cursor_wm_info.max_wm;
1458
1459                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1460                               "cursor %d\n", srwm, cursor_sr);
1461
1462                 cxsr_enabled = true;
1463         } else {
1464                 cxsr_enabled = false;
1465                 /* Turn off self refresh if both pipes are enabled */
1466                 intel_set_memory_cxsr(dev_priv, false);
1467         }
1468
1469         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1470                       srwm);
1471
1472         /* 965 has limitations... */
1473         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1474                    FW_WM(8, CURSORB) |
1475                    FW_WM(8, PLANEB) |
1476                    FW_WM(8, PLANEA));
1477         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1478                    FW_WM(8, PLANEC_OLD));
1479         /* update cursor SR watermark */
1480         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1481
1482         if (cxsr_enabled)
1483                 intel_set_memory_cxsr(dev_priv, true);
1484 }
1485
1486 #undef FW_WM
1487
1488 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1489 {
1490         struct drm_device *dev = unused_crtc->dev;
1491         struct drm_i915_private *dev_priv = dev->dev_private;
1492         const struct intel_watermark_params *wm_info;
1493         uint32_t fwater_lo;
1494         uint32_t fwater_hi;
1495         int cwm, srwm = 1;
1496         int fifo_size;
1497         int planea_wm, planeb_wm;
1498         struct drm_crtc *crtc, *enabled = NULL;
1499
1500         if (IS_I945GM(dev))
1501                 wm_info = &i945_wm_info;
1502         else if (!IS_GEN2(dev))
1503                 wm_info = &i915_wm_info;
1504         else
1505                 wm_info = &i830_a_wm_info;
1506
1507         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1508         crtc = intel_get_crtc_for_plane(dev, 0);
1509         if (intel_crtc_active(crtc)) {
1510                 const struct drm_display_mode *adjusted_mode;
1511                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1512                 if (IS_GEN2(dev))
1513                         cpp = 4;
1514
1515                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1516                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1517                                                wm_info, fifo_size, cpp,
1518                                                pessimal_latency_ns);
1519                 enabled = crtc;
1520         } else {
1521                 planea_wm = fifo_size - wm_info->guard_size;
1522                 if (planea_wm > (long)wm_info->max_wm)
1523                         planea_wm = wm_info->max_wm;
1524         }
1525
1526         if (IS_GEN2(dev))
1527                 wm_info = &i830_bc_wm_info;
1528
1529         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1530         crtc = intel_get_crtc_for_plane(dev, 1);
1531         if (intel_crtc_active(crtc)) {
1532                 const struct drm_display_mode *adjusted_mode;
1533                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1534                 if (IS_GEN2(dev))
1535                         cpp = 4;
1536
1537                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1538                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1539                                                wm_info, fifo_size, cpp,
1540                                                pessimal_latency_ns);
1541                 if (enabled == NULL)
1542                         enabled = crtc;
1543                 else
1544                         enabled = NULL;
1545         } else {
1546                 planeb_wm = fifo_size - wm_info->guard_size;
1547                 if (planeb_wm > (long)wm_info->max_wm)
1548                         planeb_wm = wm_info->max_wm;
1549         }
1550
1551         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1552
1553         if (IS_I915GM(dev) && enabled) {
1554                 struct drm_i915_gem_object *obj;
1555
1556                 obj = intel_fb_obj(enabled->primary->state->fb);
1557
1558                 /* self-refresh seems busted with untiled */
1559                 if (obj->tiling_mode == I915_TILING_NONE)
1560                         enabled = NULL;
1561         }
1562
1563         /*
1564          * Overlay gets an aggressive default since video jitter is bad.
1565          */
1566         cwm = 2;
1567
1568         /* Play safe and disable self-refresh before adjusting watermarks. */
1569         intel_set_memory_cxsr(dev_priv, false);
1570
1571         /* Calc sr entries for one plane configs */
1572         if (HAS_FW_BLC(dev) && enabled) {
1573                 /* self-refresh has much higher latency */
1574                 static const int sr_latency_ns = 6000;
1575                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1576                 int clock = adjusted_mode->crtc_clock;
1577                 int htotal = adjusted_mode->crtc_htotal;
1578                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1579                 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1580                 unsigned long line_time_us;
1581                 int entries;
1582
1583                 line_time_us = max(htotal * 1000 / clock, 1);
1584
1585                 /* Use ns/us then divide to preserve precision */
1586                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1587                         pixel_size * hdisplay;
1588                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1589                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1590                 srwm = wm_info->fifo_size - entries;
1591                 if (srwm < 0)
1592                         srwm = 1;
1593
1594                 if (IS_I945G(dev) || IS_I945GM(dev))
1595                         I915_WRITE(FW_BLC_SELF,
1596                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1597                 else if (IS_I915GM(dev))
1598                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1599         }
1600
1601         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1602                       planea_wm, planeb_wm, cwm, srwm);
1603
1604         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1605         fwater_hi = (cwm & 0x1f);
1606
1607         /* Set request length to 8 cachelines per fetch */
1608         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1609         fwater_hi = fwater_hi | (1 << 8);
1610
1611         I915_WRITE(FW_BLC, fwater_lo);
1612         I915_WRITE(FW_BLC2, fwater_hi);
1613
1614         if (enabled)
1615                 intel_set_memory_cxsr(dev_priv, true);
1616 }
1617
1618 static void i845_update_wm(struct drm_crtc *unused_crtc)
1619 {
1620         struct drm_device *dev = unused_crtc->dev;
1621         struct drm_i915_private *dev_priv = dev->dev_private;
1622         struct drm_crtc *crtc;
1623         const struct drm_display_mode *adjusted_mode;
1624         uint32_t fwater_lo;
1625         int planea_wm;
1626
1627         crtc = single_enabled_crtc(dev);
1628         if (crtc == NULL)
1629                 return;
1630
1631         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1632         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1633                                        &i845_wm_info,
1634                                        dev_priv->display.get_fifo_size(dev, 0),
1635                                        4, pessimal_latency_ns);
1636         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1637         fwater_lo |= (3<<8) | planea_wm;
1638
1639         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1640
1641         I915_WRITE(FW_BLC, fwater_lo);
1642 }
1643
1644 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1645 {
1646         uint32_t pixel_rate;
1647
1648         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1649
1650         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1651          * adjust the pixel_rate here. */
1652
1653         if (pipe_config->pch_pfit.enabled) {
1654                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1655                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1656
1657                 pipe_w = pipe_config->pipe_src_w;
1658                 pipe_h = pipe_config->pipe_src_h;
1659
1660                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1661                 pfit_h = pfit_size & 0xFFFF;
1662                 if (pipe_w < pfit_w)
1663                         pipe_w = pfit_w;
1664                 if (pipe_h < pfit_h)
1665                         pipe_h = pfit_h;
1666
1667                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1668                                      pfit_w * pfit_h);
1669         }
1670
1671         return pixel_rate;
1672 }
1673
1674 /* latency must be in 0.1us units. */
1675 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1676                                uint32_t latency)
1677 {
1678         uint64_t ret;
1679
1680         if (WARN(latency == 0, "Latency value missing\n"))
1681                 return UINT_MAX;
1682
1683         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1684         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1685
1686         return ret;
1687 }
1688
1689 /* latency must be in 0.1us units. */
1690 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1691                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1692                                uint32_t latency)
1693 {
1694         uint32_t ret;
1695
1696         if (WARN(latency == 0, "Latency value missing\n"))
1697                 return UINT_MAX;
1698
1699         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1700         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1701         ret = DIV_ROUND_UP(ret, 64) + 2;
1702         return ret;
1703 }
1704
1705 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1706                            uint8_t bytes_per_pixel)
1707 {
1708         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1709 }
1710
1711 struct skl_pipe_wm_parameters {
1712         bool active;
1713         uint32_t pipe_htotal;
1714         uint32_t pixel_rate; /* in KHz */
1715         struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1716 };
1717
1718 struct ilk_wm_maximums {
1719         uint16_t pri;
1720         uint16_t spr;
1721         uint16_t cur;
1722         uint16_t fbc;
1723 };
1724
1725 /* used in computing the new watermarks state */
1726 struct intel_wm_config {
1727         unsigned int num_pipes_active;
1728         bool sprites_enabled;
1729         bool sprites_scaled;
1730 };
1731
1732 /*
1733  * For both WM_PIPE and WM_LP.
1734  * mem_value must be in 0.1us units.
1735  */
1736 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1737                                    const struct intel_plane_state *pstate,
1738                                    uint32_t mem_value,
1739                                    bool is_lp)
1740 {
1741         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1742         uint32_t method1, method2;
1743
1744         if (!cstate->base.active || !pstate->visible)
1745                 return 0;
1746
1747         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1748
1749         if (!is_lp)
1750                 return method1;
1751
1752         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1753                                  cstate->base.adjusted_mode.crtc_htotal,
1754                                  drm_rect_width(&pstate->dst),
1755                                  bpp,
1756                                  mem_value);
1757
1758         return min(method1, method2);
1759 }
1760
1761 /*
1762  * For both WM_PIPE and WM_LP.
1763  * mem_value must be in 0.1us units.
1764  */
1765 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1766                                    const struct intel_plane_state *pstate,
1767                                    uint32_t mem_value)
1768 {
1769         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1770         uint32_t method1, method2;
1771
1772         if (!cstate->base.active || !pstate->visible)
1773                 return 0;
1774
1775         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1776         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1777                                  cstate->base.adjusted_mode.crtc_htotal,
1778                                  drm_rect_width(&pstate->dst),
1779                                  bpp,
1780                                  mem_value);
1781         return min(method1, method2);
1782 }
1783
1784 /*
1785  * For both WM_PIPE and WM_LP.
1786  * mem_value must be in 0.1us units.
1787  */
1788 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1789                                    const struct intel_plane_state *pstate,
1790                                    uint32_t mem_value)
1791 {
1792         /*
1793          * We treat the cursor plane as always-on for the purposes of watermark
1794          * calculation.  Until we have two-stage watermark programming merged,
1795          * this is necessary to avoid flickering.
1796          */
1797         int cpp = 4;
1798         int width = pstate->visible ? pstate->base.crtc_w : 64;
1799
1800         if (!cstate->base.active)
1801                 return 0;
1802
1803         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1804                               cstate->base.adjusted_mode.crtc_htotal,
1805                               width, cpp, mem_value);
1806 }
1807
1808 /* Only for WM_LP. */
1809 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1810                                    const struct intel_plane_state *pstate,
1811                                    uint32_t pri_val)
1812 {
1813         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1814
1815         if (!cstate->base.active || !pstate->visible)
1816                 return 0;
1817
1818         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
1819 }
1820
1821 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1822 {
1823         if (INTEL_INFO(dev)->gen >= 8)
1824                 return 3072;
1825         else if (INTEL_INFO(dev)->gen >= 7)
1826                 return 768;
1827         else
1828                 return 512;
1829 }
1830
1831 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1832                                          int level, bool is_sprite)
1833 {
1834         if (INTEL_INFO(dev)->gen >= 8)
1835                 /* BDW primary/sprite plane watermarks */
1836                 return level == 0 ? 255 : 2047;
1837         else if (INTEL_INFO(dev)->gen >= 7)
1838                 /* IVB/HSW primary/sprite plane watermarks */
1839                 return level == 0 ? 127 : 1023;
1840         else if (!is_sprite)
1841                 /* ILK/SNB primary plane watermarks */
1842                 return level == 0 ? 127 : 511;
1843         else
1844                 /* ILK/SNB sprite plane watermarks */
1845                 return level == 0 ? 63 : 255;
1846 }
1847
1848 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1849                                           int level)
1850 {
1851         if (INTEL_INFO(dev)->gen >= 7)
1852                 return level == 0 ? 63 : 255;
1853         else
1854                 return level == 0 ? 31 : 63;
1855 }
1856
1857 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1858 {
1859         if (INTEL_INFO(dev)->gen >= 8)
1860                 return 31;
1861         else
1862                 return 15;
1863 }
1864
1865 /* Calculate the maximum primary/sprite plane watermark */
1866 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1867                                      int level,
1868                                      const struct intel_wm_config *config,
1869                                      enum intel_ddb_partitioning ddb_partitioning,
1870                                      bool is_sprite)
1871 {
1872         unsigned int fifo_size = ilk_display_fifo_size(dev);
1873
1874         /* if sprites aren't enabled, sprites get nothing */
1875         if (is_sprite && !config->sprites_enabled)
1876                 return 0;
1877
1878         /* HSW allows LP1+ watermarks even with multiple pipes */
1879         if (level == 0 || config->num_pipes_active > 1) {
1880                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1881
1882                 /*
1883                  * For some reason the non self refresh
1884                  * FIFO size is only half of the self
1885                  * refresh FIFO size on ILK/SNB.
1886                  */
1887                 if (INTEL_INFO(dev)->gen <= 6)
1888                         fifo_size /= 2;
1889         }
1890
1891         if (config->sprites_enabled) {
1892                 /* level 0 is always calculated with 1:1 split */
1893                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1894                         if (is_sprite)
1895                                 fifo_size *= 5;
1896                         fifo_size /= 6;
1897                 } else {
1898                         fifo_size /= 2;
1899                 }
1900         }
1901
1902         /* clamp to max that the registers can hold */
1903         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1904 }
1905
1906 /* Calculate the maximum cursor plane watermark */
1907 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1908                                       int level,
1909                                       const struct intel_wm_config *config)
1910 {
1911         /* HSW LP1+ watermarks w/ multiple pipes */
1912         if (level > 0 && config->num_pipes_active > 1)
1913                 return 64;
1914
1915         /* otherwise just report max that registers can hold */
1916         return ilk_cursor_wm_reg_max(dev, level);
1917 }
1918
1919 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1920                                     int level,
1921                                     const struct intel_wm_config *config,
1922                                     enum intel_ddb_partitioning ddb_partitioning,
1923                                     struct ilk_wm_maximums *max)
1924 {
1925         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1926         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1927         max->cur = ilk_cursor_wm_max(dev, level, config);
1928         max->fbc = ilk_fbc_wm_reg_max(dev);
1929 }
1930
1931 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1932                                         int level,
1933                                         struct ilk_wm_maximums *max)
1934 {
1935         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1936         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1937         max->cur = ilk_cursor_wm_reg_max(dev, level);
1938         max->fbc = ilk_fbc_wm_reg_max(dev);
1939 }
1940
1941 static bool ilk_validate_wm_level(int level,
1942                                   const struct ilk_wm_maximums *max,
1943                                   struct intel_wm_level *result)
1944 {
1945         bool ret;
1946
1947         /* already determined to be invalid? */
1948         if (!result->enable)
1949                 return false;
1950
1951         result->enable = result->pri_val <= max->pri &&
1952                          result->spr_val <= max->spr &&
1953                          result->cur_val <= max->cur;
1954
1955         ret = result->enable;
1956
1957         /*
1958          * HACK until we can pre-compute everything,
1959          * and thus fail gracefully if LP0 watermarks
1960          * are exceeded...
1961          */
1962         if (level == 0 && !result->enable) {
1963                 if (result->pri_val > max->pri)
1964                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1965                                       level, result->pri_val, max->pri);
1966                 if (result->spr_val > max->spr)
1967                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1968                                       level, result->spr_val, max->spr);
1969                 if (result->cur_val > max->cur)
1970                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1971                                       level, result->cur_val, max->cur);
1972
1973                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1974                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1975                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1976                 result->enable = true;
1977         }
1978
1979         return ret;
1980 }
1981
1982 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1983                                  const struct intel_crtc *intel_crtc,
1984                                  int level,
1985                                  struct intel_crtc_state *cstate,
1986                                  struct intel_wm_level *result)
1987 {
1988         struct intel_plane *intel_plane;
1989         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1990         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1991         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1992
1993         /* WM1+ latency values stored in 0.5us units */
1994         if (level > 0) {
1995                 pri_latency *= 5;
1996                 spr_latency *= 5;
1997                 cur_latency *= 5;
1998         }
1999
2000         for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) {
2001                 struct intel_plane_state *pstate =
2002                         to_intel_plane_state(intel_plane->base.state);
2003
2004                 switch (intel_plane->base.type) {
2005                 case DRM_PLANE_TYPE_PRIMARY:
2006                         result->pri_val = ilk_compute_pri_wm(cstate, pstate,
2007                                                              pri_latency,
2008                                                              level);
2009                         result->fbc_val = ilk_compute_fbc_wm(cstate, pstate,
2010                                                              result->pri_val);
2011                         break;
2012                 case DRM_PLANE_TYPE_OVERLAY:
2013                         result->spr_val = ilk_compute_spr_wm(cstate, pstate,
2014                                                              spr_latency);
2015                         break;
2016                 case DRM_PLANE_TYPE_CURSOR:
2017                         result->cur_val = ilk_compute_cur_wm(cstate, pstate,
2018                                                              cur_latency);
2019                         break;
2020                 }
2021         }
2022
2023         result->enable = true;
2024 }
2025
2026 static uint32_t
2027 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2028 {
2029         struct drm_i915_private *dev_priv = dev->dev_private;
2030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2031         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
2032         u32 linetime, ips_linetime;
2033
2034         if (!intel_crtc->active)
2035                 return 0;
2036
2037         /* The WM are computed with base on how long it takes to fill a single
2038          * row at the given clock rate, multiplied by 8.
2039          * */
2040         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2041                                      adjusted_mode->crtc_clock);
2042         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2043                                          dev_priv->cdclk_freq);
2044
2045         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2046                PIPE_WM_LINETIME_TIME(linetime);
2047 }
2048
2049 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2050 {
2051         struct drm_i915_private *dev_priv = dev->dev_private;
2052
2053         if (IS_GEN9(dev)) {
2054                 uint32_t val;
2055                 int ret, i;
2056                 int level, max_level = ilk_wm_max_level(dev);
2057
2058                 /* read the first set of memory latencies[0:3] */
2059                 val = 0; /* data0 to be programmed to 0 for first set */
2060                 mutex_lock(&dev_priv->rps.hw_lock);
2061                 ret = sandybridge_pcode_read(dev_priv,
2062                                              GEN9_PCODE_READ_MEM_LATENCY,
2063                                              &val);
2064                 mutex_unlock(&dev_priv->rps.hw_lock);
2065
2066                 if (ret) {
2067                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2068                         return;
2069                 }
2070
2071                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2072                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2073                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2074                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2075                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2076                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2077                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2078
2079                 /* read the second set of memory latencies[4:7] */
2080                 val = 1; /* data0 to be programmed to 1 for second set */
2081                 mutex_lock(&dev_priv->rps.hw_lock);
2082                 ret = sandybridge_pcode_read(dev_priv,
2083                                              GEN9_PCODE_READ_MEM_LATENCY,
2084                                              &val);
2085                 mutex_unlock(&dev_priv->rps.hw_lock);
2086                 if (ret) {
2087                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2088                         return;
2089                 }
2090
2091                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2092                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2093                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2094                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2095                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2096                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2097                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2098
2099                 /*
2100                  * WaWmMemoryReadLatency:skl
2101                  *
2102                  * punit doesn't take into account the read latency so we need
2103                  * to add 2us to the various latency levels we retrieve from
2104                  * the punit.
2105                  *   - W0 is a bit special in that it's the only level that
2106                  *   can't be disabled if we want to have display working, so
2107                  *   we always add 2us there.
2108                  *   - For levels >=1, punit returns 0us latency when they are
2109                  *   disabled, so we respect that and don't add 2us then
2110                  *
2111                  * Additionally, if a level n (n > 1) has a 0us latency, all
2112                  * levels m (m >= n) need to be disabled. We make sure to
2113                  * sanitize the values out of the punit to satisfy this
2114                  * requirement.
2115                  */
2116                 wm[0] += 2;
2117                 for (level = 1; level <= max_level; level++)
2118                         if (wm[level] != 0)
2119                                 wm[level] += 2;
2120                         else {
2121                                 for (i = level + 1; i <= max_level; i++)
2122                                         wm[i] = 0;
2123
2124                                 break;
2125                         }
2126         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2127                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2128
2129                 wm[0] = (sskpd >> 56) & 0xFF;
2130                 if (wm[0] == 0)
2131                         wm[0] = sskpd & 0xF;
2132                 wm[1] = (sskpd >> 4) & 0xFF;
2133                 wm[2] = (sskpd >> 12) & 0xFF;
2134                 wm[3] = (sskpd >> 20) & 0x1FF;
2135                 wm[4] = (sskpd >> 32) & 0x1FF;
2136         } else if (INTEL_INFO(dev)->gen >= 6) {
2137                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2138
2139                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2140                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2141                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2142                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2143         } else if (INTEL_INFO(dev)->gen >= 5) {
2144                 uint32_t mltr = I915_READ(MLTR_ILK);
2145
2146                 /* ILK primary LP0 latency is 700 ns */
2147                 wm[0] = 7;
2148                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2149                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2150         }
2151 }
2152
2153 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2154 {
2155         /* ILK sprite LP0 latency is 1300 ns */
2156         if (INTEL_INFO(dev)->gen == 5)
2157                 wm[0] = 13;
2158 }
2159
2160 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2161 {
2162         /* ILK cursor LP0 latency is 1300 ns */
2163         if (INTEL_INFO(dev)->gen == 5)
2164                 wm[0] = 13;
2165
2166         /* WaDoubleCursorLP3Latency:ivb */
2167         if (IS_IVYBRIDGE(dev))
2168                 wm[3] *= 2;
2169 }
2170
2171 int ilk_wm_max_level(const struct drm_device *dev)
2172 {
2173         /* how many WM levels are we expecting */
2174         if (INTEL_INFO(dev)->gen >= 9)
2175                 return 7;
2176         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2177                 return 4;
2178         else if (INTEL_INFO(dev)->gen >= 6)
2179                 return 3;
2180         else
2181                 return 2;
2182 }
2183
2184 static void intel_print_wm_latency(struct drm_device *dev,
2185                                    const char *name,
2186                                    const uint16_t wm[8])
2187 {
2188         int level, max_level = ilk_wm_max_level(dev);
2189
2190         for (level = 0; level <= max_level; level++) {
2191                 unsigned int latency = wm[level];
2192
2193                 if (latency == 0) {
2194                         DRM_ERROR("%s WM%d latency not provided\n",
2195                                   name, level);
2196                         continue;
2197                 }
2198
2199                 /*
2200                  * - latencies are in us on gen9.
2201                  * - before then, WM1+ latency values are in 0.5us units
2202                  */
2203                 if (IS_GEN9(dev))
2204                         latency *= 10;
2205                 else if (level > 0)
2206                         latency *= 5;
2207
2208                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2209                               name, level, wm[level],
2210                               latency / 10, latency % 10);
2211         }
2212 }
2213
2214 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2215                                     uint16_t wm[5], uint16_t min)
2216 {
2217         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2218
2219         if (wm[0] >= min)
2220                 return false;
2221
2222         wm[0] = max(wm[0], min);
2223         for (level = 1; level <= max_level; level++)
2224                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2225
2226         return true;
2227 }
2228
2229 static void snb_wm_latency_quirk(struct drm_device *dev)
2230 {
2231         struct drm_i915_private *dev_priv = dev->dev_private;
2232         bool changed;
2233
2234         /*
2235          * The BIOS provided WM memory latency values are often
2236          * inadequate for high resolution displays. Adjust them.
2237          */
2238         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2239                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2240                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2241
2242         if (!changed)
2243                 return;
2244
2245         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2246         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2247         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2248         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2249 }
2250
2251 static void ilk_setup_wm_latency(struct drm_device *dev)
2252 {
2253         struct drm_i915_private *dev_priv = dev->dev_private;
2254
2255         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2256
2257         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2258                sizeof(dev_priv->wm.pri_latency));
2259         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2260                sizeof(dev_priv->wm.pri_latency));
2261
2262         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2263         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2264
2265         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2266         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2267         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2268
2269         if (IS_GEN6(dev))
2270                 snb_wm_latency_quirk(dev);
2271 }
2272
2273 static void skl_setup_wm_latency(struct drm_device *dev)
2274 {
2275         struct drm_i915_private *dev_priv = dev->dev_private;
2276
2277         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2278         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2279 }
2280
2281 static void ilk_compute_wm_config(struct drm_device *dev,
2282                                   struct intel_wm_config *config)
2283 {
2284         struct intel_crtc *intel_crtc;
2285
2286         /* Compute the currently _active_ config */
2287         for_each_intel_crtc(dev, intel_crtc) {
2288                 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2289
2290                 if (!wm->pipe_enabled)
2291                         continue;
2292
2293                 config->sprites_enabled |= wm->sprites_enabled;
2294                 config->sprites_scaled |= wm->sprites_scaled;
2295                 config->num_pipes_active++;
2296         }
2297 }
2298
2299 /* Compute new watermarks for the pipe */
2300 static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,
2301                                   struct intel_pipe_wm *pipe_wm)
2302 {
2303         struct drm_crtc *crtc = cstate->base.crtc;
2304         struct drm_device *dev = crtc->dev;
2305         const struct drm_i915_private *dev_priv = dev->dev_private;
2306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2307         struct intel_plane *intel_plane;
2308         struct intel_plane_state *sprstate = NULL;
2309         int level, max_level = ilk_wm_max_level(dev);
2310         /* LP0 watermark maximums depend on this pipe alone */
2311         struct intel_wm_config config = {
2312                 .num_pipes_active = 1,
2313         };
2314         struct ilk_wm_maximums max;
2315
2316         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2317                 if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) {
2318                         sprstate = to_intel_plane_state(intel_plane->base.state);
2319                         break;
2320                 }
2321         }
2322
2323         config.sprites_enabled = sprstate->visible;
2324         config.sprites_scaled = sprstate->visible &&
2325                 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2326                 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2327
2328         pipe_wm->pipe_enabled = cstate->base.active;
2329         pipe_wm->sprites_enabled = sprstate->visible;
2330         pipe_wm->sprites_scaled = config.sprites_scaled;
2331
2332         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2333         if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2334                 max_level = 1;
2335
2336         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2337         if (config.sprites_scaled)
2338                 max_level = 0;
2339
2340         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]);
2341
2342         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2343                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2344
2345         /* LP0 watermarks always use 1/2 DDB partitioning */
2346         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2347
2348         /* At least LP0 must be valid */
2349         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2350                 return false;
2351
2352         ilk_compute_wm_reg_maximums(dev, 1, &max);
2353
2354         for (level = 1; level <= max_level; level++) {
2355                 struct intel_wm_level wm = {};
2356
2357                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm);
2358
2359                 /*
2360                  * Disable any watermark level that exceeds the
2361                  * register maximums since such watermarks are
2362                  * always invalid.
2363                  */
2364                 if (!ilk_validate_wm_level(level, &max, &wm))
2365                         break;
2366
2367                 pipe_wm->wm[level] = wm;
2368         }
2369
2370         return true;
2371 }
2372
2373 /*
2374  * Merge the watermarks from all active pipes for a specific level.
2375  */
2376 static void ilk_merge_wm_level(struct drm_device *dev,
2377                                int level,
2378                                struct intel_wm_level *ret_wm)
2379 {
2380         const struct intel_crtc *intel_crtc;
2381
2382         ret_wm->enable = true;
2383
2384         for_each_intel_crtc(dev, intel_crtc) {
2385                 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2386                 const struct intel_wm_level *wm = &active->wm[level];
2387
2388                 if (!active->pipe_enabled)
2389                         continue;
2390
2391                 /*
2392                  * The watermark values may have been used in the past,
2393                  * so we must maintain them in the registers for some
2394                  * time even if the level is now disabled.
2395                  */
2396                 if (!wm->enable)
2397                         ret_wm->enable = false;
2398
2399                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2400                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2401                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2402                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2403         }
2404 }
2405
2406 /*
2407  * Merge all low power watermarks for all active pipes.
2408  */
2409 static void ilk_wm_merge(struct drm_device *dev,
2410                          const struct intel_wm_config *config,
2411                          const struct ilk_wm_maximums *max,
2412                          struct intel_pipe_wm *merged)
2413 {
2414         struct drm_i915_private *dev_priv = dev->dev_private;
2415         int level, max_level = ilk_wm_max_level(dev);
2416         int last_enabled_level = max_level;
2417
2418         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2419         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2420             config->num_pipes_active > 1)
2421                 return;
2422
2423         /* ILK: FBC WM must be disabled always */
2424         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2425
2426         /* merge each WM1+ level */
2427         for (level = 1; level <= max_level; level++) {
2428                 struct intel_wm_level *wm = &merged->wm[level];
2429
2430                 ilk_merge_wm_level(dev, level, wm);
2431
2432                 if (level > last_enabled_level)
2433                         wm->enable = false;
2434                 else if (!ilk_validate_wm_level(level, max, wm))
2435                         /* make sure all following levels get disabled */
2436                         last_enabled_level = level - 1;
2437
2438                 /*
2439                  * The spec says it is preferred to disable
2440                  * FBC WMs instead of disabling a WM level.
2441                  */
2442                 if (wm->fbc_val > max->fbc) {
2443                         if (wm->enable)
2444                                 merged->fbc_wm_enabled = false;
2445                         wm->fbc_val = 0;
2446                 }
2447         }
2448
2449         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2450         /*
2451          * FIXME this is racy. FBC might get enabled later.
2452          * What we should check here is whether FBC can be
2453          * enabled sometime later.
2454          */
2455         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2456             intel_fbc_enabled(dev_priv)) {
2457                 for (level = 2; level <= max_level; level++) {
2458                         struct intel_wm_level *wm = &merged->wm[level];
2459
2460                         wm->enable = false;
2461                 }
2462         }
2463 }
2464
2465 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2466 {
2467         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2468         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2469 }
2470
2471 /* The value we need to program into the WM_LPx latency field */
2472 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2473 {
2474         struct drm_i915_private *dev_priv = dev->dev_private;
2475
2476         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2477                 return 2 * level;
2478         else
2479                 return dev_priv->wm.pri_latency[level];
2480 }
2481
2482 static void ilk_compute_wm_results(struct drm_device *dev,
2483                                    const struct intel_pipe_wm *merged,
2484                                    enum intel_ddb_partitioning partitioning,
2485                                    struct ilk_wm_values *results)
2486 {
2487         struct intel_crtc *intel_crtc;
2488         int level, wm_lp;
2489
2490         results->enable_fbc_wm = merged->fbc_wm_enabled;
2491         results->partitioning = partitioning;
2492
2493         /* LP1+ register values */
2494         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2495                 const struct intel_wm_level *r;
2496
2497                 level = ilk_wm_lp_to_level(wm_lp, merged);
2498
2499                 r = &merged->wm[level];
2500
2501                 /*
2502                  * Maintain the watermark values even if the level is
2503                  * disabled. Doing otherwise could cause underruns.
2504                  */
2505                 results->wm_lp[wm_lp - 1] =
2506                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2507                         (r->pri_val << WM1_LP_SR_SHIFT) |
2508                         r->cur_val;
2509
2510                 if (r->enable)
2511                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2512
2513                 if (INTEL_INFO(dev)->gen >= 8)
2514                         results->wm_lp[wm_lp - 1] |=
2515                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2516                 else
2517                         results->wm_lp[wm_lp - 1] |=
2518                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2519
2520                 /*
2521                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2522                  * level is disabled. Doing otherwise could cause underruns.
2523                  */
2524                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2525                         WARN_ON(wm_lp != 1);
2526                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2527                 } else
2528                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2529         }
2530
2531         /* LP0 register values */
2532         for_each_intel_crtc(dev, intel_crtc) {
2533                 enum pipe pipe = intel_crtc->pipe;
2534                 const struct intel_wm_level *r =
2535                         &intel_crtc->wm.active.wm[0];
2536
2537                 if (WARN_ON(!r->enable))
2538                         continue;
2539
2540                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2541
2542                 results->wm_pipe[pipe] =
2543                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2544                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2545                         r->cur_val;
2546         }
2547 }
2548
2549 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2550  * case both are at the same level. Prefer r1 in case they're the same. */
2551 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2552                                                   struct intel_pipe_wm *r1,
2553                                                   struct intel_pipe_wm *r2)
2554 {
2555         int level, max_level = ilk_wm_max_level(dev);
2556         int level1 = 0, level2 = 0;
2557
2558         for (level = 1; level <= max_level; level++) {
2559                 if (r1->wm[level].enable)
2560                         level1 = level;
2561                 if (r2->wm[level].enable)
2562                         level2 = level;
2563         }
2564
2565         if (level1 == level2) {
2566                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2567                         return r2;
2568                 else
2569                         return r1;
2570         } else if (level1 > level2) {
2571                 return r1;
2572         } else {
2573                 return r2;
2574         }
2575 }
2576
2577 /* dirty bits used to track which watermarks need changes */
2578 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2579 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2580 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2581 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2582 #define WM_DIRTY_FBC (1 << 24)
2583 #define WM_DIRTY_DDB (1 << 25)
2584
2585 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2586                                          const struct ilk_wm_values *old,
2587                                          const struct ilk_wm_values *new)
2588 {
2589         unsigned int dirty = 0;
2590         enum pipe pipe;
2591         int wm_lp;
2592
2593         for_each_pipe(dev_priv, pipe) {
2594                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2595                         dirty |= WM_DIRTY_LINETIME(pipe);
2596                         /* Must disable LP1+ watermarks too */
2597                         dirty |= WM_DIRTY_LP_ALL;
2598                 }
2599
2600                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2601                         dirty |= WM_DIRTY_PIPE(pipe);
2602                         /* Must disable LP1+ watermarks too */
2603                         dirty |= WM_DIRTY_LP_ALL;
2604                 }
2605         }
2606
2607         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2608                 dirty |= WM_DIRTY_FBC;
2609                 /* Must disable LP1+ watermarks too */
2610                 dirty |= WM_DIRTY_LP_ALL;
2611         }
2612
2613         if (old->partitioning != new->partitioning) {
2614                 dirty |= WM_DIRTY_DDB;
2615                 /* Must disable LP1+ watermarks too */
2616                 dirty |= WM_DIRTY_LP_ALL;
2617         }
2618
2619         /* LP1+ watermarks already deemed dirty, no need to continue */
2620         if (dirty & WM_DIRTY_LP_ALL)
2621                 return dirty;
2622
2623         /* Find the lowest numbered LP1+ watermark in need of an update... */
2624         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2625                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2626                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2627                         break;
2628         }
2629
2630         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2631         for (; wm_lp <= 3; wm_lp++)
2632                 dirty |= WM_DIRTY_LP(wm_lp);
2633
2634         return dirty;
2635 }
2636
2637 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2638                                unsigned int dirty)
2639 {
2640         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2641         bool changed = false;
2642
2643         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2644                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2645                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2646                 changed = true;
2647         }
2648         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2649                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2650                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2651                 changed = true;
2652         }
2653         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2654                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2655                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2656                 changed = true;
2657         }
2658
2659         /*
2660          * Don't touch WM1S_LP_EN here.
2661          * Doing so could cause underruns.
2662          */
2663
2664         return changed;
2665 }
2666
2667 /*
2668  * The spec says we shouldn't write when we don't need, because every write
2669  * causes WMs to be re-evaluated, expending some power.
2670  */
2671 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2672                                 struct ilk_wm_values *results)
2673 {
2674         struct drm_device *dev = dev_priv->dev;
2675         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2676         unsigned int dirty;
2677         uint32_t val;
2678
2679         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2680         if (!dirty)
2681                 return;
2682
2683         _ilk_disable_lp_wm(dev_priv, dirty);
2684
2685         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2686                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2687         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2688                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2689         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2690                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2691
2692         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2693                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2694         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2695                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2696         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2697                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2698
2699         if (dirty & WM_DIRTY_DDB) {
2700                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2701                         val = I915_READ(WM_MISC);
2702                         if (results->partitioning == INTEL_DDB_PART_1_2)
2703                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2704                         else
2705                                 val |= WM_MISC_DATA_PARTITION_5_6;
2706                         I915_WRITE(WM_MISC, val);
2707                 } else {
2708                         val = I915_READ(DISP_ARB_CTL2);
2709                         if (results->partitioning == INTEL_DDB_PART_1_2)
2710                                 val &= ~DISP_DATA_PARTITION_5_6;
2711                         else
2712                                 val |= DISP_DATA_PARTITION_5_6;
2713                         I915_WRITE(DISP_ARB_CTL2, val);
2714                 }
2715         }
2716
2717         if (dirty & WM_DIRTY_FBC) {
2718                 val = I915_READ(DISP_ARB_CTL);
2719                 if (results->enable_fbc_wm)
2720                         val &= ~DISP_FBC_WM_DIS;
2721                 else
2722                         val |= DISP_FBC_WM_DIS;
2723                 I915_WRITE(DISP_ARB_CTL, val);
2724         }
2725
2726         if (dirty & WM_DIRTY_LP(1) &&
2727             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2728                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2729
2730         if (INTEL_INFO(dev)->gen >= 7) {
2731                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2732                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2733                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2734                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2735         }
2736
2737         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2738                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2739         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2740                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2741         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2742                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2743
2744         dev_priv->wm.hw = *results;
2745 }
2746
2747 static bool ilk_disable_lp_wm(struct drm_device *dev)
2748 {
2749         struct drm_i915_private *dev_priv = dev->dev_private;
2750
2751         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2752 }
2753
2754 /*
2755  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2756  * different active planes.
2757  */
2758
2759 #define SKL_DDB_SIZE            896     /* in blocks */
2760 #define BXT_DDB_SIZE            512
2761
2762 static void
2763 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2764                                    struct drm_crtc *for_crtc,
2765                                    const struct intel_wm_config *config,
2766                                    const struct skl_pipe_wm_parameters *params,
2767                                    struct skl_ddb_entry *alloc /* out */)
2768 {
2769         struct drm_crtc *crtc;
2770         unsigned int pipe_size, ddb_size;
2771         int nth_active_pipe;
2772
2773         if (!params->active) {
2774                 alloc->start = 0;
2775                 alloc->end = 0;
2776                 return;
2777         }
2778
2779         if (IS_BROXTON(dev))
2780                 ddb_size = BXT_DDB_SIZE;
2781         else
2782                 ddb_size = SKL_DDB_SIZE;
2783
2784         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2785
2786         nth_active_pipe = 0;
2787         for_each_crtc(dev, crtc) {
2788                 if (!to_intel_crtc(crtc)->active)
2789                         continue;
2790
2791                 if (crtc == for_crtc)
2792                         break;
2793
2794                 nth_active_pipe++;
2795         }
2796
2797         pipe_size = ddb_size / config->num_pipes_active;
2798         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2799         alloc->end = alloc->start + pipe_size;
2800 }
2801
2802 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2803 {
2804         if (config->num_pipes_active == 1)
2805                 return 32;
2806
2807         return 8;
2808 }
2809
2810 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2811 {
2812         entry->start = reg & 0x3ff;
2813         entry->end = (reg >> 16) & 0x3ff;
2814         if (entry->end)
2815                 entry->end += 1;
2816 }
2817
2818 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2819                           struct skl_ddb_allocation *ddb /* out */)
2820 {
2821         enum pipe pipe;
2822         int plane;
2823         u32 val;
2824
2825         memset(ddb, 0, sizeof(*ddb));
2826
2827         for_each_pipe(dev_priv, pipe) {
2828                 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2829                         continue;
2830
2831                 for_each_plane(dev_priv, pipe, plane) {
2832                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2833                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2834                                                    val);
2835                 }
2836
2837                 val = I915_READ(CUR_BUF_CFG(pipe));
2838                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2839                                            val);
2840         }
2841 }
2842
2843 static unsigned int
2844 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
2845 {
2846
2847         /* for planar format */
2848         if (p->y_bytes_per_pixel) {
2849                 if (y)  /* y-plane data rate */
2850                         return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2851                 else    /* uv-plane data rate */
2852                         return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2853         }
2854
2855         /* for packed formats */
2856         return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2857 }
2858
2859 /*
2860  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2861  * a 8192x4096@32bpp framebuffer:
2862  *   3 * 4096 * 8192  * 4 < 2^32
2863  */
2864 static unsigned int
2865 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2866                                  const struct skl_pipe_wm_parameters *params)
2867 {
2868         unsigned int total_data_rate = 0;
2869         int plane;
2870
2871         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2872                 const struct intel_plane_wm_parameters *p;
2873
2874                 p = &params->plane[plane];
2875                 if (!p->enabled)
2876                         continue;
2877
2878                 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2879                 if (p->y_bytes_per_pixel) {
2880                         total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2881                 }
2882         }
2883
2884         return total_data_rate;
2885 }
2886
2887 static void
2888 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2889                       const struct intel_wm_config *config,
2890                       const struct skl_pipe_wm_parameters *params,
2891                       struct skl_ddb_allocation *ddb /* out */)
2892 {
2893         struct drm_device *dev = crtc->dev;
2894         struct drm_i915_private *dev_priv = dev->dev_private;
2895         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2896         enum pipe pipe = intel_crtc->pipe;
2897         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2898         uint16_t alloc_size, start, cursor_blocks;
2899         uint16_t minimum[I915_MAX_PLANES];
2900         uint16_t y_minimum[I915_MAX_PLANES];
2901         unsigned int total_data_rate;
2902         int plane;
2903
2904         skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2905         alloc_size = skl_ddb_entry_size(alloc);
2906         if (alloc_size == 0) {
2907                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2908                 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2909                        sizeof(ddb->plane[pipe][PLANE_CURSOR]));
2910                 return;
2911         }
2912
2913         cursor_blocks = skl_cursor_allocation(config);
2914         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2915         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
2916
2917         alloc_size -= cursor_blocks;
2918         alloc->end -= cursor_blocks;
2919
2920         /* 1. Allocate the mininum required blocks for each active plane */
2921         for_each_plane(dev_priv, pipe, plane) {
2922                 const struct intel_plane_wm_parameters *p;
2923
2924                 p = &params->plane[plane];
2925                 if (!p->enabled)
2926                         continue;
2927
2928                 minimum[plane] = 8;
2929                 alloc_size -= minimum[plane];
2930                 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2931                 alloc_size -= y_minimum[plane];
2932         }
2933
2934         /*
2935          * 2. Distribute the remaining space in proportion to the amount of
2936          * data each plane needs to fetch from memory.
2937          *
2938          * FIXME: we may not allocate every single block here.
2939          */
2940         total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2941
2942         start = alloc->start;
2943         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2944                 const struct intel_plane_wm_parameters *p;
2945                 unsigned int data_rate, y_data_rate;
2946                 uint16_t plane_blocks, y_plane_blocks = 0;
2947
2948                 p = &params->plane[plane];
2949                 if (!p->enabled)
2950                         continue;
2951
2952                 data_rate = skl_plane_relative_data_rate(p, 0);
2953
2954                 /*
2955                  * allocation for (packed formats) or (uv-plane part of planar format):
2956                  * promote the expression to 64 bits to avoid overflowing, the
2957                  * result is < available as data_rate / total_data_rate < 1
2958                  */
2959                 plane_blocks = minimum[plane];
2960                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2961                                         total_data_rate);
2962
2963                 ddb->plane[pipe][plane].start = start;
2964                 ddb->plane[pipe][plane].end = start + plane_blocks;
2965
2966                 start += plane_blocks;
2967
2968                 /*
2969                  * allocation for y_plane part of planar format:
2970                  */
2971                 if (p->y_bytes_per_pixel) {
2972                         y_data_rate = skl_plane_relative_data_rate(p, 1);
2973                         y_plane_blocks = y_minimum[plane];
2974                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
2975                                                 total_data_rate);
2976
2977                         ddb->y_plane[pipe][plane].start = start;
2978                         ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
2979
2980                         start += y_plane_blocks;
2981                 }
2982
2983         }
2984
2985 }
2986
2987 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2988 {
2989         /* TODO: Take into account the scalers once we support them */
2990         return config->base.adjusted_mode.crtc_clock;
2991 }
2992
2993 /*
2994  * The max latency should be 257 (max the punit can code is 255 and we add 2us
2995  * for the read latency) and bytes_per_pixel should always be <= 8, so that
2996  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2997  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2998 */
2999 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3000                                uint32_t latency)
3001 {
3002         uint32_t wm_intermediate_val, ret;
3003
3004         if (latency == 0)
3005                 return UINT_MAX;
3006
3007         wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3008         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3009
3010         return ret;
3011 }
3012
3013 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3014                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3015                                uint64_t tiling, uint32_t latency)
3016 {
3017         uint32_t ret;
3018         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3019         uint32_t wm_intermediate_val;
3020
3021         if (latency == 0)
3022                 return UINT_MAX;
3023
3024         plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3025
3026         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3027             tiling == I915_FORMAT_MOD_Yf_TILED) {
3028                 plane_bytes_per_line *= 4;
3029                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3030                 plane_blocks_per_line /= 4;
3031         } else {
3032                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3033         }
3034
3035         wm_intermediate_val = latency * pixel_rate;
3036         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3037                                 plane_blocks_per_line;
3038
3039         return ret;
3040 }
3041
3042 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3043                                        const struct intel_crtc *intel_crtc)
3044 {
3045         struct drm_device *dev = intel_crtc->base.dev;
3046         struct drm_i915_private *dev_priv = dev->dev_private;
3047         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3048         enum pipe pipe = intel_crtc->pipe;
3049
3050         if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3051                    sizeof(new_ddb->plane[pipe])))
3052                 return true;
3053
3054         if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR],
3055                     sizeof(new_ddb->plane[pipe][PLANE_CURSOR])))
3056                 return true;
3057
3058         return false;
3059 }
3060
3061 static void skl_compute_wm_global_parameters(struct drm_device *dev,
3062                                              struct intel_wm_config *config)
3063 {
3064         struct drm_crtc *crtc;
3065         struct drm_plane *plane;
3066
3067         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3068                 config->num_pipes_active += to_intel_crtc(crtc)->active;
3069
3070         /* FIXME: I don't think we need those two global parameters on SKL */
3071         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3072                 struct intel_plane *intel_plane = to_intel_plane(plane);
3073
3074                 config->sprites_enabled |= intel_plane->wm.enabled;
3075                 config->sprites_scaled |= intel_plane->wm.scaled;
3076         }
3077 }
3078
3079 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3080                                            struct skl_pipe_wm_parameters *p)
3081 {
3082         struct drm_device *dev = crtc->dev;
3083         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084         enum pipe pipe = intel_crtc->pipe;
3085         struct drm_plane *plane;
3086         struct drm_framebuffer *fb;
3087         int i = 1; /* Index for sprite planes start */
3088
3089         p->active = intel_crtc->active;
3090         if (p->active) {
3091                 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3092                 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
3093
3094                 fb = crtc->primary->state->fb;
3095                 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
3096                 if (fb) {
3097                         p->plane[0].enabled = true;
3098                         p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3099                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3100                                 drm_format_plane_cpp(fb->pixel_format, 0);
3101                         p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3102                                 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
3103                         p->plane[0].tiling = fb->modifier[0];
3104                 } else {
3105                         p->plane[0].enabled = false;
3106                         p->plane[0].bytes_per_pixel = 0;
3107                         p->plane[0].y_bytes_per_pixel = 0;
3108                         p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3109                 }
3110                 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3111                 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
3112                 p->plane[0].rotation = crtc->primary->state->rotation;
3113
3114                 fb = crtc->cursor->state->fb;
3115                 p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0;
3116                 if (fb) {
3117                         p->plane[PLANE_CURSOR].enabled = true;
3118                         p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8;
3119                         p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w;
3120                         p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h;
3121                 } else {
3122                         p->plane[PLANE_CURSOR].enabled = false;
3123                         p->plane[PLANE_CURSOR].bytes_per_pixel = 0;
3124                         p->plane[PLANE_CURSOR].horiz_pixels = 64;
3125                         p->plane[PLANE_CURSOR].vert_pixels = 64;
3126                 }
3127         }
3128
3129         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3130                 struct intel_plane *intel_plane = to_intel_plane(plane);
3131
3132                 if (intel_plane->pipe == pipe &&
3133                         plane->type == DRM_PLANE_TYPE_OVERLAY)
3134                         p->plane[i++] = intel_plane->wm;
3135         }
3136 }
3137
3138 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3139                                  struct skl_pipe_wm_parameters *p,
3140                                  struct intel_plane_wm_parameters *p_params,
3141                                  uint16_t ddb_allocation,
3142                                  int level,
3143                                  uint16_t *out_blocks, /* out */
3144                                  uint8_t *out_lines /* out */)
3145 {
3146         uint32_t latency = dev_priv->wm.skl_latency[level];
3147         uint32_t method1, method2;
3148         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3149         uint32_t res_blocks, res_lines;
3150         uint32_t selected_result;
3151         uint8_t bytes_per_pixel;
3152
3153         if (latency == 0 || !p->active || !p_params->enabled)
3154                 return false;
3155
3156         bytes_per_pixel = p_params->y_bytes_per_pixel ?
3157                 p_params->y_bytes_per_pixel :
3158                 p_params->bytes_per_pixel;
3159         method1 = skl_wm_method1(p->pixel_rate,
3160                                  bytes_per_pixel,
3161                                  latency);
3162         method2 = skl_wm_method2(p->pixel_rate,
3163                                  p->pipe_htotal,
3164                                  p_params->horiz_pixels,
3165                                  bytes_per_pixel,
3166                                  p_params->tiling,
3167                                  latency);
3168
3169         plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
3170         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3171
3172         if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3173             p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
3174                 uint32_t min_scanlines = 4;
3175                 uint32_t y_tile_minimum;
3176                 if (intel_rotation_90_or_270(p_params->rotation)) {
3177                         switch (p_params->bytes_per_pixel) {
3178                         case 1:
3179                                 min_scanlines = 16;
3180                                 break;
3181                         case 2:
3182                                 min_scanlines = 8;
3183                                 break;
3184                         case 8:
3185                                 WARN(1, "Unsupported pixel depth for rotation");
3186                         }
3187                 }
3188                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3189                 selected_result = max(method2, y_tile_minimum);
3190         } else {
3191                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3192                         selected_result = min(method1, method2);
3193                 else
3194                         selected_result = method1;
3195         }
3196
3197         res_blocks = selected_result + 1;
3198         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3199
3200         if (level >= 1 && level <= 7) {
3201                 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3202                     p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3203                         res_lines += 4;
3204                 else
3205                         res_blocks++;
3206         }
3207
3208         if (res_blocks >= ddb_allocation || res_lines > 31)
3209                 return false;
3210
3211         *out_blocks = res_blocks;
3212         *out_lines = res_lines;
3213
3214         return true;
3215 }
3216
3217 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3218                                  struct skl_ddb_allocation *ddb,
3219                                  struct skl_pipe_wm_parameters *p,
3220                                  enum pipe pipe,
3221                                  int level,
3222                                  int num_planes,
3223                                  struct skl_wm_level *result)
3224 {
3225         uint16_t ddb_blocks;
3226         int i;
3227
3228         for (i = 0; i < num_planes; i++) {
3229                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3230
3231                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3232                                                 p, &p->plane[i],
3233                                                 ddb_blocks,
3234                                                 level,
3235                                                 &result->plane_res_b[i],
3236                                                 &result->plane_res_l[i]);
3237         }
3238
3239         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]);
3240         result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p,
3241                                                  &p->plane[PLANE_CURSOR],
3242                                                  ddb_blocks, level,
3243                                                  &result->plane_res_b[PLANE_CURSOR],
3244                                                  &result->plane_res_l[PLANE_CURSOR]);
3245 }
3246
3247 static uint32_t
3248 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3249 {
3250         if (!to_intel_crtc(crtc)->active)
3251                 return 0;
3252
3253         if (WARN_ON(p->pixel_rate == 0))
3254                 return 0;
3255
3256         return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3257 }
3258
3259 static void skl_compute_transition_wm(struct drm_crtc *crtc,
3260                                       struct skl_pipe_wm_parameters *params,
3261                                       struct skl_wm_level *trans_wm /* out */)
3262 {
3263         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3264         int i;
3265
3266         if (!params->active)
3267                 return;
3268
3269         /* Until we know more, just disable transition WMs */
3270         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3271                 trans_wm->plane_en[i] = false;
3272         trans_wm->plane_en[PLANE_CURSOR] = false;
3273 }
3274
3275 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3276                                 struct skl_ddb_allocation *ddb,
3277                                 struct skl_pipe_wm_parameters *params,
3278                                 struct skl_pipe_wm *pipe_wm)
3279 {
3280         struct drm_device *dev = crtc->dev;
3281         const struct drm_i915_private *dev_priv = dev->dev_private;
3282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3283         int level, max_level = ilk_wm_max_level(dev);
3284
3285         for (level = 0; level <= max_level; level++) {
3286                 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3287                                      level, intel_num_planes(intel_crtc),
3288                                      &pipe_wm->wm[level]);
3289         }
3290         pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3291
3292         skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3293 }
3294
3295 static void skl_compute_wm_results(struct drm_device *dev,
3296                                    struct skl_pipe_wm_parameters *p,
3297                                    struct skl_pipe_wm *p_wm,
3298                                    struct skl_wm_values *r,
3299                                    struct intel_crtc *intel_crtc)
3300 {
3301         int level, max_level = ilk_wm_max_level(dev);
3302         enum pipe pipe = intel_crtc->pipe;
3303         uint32_t temp;
3304         int i;
3305
3306         for (level = 0; level <= max_level; level++) {
3307                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3308                         temp = 0;
3309
3310                         temp |= p_wm->wm[level].plane_res_l[i] <<
3311                                         PLANE_WM_LINES_SHIFT;
3312                         temp |= p_wm->wm[level].plane_res_b[i];
3313                         if (p_wm->wm[level].plane_en[i])
3314                                 temp |= PLANE_WM_EN;
3315
3316                         r->plane[pipe][i][level] = temp;
3317                 }
3318
3319                 temp = 0;
3320
3321                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3322                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3323
3324                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3325                         temp |= PLANE_WM_EN;
3326
3327                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3328
3329         }
3330
3331         /* transition WMs */
3332         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3333                 temp = 0;
3334                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3335                 temp |= p_wm->trans_wm.plane_res_b[i];
3336                 if (p_wm->trans_wm.plane_en[i])
3337                         temp |= PLANE_WM_EN;
3338
3339                 r->plane_trans[pipe][i] = temp;
3340         }
3341
3342         temp = 0;
3343         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3344         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3345         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3346                 temp |= PLANE_WM_EN;
3347
3348         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3349
3350         r->wm_linetime[pipe] = p_wm->linetime;
3351 }
3352
3353 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3354                                 const struct skl_ddb_entry *entry)
3355 {
3356         if (entry->end)
3357                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3358         else
3359                 I915_WRITE(reg, 0);
3360 }
3361
3362 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3363                                 const struct skl_wm_values *new)
3364 {
3365         struct drm_device *dev = dev_priv->dev;
3366         struct intel_crtc *crtc;
3367
3368         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3369                 int i, level, max_level = ilk_wm_max_level(dev);
3370                 enum pipe pipe = crtc->pipe;
3371
3372                 if (!new->dirty[pipe])
3373                         continue;
3374
3375                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3376
3377                 for (level = 0; level <= max_level; level++) {
3378                         for (i = 0; i < intel_num_planes(crtc); i++)
3379                                 I915_WRITE(PLANE_WM(pipe, i, level),
3380                                            new->plane[pipe][i][level]);
3381                         I915_WRITE(CUR_WM(pipe, level),
3382                                    new->plane[pipe][PLANE_CURSOR][level]);
3383                 }
3384                 for (i = 0; i < intel_num_planes(crtc); i++)
3385                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3386                                    new->plane_trans[pipe][i]);
3387                 I915_WRITE(CUR_WM_TRANS(pipe),
3388                            new->plane_trans[pipe][PLANE_CURSOR]);
3389
3390                 for (i = 0; i < intel_num_planes(crtc); i++) {
3391                         skl_ddb_entry_write(dev_priv,
3392                                             PLANE_BUF_CFG(pipe, i),
3393                                             &new->ddb.plane[pipe][i]);
3394                         skl_ddb_entry_write(dev_priv,
3395                                             PLANE_NV12_BUF_CFG(pipe, i),
3396                                             &new->ddb.y_plane[pipe][i]);
3397                 }
3398
3399                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3400                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3401         }
3402 }
3403
3404 /*
3405  * When setting up a new DDB allocation arrangement, we need to correctly
3406  * sequence the times at which the new allocations for the pipes are taken into
3407  * account or we'll have pipes fetching from space previously allocated to
3408  * another pipe.
3409  *
3410  * Roughly the sequence looks like:
3411  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3412  *     overlapping with a previous light-up pipe (another way to put it is:
3413  *     pipes with their new allocation strickly included into their old ones).
3414  *  2. re-allocate the other pipes that get their allocation reduced
3415  *  3. allocate the pipes having their allocation increased
3416  *
3417  * Steps 1. and 2. are here to take care of the following case:
3418  * - Initially DDB looks like this:
3419  *     |   B    |   C    |
3420  * - enable pipe A.
3421  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3422  *   allocation
3423  *     |  A  |  B  |  C  |
3424  *
3425  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3426  */
3427
3428 static void
3429 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3430 {
3431         int plane;
3432
3433         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3434
3435         for_each_plane(dev_priv, pipe, plane) {
3436                 I915_WRITE(PLANE_SURF(pipe, plane),
3437                            I915_READ(PLANE_SURF(pipe, plane)));
3438         }
3439         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3440 }
3441
3442 static bool
3443 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3444                             const struct skl_ddb_allocation *new,
3445                             enum pipe pipe)
3446 {
3447         uint16_t old_size, new_size;
3448
3449         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3450         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3451
3452         return old_size != new_size &&
3453                new->pipe[pipe].start >= old->pipe[pipe].start &&
3454                new->pipe[pipe].end <= old->pipe[pipe].end;
3455 }
3456
3457 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3458                                 struct skl_wm_values *new_values)
3459 {
3460         struct drm_device *dev = dev_priv->dev;
3461         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3462         bool reallocated[I915_MAX_PIPES] = {};
3463         struct intel_crtc *crtc;
3464         enum pipe pipe;
3465
3466         new_ddb = &new_values->ddb;
3467         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3468
3469         /*
3470          * First pass: flush the pipes with the new allocation contained into
3471          * the old space.
3472          *
3473          * We'll wait for the vblank on those pipes to ensure we can safely
3474          * re-allocate the freed space without this pipe fetching from it.
3475          */
3476         for_each_intel_crtc(dev, crtc) {
3477                 if (!crtc->active)
3478                         continue;
3479
3480                 pipe = crtc->pipe;
3481
3482                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3483                         continue;
3484
3485                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3486                 intel_wait_for_vblank(dev, pipe);
3487
3488                 reallocated[pipe] = true;
3489         }
3490
3491
3492         /*
3493          * Second pass: flush the pipes that are having their allocation
3494          * reduced, but overlapping with a previous allocation.
3495          *
3496          * Here as well we need to wait for the vblank to make sure the freed
3497          * space is not used anymore.
3498          */
3499         for_each_intel_crtc(dev, crtc) {
3500                 if (!crtc->active)
3501                         continue;
3502
3503                 pipe = crtc->pipe;
3504
3505                 if (reallocated[pipe])
3506                         continue;
3507
3508                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3509                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3510                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3511                         intel_wait_for_vblank(dev, pipe);
3512                         reallocated[pipe] = true;
3513                 }
3514         }
3515
3516         /*
3517          * Third pass: flush the pipes that got more space allocated.
3518          *
3519          * We don't need to actively wait for the update here, next vblank
3520          * will just get more DDB space with the correct WM values.
3521          */
3522         for_each_intel_crtc(dev, crtc) {
3523                 if (!crtc->active)
3524                         continue;
3525
3526                 pipe = crtc->pipe;
3527
3528                 /*
3529                  * At this point, only the pipes more space than before are
3530                  * left to re-allocate.
3531                  */
3532                 if (reallocated[pipe])
3533                         continue;
3534
3535                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3536         }
3537 }
3538
3539 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3540                                struct skl_pipe_wm_parameters *params,
3541                                struct intel_wm_config *config,
3542                                struct skl_ddb_allocation *ddb, /* out */
3543                                struct skl_pipe_wm *pipe_wm /* out */)
3544 {
3545         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546
3547         skl_compute_wm_pipe_parameters(crtc, params);
3548         skl_allocate_pipe_ddb(crtc, config, params, ddb);
3549         skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3550
3551         if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3552                 return false;
3553
3554         intel_crtc->wm.skl_active = *pipe_wm;
3555
3556         return true;
3557 }
3558
3559 static void skl_update_other_pipe_wm(struct drm_device *dev,
3560                                      struct drm_crtc *crtc,
3561                                      struct intel_wm_config *config,
3562                                      struct skl_wm_values *r)
3563 {
3564         struct intel_crtc *intel_crtc;
3565         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3566
3567         /*
3568          * If the WM update hasn't changed the allocation for this_crtc (the
3569          * crtc we are currently computing the new WM values for), other
3570          * enabled crtcs will keep the same allocation and we don't need to
3571          * recompute anything for them.
3572          */
3573         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3574                 return;
3575
3576         /*
3577          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3578          * other active pipes need new DDB allocation and WM values.
3579          */
3580         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3581                                 base.head) {
3582                 struct skl_pipe_wm_parameters params = {};
3583                 struct skl_pipe_wm pipe_wm = {};
3584                 bool wm_changed;
3585
3586                 if (this_crtc->pipe == intel_crtc->pipe)
3587                         continue;
3588
3589                 if (!intel_crtc->active)
3590                         continue;
3591
3592                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3593                                                 &params, config,
3594                                                 &r->ddb, &pipe_wm);
3595
3596                 /*
3597                  * If we end up re-computing the other pipe WM values, it's
3598                  * because it was really needed, so we expect the WM values to
3599                  * be different.
3600                  */
3601                 WARN_ON(!wm_changed);
3602
3603                 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3604                 r->dirty[intel_crtc->pipe] = true;
3605         }
3606 }
3607
3608 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3609 {
3610         watermarks->wm_linetime[pipe] = 0;
3611         memset(watermarks->plane[pipe], 0,
3612                sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3613         memset(watermarks->plane_trans[pipe],
3614                0, sizeof(uint32_t) * I915_MAX_PLANES);
3615         watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3616
3617         /* Clear ddb entries for pipe */
3618         memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3619         memset(&watermarks->ddb.plane[pipe], 0,
3620                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3621         memset(&watermarks->ddb.y_plane[pipe], 0,
3622                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3623         memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3624                sizeof(struct skl_ddb_entry));
3625
3626 }
3627
3628 static void skl_update_wm(struct drm_crtc *crtc)
3629 {
3630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631         struct drm_device *dev = crtc->dev;
3632         struct drm_i915_private *dev_priv = dev->dev_private;
3633         struct skl_pipe_wm_parameters params = {};
3634         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3635         struct skl_pipe_wm pipe_wm = {};
3636         struct intel_wm_config config = {};
3637
3638
3639         /* Clear all dirty flags */
3640         memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3641
3642         skl_clear_wm(results, intel_crtc->pipe);
3643
3644         skl_compute_wm_global_parameters(dev, &config);
3645
3646         if (!skl_update_pipe_wm(crtc, &params, &config,
3647                                 &results->ddb, &pipe_wm))
3648                 return;
3649
3650         skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3651         results->dirty[intel_crtc->pipe] = true;
3652
3653         skl_update_other_pipe_wm(dev, crtc, &config, results);
3654         skl_write_wm_values(dev_priv, results);
3655         skl_flush_wm_values(dev_priv, results);
3656
3657         /* store the new configuration */
3658         dev_priv->wm.skl_hw = *results;
3659 }
3660
3661 static void
3662 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3663                      uint32_t sprite_width, uint32_t sprite_height,
3664                      int pixel_size, bool enabled, bool scaled)
3665 {
3666         struct intel_plane *intel_plane = to_intel_plane(plane);
3667         struct drm_framebuffer *fb = plane->state->fb;
3668
3669         intel_plane->wm.enabled = enabled;
3670         intel_plane->wm.scaled = scaled;
3671         intel_plane->wm.horiz_pixels = sprite_width;
3672         intel_plane->wm.vert_pixels = sprite_height;
3673         intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3674
3675         /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3676         intel_plane->wm.bytes_per_pixel =
3677                 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3678                 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3679         intel_plane->wm.y_bytes_per_pixel =
3680                 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3681                 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3682
3683         /*
3684          * Framebuffer can be NULL on plane disable, but it does not
3685          * matter for watermarks if we assume no tiling in that case.
3686          */
3687         if (fb)
3688                 intel_plane->wm.tiling = fb->modifier[0];
3689         intel_plane->wm.rotation = plane->state->rotation;
3690
3691         skl_update_wm(crtc);
3692 }
3693
3694 static void ilk_update_wm(struct drm_crtc *crtc)
3695 {
3696         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3697         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3698         struct drm_device *dev = crtc->dev;
3699         struct drm_i915_private *dev_priv = dev->dev_private;
3700         struct ilk_wm_maximums max;
3701         struct ilk_wm_values results = {};
3702         enum intel_ddb_partitioning partitioning;
3703         struct intel_pipe_wm pipe_wm = {};
3704         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3705         struct intel_wm_config config = {};
3706
3707         WARN_ON(cstate->base.active != intel_crtc->active);
3708
3709         intel_compute_pipe_wm(cstate, &pipe_wm);
3710
3711         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3712                 return;
3713
3714         intel_crtc->wm.active = pipe_wm;
3715
3716         ilk_compute_wm_config(dev, &config);
3717
3718         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3719         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3720
3721         /* 5/6 split only in single pipe config on IVB+ */
3722         if (INTEL_INFO(dev)->gen >= 7 &&
3723             config.num_pipes_active == 1 && config.sprites_enabled) {
3724                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3725                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3726
3727                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3728         } else {
3729                 best_lp_wm = &lp_wm_1_2;
3730         }
3731
3732         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3733                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3734
3735         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3736
3737         ilk_write_wm_values(dev_priv, &results);
3738 }
3739
3740 static void
3741 ilk_update_sprite_wm(struct drm_plane *plane,
3742                      struct drm_crtc *crtc,
3743                      uint32_t sprite_width, uint32_t sprite_height,
3744                      int pixel_size, bool enabled, bool scaled)
3745 {
3746         struct drm_device *dev = plane->dev;
3747         struct intel_plane *intel_plane = to_intel_plane(plane);
3748
3749         /*
3750          * IVB workaround: must disable low power watermarks for at least
3751          * one frame before enabling scaling.  LP watermarks can be re-enabled
3752          * when scaling is disabled.
3753          *
3754          * WaCxSRDisabledForSpriteScaling:ivb
3755          */
3756         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3757                 intel_wait_for_vblank(dev, intel_plane->pipe);
3758
3759         ilk_update_wm(crtc);
3760 }
3761
3762 static void skl_pipe_wm_active_state(uint32_t val,
3763                                      struct skl_pipe_wm *active,
3764                                      bool is_transwm,
3765                                      bool is_cursor,
3766                                      int i,
3767                                      int level)
3768 {
3769         bool is_enabled = (val & PLANE_WM_EN) != 0;
3770
3771         if (!is_transwm) {
3772                 if (!is_cursor) {
3773                         active->wm[level].plane_en[i] = is_enabled;
3774                         active->wm[level].plane_res_b[i] =
3775                                         val & PLANE_WM_BLOCKS_MASK;
3776                         active->wm[level].plane_res_l[i] =
3777                                         (val >> PLANE_WM_LINES_SHIFT) &
3778                                                 PLANE_WM_LINES_MASK;
3779                 } else {
3780                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3781                         active->wm[level].plane_res_b[PLANE_CURSOR] =
3782                                         val & PLANE_WM_BLOCKS_MASK;
3783                         active->wm[level].plane_res_l[PLANE_CURSOR] =
3784                                         (val >> PLANE_WM_LINES_SHIFT) &
3785                                                 PLANE_WM_LINES_MASK;
3786                 }
3787         } else {
3788                 if (!is_cursor) {
3789                         active->trans_wm.plane_en[i] = is_enabled;
3790                         active->trans_wm.plane_res_b[i] =
3791                                         val & PLANE_WM_BLOCKS_MASK;
3792                         active->trans_wm.plane_res_l[i] =
3793                                         (val >> PLANE_WM_LINES_SHIFT) &
3794                                                 PLANE_WM_LINES_MASK;
3795                 } else {
3796                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3797                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
3798                                         val & PLANE_WM_BLOCKS_MASK;
3799                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
3800                                         (val >> PLANE_WM_LINES_SHIFT) &
3801                                                 PLANE_WM_LINES_MASK;
3802                 }
3803         }
3804 }
3805
3806 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3807 {
3808         struct drm_device *dev = crtc->dev;
3809         struct drm_i915_private *dev_priv = dev->dev_private;
3810         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3811         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3812         struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3813         enum pipe pipe = intel_crtc->pipe;
3814         int level, i, max_level;
3815         uint32_t temp;
3816
3817         max_level = ilk_wm_max_level(dev);
3818
3819         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3820
3821         for (level = 0; level <= max_level; level++) {
3822                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3823                         hw->plane[pipe][i][level] =
3824                                         I915_READ(PLANE_WM(pipe, i, level));
3825                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3826         }
3827
3828         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3829                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3830         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3831
3832         if (!intel_crtc->active)
3833                 return;
3834
3835         hw->dirty[pipe] = true;
3836
3837         active->linetime = hw->wm_linetime[pipe];
3838
3839         for (level = 0; level <= max_level; level++) {
3840                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3841                         temp = hw->plane[pipe][i][level];
3842                         skl_pipe_wm_active_state(temp, active, false,
3843                                                 false, i, level);
3844                 }
3845                 temp = hw->plane[pipe][PLANE_CURSOR][level];
3846                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3847         }
3848
3849         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3850                 temp = hw->plane_trans[pipe][i];
3851                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3852         }
3853
3854         temp = hw->plane_trans[pipe][PLANE_CURSOR];
3855         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3856 }
3857
3858 void skl_wm_get_hw_state(struct drm_device *dev)
3859 {
3860         struct drm_i915_private *dev_priv = dev->dev_private;
3861         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3862         struct drm_crtc *crtc;
3863
3864         skl_ddb_get_hw_state(dev_priv, ddb);
3865         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3866                 skl_pipe_wm_get_hw_state(crtc);
3867 }
3868
3869 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3870 {
3871         struct drm_device *dev = crtc->dev;
3872         struct drm_i915_private *dev_priv = dev->dev_private;
3873         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3875         struct intel_pipe_wm *active = &intel_crtc->wm.active;
3876         enum pipe pipe = intel_crtc->pipe;
3877         static const unsigned int wm0_pipe_reg[] = {
3878                 [PIPE_A] = WM0_PIPEA_ILK,
3879                 [PIPE_B] = WM0_PIPEB_ILK,
3880                 [PIPE_C] = WM0_PIPEC_IVB,
3881         };
3882
3883         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3884         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3885                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3886
3887         memset(active, 0, sizeof(*active));
3888
3889         active->pipe_enabled = intel_crtc->active;
3890
3891         if (active->pipe_enabled) {
3892                 u32 tmp = hw->wm_pipe[pipe];
3893
3894                 /*
3895                  * For active pipes LP0 watermark is marked as
3896                  * enabled, and LP1+ watermaks as disabled since
3897                  * we can't really reverse compute them in case
3898                  * multiple pipes are active.
3899                  */
3900                 active->wm[0].enable = true;
3901                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3902                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3903                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3904                 active->linetime = hw->wm_linetime[pipe];
3905         } else {
3906                 int level, max_level = ilk_wm_max_level(dev);
3907
3908                 /*
3909                  * For inactive pipes, all watermark levels
3910                  * should be marked as enabled but zeroed,
3911                  * which is what we'd compute them to.
3912                  */
3913                 for (level = 0; level <= max_level; level++)
3914                         active->wm[level].enable = true;
3915         }
3916 }
3917
3918 #define _FW_WM(value, plane) \
3919         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3920 #define _FW_WM_VLV(value, plane) \
3921         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3922
3923 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3924                                struct vlv_wm_values *wm)
3925 {
3926         enum pipe pipe;
3927         uint32_t tmp;
3928
3929         for_each_pipe(dev_priv, pipe) {
3930                 tmp = I915_READ(VLV_DDL(pipe));
3931
3932                 wm->ddl[pipe].primary =
3933                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3934                 wm->ddl[pipe].cursor =
3935                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3936                 wm->ddl[pipe].sprite[0] =
3937                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3938                 wm->ddl[pipe].sprite[1] =
3939                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3940         }
3941
3942         tmp = I915_READ(DSPFW1);
3943         wm->sr.plane = _FW_WM(tmp, SR);
3944         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3945         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3946         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3947
3948         tmp = I915_READ(DSPFW2);
3949         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3950         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3951         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3952
3953         tmp = I915_READ(DSPFW3);
3954         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3955
3956         if (IS_CHERRYVIEW(dev_priv)) {
3957                 tmp = I915_READ(DSPFW7_CHV);
3958                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3959                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3960
3961                 tmp = I915_READ(DSPFW8_CHV);
3962                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3963                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3964
3965                 tmp = I915_READ(DSPFW9_CHV);
3966                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3967                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3968
3969                 tmp = I915_READ(DSPHOWM);
3970                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3971                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3972                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3973                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3974                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3975                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3976                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3977                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3978                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3979                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3980         } else {
3981                 tmp = I915_READ(DSPFW7);
3982                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3983                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3984
3985                 tmp = I915_READ(DSPHOWM);
3986                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3987                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3988                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3989                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3990                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3991                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3992                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3993         }
3994 }
3995
3996 #undef _FW_WM
3997 #undef _FW_WM_VLV
3998
3999 void vlv_wm_get_hw_state(struct drm_device *dev)
4000 {
4001         struct drm_i915_private *dev_priv = to_i915(dev);
4002         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4003         struct intel_plane *plane;
4004         enum pipe pipe;
4005         u32 val;
4006
4007         vlv_read_wm_values(dev_priv, wm);
4008
4009         for_each_intel_plane(dev, plane) {
4010                 switch (plane->base.type) {
4011                         int sprite;
4012                 case DRM_PLANE_TYPE_CURSOR:
4013                         plane->wm.fifo_size = 63;
4014                         break;
4015                 case DRM_PLANE_TYPE_PRIMARY:
4016                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4017                         break;
4018                 case DRM_PLANE_TYPE_OVERLAY:
4019                         sprite = plane->plane;
4020                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4021                         break;
4022                 }
4023         }
4024
4025         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4026         wm->level = VLV_WM_LEVEL_PM2;
4027
4028         if (IS_CHERRYVIEW(dev_priv)) {
4029                 mutex_lock(&dev_priv->rps.hw_lock);
4030
4031                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4032                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4033                         wm->level = VLV_WM_LEVEL_PM5;
4034
4035                 /*
4036                  * If DDR DVFS is disabled in the BIOS, Punit
4037                  * will never ack the request. So if that happens
4038                  * assume we don't have to enable/disable DDR DVFS
4039                  * dynamically. To test that just set the REQ_ACK
4040                  * bit to poke the Punit, but don't change the
4041                  * HIGH/LOW bits so that we don't actually change
4042                  * the current state.
4043                  */
4044                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4045                 val |= FORCE_DDR_FREQ_REQ_ACK;
4046                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4047
4048                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4049                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4050                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4051                                       "assuming DDR DVFS is disabled\n");
4052                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4053                 } else {
4054                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4055                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4056                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4057                 }
4058
4059                 mutex_unlock(&dev_priv->rps.hw_lock);
4060         }
4061
4062         for_each_pipe(dev_priv, pipe)
4063                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4064                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4065                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4066
4067         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4068                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4069 }
4070
4071 void ilk_wm_get_hw_state(struct drm_device *dev)
4072 {
4073         struct drm_i915_private *dev_priv = dev->dev_private;
4074         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4075         struct drm_crtc *crtc;
4076
4077         for_each_crtc(dev, crtc)
4078                 ilk_pipe_wm_get_hw_state(crtc);
4079
4080         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4081         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4082         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4083
4084         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4085         if (INTEL_INFO(dev)->gen >= 7) {
4086                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4087                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4088         }
4089
4090         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4091                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4092                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4093         else if (IS_IVYBRIDGE(dev))
4094                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4095                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4096
4097         hw->enable_fbc_wm =
4098                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4099 }
4100
4101 /**
4102  * intel_update_watermarks - update FIFO watermark values based on current modes
4103  *
4104  * Calculate watermark values for the various WM regs based on current mode
4105  * and plane configuration.
4106  *
4107  * There are several cases to deal with here:
4108  *   - normal (i.e. non-self-refresh)
4109  *   - self-refresh (SR) mode
4110  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4111  *   - lines are small relative to FIFO size (buffer can hold more than 2
4112  *     lines), so need to account for TLB latency
4113  *
4114  *   The normal calculation is:
4115  *     watermark = dotclock * bytes per pixel * latency
4116  *   where latency is platform & configuration dependent (we assume pessimal
4117  *   values here).
4118  *
4119  *   The SR calculation is:
4120  *     watermark = (trunc(latency/line time)+1) * surface width *
4121  *       bytes per pixel
4122  *   where
4123  *     line time = htotal / dotclock
4124  *     surface width = hdisplay for normal plane and 64 for cursor
4125  *   and latency is assumed to be high, as above.
4126  *
4127  * The final value programmed to the register should always be rounded up,
4128  * and include an extra 2 entries to account for clock crossings.
4129  *
4130  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4131  * to set the non-SR watermarks to 8.
4132  */
4133 void intel_update_watermarks(struct drm_crtc *crtc)
4134 {
4135         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4136
4137         if (dev_priv->display.update_wm)
4138                 dev_priv->display.update_wm(crtc);
4139 }
4140
4141 void intel_update_sprite_watermarks(struct drm_plane *plane,
4142                                     struct drm_crtc *crtc,
4143                                     uint32_t sprite_width,
4144                                     uint32_t sprite_height,
4145                                     int pixel_size,
4146                                     bool enabled, bool scaled)
4147 {
4148         struct drm_i915_private *dev_priv = plane->dev->dev_private;
4149
4150         if (dev_priv->display.update_sprite_wm)
4151                 dev_priv->display.update_sprite_wm(plane, crtc,
4152                                                    sprite_width, sprite_height,
4153                                                    pixel_size, enabled, scaled);
4154 }
4155
4156 /**
4157  * Lock protecting IPS related data structures
4158  */
4159 DEFINE_SPINLOCK(mchdev_lock);
4160
4161 /* Global for IPS driver to get at the current i915 device. Protected by
4162  * mchdev_lock. */
4163 static struct drm_i915_private *i915_mch_dev;
4164
4165 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4166 {
4167         struct drm_i915_private *dev_priv = dev->dev_private;
4168         u16 rgvswctl;
4169
4170         assert_spin_locked(&mchdev_lock);
4171
4172         rgvswctl = I915_READ16(MEMSWCTL);
4173         if (rgvswctl & MEMCTL_CMD_STS) {
4174                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4175                 return false; /* still busy with another command */
4176         }
4177
4178         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4179                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4180         I915_WRITE16(MEMSWCTL, rgvswctl);
4181         POSTING_READ16(MEMSWCTL);
4182
4183         rgvswctl |= MEMCTL_CMD_STS;
4184         I915_WRITE16(MEMSWCTL, rgvswctl);
4185
4186         return true;
4187 }
4188
4189 static void ironlake_enable_drps(struct drm_device *dev)
4190 {
4191         struct drm_i915_private *dev_priv = dev->dev_private;
4192         u32 rgvmodectl = I915_READ(MEMMODECTL);
4193         u8 fmax, fmin, fstart, vstart;
4194
4195         spin_lock_irq(&mchdev_lock);
4196
4197         /* Enable temp reporting */
4198         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4199         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4200
4201         /* 100ms RC evaluation intervals */
4202         I915_WRITE(RCUPEI, 100000);
4203         I915_WRITE(RCDNEI, 100000);
4204
4205         /* Set max/min thresholds to 90ms and 80ms respectively */
4206         I915_WRITE(RCBMAXAVG, 90000);
4207         I915_WRITE(RCBMINAVG, 80000);
4208
4209         I915_WRITE(MEMIHYST, 1);
4210
4211         /* Set up min, max, and cur for interrupt handling */
4212         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4213         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4214         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4215                 MEMMODE_FSTART_SHIFT;
4216
4217         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4218                 PXVFREQ_PX_SHIFT;
4219
4220         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4221         dev_priv->ips.fstart = fstart;
4222
4223         dev_priv->ips.max_delay = fstart;
4224         dev_priv->ips.min_delay = fmin;
4225         dev_priv->ips.cur_delay = fstart;
4226
4227         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4228                          fmax, fmin, fstart);
4229
4230         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4231
4232         /*
4233          * Interrupts will be enabled in ironlake_irq_postinstall
4234          */
4235
4236         I915_WRITE(VIDSTART, vstart);
4237         POSTING_READ(VIDSTART);
4238
4239         rgvmodectl |= MEMMODE_SWMODE_EN;
4240         I915_WRITE(MEMMODECTL, rgvmodectl);
4241
4242         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4243                 DRM_ERROR("stuck trying to change perf mode\n");
4244         mdelay(1);
4245
4246         ironlake_set_drps(dev, fstart);
4247
4248         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4249                 I915_READ(DDREC) + I915_READ(CSIEC);
4250         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4251         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4252         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4253
4254         spin_unlock_irq(&mchdev_lock);
4255 }
4256
4257 static void ironlake_disable_drps(struct drm_device *dev)
4258 {
4259         struct drm_i915_private *dev_priv = dev->dev_private;
4260         u16 rgvswctl;
4261
4262         spin_lock_irq(&mchdev_lock);
4263
4264         rgvswctl = I915_READ16(MEMSWCTL);
4265
4266         /* Ack interrupts, disable EFC interrupt */
4267         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4268         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4269         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4270         I915_WRITE(DEIIR, DE_PCU_EVENT);
4271         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4272
4273         /* Go back to the starting frequency */
4274         ironlake_set_drps(dev, dev_priv->ips.fstart);
4275         mdelay(1);
4276         rgvswctl |= MEMCTL_CMD_STS;
4277         I915_WRITE(MEMSWCTL, rgvswctl);
4278         mdelay(1);
4279
4280         spin_unlock_irq(&mchdev_lock);
4281 }
4282
4283 /* There's a funny hw issue where the hw returns all 0 when reading from
4284  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4285  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4286  * all limits and the gpu stuck at whatever frequency it is at atm).
4287  */
4288 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4289 {
4290         u32 limits;
4291
4292         /* Only set the down limit when we've reached the lowest level to avoid
4293          * getting more interrupts, otherwise leave this clear. This prevents a
4294          * race in the hw when coming out of rc6: There's a tiny window where
4295          * the hw runs at the minimal clock before selecting the desired
4296          * frequency, if the down threshold expires in that window we will not
4297          * receive a down interrupt. */
4298         if (IS_GEN9(dev_priv->dev)) {
4299                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4300                 if (val <= dev_priv->rps.min_freq_softlimit)
4301                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4302         } else {
4303                 limits = dev_priv->rps.max_freq_softlimit << 24;
4304                 if (val <= dev_priv->rps.min_freq_softlimit)
4305                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4306         }
4307
4308         return limits;
4309 }
4310
4311 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4312 {
4313         int new_power;
4314         u32 threshold_up = 0, threshold_down = 0; /* in % */
4315         u32 ei_up = 0, ei_down = 0;
4316
4317         new_power = dev_priv->rps.power;
4318         switch (dev_priv->rps.power) {
4319         case LOW_POWER:
4320                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4321                         new_power = BETWEEN;
4322                 break;
4323
4324         case BETWEEN:
4325                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4326                         new_power = LOW_POWER;
4327                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4328                         new_power = HIGH_POWER;
4329                 break;
4330
4331         case HIGH_POWER:
4332                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4333                         new_power = BETWEEN;
4334                 break;
4335         }
4336         /* Max/min bins are special */
4337         if (val <= dev_priv->rps.min_freq_softlimit)
4338                 new_power = LOW_POWER;
4339         if (val >= dev_priv->rps.max_freq_softlimit)
4340                 new_power = HIGH_POWER;
4341         if (new_power == dev_priv->rps.power)
4342                 return;
4343
4344         /* Note the units here are not exactly 1us, but 1280ns. */
4345         switch (new_power) {
4346         case LOW_POWER:
4347                 /* Upclock if more than 95% busy over 16ms */
4348                 ei_up = 16000;
4349                 threshold_up = 95;
4350
4351                 /* Downclock if less than 85% busy over 32ms */
4352                 ei_down = 32000;
4353                 threshold_down = 85;
4354                 break;
4355
4356         case BETWEEN:
4357                 /* Upclock if more than 90% busy over 13ms */
4358                 ei_up = 13000;
4359                 threshold_up = 90;
4360
4361                 /* Downclock if less than 75% busy over 32ms */
4362                 ei_down = 32000;
4363                 threshold_down = 75;
4364                 break;
4365
4366         case HIGH_POWER:
4367                 /* Upclock if more than 85% busy over 10ms */
4368                 ei_up = 10000;
4369                 threshold_up = 85;
4370
4371                 /* Downclock if less than 60% busy over 32ms */
4372                 ei_down = 32000;
4373                 threshold_down = 60;
4374                 break;
4375         }
4376
4377         I915_WRITE(GEN6_RP_UP_EI,
4378                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4379         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4380                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4381
4382         I915_WRITE(GEN6_RP_DOWN_EI,
4383                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4384         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4385                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4386
4387          I915_WRITE(GEN6_RP_CONTROL,
4388                     GEN6_RP_MEDIA_TURBO |
4389                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4390                     GEN6_RP_MEDIA_IS_GFX |
4391                     GEN6_RP_ENABLE |
4392                     GEN6_RP_UP_BUSY_AVG |
4393                     GEN6_RP_DOWN_IDLE_AVG);
4394
4395         dev_priv->rps.power = new_power;
4396         dev_priv->rps.up_threshold = threshold_up;
4397         dev_priv->rps.down_threshold = threshold_down;
4398         dev_priv->rps.last_adj = 0;
4399 }
4400
4401 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4402 {
4403         u32 mask = 0;
4404
4405         if (val > dev_priv->rps.min_freq_softlimit)
4406                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4407         if (val < dev_priv->rps.max_freq_softlimit)
4408                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4409
4410         mask &= dev_priv->pm_rps_events;
4411
4412         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4413 }
4414
4415 /* gen6_set_rps is called to update the frequency request, but should also be
4416  * called when the range (min_delay and max_delay) is modified so that we can
4417  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4418 static void gen6_set_rps(struct drm_device *dev, u8 val)
4419 {
4420         struct drm_i915_private *dev_priv = dev->dev_private;
4421
4422         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4423         if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
4424                 return;
4425
4426         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4427         WARN_ON(val > dev_priv->rps.max_freq);
4428         WARN_ON(val < dev_priv->rps.min_freq);
4429
4430         /* min/max delay may still have been modified so be sure to
4431          * write the limits value.
4432          */
4433         if (val != dev_priv->rps.cur_freq) {
4434                 gen6_set_rps_thresholds(dev_priv, val);
4435
4436                 if (IS_GEN9(dev))
4437                         I915_WRITE(GEN6_RPNSWREQ,
4438                                    GEN9_FREQUENCY(val));
4439                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4440                         I915_WRITE(GEN6_RPNSWREQ,
4441                                    HSW_FREQUENCY(val));
4442                 else
4443                         I915_WRITE(GEN6_RPNSWREQ,
4444                                    GEN6_FREQUENCY(val) |
4445                                    GEN6_OFFSET(0) |
4446                                    GEN6_AGGRESSIVE_TURBO);
4447         }
4448
4449         /* Make sure we continue to get interrupts
4450          * until we hit the minimum or maximum frequencies.
4451          */
4452         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4453         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4454
4455         POSTING_READ(GEN6_RPNSWREQ);
4456
4457         dev_priv->rps.cur_freq = val;
4458         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4459 }
4460
4461 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4462 {
4463         struct drm_i915_private *dev_priv = dev->dev_private;
4464
4465         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4466         WARN_ON(val > dev_priv->rps.max_freq);
4467         WARN_ON(val < dev_priv->rps.min_freq);
4468
4469         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4470                       "Odd GPU freq value\n"))
4471                 val &= ~1;
4472
4473         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4474
4475         if (val != dev_priv->rps.cur_freq) {
4476                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4477                 if (!IS_CHERRYVIEW(dev_priv))
4478                         gen6_set_rps_thresholds(dev_priv, val);
4479         }
4480
4481         dev_priv->rps.cur_freq = val;
4482         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4483 }
4484
4485 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4486  *
4487  * * If Gfx is Idle, then
4488  * 1. Forcewake Media well.
4489  * 2. Request idle freq.
4490  * 3. Release Forcewake of Media well.
4491 */
4492 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4493 {
4494         u32 val = dev_priv->rps.idle_freq;
4495
4496         if (dev_priv->rps.cur_freq <= val)
4497                 return;
4498
4499         /* Wake up the media well, as that takes a lot less
4500          * power than the Render well. */
4501         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4502         valleyview_set_rps(dev_priv->dev, val);
4503         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4504 }
4505
4506 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4507 {
4508         mutex_lock(&dev_priv->rps.hw_lock);
4509         if (dev_priv->rps.enabled) {
4510                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4511                         gen6_rps_reset_ei(dev_priv);
4512                 I915_WRITE(GEN6_PMINTRMSK,
4513                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4514         }
4515         mutex_unlock(&dev_priv->rps.hw_lock);
4516 }
4517
4518 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4519 {
4520         struct drm_device *dev = dev_priv->dev;
4521
4522         mutex_lock(&dev_priv->rps.hw_lock);
4523         if (dev_priv->rps.enabled) {
4524                 if (IS_VALLEYVIEW(dev))
4525                         vlv_set_rps_idle(dev_priv);
4526                 else
4527                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4528                 dev_priv->rps.last_adj = 0;
4529                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4530         }
4531         mutex_unlock(&dev_priv->rps.hw_lock);
4532
4533         spin_lock(&dev_priv->rps.client_lock);
4534         while (!list_empty(&dev_priv->rps.clients))
4535                 list_del_init(dev_priv->rps.clients.next);
4536         spin_unlock(&dev_priv->rps.client_lock);
4537 }
4538
4539 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4540                     struct intel_rps_client *rps,
4541                     unsigned long submitted)
4542 {
4543         /* This is intentionally racy! We peek at the state here, then
4544          * validate inside the RPS worker.
4545          */
4546         if (!(dev_priv->mm.busy &&
4547               dev_priv->rps.enabled &&
4548               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4549                 return;
4550
4551         /* Force a RPS boost (and don't count it against the client) if
4552          * the GPU is severely congested.
4553          */
4554         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4555                 rps = NULL;
4556
4557         spin_lock(&dev_priv->rps.client_lock);
4558         if (rps == NULL || list_empty(&rps->link)) {
4559                 spin_lock_irq(&dev_priv->irq_lock);
4560                 if (dev_priv->rps.interrupts_enabled) {
4561                         dev_priv->rps.client_boost = true;
4562                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4563                 }
4564                 spin_unlock_irq(&dev_priv->irq_lock);
4565
4566                 if (rps != NULL) {
4567                         list_add(&rps->link, &dev_priv->rps.clients);
4568                         rps->boosts++;
4569                 } else
4570                         dev_priv->rps.boosts++;
4571         }
4572         spin_unlock(&dev_priv->rps.client_lock);
4573 }
4574
4575 void intel_set_rps(struct drm_device *dev, u8 val)
4576 {
4577         if (IS_VALLEYVIEW(dev))
4578                 valleyview_set_rps(dev, val);
4579         else
4580                 gen6_set_rps(dev, val);
4581 }
4582
4583 static void gen9_disable_rps(struct drm_device *dev)
4584 {
4585         struct drm_i915_private *dev_priv = dev->dev_private;
4586
4587         I915_WRITE(GEN6_RC_CONTROL, 0);
4588         I915_WRITE(GEN9_PG_ENABLE, 0);
4589 }
4590
4591 static void gen6_disable_rps(struct drm_device *dev)
4592 {
4593         struct drm_i915_private *dev_priv = dev->dev_private;
4594
4595         I915_WRITE(GEN6_RC_CONTROL, 0);
4596         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4597 }
4598
4599 static void cherryview_disable_rps(struct drm_device *dev)
4600 {
4601         struct drm_i915_private *dev_priv = dev->dev_private;
4602
4603         I915_WRITE(GEN6_RC_CONTROL, 0);
4604 }
4605
4606 static void valleyview_disable_rps(struct drm_device *dev)
4607 {
4608         struct drm_i915_private *dev_priv = dev->dev_private;
4609
4610         /* we're doing forcewake before Disabling RC6,
4611          * This what the BIOS expects when going into suspend */
4612         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4613
4614         I915_WRITE(GEN6_RC_CONTROL, 0);
4615
4616         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4617 }
4618
4619 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4620 {
4621         if (IS_VALLEYVIEW(dev)) {
4622                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4623                         mode = GEN6_RC_CTL_RC6_ENABLE;
4624                 else
4625                         mode = 0;
4626         }
4627         if (HAS_RC6p(dev))
4628                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4629                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4630                               (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4631                               (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4632
4633         else
4634                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4635                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4636 }
4637
4638 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4639 {
4640         /* No RC6 before Ironlake and code is gone for ilk. */
4641         if (INTEL_INFO(dev)->gen < 6)
4642                 return 0;
4643
4644         /* Respect the kernel parameter if it is set */
4645         if (enable_rc6 >= 0) {
4646                 int mask;
4647
4648                 if (HAS_RC6p(dev))
4649                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4650                                INTEL_RC6pp_ENABLE;
4651                 else
4652                         mask = INTEL_RC6_ENABLE;
4653
4654                 if ((enable_rc6 & mask) != enable_rc6)
4655                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4656                                       enable_rc6 & mask, enable_rc6, mask);
4657
4658                 return enable_rc6 & mask;
4659         }
4660
4661         if (IS_IVYBRIDGE(dev))
4662                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4663
4664         return INTEL_RC6_ENABLE;
4665 }
4666
4667 int intel_enable_rc6(const struct drm_device *dev)
4668 {
4669         return i915.enable_rc6;
4670 }
4671
4672 static void gen6_init_rps_frequencies(struct drm_device *dev)
4673 {
4674         struct drm_i915_private *dev_priv = dev->dev_private;
4675         uint32_t rp_state_cap;
4676         u32 ddcc_status = 0;
4677         int ret;
4678
4679         /* All of these values are in units of 50MHz */
4680         dev_priv->rps.cur_freq          = 0;
4681         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4682         if (IS_BROXTON(dev)) {
4683                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4684                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4685                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4686                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4687         } else {
4688                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4689                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4690                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4691                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4692         }
4693
4694         /* hw_max = RP0 until we check for overclocking */
4695         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4696
4697         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4698         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
4699                 ret = sandybridge_pcode_read(dev_priv,
4700                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4701                                         &ddcc_status);
4702                 if (0 == ret)
4703                         dev_priv->rps.efficient_freq =
4704                                 clamp_t(u8,
4705                                         ((ddcc_status >> 8) & 0xff),
4706                                         dev_priv->rps.min_freq,
4707                                         dev_priv->rps.max_freq);
4708         }
4709
4710         if (IS_SKYLAKE(dev)) {
4711                 /* Store the frequency values in 16.66 MHZ units, which is
4712                    the natural hardware unit for SKL */
4713                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4714                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4715                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4716                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4717                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4718         }
4719
4720         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4721
4722         /* Preserve min/max settings in case of re-init */
4723         if (dev_priv->rps.max_freq_softlimit == 0)
4724                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4725
4726         if (dev_priv->rps.min_freq_softlimit == 0) {
4727                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4728                         dev_priv->rps.min_freq_softlimit =
4729                                 max_t(int, dev_priv->rps.efficient_freq,
4730                                       intel_freq_opcode(dev_priv, 450));
4731                 else
4732                         dev_priv->rps.min_freq_softlimit =
4733                                 dev_priv->rps.min_freq;
4734         }
4735 }
4736
4737 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4738 static void gen9_enable_rps(struct drm_device *dev)
4739 {
4740         struct drm_i915_private *dev_priv = dev->dev_private;
4741
4742         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4743
4744         gen6_init_rps_frequencies(dev);
4745
4746         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4747         if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
4748                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4749                 return;
4750         }
4751
4752         /* Program defaults and thresholds for RPS*/
4753         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4754                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4755
4756         /* 1 second timeout*/
4757         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4758                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4759
4760         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4761
4762         /* Leaning on the below call to gen6_set_rps to program/setup the
4763          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4764          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4765         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4766         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4767
4768         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4769 }
4770
4771 static void gen9_enable_rc6(struct drm_device *dev)
4772 {
4773         struct drm_i915_private *dev_priv = dev->dev_private;
4774         struct intel_engine_cs *ring;
4775         uint32_t rc6_mask = 0;
4776         int unused;
4777
4778         /* 1a: Software RC state - RC0 */
4779         I915_WRITE(GEN6_RC_STATE, 0);
4780
4781         /* 1b: Get forcewake during program sequence. Although the driver
4782          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4783         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4784
4785         /* 2a: Disable RC states. */
4786         I915_WRITE(GEN6_RC_CONTROL, 0);
4787
4788         /* 2b: Program RC6 thresholds.*/
4789
4790         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4791         if (IS_SKYLAKE(dev))
4792                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4793         else
4794                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4795         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4796         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4797         for_each_ring(ring, dev_priv, unused)
4798                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4799
4800         if (HAS_GUC_UCODE(dev))
4801                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4802
4803         I915_WRITE(GEN6_RC_SLEEP, 0);
4804
4805         /* 2c: Program Coarse Power Gating Policies. */
4806         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4807         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4808
4809         /* 3a: Enable RC6 */
4810         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4811                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4812         DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4813                         "on" : "off");
4814         /* WaRsUseTimeoutMode */
4815         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
4816             (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) {
4817                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4818                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4819                            GEN7_RC_CTL_TO_MODE |
4820                            rc6_mask);
4821         } else {
4822                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4823                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4824                            GEN6_RC_CTL_EI_MODE(1) |
4825                            rc6_mask);
4826         }
4827
4828         /*
4829          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4830          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4831          */
4832         if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4833             ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_F0)))
4834                 I915_WRITE(GEN9_PG_ENABLE, 0);
4835         else
4836                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4837                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4838
4839         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4840
4841 }
4842
4843 static void gen8_enable_rps(struct drm_device *dev)
4844 {
4845         struct drm_i915_private *dev_priv = dev->dev_private;
4846         struct intel_engine_cs *ring;
4847         uint32_t rc6_mask = 0;
4848         int unused;
4849
4850         /* 1a: Software RC state - RC0 */
4851         I915_WRITE(GEN6_RC_STATE, 0);
4852
4853         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4854          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4855         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4856
4857         /* 2a: Disable RC states. */
4858         I915_WRITE(GEN6_RC_CONTROL, 0);
4859
4860         /* Initialize rps frequencies */
4861         gen6_init_rps_frequencies(dev);
4862
4863         /* 2b: Program RC6 thresholds.*/
4864         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4865         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4866         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4867         for_each_ring(ring, dev_priv, unused)
4868                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4869         I915_WRITE(GEN6_RC_SLEEP, 0);
4870         if (IS_BROADWELL(dev))
4871                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4872         else
4873                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4874
4875         /* 3: Enable RC6 */
4876         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4877                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4878         intel_print_rc6_info(dev, rc6_mask);
4879         if (IS_BROADWELL(dev))
4880                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4881                                 GEN7_RC_CTL_TO_MODE |
4882                                 rc6_mask);
4883         else
4884                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4885                                 GEN6_RC_CTL_EI_MODE(1) |
4886                                 rc6_mask);
4887
4888         /* 4 Program defaults and thresholds for RPS*/
4889         I915_WRITE(GEN6_RPNSWREQ,
4890                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4891         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4892                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4893         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4894         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4895
4896         /* Docs recommend 900MHz, and 300 MHz respectively */
4897         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4898                    dev_priv->rps.max_freq_softlimit << 24 |
4899                    dev_priv->rps.min_freq_softlimit << 16);
4900
4901         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4902         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4903         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4904         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4905
4906         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4907
4908         /* 5: Enable RPS */
4909         I915_WRITE(GEN6_RP_CONTROL,
4910                    GEN6_RP_MEDIA_TURBO |
4911                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4912                    GEN6_RP_MEDIA_IS_GFX |
4913                    GEN6_RP_ENABLE |
4914                    GEN6_RP_UP_BUSY_AVG |
4915                    GEN6_RP_DOWN_IDLE_AVG);
4916
4917         /* 6: Ring frequency + overclocking (our driver does this later */
4918
4919         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4920         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4921
4922         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4923 }
4924
4925 static void gen6_enable_rps(struct drm_device *dev)
4926 {
4927         struct drm_i915_private *dev_priv = dev->dev_private;
4928         struct intel_engine_cs *ring;
4929         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4930         u32 gtfifodbg;
4931         int rc6_mode;
4932         int i, ret;
4933
4934         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4935
4936         /* Here begins a magic sequence of register writes to enable
4937          * auto-downclocking.
4938          *
4939          * Perhaps there might be some value in exposing these to
4940          * userspace...
4941          */
4942         I915_WRITE(GEN6_RC_STATE, 0);
4943
4944         /* Clear the DBG now so we don't confuse earlier errors */
4945         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4946                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4947                 I915_WRITE(GTFIFODBG, gtfifodbg);
4948         }
4949
4950         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4951
4952         /* Initialize rps frequencies */
4953         gen6_init_rps_frequencies(dev);
4954
4955         /* disable the counters and set deterministic thresholds */
4956         I915_WRITE(GEN6_RC_CONTROL, 0);
4957
4958         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4959         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4960         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4961         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4962         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4963
4964         for_each_ring(ring, dev_priv, i)
4965                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4966
4967         I915_WRITE(GEN6_RC_SLEEP, 0);
4968         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4969         if (IS_IVYBRIDGE(dev))
4970                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4971         else
4972                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4973         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4974         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4975
4976         /* Check if we are enabling RC6 */
4977         rc6_mode = intel_enable_rc6(dev_priv->dev);
4978         if (rc6_mode & INTEL_RC6_ENABLE)
4979                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4980
4981         /* We don't use those on Haswell */
4982         if (!IS_HASWELL(dev)) {
4983                 if (rc6_mode & INTEL_RC6p_ENABLE)
4984                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4985
4986                 if (rc6_mode & INTEL_RC6pp_ENABLE)
4987                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4988         }
4989
4990         intel_print_rc6_info(dev, rc6_mask);
4991
4992         I915_WRITE(GEN6_RC_CONTROL,
4993                    rc6_mask |
4994                    GEN6_RC_CTL_EI_MODE(1) |
4995                    GEN6_RC_CTL_HW_ENABLE);
4996
4997         /* Power down if completely idle for over 50ms */
4998         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4999         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5000
5001         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5002         if (ret)
5003                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5004
5005         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5006         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5007                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5008                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5009                                  (pcu_mbox & 0xff) * 50);
5010                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5011         }
5012
5013         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5014         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5015
5016         rc6vids = 0;
5017         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5018         if (IS_GEN6(dev) && ret) {
5019                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5020         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5021                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5022                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5023                 rc6vids &= 0xffff00;
5024                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5025                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5026                 if (ret)
5027                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5028         }
5029
5030         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5031 }
5032
5033 static void __gen6_update_ring_freq(struct drm_device *dev)
5034 {
5035         struct drm_i915_private *dev_priv = dev->dev_private;
5036         int min_freq = 15;
5037         unsigned int gpu_freq;
5038         unsigned int max_ia_freq, min_ring_freq;
5039         unsigned int max_gpu_freq, min_gpu_freq;
5040         int scaling_factor = 180;
5041         struct cpufreq_policy *policy;
5042
5043         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5044
5045         policy = cpufreq_cpu_get(0);
5046         if (policy) {
5047                 max_ia_freq = policy->cpuinfo.max_freq;
5048                 cpufreq_cpu_put(policy);
5049         } else {
5050                 /*
5051                  * Default to measured freq if none found, PCU will ensure we
5052                  * don't go over
5053                  */
5054                 max_ia_freq = tsc_khz;
5055         }
5056
5057         /* Convert from kHz to MHz */
5058         max_ia_freq /= 1000;
5059
5060         min_ring_freq = I915_READ(DCLK) & 0xf;
5061         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5062         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5063
5064         if (IS_SKYLAKE(dev)) {
5065                 /* Convert GT frequency to 50 HZ units */
5066                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5067                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5068         } else {
5069                 min_gpu_freq = dev_priv->rps.min_freq;
5070                 max_gpu_freq = dev_priv->rps.max_freq;
5071         }
5072
5073         /*
5074          * For each potential GPU frequency, load a ring frequency we'd like
5075          * to use for memory access.  We do this by specifying the IA frequency
5076          * the PCU should use as a reference to determine the ring frequency.
5077          */
5078         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5079                 int diff = max_gpu_freq - gpu_freq;
5080                 unsigned int ia_freq = 0, ring_freq = 0;
5081
5082                 if (IS_SKYLAKE(dev)) {
5083                         /*
5084                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5085                          * No floor required for ring frequency on SKL.
5086                          */
5087                         ring_freq = gpu_freq;
5088                 } else if (INTEL_INFO(dev)->gen >= 8) {
5089                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5090                         ring_freq = max(min_ring_freq, gpu_freq);
5091                 } else if (IS_HASWELL(dev)) {
5092                         ring_freq = mult_frac(gpu_freq, 5, 4);
5093                         ring_freq = max(min_ring_freq, ring_freq);
5094                         /* leave ia_freq as the default, chosen by cpufreq */
5095                 } else {
5096                         /* On older processors, there is no separate ring
5097                          * clock domain, so in order to boost the bandwidth
5098                          * of the ring, we need to upclock the CPU (ia_freq).
5099                          *
5100                          * For GPU frequencies less than 750MHz,
5101                          * just use the lowest ring freq.
5102                          */
5103                         if (gpu_freq < min_freq)
5104                                 ia_freq = 800;
5105                         else
5106                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5107                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5108                 }
5109
5110                 sandybridge_pcode_write(dev_priv,
5111                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5112                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5113                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5114                                         gpu_freq);
5115         }
5116 }
5117
5118 void gen6_update_ring_freq(struct drm_device *dev)
5119 {
5120         struct drm_i915_private *dev_priv = dev->dev_private;
5121
5122         if (!HAS_CORE_RING_FREQ(dev))
5123                 return;
5124
5125         mutex_lock(&dev_priv->rps.hw_lock);
5126         __gen6_update_ring_freq(dev);
5127         mutex_unlock(&dev_priv->rps.hw_lock);
5128 }
5129
5130 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5131 {
5132         struct drm_device *dev = dev_priv->dev;
5133         u32 val, rp0;
5134
5135         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5136
5137         switch (INTEL_INFO(dev)->eu_total) {
5138         case 8:
5139                 /* (2 * 4) config */
5140                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5141                 break;
5142         case 12:
5143                 /* (2 * 6) config */
5144                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5145                 break;
5146         case 16:
5147                 /* (2 * 8) config */
5148         default:
5149                 /* Setting (2 * 8) Min RP0 for any other combination */
5150                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5151                 break;
5152         }
5153
5154         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5155
5156         return rp0;
5157 }
5158
5159 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5160 {
5161         u32 val, rpe;
5162
5163         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5164         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5165
5166         return rpe;
5167 }
5168
5169 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5170 {
5171         u32 val, rp1;
5172
5173         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5174         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5175
5176         return rp1;
5177 }
5178
5179 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5180 {
5181         u32 val, rp1;
5182
5183         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5184
5185         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5186
5187         return rp1;
5188 }
5189
5190 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5191 {
5192         u32 val, rp0;
5193
5194         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5195
5196         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5197         /* Clamp to max */
5198         rp0 = min_t(u32, rp0, 0xea);
5199
5200         return rp0;
5201 }
5202
5203 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5204 {
5205         u32 val, rpe;
5206
5207         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5208         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5209         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5210         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5211
5212         return rpe;
5213 }
5214
5215 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5216 {
5217         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5218 }
5219
5220 /* Check that the pctx buffer wasn't move under us. */
5221 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5222 {
5223         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5224
5225         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5226                              dev_priv->vlv_pctx->stolen->start);
5227 }
5228
5229
5230 /* Check that the pcbr address is not empty. */
5231 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5232 {
5233         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5234
5235         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5236 }
5237
5238 static void cherryview_setup_pctx(struct drm_device *dev)
5239 {
5240         struct drm_i915_private *dev_priv = dev->dev_private;
5241         unsigned long pctx_paddr, paddr;
5242         struct i915_gtt *gtt = &dev_priv->gtt;
5243         u32 pcbr;
5244         int pctx_size = 32*1024;
5245
5246         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5247
5248         pcbr = I915_READ(VLV_PCBR);
5249         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5250                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5251                 paddr = (dev_priv->mm.stolen_base +
5252                          (gtt->stolen_size - pctx_size));
5253
5254                 pctx_paddr = (paddr & (~4095));
5255                 I915_WRITE(VLV_PCBR, pctx_paddr);
5256         }
5257
5258         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5259 }
5260
5261 static void valleyview_setup_pctx(struct drm_device *dev)
5262 {
5263         struct drm_i915_private *dev_priv = dev->dev_private;
5264         struct drm_i915_gem_object *pctx;
5265         unsigned long pctx_paddr;
5266         u32 pcbr;
5267         int pctx_size = 24*1024;
5268
5269         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5270
5271         pcbr = I915_READ(VLV_PCBR);
5272         if (pcbr) {
5273                 /* BIOS set it up already, grab the pre-alloc'd space */
5274                 int pcbr_offset;
5275
5276                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5277                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5278                                                                       pcbr_offset,
5279                                                                       I915_GTT_OFFSET_NONE,
5280                                                                       pctx_size);
5281                 goto out;
5282         }
5283
5284         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5285
5286         /*
5287          * From the Gunit register HAS:
5288          * The Gfx driver is expected to program this register and ensure
5289          * proper allocation within Gfx stolen memory.  For example, this
5290          * register should be programmed such than the PCBR range does not
5291          * overlap with other ranges, such as the frame buffer, protected
5292          * memory, or any other relevant ranges.
5293          */
5294         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5295         if (!pctx) {
5296                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5297                 return;
5298         }
5299
5300         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5301         I915_WRITE(VLV_PCBR, pctx_paddr);
5302
5303 out:
5304         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5305         dev_priv->vlv_pctx = pctx;
5306 }
5307
5308 static void valleyview_cleanup_pctx(struct drm_device *dev)
5309 {
5310         struct drm_i915_private *dev_priv = dev->dev_private;
5311
5312         if (WARN_ON(!dev_priv->vlv_pctx))
5313                 return;
5314
5315         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5316         dev_priv->vlv_pctx = NULL;
5317 }
5318
5319 static void valleyview_init_gt_powersave(struct drm_device *dev)
5320 {
5321         struct drm_i915_private *dev_priv = dev->dev_private;
5322         u32 val;
5323
5324         valleyview_setup_pctx(dev);
5325
5326         mutex_lock(&dev_priv->rps.hw_lock);
5327
5328         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5329         switch ((val >> 6) & 3) {
5330         case 0:
5331         case 1:
5332                 dev_priv->mem_freq = 800;
5333                 break;
5334         case 2:
5335                 dev_priv->mem_freq = 1066;
5336                 break;
5337         case 3:
5338                 dev_priv->mem_freq = 1333;
5339                 break;
5340         }
5341         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5342
5343         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5344         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5345         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5346                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5347                          dev_priv->rps.max_freq);
5348
5349         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5350         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5351                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5352                          dev_priv->rps.efficient_freq);
5353
5354         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5355         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5356                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5357                          dev_priv->rps.rp1_freq);
5358
5359         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5360         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5361                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5362                          dev_priv->rps.min_freq);
5363
5364         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5365
5366         /* Preserve min/max settings in case of re-init */
5367         if (dev_priv->rps.max_freq_softlimit == 0)
5368                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5369
5370         if (dev_priv->rps.min_freq_softlimit == 0)
5371                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5372
5373         mutex_unlock(&dev_priv->rps.hw_lock);
5374 }
5375
5376 static void cherryview_init_gt_powersave(struct drm_device *dev)
5377 {
5378         struct drm_i915_private *dev_priv = dev->dev_private;
5379         u32 val;
5380
5381         cherryview_setup_pctx(dev);
5382
5383         mutex_lock(&dev_priv->rps.hw_lock);
5384
5385         mutex_lock(&dev_priv->sb_lock);
5386         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5387         mutex_unlock(&dev_priv->sb_lock);
5388
5389         switch ((val >> 2) & 0x7) {
5390         case 3:
5391                 dev_priv->mem_freq = 2000;
5392                 break;
5393         default:
5394                 dev_priv->mem_freq = 1600;
5395                 break;
5396         }
5397         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5398
5399         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5400         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5401         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5402                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5403                          dev_priv->rps.max_freq);
5404
5405         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5406         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5407                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5408                          dev_priv->rps.efficient_freq);
5409
5410         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5411         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5412                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5413                          dev_priv->rps.rp1_freq);
5414
5415         /* PUnit validated range is only [RPe, RP0] */
5416         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5417         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5418                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5419                          dev_priv->rps.min_freq);
5420
5421         WARN_ONCE((dev_priv->rps.max_freq |
5422                    dev_priv->rps.efficient_freq |
5423                    dev_priv->rps.rp1_freq |
5424                    dev_priv->rps.min_freq) & 1,
5425                   "Odd GPU freq values\n");
5426
5427         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5428
5429         /* Preserve min/max settings in case of re-init */
5430         if (dev_priv->rps.max_freq_softlimit == 0)
5431                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5432
5433         if (dev_priv->rps.min_freq_softlimit == 0)
5434                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5435
5436         mutex_unlock(&dev_priv->rps.hw_lock);
5437 }
5438
5439 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5440 {
5441         valleyview_cleanup_pctx(dev);
5442 }
5443
5444 static void cherryview_enable_rps(struct drm_device *dev)
5445 {
5446         struct drm_i915_private *dev_priv = dev->dev_private;
5447         struct intel_engine_cs *ring;
5448         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5449         int i;
5450
5451         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5452
5453         gtfifodbg = I915_READ(GTFIFODBG);
5454         if (gtfifodbg) {
5455                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5456                                  gtfifodbg);
5457                 I915_WRITE(GTFIFODBG, gtfifodbg);
5458         }
5459
5460         cherryview_check_pctx(dev_priv);
5461
5462         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5463          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5464         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5465
5466         /*  Disable RC states. */
5467         I915_WRITE(GEN6_RC_CONTROL, 0);
5468
5469         /* 2a: Program RC6 thresholds.*/
5470         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5471         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5472         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5473
5474         for_each_ring(ring, dev_priv, i)
5475                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5476         I915_WRITE(GEN6_RC_SLEEP, 0);
5477
5478         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5479         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5480
5481         /* allows RC6 residency counter to work */
5482         I915_WRITE(VLV_COUNTER_CONTROL,
5483                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5484                                       VLV_MEDIA_RC6_COUNT_EN |
5485                                       VLV_RENDER_RC6_COUNT_EN));
5486
5487         /* For now we assume BIOS is allocating and populating the PCBR  */
5488         pcbr = I915_READ(VLV_PCBR);
5489
5490         /* 3: Enable RC6 */
5491         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5492                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5493                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5494
5495         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5496
5497         /* 4 Program defaults and thresholds for RPS*/
5498         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5499         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5500         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5501         I915_WRITE(GEN6_RP_UP_EI, 66000);
5502         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5503
5504         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5505
5506         /* 5: Enable RPS */
5507         I915_WRITE(GEN6_RP_CONTROL,
5508                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5509                    GEN6_RP_MEDIA_IS_GFX |
5510                    GEN6_RP_ENABLE |
5511                    GEN6_RP_UP_BUSY_AVG |
5512                    GEN6_RP_DOWN_IDLE_AVG);
5513
5514         /* Setting Fixed Bias */
5515         val = VLV_OVERRIDE_EN |
5516                   VLV_SOC_TDP_EN |
5517                   CHV_BIAS_CPU_50_SOC_50;
5518         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5519
5520         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5521
5522         /* RPS code assumes GPLL is used */
5523         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5524
5525         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5526         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5527
5528         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5529         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5530                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5531                          dev_priv->rps.cur_freq);
5532
5533         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5534                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5535                          dev_priv->rps.efficient_freq);
5536
5537         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5538
5539         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5540 }
5541
5542 static void valleyview_enable_rps(struct drm_device *dev)
5543 {
5544         struct drm_i915_private *dev_priv = dev->dev_private;
5545         struct intel_engine_cs *ring;
5546         u32 gtfifodbg, val, rc6_mode = 0;
5547         int i;
5548
5549         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5550
5551         valleyview_check_pctx(dev_priv);
5552
5553         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5554                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5555                                  gtfifodbg);
5556                 I915_WRITE(GTFIFODBG, gtfifodbg);
5557         }
5558
5559         /* If VLV, Forcewake all wells, else re-direct to regular path */
5560         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5561
5562         /*  Disable RC states. */
5563         I915_WRITE(GEN6_RC_CONTROL, 0);
5564
5565         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5566         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5567         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5568         I915_WRITE(GEN6_RP_UP_EI, 66000);
5569         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5570
5571         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5572
5573         I915_WRITE(GEN6_RP_CONTROL,
5574                    GEN6_RP_MEDIA_TURBO |
5575                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5576                    GEN6_RP_MEDIA_IS_GFX |
5577                    GEN6_RP_ENABLE |
5578                    GEN6_RP_UP_BUSY_AVG |
5579                    GEN6_RP_DOWN_IDLE_CONT);
5580
5581         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5582         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5583         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5584
5585         for_each_ring(ring, dev_priv, i)
5586                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5587
5588         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5589
5590         /* allows RC6 residency counter to work */
5591         I915_WRITE(VLV_COUNTER_CONTROL,
5592                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5593                                       VLV_RENDER_RC0_COUNT_EN |
5594                                       VLV_MEDIA_RC6_COUNT_EN |
5595                                       VLV_RENDER_RC6_COUNT_EN));
5596
5597         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5598                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5599
5600         intel_print_rc6_info(dev, rc6_mode);
5601
5602         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5603
5604         /* Setting Fixed Bias */
5605         val = VLV_OVERRIDE_EN |
5606                   VLV_SOC_TDP_EN |
5607                   VLV_BIAS_CPU_125_SOC_875;
5608         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5609
5610         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5611
5612         /* RPS code assumes GPLL is used */
5613         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5614
5615         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5616         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5617
5618         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5619         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5620                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5621                          dev_priv->rps.cur_freq);
5622
5623         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5624                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5625                          dev_priv->rps.efficient_freq);
5626
5627         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5628
5629         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5630 }
5631
5632 static unsigned long intel_pxfreq(u32 vidfreq)
5633 {
5634         unsigned long freq;
5635         int div = (vidfreq & 0x3f0000) >> 16;
5636         int post = (vidfreq & 0x3000) >> 12;
5637         int pre = (vidfreq & 0x7);
5638
5639         if (!pre)
5640                 return 0;
5641
5642         freq = ((div * 133333) / ((1<<post) * pre));
5643
5644         return freq;
5645 }
5646
5647 static const struct cparams {
5648         u16 i;
5649         u16 t;
5650         u16 m;
5651         u16 c;
5652 } cparams[] = {
5653         { 1, 1333, 301, 28664 },
5654         { 1, 1066, 294, 24460 },
5655         { 1, 800, 294, 25192 },
5656         { 0, 1333, 276, 27605 },
5657         { 0, 1066, 276, 27605 },
5658         { 0, 800, 231, 23784 },
5659 };
5660
5661 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5662 {
5663         u64 total_count, diff, ret;
5664         u32 count1, count2, count3, m = 0, c = 0;
5665         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5666         int i;
5667
5668         assert_spin_locked(&mchdev_lock);
5669
5670         diff1 = now - dev_priv->ips.last_time1;
5671
5672         /* Prevent division-by-zero if we are asking too fast.
5673          * Also, we don't get interesting results if we are polling
5674          * faster than once in 10ms, so just return the saved value
5675          * in such cases.
5676          */
5677         if (diff1 <= 10)
5678                 return dev_priv->ips.chipset_power;
5679
5680         count1 = I915_READ(DMIEC);
5681         count2 = I915_READ(DDREC);
5682         count3 = I915_READ(CSIEC);
5683
5684         total_count = count1 + count2 + count3;
5685
5686         /* FIXME: handle per-counter overflow */
5687         if (total_count < dev_priv->ips.last_count1) {
5688                 diff = ~0UL - dev_priv->ips.last_count1;
5689                 diff += total_count;
5690         } else {
5691                 diff = total_count - dev_priv->ips.last_count1;
5692         }
5693
5694         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5695                 if (cparams[i].i == dev_priv->ips.c_m &&
5696                     cparams[i].t == dev_priv->ips.r_t) {
5697                         m = cparams[i].m;
5698                         c = cparams[i].c;
5699                         break;
5700                 }
5701         }
5702
5703         diff = div_u64(diff, diff1);
5704         ret = ((m * diff) + c);
5705         ret = div_u64(ret, 10);
5706
5707         dev_priv->ips.last_count1 = total_count;
5708         dev_priv->ips.last_time1 = now;
5709
5710         dev_priv->ips.chipset_power = ret;
5711
5712         return ret;
5713 }
5714
5715 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5716 {
5717         struct drm_device *dev = dev_priv->dev;
5718         unsigned long val;
5719
5720         if (INTEL_INFO(dev)->gen != 5)
5721                 return 0;
5722
5723         spin_lock_irq(&mchdev_lock);
5724
5725         val = __i915_chipset_val(dev_priv);
5726
5727         spin_unlock_irq(&mchdev_lock);
5728
5729         return val;
5730 }
5731
5732 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5733 {
5734         unsigned long m, x, b;
5735         u32 tsfs;
5736
5737         tsfs = I915_READ(TSFS);
5738
5739         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5740         x = I915_READ8(TR1);
5741
5742         b = tsfs & TSFS_INTR_MASK;
5743
5744         return ((m * x) / 127) - b;
5745 }
5746
5747 static int _pxvid_to_vd(u8 pxvid)
5748 {
5749         if (pxvid == 0)
5750                 return 0;
5751
5752         if (pxvid >= 8 && pxvid < 31)
5753                 pxvid = 31;
5754
5755         return (pxvid + 2) * 125;
5756 }
5757
5758 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5759 {
5760         struct drm_device *dev = dev_priv->dev;
5761         const int vd = _pxvid_to_vd(pxvid);
5762         const int vm = vd - 1125;
5763
5764         if (INTEL_INFO(dev)->is_mobile)
5765                 return vm > 0 ? vm : 0;
5766
5767         return vd;
5768 }
5769
5770 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5771 {
5772         u64 now, diff, diffms;
5773         u32 count;
5774
5775         assert_spin_locked(&mchdev_lock);
5776
5777         now = ktime_get_raw_ns();
5778         diffms = now - dev_priv->ips.last_time2;
5779         do_div(diffms, NSEC_PER_MSEC);
5780
5781         /* Don't divide by 0 */
5782         if (!diffms)
5783                 return;
5784
5785         count = I915_READ(GFXEC);
5786
5787         if (count < dev_priv->ips.last_count2) {
5788                 diff = ~0UL - dev_priv->ips.last_count2;
5789                 diff += count;
5790         } else {
5791                 diff = count - dev_priv->ips.last_count2;
5792         }
5793
5794         dev_priv->ips.last_count2 = count;
5795         dev_priv->ips.last_time2 = now;
5796
5797         /* More magic constants... */
5798         diff = diff * 1181;
5799         diff = div_u64(diff, diffms * 10);
5800         dev_priv->ips.gfx_power = diff;
5801 }
5802
5803 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5804 {
5805         struct drm_device *dev = dev_priv->dev;
5806
5807         if (INTEL_INFO(dev)->gen != 5)
5808                 return;
5809
5810         spin_lock_irq(&mchdev_lock);
5811
5812         __i915_update_gfx_val(dev_priv);
5813
5814         spin_unlock_irq(&mchdev_lock);
5815 }
5816
5817 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5818 {
5819         unsigned long t, corr, state1, corr2, state2;
5820         u32 pxvid, ext_v;
5821
5822         assert_spin_locked(&mchdev_lock);
5823
5824         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5825         pxvid = (pxvid >> 24) & 0x7f;
5826         ext_v = pvid_to_extvid(dev_priv, pxvid);
5827
5828         state1 = ext_v;
5829
5830         t = i915_mch_val(dev_priv);
5831
5832         /* Revel in the empirically derived constants */
5833
5834         /* Correction factor in 1/100000 units */
5835         if (t > 80)
5836                 corr = ((t * 2349) + 135940);
5837         else if (t >= 50)
5838                 corr = ((t * 964) + 29317);
5839         else /* < 50 */
5840                 corr = ((t * 301) + 1004);
5841
5842         corr = corr * ((150142 * state1) / 10000 - 78642);
5843         corr /= 100000;
5844         corr2 = (corr * dev_priv->ips.corr);
5845
5846         state2 = (corr2 * state1) / 10000;
5847         state2 /= 100; /* convert to mW */
5848
5849         __i915_update_gfx_val(dev_priv);
5850
5851         return dev_priv->ips.gfx_power + state2;
5852 }
5853
5854 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5855 {
5856         struct drm_device *dev = dev_priv->dev;
5857         unsigned long val;
5858
5859         if (INTEL_INFO(dev)->gen != 5)
5860                 return 0;
5861
5862         spin_lock_irq(&mchdev_lock);
5863
5864         val = __i915_gfx_val(dev_priv);
5865
5866         spin_unlock_irq(&mchdev_lock);
5867
5868         return val;
5869 }
5870
5871 /**
5872  * i915_read_mch_val - return value for IPS use
5873  *
5874  * Calculate and return a value for the IPS driver to use when deciding whether
5875  * we have thermal and power headroom to increase CPU or GPU power budget.
5876  */
5877 unsigned long i915_read_mch_val(void)
5878 {
5879         struct drm_i915_private *dev_priv;
5880         unsigned long chipset_val, graphics_val, ret = 0;
5881
5882         spin_lock_irq(&mchdev_lock);
5883         if (!i915_mch_dev)
5884                 goto out_unlock;
5885         dev_priv = i915_mch_dev;
5886
5887         chipset_val = __i915_chipset_val(dev_priv);
5888         graphics_val = __i915_gfx_val(dev_priv);
5889
5890         ret = chipset_val + graphics_val;
5891
5892 out_unlock:
5893         spin_unlock_irq(&mchdev_lock);
5894
5895         return ret;
5896 }
5897 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5898
5899 /**
5900  * i915_gpu_raise - raise GPU frequency limit
5901  *
5902  * Raise the limit; IPS indicates we have thermal headroom.
5903  */
5904 bool i915_gpu_raise(void)
5905 {
5906         struct drm_i915_private *dev_priv;
5907         bool ret = true;
5908
5909         spin_lock_irq(&mchdev_lock);
5910         if (!i915_mch_dev) {
5911                 ret = false;
5912                 goto out_unlock;
5913         }
5914         dev_priv = i915_mch_dev;
5915
5916         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5917                 dev_priv->ips.max_delay--;
5918
5919 out_unlock:
5920         spin_unlock_irq(&mchdev_lock);
5921
5922         return ret;
5923 }
5924 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5925
5926 /**
5927  * i915_gpu_lower - lower GPU frequency limit
5928  *
5929  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5930  * frequency maximum.
5931  */
5932 bool i915_gpu_lower(void)
5933 {
5934         struct drm_i915_private *dev_priv;
5935         bool ret = true;
5936
5937         spin_lock_irq(&mchdev_lock);
5938         if (!i915_mch_dev) {
5939                 ret = false;
5940                 goto out_unlock;
5941         }
5942         dev_priv = i915_mch_dev;
5943
5944         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5945                 dev_priv->ips.max_delay++;
5946
5947 out_unlock:
5948         spin_unlock_irq(&mchdev_lock);
5949
5950         return ret;
5951 }
5952 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5953
5954 /**
5955  * i915_gpu_busy - indicate GPU business to IPS
5956  *
5957  * Tell the IPS driver whether or not the GPU is busy.
5958  */
5959 bool i915_gpu_busy(void)
5960 {
5961         struct drm_i915_private *dev_priv;
5962         struct intel_engine_cs *ring;
5963         bool ret = false;
5964         int i;
5965
5966         spin_lock_irq(&mchdev_lock);
5967         if (!i915_mch_dev)
5968                 goto out_unlock;
5969         dev_priv = i915_mch_dev;
5970
5971         for_each_ring(ring, dev_priv, i)
5972                 ret |= !list_empty(&ring->request_list);
5973
5974 out_unlock:
5975         spin_unlock_irq(&mchdev_lock);
5976
5977         return ret;
5978 }
5979 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5980
5981 /**
5982  * i915_gpu_turbo_disable - disable graphics turbo
5983  *
5984  * Disable graphics turbo by resetting the max frequency and setting the
5985  * current frequency to the default.
5986  */
5987 bool i915_gpu_turbo_disable(void)
5988 {
5989         struct drm_i915_private *dev_priv;
5990         bool ret = true;
5991
5992         spin_lock_irq(&mchdev_lock);
5993         if (!i915_mch_dev) {
5994                 ret = false;
5995                 goto out_unlock;
5996         }
5997         dev_priv = i915_mch_dev;
5998
5999         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6000
6001         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6002                 ret = false;
6003
6004 out_unlock:
6005         spin_unlock_irq(&mchdev_lock);
6006
6007         return ret;
6008 }
6009 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6010
6011 /**
6012  * Tells the intel_ips driver that the i915 driver is now loaded, if
6013  * IPS got loaded first.
6014  *
6015  * This awkward dance is so that neither module has to depend on the
6016  * other in order for IPS to do the appropriate communication of
6017  * GPU turbo limits to i915.
6018  */
6019 static void
6020 ips_ping_for_i915_load(void)
6021 {
6022         void (*link)(void);
6023
6024         link = symbol_get(ips_link_to_i915_driver);
6025         if (link) {
6026                 link();
6027                 symbol_put(ips_link_to_i915_driver);
6028         }
6029 }
6030
6031 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6032 {
6033         /* We only register the i915 ips part with intel-ips once everything is
6034          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6035         spin_lock_irq(&mchdev_lock);
6036         i915_mch_dev = dev_priv;
6037         spin_unlock_irq(&mchdev_lock);
6038
6039         ips_ping_for_i915_load();
6040 }
6041
6042 void intel_gpu_ips_teardown(void)
6043 {
6044         spin_lock_irq(&mchdev_lock);
6045         i915_mch_dev = NULL;
6046         spin_unlock_irq(&mchdev_lock);
6047 }
6048
6049 static void intel_init_emon(struct drm_device *dev)
6050 {
6051         struct drm_i915_private *dev_priv = dev->dev_private;
6052         u32 lcfuse;
6053         u8 pxw[16];
6054         int i;
6055
6056         /* Disable to program */
6057         I915_WRITE(ECR, 0);
6058         POSTING_READ(ECR);
6059
6060         /* Program energy weights for various events */
6061         I915_WRITE(SDEW, 0x15040d00);
6062         I915_WRITE(CSIEW0, 0x007f0000);
6063         I915_WRITE(CSIEW1, 0x1e220004);
6064         I915_WRITE(CSIEW2, 0x04000004);
6065
6066         for (i = 0; i < 5; i++)
6067                 I915_WRITE(PEW(i), 0);
6068         for (i = 0; i < 3; i++)
6069                 I915_WRITE(DEW(i), 0);
6070
6071         /* Program P-state weights to account for frequency power adjustment */
6072         for (i = 0; i < 16; i++) {
6073                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6074                 unsigned long freq = intel_pxfreq(pxvidfreq);
6075                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6076                         PXVFREQ_PX_SHIFT;
6077                 unsigned long val;
6078
6079                 val = vid * vid;
6080                 val *= (freq / 1000);
6081                 val *= 255;
6082                 val /= (127*127*900);
6083                 if (val > 0xff)
6084                         DRM_ERROR("bad pxval: %ld\n", val);
6085                 pxw[i] = val;
6086         }
6087         /* Render standby states get 0 weight */
6088         pxw[14] = 0;
6089         pxw[15] = 0;
6090
6091         for (i = 0; i < 4; i++) {
6092                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6093                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6094                 I915_WRITE(PXW(i), val);
6095         }
6096
6097         /* Adjust magic regs to magic values (more experimental results) */
6098         I915_WRITE(OGW0, 0);
6099         I915_WRITE(OGW1, 0);
6100         I915_WRITE(EG0, 0x00007f00);
6101         I915_WRITE(EG1, 0x0000000e);
6102         I915_WRITE(EG2, 0x000e0000);
6103         I915_WRITE(EG3, 0x68000300);
6104         I915_WRITE(EG4, 0x42000000);
6105         I915_WRITE(EG5, 0x00140031);
6106         I915_WRITE(EG6, 0);
6107         I915_WRITE(EG7, 0);
6108
6109         for (i = 0; i < 8; i++)
6110                 I915_WRITE(PXWL(i), 0);
6111
6112         /* Enable PMON + select events */
6113         I915_WRITE(ECR, 0x80000019);
6114
6115         lcfuse = I915_READ(LCFUSE02);
6116
6117         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6118 }
6119
6120 void intel_init_gt_powersave(struct drm_device *dev)
6121 {
6122         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6123
6124         if (IS_CHERRYVIEW(dev))
6125                 cherryview_init_gt_powersave(dev);
6126         else if (IS_VALLEYVIEW(dev))
6127                 valleyview_init_gt_powersave(dev);
6128 }
6129
6130 void intel_cleanup_gt_powersave(struct drm_device *dev)
6131 {
6132         if (IS_CHERRYVIEW(dev))
6133                 return;
6134         else if (IS_VALLEYVIEW(dev))
6135                 valleyview_cleanup_gt_powersave(dev);
6136 }
6137
6138 static void gen6_suspend_rps(struct drm_device *dev)
6139 {
6140         struct drm_i915_private *dev_priv = dev->dev_private;
6141
6142         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6143
6144         gen6_disable_rps_interrupts(dev);
6145 }
6146
6147 /**
6148  * intel_suspend_gt_powersave - suspend PM work and helper threads
6149  * @dev: drm device
6150  *
6151  * We don't want to disable RC6 or other features here, we just want
6152  * to make sure any work we've queued has finished and won't bother
6153  * us while we're suspended.
6154  */
6155 void intel_suspend_gt_powersave(struct drm_device *dev)
6156 {
6157         struct drm_i915_private *dev_priv = dev->dev_private;
6158
6159         if (INTEL_INFO(dev)->gen < 6)
6160                 return;
6161
6162         gen6_suspend_rps(dev);
6163
6164         /* Force GPU to min freq during suspend */
6165         gen6_rps_idle(dev_priv);
6166 }
6167
6168 void intel_disable_gt_powersave(struct drm_device *dev)
6169 {
6170         struct drm_i915_private *dev_priv = dev->dev_private;
6171
6172         if (IS_IRONLAKE_M(dev)) {
6173                 ironlake_disable_drps(dev);
6174         } else if (INTEL_INFO(dev)->gen >= 6) {
6175                 intel_suspend_gt_powersave(dev);
6176
6177                 mutex_lock(&dev_priv->rps.hw_lock);
6178                 if (INTEL_INFO(dev)->gen >= 9)
6179                         gen9_disable_rps(dev);
6180                 else if (IS_CHERRYVIEW(dev))
6181                         cherryview_disable_rps(dev);
6182                 else if (IS_VALLEYVIEW(dev))
6183                         valleyview_disable_rps(dev);
6184                 else
6185                         gen6_disable_rps(dev);
6186
6187                 dev_priv->rps.enabled = false;
6188                 mutex_unlock(&dev_priv->rps.hw_lock);
6189         }
6190 }
6191
6192 static void intel_gen6_powersave_work(struct work_struct *work)
6193 {
6194         struct drm_i915_private *dev_priv =
6195                 container_of(work, struct drm_i915_private,
6196                              rps.delayed_resume_work.work);
6197         struct drm_device *dev = dev_priv->dev;
6198
6199         mutex_lock(&dev_priv->rps.hw_lock);
6200
6201         gen6_reset_rps_interrupts(dev);
6202
6203         if (IS_CHERRYVIEW(dev)) {
6204                 cherryview_enable_rps(dev);
6205         } else if (IS_VALLEYVIEW(dev)) {
6206                 valleyview_enable_rps(dev);
6207         } else if (INTEL_INFO(dev)->gen >= 9) {
6208                 gen9_enable_rc6(dev);
6209                 gen9_enable_rps(dev);
6210                 if (IS_SKYLAKE(dev))
6211                         __gen6_update_ring_freq(dev);
6212         } else if (IS_BROADWELL(dev)) {
6213                 gen8_enable_rps(dev);
6214                 __gen6_update_ring_freq(dev);
6215         } else {
6216                 gen6_enable_rps(dev);
6217                 __gen6_update_ring_freq(dev);
6218         }
6219
6220         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6221         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6222
6223         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6224         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6225
6226         dev_priv->rps.enabled = true;
6227
6228         gen6_enable_rps_interrupts(dev);
6229
6230         mutex_unlock(&dev_priv->rps.hw_lock);
6231
6232         intel_runtime_pm_put(dev_priv);
6233 }
6234
6235 void intel_enable_gt_powersave(struct drm_device *dev)
6236 {
6237         struct drm_i915_private *dev_priv = dev->dev_private;
6238
6239         /* Powersaving is controlled by the host when inside a VM */
6240         if (intel_vgpu_active(dev))
6241                 return;
6242
6243         if (IS_IRONLAKE_M(dev)) {
6244                 mutex_lock(&dev->struct_mutex);
6245                 ironlake_enable_drps(dev);
6246                 intel_init_emon(dev);
6247                 mutex_unlock(&dev->struct_mutex);
6248         } else if (INTEL_INFO(dev)->gen >= 6) {
6249                 /*
6250                  * PCU communication is slow and this doesn't need to be
6251                  * done at any specific time, so do this out of our fast path
6252                  * to make resume and init faster.
6253                  *
6254                  * We depend on the HW RC6 power context save/restore
6255                  * mechanism when entering D3 through runtime PM suspend. So
6256                  * disable RPM until RPS/RC6 is properly setup. We can only
6257                  * get here via the driver load/system resume/runtime resume
6258                  * paths, so the _noresume version is enough (and in case of
6259                  * runtime resume it's necessary).
6260                  */
6261                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6262                                            round_jiffies_up_relative(HZ)))
6263                         intel_runtime_pm_get_noresume(dev_priv);
6264         }
6265 }
6266
6267 void intel_reset_gt_powersave(struct drm_device *dev)
6268 {
6269         struct drm_i915_private *dev_priv = dev->dev_private;
6270
6271         if (INTEL_INFO(dev)->gen < 6)
6272                 return;
6273
6274         gen6_suspend_rps(dev);
6275         dev_priv->rps.enabled = false;
6276 }
6277
6278 static void ibx_init_clock_gating(struct drm_device *dev)
6279 {
6280         struct drm_i915_private *dev_priv = dev->dev_private;
6281
6282         /*
6283          * On Ibex Peak and Cougar Point, we need to disable clock
6284          * gating for the panel power sequencer or it will fail to
6285          * start up when no ports are active.
6286          */
6287         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6288 }
6289
6290 static void g4x_disable_trickle_feed(struct drm_device *dev)
6291 {
6292         struct drm_i915_private *dev_priv = dev->dev_private;
6293         enum pipe pipe;
6294
6295         for_each_pipe(dev_priv, pipe) {
6296                 I915_WRITE(DSPCNTR(pipe),
6297                            I915_READ(DSPCNTR(pipe)) |
6298                            DISPPLANE_TRICKLE_FEED_DISABLE);
6299
6300                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6301                 POSTING_READ(DSPSURF(pipe));
6302         }
6303 }
6304
6305 static void ilk_init_lp_watermarks(struct drm_device *dev)
6306 {
6307         struct drm_i915_private *dev_priv = dev->dev_private;
6308
6309         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6310         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6311         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6312
6313         /*
6314          * Don't touch WM1S_LP_EN here.
6315          * Doing so could cause underruns.
6316          */
6317 }
6318
6319 static void ironlake_init_clock_gating(struct drm_device *dev)
6320 {
6321         struct drm_i915_private *dev_priv = dev->dev_private;
6322         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6323
6324         /*
6325          * Required for FBC
6326          * WaFbcDisableDpfcClockGating:ilk
6327          */
6328         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6329                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6330                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6331
6332         I915_WRITE(PCH_3DCGDIS0,
6333                    MARIUNIT_CLOCK_GATE_DISABLE |
6334                    SVSMUNIT_CLOCK_GATE_DISABLE);
6335         I915_WRITE(PCH_3DCGDIS1,
6336                    VFMUNIT_CLOCK_GATE_DISABLE);
6337
6338         /*
6339          * According to the spec the following bits should be set in
6340          * order to enable memory self-refresh
6341          * The bit 22/21 of 0x42004
6342          * The bit 5 of 0x42020
6343          * The bit 15 of 0x45000
6344          */
6345         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6346                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6347                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6348         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6349         I915_WRITE(DISP_ARB_CTL,
6350                    (I915_READ(DISP_ARB_CTL) |
6351                     DISP_FBC_WM_DIS));
6352
6353         ilk_init_lp_watermarks(dev);
6354
6355         /*
6356          * Based on the document from hardware guys the following bits
6357          * should be set unconditionally in order to enable FBC.
6358          * The bit 22 of 0x42000
6359          * The bit 22 of 0x42004
6360          * The bit 7,8,9 of 0x42020.
6361          */
6362         if (IS_IRONLAKE_M(dev)) {
6363                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6364                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6365                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6366                            ILK_FBCQ_DIS);
6367                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6368                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6369                            ILK_DPARB_GATE);
6370         }
6371
6372         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6373
6374         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6375                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6376                    ILK_ELPIN_409_SELECT);
6377         I915_WRITE(_3D_CHICKEN2,
6378                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6379                    _3D_CHICKEN2_WM_READ_PIPELINED);
6380
6381         /* WaDisableRenderCachePipelinedFlush:ilk */
6382         I915_WRITE(CACHE_MODE_0,
6383                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6384
6385         /* WaDisable_RenderCache_OperationalFlush:ilk */
6386         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6387
6388         g4x_disable_trickle_feed(dev);
6389
6390         ibx_init_clock_gating(dev);
6391 }
6392
6393 static void cpt_init_clock_gating(struct drm_device *dev)
6394 {
6395         struct drm_i915_private *dev_priv = dev->dev_private;
6396         int pipe;
6397         uint32_t val;
6398
6399         /*
6400          * On Ibex Peak and Cougar Point, we need to disable clock
6401          * gating for the panel power sequencer or it will fail to
6402          * start up when no ports are active.
6403          */
6404         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6405                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6406                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6407         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6408                    DPLS_EDP_PPS_FIX_DIS);
6409         /* The below fixes the weird display corruption, a few pixels shifted
6410          * downward, on (only) LVDS of some HP laptops with IVY.
6411          */
6412         for_each_pipe(dev_priv, pipe) {
6413                 val = I915_READ(TRANS_CHICKEN2(pipe));
6414                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6415                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6416                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6417                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6418                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6419                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6420                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6421                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6422         }
6423         /* WADP0ClockGatingDisable */
6424         for_each_pipe(dev_priv, pipe) {
6425                 I915_WRITE(TRANS_CHICKEN1(pipe),
6426                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6427         }
6428 }
6429
6430 static void gen6_check_mch_setup(struct drm_device *dev)
6431 {
6432         struct drm_i915_private *dev_priv = dev->dev_private;
6433         uint32_t tmp;
6434
6435         tmp = I915_READ(MCH_SSKPD);
6436         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6437                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6438                               tmp);
6439 }
6440
6441 static void gen6_init_clock_gating(struct drm_device *dev)
6442 {
6443         struct drm_i915_private *dev_priv = dev->dev_private;
6444         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6445
6446         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6447
6448         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6449                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6450                    ILK_ELPIN_409_SELECT);
6451
6452         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6453         I915_WRITE(_3D_CHICKEN,
6454                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6455
6456         /* WaDisable_RenderCache_OperationalFlush:snb */
6457         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6458
6459         /*
6460          * BSpec recoomends 8x4 when MSAA is used,
6461          * however in practice 16x4 seems fastest.
6462          *
6463          * Note that PS/WM thread counts depend on the WIZ hashing
6464          * disable bit, which we don't touch here, but it's good
6465          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6466          */
6467         I915_WRITE(GEN6_GT_MODE,
6468                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6469
6470         ilk_init_lp_watermarks(dev);
6471
6472         I915_WRITE(CACHE_MODE_0,
6473                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6474
6475         I915_WRITE(GEN6_UCGCTL1,
6476                    I915_READ(GEN6_UCGCTL1) |
6477                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6478                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6479
6480         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6481          * gating disable must be set.  Failure to set it results in
6482          * flickering pixels due to Z write ordering failures after
6483          * some amount of runtime in the Mesa "fire" demo, and Unigine
6484          * Sanctuary and Tropics, and apparently anything else with
6485          * alpha test or pixel discard.
6486          *
6487          * According to the spec, bit 11 (RCCUNIT) must also be set,
6488          * but we didn't debug actual testcases to find it out.
6489          *
6490          * WaDisableRCCUnitClockGating:snb
6491          * WaDisableRCPBUnitClockGating:snb
6492          */
6493         I915_WRITE(GEN6_UCGCTL2,
6494                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6495                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6496
6497         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6498         I915_WRITE(_3D_CHICKEN3,
6499                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6500
6501         /*
6502          * Bspec says:
6503          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6504          * 3DSTATE_SF number of SF output attributes is more than 16."
6505          */
6506         I915_WRITE(_3D_CHICKEN3,
6507                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6508
6509         /*
6510          * According to the spec the following bits should be
6511          * set in order to enable memory self-refresh and fbc:
6512          * The bit21 and bit22 of 0x42000
6513          * The bit21 and bit22 of 0x42004
6514          * The bit5 and bit7 of 0x42020
6515          * The bit14 of 0x70180
6516          * The bit14 of 0x71180
6517          *
6518          * WaFbcAsynchFlipDisableFbcQueue:snb
6519          */
6520         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6521                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6522                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6523         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6524                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6525                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6526         I915_WRITE(ILK_DSPCLK_GATE_D,
6527                    I915_READ(ILK_DSPCLK_GATE_D) |
6528                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6529                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6530
6531         g4x_disable_trickle_feed(dev);
6532
6533         cpt_init_clock_gating(dev);
6534
6535         gen6_check_mch_setup(dev);
6536 }
6537
6538 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6539 {
6540         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6541
6542         /*
6543          * WaVSThreadDispatchOverride:ivb,vlv
6544          *
6545          * This actually overrides the dispatch
6546          * mode for all thread types.
6547          */
6548         reg &= ~GEN7_FF_SCHED_MASK;
6549         reg |= GEN7_FF_TS_SCHED_HW;
6550         reg |= GEN7_FF_VS_SCHED_HW;
6551         reg |= GEN7_FF_DS_SCHED_HW;
6552
6553         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6554 }
6555
6556 static void lpt_init_clock_gating(struct drm_device *dev)
6557 {
6558         struct drm_i915_private *dev_priv = dev->dev_private;
6559
6560         /*
6561          * TODO: this bit should only be enabled when really needed, then
6562          * disabled when not needed anymore in order to save power.
6563          */
6564         if (HAS_PCH_LPT_LP(dev))
6565                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6566                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6567                            PCH_LP_PARTITION_LEVEL_DISABLE);
6568
6569         /* WADPOClockGatingDisable:hsw */
6570         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6571                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6572                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6573 }
6574
6575 static void lpt_suspend_hw(struct drm_device *dev)
6576 {
6577         struct drm_i915_private *dev_priv = dev->dev_private;
6578
6579         if (HAS_PCH_LPT_LP(dev)) {
6580                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6581
6582                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6583                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6584         }
6585 }
6586
6587 static void broadwell_init_clock_gating(struct drm_device *dev)
6588 {
6589         struct drm_i915_private *dev_priv = dev->dev_private;
6590         enum pipe pipe;
6591         uint32_t misccpctl;
6592
6593         ilk_init_lp_watermarks(dev);
6594
6595         /* WaSwitchSolVfFArbitrationPriority:bdw */
6596         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6597
6598         /* WaPsrDPAMaskVBlankInSRD:bdw */
6599         I915_WRITE(CHICKEN_PAR1_1,
6600                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6601
6602         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6603         for_each_pipe(dev_priv, pipe) {
6604                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6605                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6606                            BDW_DPRS_MASK_VBLANK_SRD);
6607         }
6608
6609         /* WaVSRefCountFullforceMissDisable:bdw */
6610         /* WaDSRefCountFullforceMissDisable:bdw */
6611         I915_WRITE(GEN7_FF_THREAD_MODE,
6612                    I915_READ(GEN7_FF_THREAD_MODE) &
6613                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6614
6615         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6616                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6617
6618         /* WaDisableSDEUnitClockGating:bdw */
6619         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6620                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6621
6622         /*
6623          * WaProgramL3SqcReg1Default:bdw
6624          * WaTempDisableDOPClkGating:bdw
6625          */
6626         misccpctl = I915_READ(GEN7_MISCCPCTL);
6627         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6628         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6629         /*
6630          * Wait at least 100 clocks before re-enabling clock gating. See
6631          * the definition of L3SQCREG1 in BSpec.
6632          */
6633         POSTING_READ(GEN8_L3SQCREG1);
6634         udelay(1);
6635         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6636
6637         /*
6638          * WaGttCachingOffByDefault:bdw
6639          * GTT cache may not work with big pages, so if those
6640          * are ever enabled GTT cache may need to be disabled.
6641          */
6642         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6643
6644         lpt_init_clock_gating(dev);
6645 }
6646
6647 static void haswell_init_clock_gating(struct drm_device *dev)
6648 {
6649         struct drm_i915_private *dev_priv = dev->dev_private;
6650
6651         ilk_init_lp_watermarks(dev);
6652
6653         /* L3 caching of data atomics doesn't work -- disable it. */
6654         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6655         I915_WRITE(HSW_ROW_CHICKEN3,
6656                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6657
6658         /* This is required by WaCatErrorRejectionIssue:hsw */
6659         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6660                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6661                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6662
6663         /* WaVSRefCountFullforceMissDisable:hsw */
6664         I915_WRITE(GEN7_FF_THREAD_MODE,
6665                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6666
6667         /* WaDisable_RenderCache_OperationalFlush:hsw */
6668         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6669
6670         /* enable HiZ Raw Stall Optimization */
6671         I915_WRITE(CACHE_MODE_0_GEN7,
6672                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6673
6674         /* WaDisable4x2SubspanOptimization:hsw */
6675         I915_WRITE(CACHE_MODE_1,
6676                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6677
6678         /*
6679          * BSpec recommends 8x4 when MSAA is used,
6680          * however in practice 16x4 seems fastest.
6681          *
6682          * Note that PS/WM thread counts depend on the WIZ hashing
6683          * disable bit, which we don't touch here, but it's good
6684          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6685          */
6686         I915_WRITE(GEN7_GT_MODE,
6687                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6688
6689         /* WaSampleCChickenBitEnable:hsw */
6690         I915_WRITE(HALF_SLICE_CHICKEN3,
6691                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6692
6693         /* WaSwitchSolVfFArbitrationPriority:hsw */
6694         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6695
6696         /* WaRsPkgCStateDisplayPMReq:hsw */
6697         I915_WRITE(CHICKEN_PAR1_1,
6698                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6699
6700         lpt_init_clock_gating(dev);
6701 }
6702
6703 static void ivybridge_init_clock_gating(struct drm_device *dev)
6704 {
6705         struct drm_i915_private *dev_priv = dev->dev_private;
6706         uint32_t snpcr;
6707
6708         ilk_init_lp_watermarks(dev);
6709
6710         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6711
6712         /* WaDisableEarlyCull:ivb */
6713         I915_WRITE(_3D_CHICKEN3,
6714                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6715
6716         /* WaDisableBackToBackFlipFix:ivb */
6717         I915_WRITE(IVB_CHICKEN3,
6718                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6719                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6720
6721         /* WaDisablePSDDualDispatchEnable:ivb */
6722         if (IS_IVB_GT1(dev))
6723                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6724                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6725
6726         /* WaDisable_RenderCache_OperationalFlush:ivb */
6727         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6728
6729         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6730         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6731                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6732
6733         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6734         I915_WRITE(GEN7_L3CNTLREG1,
6735                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6736         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6737                    GEN7_WA_L3_CHICKEN_MODE);
6738         if (IS_IVB_GT1(dev))
6739                 I915_WRITE(GEN7_ROW_CHICKEN2,
6740                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6741         else {
6742                 /* must write both registers */
6743                 I915_WRITE(GEN7_ROW_CHICKEN2,
6744                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6745                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6746                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6747         }
6748
6749         /* WaForceL3Serialization:ivb */
6750         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6751                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6752
6753         /*
6754          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6755          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6756          */
6757         I915_WRITE(GEN6_UCGCTL2,
6758                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6759
6760         /* This is required by WaCatErrorRejectionIssue:ivb */
6761         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6762                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6763                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6764
6765         g4x_disable_trickle_feed(dev);
6766
6767         gen7_setup_fixed_func_scheduler(dev_priv);
6768
6769         if (0) { /* causes HiZ corruption on ivb:gt1 */
6770                 /* enable HiZ Raw Stall Optimization */
6771                 I915_WRITE(CACHE_MODE_0_GEN7,
6772                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6773         }
6774
6775         /* WaDisable4x2SubspanOptimization:ivb */
6776         I915_WRITE(CACHE_MODE_1,
6777                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6778
6779         /*
6780          * BSpec recommends 8x4 when MSAA is used,
6781          * however in practice 16x4 seems fastest.
6782          *
6783          * Note that PS/WM thread counts depend on the WIZ hashing
6784          * disable bit, which we don't touch here, but it's good
6785          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6786          */
6787         I915_WRITE(GEN7_GT_MODE,
6788                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6789
6790         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6791         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6792         snpcr |= GEN6_MBC_SNPCR_MED;
6793         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6794
6795         if (!HAS_PCH_NOP(dev))
6796                 cpt_init_clock_gating(dev);
6797
6798         gen6_check_mch_setup(dev);
6799 }
6800
6801 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6802 {
6803         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6804
6805         /*
6806          * Disable trickle feed and enable pnd deadline calculation
6807          */
6808         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6809         I915_WRITE(CBR1_VLV, 0);
6810 }
6811
6812 static void valleyview_init_clock_gating(struct drm_device *dev)
6813 {
6814         struct drm_i915_private *dev_priv = dev->dev_private;
6815
6816         vlv_init_display_clock_gating(dev_priv);
6817
6818         /* WaDisableEarlyCull:vlv */
6819         I915_WRITE(_3D_CHICKEN3,
6820                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6821
6822         /* WaDisableBackToBackFlipFix:vlv */
6823         I915_WRITE(IVB_CHICKEN3,
6824                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6825                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6826
6827         /* WaPsdDispatchEnable:vlv */
6828         /* WaDisablePSDDualDispatchEnable:vlv */
6829         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6830                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6831                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6832
6833         /* WaDisable_RenderCache_OperationalFlush:vlv */
6834         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6835
6836         /* WaForceL3Serialization:vlv */
6837         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6838                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6839
6840         /* WaDisableDopClockGating:vlv */
6841         I915_WRITE(GEN7_ROW_CHICKEN2,
6842                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6843
6844         /* This is required by WaCatErrorRejectionIssue:vlv */
6845         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6846                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6847                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6848
6849         gen7_setup_fixed_func_scheduler(dev_priv);
6850
6851         /*
6852          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6853          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6854          */
6855         I915_WRITE(GEN6_UCGCTL2,
6856                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6857
6858         /* WaDisableL3Bank2xClockGate:vlv
6859          * Disabling L3 clock gating- MMIO 940c[25] = 1
6860          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6861         I915_WRITE(GEN7_UCGCTL4,
6862                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6863
6864         /*
6865          * BSpec says this must be set, even though
6866          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6867          */
6868         I915_WRITE(CACHE_MODE_1,
6869                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6870
6871         /*
6872          * BSpec recommends 8x4 when MSAA is used,
6873          * however in practice 16x4 seems fastest.
6874          *
6875          * Note that PS/WM thread counts depend on the WIZ hashing
6876          * disable bit, which we don't touch here, but it's good
6877          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6878          */
6879         I915_WRITE(GEN7_GT_MODE,
6880                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6881
6882         /*
6883          * WaIncreaseL3CreditsForVLVB0:vlv
6884          * This is the hardware default actually.
6885          */
6886         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6887
6888         /*
6889          * WaDisableVLVClockGating_VBIIssue:vlv
6890          * Disable clock gating on th GCFG unit to prevent a delay
6891          * in the reporting of vblank events.
6892          */
6893         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6894 }
6895
6896 static void cherryview_init_clock_gating(struct drm_device *dev)
6897 {
6898         struct drm_i915_private *dev_priv = dev->dev_private;
6899
6900         vlv_init_display_clock_gating(dev_priv);
6901
6902         /* WaVSRefCountFullforceMissDisable:chv */
6903         /* WaDSRefCountFullforceMissDisable:chv */
6904         I915_WRITE(GEN7_FF_THREAD_MODE,
6905                    I915_READ(GEN7_FF_THREAD_MODE) &
6906                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6907
6908         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6909         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6910                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6911
6912         /* WaDisableCSUnitClockGating:chv */
6913         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6914                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6915
6916         /* WaDisableSDEUnitClockGating:chv */
6917         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6918                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6919
6920         /*
6921          * GTT cache may not work with big pages, so if those
6922          * are ever enabled GTT cache may need to be disabled.
6923          */
6924         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6925 }
6926
6927 static void g4x_init_clock_gating(struct drm_device *dev)
6928 {
6929         struct drm_i915_private *dev_priv = dev->dev_private;
6930         uint32_t dspclk_gate;
6931
6932         I915_WRITE(RENCLK_GATE_D1, 0);
6933         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6934                    GS_UNIT_CLOCK_GATE_DISABLE |
6935                    CL_UNIT_CLOCK_GATE_DISABLE);
6936         I915_WRITE(RAMCLK_GATE_D, 0);
6937         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6938                 OVRUNIT_CLOCK_GATE_DISABLE |
6939                 OVCUNIT_CLOCK_GATE_DISABLE;
6940         if (IS_GM45(dev))
6941                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6942         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6943
6944         /* WaDisableRenderCachePipelinedFlush */
6945         I915_WRITE(CACHE_MODE_0,
6946                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6947
6948         /* WaDisable_RenderCache_OperationalFlush:g4x */
6949         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6950
6951         g4x_disable_trickle_feed(dev);
6952 }
6953
6954 static void crestline_init_clock_gating(struct drm_device *dev)
6955 {
6956         struct drm_i915_private *dev_priv = dev->dev_private;
6957
6958         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6959         I915_WRITE(RENCLK_GATE_D2, 0);
6960         I915_WRITE(DSPCLK_GATE_D, 0);
6961         I915_WRITE(RAMCLK_GATE_D, 0);
6962         I915_WRITE16(DEUC, 0);
6963         I915_WRITE(MI_ARB_STATE,
6964                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6965
6966         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6967         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6968 }
6969
6970 static void broadwater_init_clock_gating(struct drm_device *dev)
6971 {
6972         struct drm_i915_private *dev_priv = dev->dev_private;
6973
6974         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6975                    I965_RCC_CLOCK_GATE_DISABLE |
6976                    I965_RCPB_CLOCK_GATE_DISABLE |
6977                    I965_ISC_CLOCK_GATE_DISABLE |
6978                    I965_FBC_CLOCK_GATE_DISABLE);
6979         I915_WRITE(RENCLK_GATE_D2, 0);
6980         I915_WRITE(MI_ARB_STATE,
6981                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6982
6983         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6984         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6985 }
6986
6987 static void gen3_init_clock_gating(struct drm_device *dev)
6988 {
6989         struct drm_i915_private *dev_priv = dev->dev_private;
6990         u32 dstate = I915_READ(D_STATE);
6991
6992         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6993                 DSTATE_DOT_CLOCK_GATING;
6994         I915_WRITE(D_STATE, dstate);
6995
6996         if (IS_PINEVIEW(dev))
6997                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6998
6999         /* IIR "flip pending" means done if this bit is set */
7000         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7001
7002         /* interrupts should cause a wake up from C3 */
7003         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7004
7005         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7006         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7007
7008         I915_WRITE(MI_ARB_STATE,
7009                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7010 }
7011
7012 static void i85x_init_clock_gating(struct drm_device *dev)
7013 {
7014         struct drm_i915_private *dev_priv = dev->dev_private;
7015
7016         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7017
7018         /* interrupts should cause a wake up from C3 */
7019         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7020                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7021
7022         I915_WRITE(MEM_MODE,
7023                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7024 }
7025
7026 static void i830_init_clock_gating(struct drm_device *dev)
7027 {
7028         struct drm_i915_private *dev_priv = dev->dev_private;
7029
7030         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7031
7032         I915_WRITE(MEM_MODE,
7033                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7034                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7035 }
7036
7037 void intel_init_clock_gating(struct drm_device *dev)
7038 {
7039         struct drm_i915_private *dev_priv = dev->dev_private;
7040
7041         if (dev_priv->display.init_clock_gating)
7042                 dev_priv->display.init_clock_gating(dev);
7043 }
7044
7045 void intel_suspend_hw(struct drm_device *dev)
7046 {
7047         if (HAS_PCH_LPT(dev))
7048                 lpt_suspend_hw(dev);
7049 }
7050
7051 /* Set up chip specific power management-related functions */
7052 void intel_init_pm(struct drm_device *dev)
7053 {
7054         struct drm_i915_private *dev_priv = dev->dev_private;
7055
7056         intel_fbc_init(dev_priv);
7057
7058         /* For cxsr */
7059         if (IS_PINEVIEW(dev))
7060                 i915_pineview_get_mem_freq(dev);
7061         else if (IS_GEN5(dev))
7062                 i915_ironlake_get_mem_freq(dev);
7063
7064         /* For FIFO watermark updates */
7065         if (INTEL_INFO(dev)->gen >= 9) {
7066                 skl_setup_wm_latency(dev);
7067
7068                 if (IS_BROXTON(dev))
7069                         dev_priv->display.init_clock_gating =
7070                                 bxt_init_clock_gating;
7071                 dev_priv->display.update_wm = skl_update_wm;
7072                 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
7073         } else if (HAS_PCH_SPLIT(dev)) {
7074                 ilk_setup_wm_latency(dev);
7075
7076                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7077                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7078                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7079                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7080                         dev_priv->display.update_wm = ilk_update_wm;
7081                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7082                 } else {
7083                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7084                                       "Disable CxSR\n");
7085                 }
7086
7087                 if (IS_GEN5(dev))
7088                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7089                 else if (IS_GEN6(dev))
7090                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7091                 else if (IS_IVYBRIDGE(dev))
7092                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7093                 else if (IS_HASWELL(dev))
7094                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7095                 else if (INTEL_INFO(dev)->gen == 8)
7096                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7097         } else if (IS_CHERRYVIEW(dev)) {
7098                 vlv_setup_wm_latency(dev);
7099
7100                 dev_priv->display.update_wm = vlv_update_wm;
7101                 dev_priv->display.init_clock_gating =
7102                         cherryview_init_clock_gating;
7103         } else if (IS_VALLEYVIEW(dev)) {
7104                 vlv_setup_wm_latency(dev);
7105
7106                 dev_priv->display.update_wm = vlv_update_wm;
7107                 dev_priv->display.init_clock_gating =
7108                         valleyview_init_clock_gating;
7109         } else if (IS_PINEVIEW(dev)) {
7110                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7111                                             dev_priv->is_ddr3,
7112                                             dev_priv->fsb_freq,
7113                                             dev_priv->mem_freq)) {
7114                         DRM_INFO("failed to find known CxSR latency "
7115                                  "(found ddr%s fsb freq %d, mem freq %d), "
7116                                  "disabling CxSR\n",
7117                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7118                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7119                         /* Disable CxSR and never update its watermark again */
7120                         intel_set_memory_cxsr(dev_priv, false);
7121                         dev_priv->display.update_wm = NULL;
7122                 } else
7123                         dev_priv->display.update_wm = pineview_update_wm;
7124                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7125         } else if (IS_G4X(dev)) {
7126                 dev_priv->display.update_wm = g4x_update_wm;
7127                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7128         } else if (IS_GEN4(dev)) {
7129                 dev_priv->display.update_wm = i965_update_wm;
7130                 if (IS_CRESTLINE(dev))
7131                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7132                 else if (IS_BROADWATER(dev))
7133                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7134         } else if (IS_GEN3(dev)) {
7135                 dev_priv->display.update_wm = i9xx_update_wm;
7136                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7137                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7138         } else if (IS_GEN2(dev)) {
7139                 if (INTEL_INFO(dev)->num_pipes == 1) {
7140                         dev_priv->display.update_wm = i845_update_wm;
7141                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7142                 } else {
7143                         dev_priv->display.update_wm = i9xx_update_wm;
7144                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7145                 }
7146
7147                 if (IS_I85X(dev) || IS_I865G(dev))
7148                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7149                 else
7150                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
7151         } else {
7152                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7153         }
7154 }
7155
7156 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7157 {
7158         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7159
7160         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7161                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7162                 return -EAGAIN;
7163         }
7164
7165         I915_WRITE(GEN6_PCODE_DATA, *val);
7166         I915_WRITE(GEN6_PCODE_DATA1, 0);
7167         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7168
7169         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7170                      500)) {
7171                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7172                 return -ETIMEDOUT;
7173         }
7174
7175         *val = I915_READ(GEN6_PCODE_DATA);
7176         I915_WRITE(GEN6_PCODE_DATA, 0);
7177
7178         return 0;
7179 }
7180
7181 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7182 {
7183         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7184
7185         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7186                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7187                 return -EAGAIN;
7188         }
7189
7190         I915_WRITE(GEN6_PCODE_DATA, val);
7191         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7192
7193         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7194                      500)) {
7195                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7196                 return -ETIMEDOUT;
7197         }
7198
7199         I915_WRITE(GEN6_PCODE_DATA, 0);
7200
7201         return 0;
7202 }
7203
7204 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7205 {
7206         switch (czclk_freq) {
7207         case 200:
7208                 return 10;
7209         case 267:
7210                 return 12;
7211         case 320:
7212         case 333:
7213                 return 16;
7214         case 400:
7215                 return 20;
7216         default:
7217                 return -1;
7218         }
7219 }
7220
7221 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7222 {
7223         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7224
7225         div = vlv_gpu_freq_div(czclk_freq);
7226         if (div < 0)
7227                 return div;
7228
7229         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7230 }
7231
7232 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7233 {
7234         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7235
7236         mul = vlv_gpu_freq_div(czclk_freq);
7237         if (mul < 0)
7238                 return mul;
7239
7240         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7241 }
7242
7243 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7244 {
7245         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7246
7247         div = vlv_gpu_freq_div(czclk_freq) / 2;
7248         if (div < 0)
7249                 return div;
7250
7251         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7252 }
7253
7254 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7255 {
7256         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7257
7258         mul = vlv_gpu_freq_div(czclk_freq) / 2;
7259         if (mul < 0)
7260                 return mul;
7261
7262         /* CHV needs even values */
7263         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7264 }
7265
7266 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7267 {
7268         if (IS_GEN9(dev_priv->dev))
7269                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7270                                          GEN9_FREQ_SCALER);
7271         else if (IS_CHERRYVIEW(dev_priv->dev))
7272                 return chv_gpu_freq(dev_priv, val);
7273         else if (IS_VALLEYVIEW(dev_priv->dev))
7274                 return byt_gpu_freq(dev_priv, val);
7275         else
7276                 return val * GT_FREQUENCY_MULTIPLIER;
7277 }
7278
7279 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7280 {
7281         if (IS_GEN9(dev_priv->dev))
7282                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7283                                          GT_FREQUENCY_MULTIPLIER);
7284         else if (IS_CHERRYVIEW(dev_priv->dev))
7285                 return chv_freq_opcode(dev_priv, val);
7286         else if (IS_VALLEYVIEW(dev_priv->dev))
7287                 return byt_freq_opcode(dev_priv, val);
7288         else
7289                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7290 }
7291
7292 struct request_boost {
7293         struct work_struct work;
7294         struct drm_i915_gem_request *req;
7295 };
7296
7297 static void __intel_rps_boost_work(struct work_struct *work)
7298 {
7299         struct request_boost *boost = container_of(work, struct request_boost, work);
7300         struct drm_i915_gem_request *req = boost->req;
7301
7302         if (!i915_gem_request_completed(req, true))
7303                 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7304                                req->emitted_jiffies);
7305
7306         i915_gem_request_unreference__unlocked(req);
7307         kfree(boost);
7308 }
7309
7310 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7311                                        struct drm_i915_gem_request *req)
7312 {
7313         struct request_boost *boost;
7314
7315         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7316                 return;
7317
7318         if (i915_gem_request_completed(req, true))
7319                 return;
7320
7321         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7322         if (boost == NULL)
7323                 return;
7324
7325         i915_gem_request_reference(req);
7326         boost->req = req;
7327
7328         INIT_WORK(&boost->work, __intel_rps_boost_work);
7329         queue_work(to_i915(dev)->wq, &boost->work);
7330 }
7331
7332 void intel_pm_setup(struct drm_device *dev)
7333 {
7334         struct drm_i915_private *dev_priv = dev->dev_private;
7335
7336         mutex_init(&dev_priv->rps.hw_lock);
7337         spin_lock_init(&dev_priv->rps.client_lock);
7338
7339         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7340                           intel_gen6_powersave_work);
7341         INIT_LIST_HEAD(&dev_priv->rps.clients);
7342         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7343         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7344
7345         dev_priv->pm.suspended = false;
7346 }