2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
69 static void i8xx_disable_fbc(struct drm_device *dev)
71 struct drm_i915_private *dev_priv = dev->dev_private;
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
88 DRM_DEBUG_KMS("disabled FBC\n");
91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->primary->fb;
96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
107 /* FBC_CTL wants 32B or 64B units */
109 cfb_pitch = (cfb_pitch / 32) - 1;
111 cfb_pitch = (cfb_pitch / 64) - 1;
114 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
115 I915_WRITE(FBC_TAG + (i * 4), 0);
121 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
122 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
123 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
124 I915_WRITE(FBC_FENCE_OFF, crtc->y);
128 fbc_ctl = I915_READ(FBC_CONTROL);
129 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
130 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
132 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
133 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
134 fbc_ctl |= obj->fence_reg;
135 I915_WRITE(FBC_CONTROL, fbc_ctl);
137 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
138 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
141 static bool i8xx_fbc_enabled(struct drm_device *dev)
143 struct drm_i915_private *dev_priv = dev->dev_private;
145 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
148 static void g4x_enable_fbc(struct drm_crtc *crtc)
150 struct drm_device *dev = crtc->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private;
152 struct drm_framebuffer *fb = crtc->primary->fb;
153 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
154 struct drm_i915_gem_object *obj = intel_fb->obj;
155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
158 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
159 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
160 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
162 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
163 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
165 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
168 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
170 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
173 static void g4x_disable_fbc(struct drm_device *dev)
175 struct drm_i915_private *dev_priv = dev->dev_private;
178 /* Disable compression */
179 dpfc_ctl = I915_READ(DPFC_CONTROL);
180 if (dpfc_ctl & DPFC_CTL_EN) {
181 dpfc_ctl &= ~DPFC_CTL_EN;
182 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
184 DRM_DEBUG_KMS("disabled FBC\n");
188 static bool g4x_fbc_enabled(struct drm_device *dev)
190 struct drm_i915_private *dev_priv = dev->dev_private;
192 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
195 static void sandybridge_blit_fbc_update(struct drm_device *dev)
197 struct drm_i915_private *dev_priv = dev->dev_private;
200 /* Make sure blitter notifies FBC of writes */
202 /* Blitter is part of Media powerwell on VLV. No impact of
203 * his param in other platforms for now */
204 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
206 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
207 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
208 GEN6_BLITTER_LOCK_SHIFT;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
211 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
212 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
213 GEN6_BLITTER_LOCK_SHIFT);
214 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
215 POSTING_READ(GEN6_BLITTER_ECOSKPD);
217 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
220 static void ironlake_enable_fbc(struct drm_crtc *crtc)
222 struct drm_device *dev = crtc->dev;
223 struct drm_i915_private *dev_priv = dev->dev_private;
224 struct drm_framebuffer *fb = crtc->primary->fb;
225 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
226 struct drm_i915_gem_object *obj = intel_fb->obj;
227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
230 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
231 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
232 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
234 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
237 dpfc_ctl |= obj->fence_reg;
239 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
240 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
245 I915_WRITE(SNB_DPFC_CTL_SA,
246 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
247 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
248 sandybridge_blit_fbc_update(dev);
251 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
254 static void ironlake_disable_fbc(struct drm_device *dev)
256 struct drm_i915_private *dev_priv = dev->dev_private;
259 /* Disable compression */
260 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
261 if (dpfc_ctl & DPFC_CTL_EN) {
262 dpfc_ctl &= ~DPFC_CTL_EN;
263 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
265 DRM_DEBUG_KMS("disabled FBC\n");
269 static bool ironlake_fbc_enabled(struct drm_device *dev)
271 struct drm_i915_private *dev_priv = dev->dev_private;
273 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
276 static void gen7_enable_fbc(struct drm_crtc *crtc)
278 struct drm_device *dev = crtc->dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
280 struct drm_framebuffer *fb = crtc->primary->fb;
281 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
282 struct drm_i915_gem_object *obj = intel_fb->obj;
283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
286 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
287 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
288 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
290 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
291 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
293 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
295 if (IS_IVYBRIDGE(dev)) {
296 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
297 I915_WRITE(ILK_DISPLAY_CHICKEN1,
298 I915_READ(ILK_DISPLAY_CHICKEN1) |
301 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
302 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
303 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
307 I915_WRITE(SNB_DPFC_CTL_SA,
308 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
309 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
311 sandybridge_blit_fbc_update(dev);
313 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
316 bool intel_fbc_enabled(struct drm_device *dev)
318 struct drm_i915_private *dev_priv = dev->dev_private;
320 if (!dev_priv->display.fbc_enabled)
323 return dev_priv->display.fbc_enabled(dev);
326 static void intel_fbc_work_fn(struct work_struct *__work)
328 struct intel_fbc_work *work =
329 container_of(to_delayed_work(__work),
330 struct intel_fbc_work, work);
331 struct drm_device *dev = work->crtc->dev;
332 struct drm_i915_private *dev_priv = dev->dev_private;
334 mutex_lock(&dev->struct_mutex);
335 if (work == dev_priv->fbc.fbc_work) {
336 /* Double check that we haven't switched fb without cancelling
339 if (work->crtc->primary->fb == work->fb) {
340 dev_priv->display.enable_fbc(work->crtc);
342 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
343 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
344 dev_priv->fbc.y = work->crtc->y;
347 dev_priv->fbc.fbc_work = NULL;
349 mutex_unlock(&dev->struct_mutex);
354 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
356 if (dev_priv->fbc.fbc_work == NULL)
359 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
361 /* Synchronisation is provided by struct_mutex and checking of
362 * dev_priv->fbc.fbc_work, so we can perform the cancellation
363 * entirely asynchronously.
365 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
366 /* tasklet was killed before being run, clean up */
367 kfree(dev_priv->fbc.fbc_work);
369 /* Mark the work as no longer wanted so that if it does
370 * wake-up (because the work was already running and waiting
371 * for our mutex), it will discover that is no longer
374 dev_priv->fbc.fbc_work = NULL;
377 static void intel_enable_fbc(struct drm_crtc *crtc)
379 struct intel_fbc_work *work;
380 struct drm_device *dev = crtc->dev;
381 struct drm_i915_private *dev_priv = dev->dev_private;
383 if (!dev_priv->display.enable_fbc)
386 intel_cancel_fbc_work(dev_priv);
388 work = kzalloc(sizeof(*work), GFP_KERNEL);
390 DRM_ERROR("Failed to allocate FBC work structure\n");
391 dev_priv->display.enable_fbc(crtc);
396 work->fb = crtc->primary->fb;
397 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
399 dev_priv->fbc.fbc_work = work;
401 /* Delay the actual enabling to let pageflipping cease and the
402 * display to settle before starting the compression. Note that
403 * this delay also serves a second purpose: it allows for a
404 * vblank to pass after disabling the FBC before we attempt
405 * to modify the control registers.
407 * A more complicated solution would involve tracking vblanks
408 * following the termination of the page-flipping sequence
409 * and indeed performing the enable as a co-routine and not
410 * waiting synchronously upon the vblank.
412 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
414 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
417 void intel_disable_fbc(struct drm_device *dev)
419 struct drm_i915_private *dev_priv = dev->dev_private;
421 intel_cancel_fbc_work(dev_priv);
423 if (!dev_priv->display.disable_fbc)
426 dev_priv->display.disable_fbc(dev);
427 dev_priv->fbc.plane = -1;
430 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
431 enum no_fbc_reason reason)
433 if (dev_priv->fbc.no_fbc_reason == reason)
436 dev_priv->fbc.no_fbc_reason = reason;
441 * intel_update_fbc - enable/disable FBC as needed
442 * @dev: the drm_device
444 * Set up the framebuffer compression hardware at mode set time. We
445 * enable it if possible:
446 * - plane A only (on pre-965)
447 * - no pixel mulitply/line duplication
448 * - no alpha buffer discard
450 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
452 * We can't assume that any compression will take place (worst case),
453 * so the compressed buffer has to be the same size as the uncompressed
454 * one. It also must reside (along with the line length buffer) in
457 * We need to enable/disable FBC on a global basis.
459 void intel_update_fbc(struct drm_device *dev)
461 struct drm_i915_private *dev_priv = dev->dev_private;
462 struct drm_crtc *crtc = NULL, *tmp_crtc;
463 struct intel_crtc *intel_crtc;
464 struct drm_framebuffer *fb;
465 struct intel_framebuffer *intel_fb;
466 struct drm_i915_gem_object *obj;
467 const struct drm_display_mode *adjusted_mode;
468 unsigned int max_width, max_height;
471 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
475 if (!i915.powersave) {
476 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
477 DRM_DEBUG_KMS("fbc disabled per module param\n");
482 * If FBC is already on, we just have to verify that we can
483 * keep it that way...
484 * Need to disable if:
485 * - more than one pipe is active
486 * - changing FBC params (stride, fence, mode)
487 * - new fb is too large to fit in compressed buffer
488 * - going to an unsupported config (interlace, pixel multiply, etc.)
490 for_each_crtc(dev, tmp_crtc) {
491 if (intel_crtc_active(tmp_crtc) &&
492 to_intel_crtc(tmp_crtc)->primary_enabled) {
494 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
495 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
502 if (!crtc || crtc->primary->fb == NULL) {
503 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
504 DRM_DEBUG_KMS("no output, disabling\n");
508 intel_crtc = to_intel_crtc(crtc);
509 fb = crtc->primary->fb;
510 intel_fb = to_intel_framebuffer(fb);
512 adjusted_mode = &intel_crtc->config.adjusted_mode;
514 if (i915.enable_fbc < 0) {
515 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
516 DRM_DEBUG_KMS("disabled per chip default\n");
519 if (!i915.enable_fbc) {
520 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
521 DRM_DEBUG_KMS("fbc disabled per module param\n");
524 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
525 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
526 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
527 DRM_DEBUG_KMS("mode incompatible with compression, "
532 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
539 if (intel_crtc->config.pipe_src_w > max_width ||
540 intel_crtc->config.pipe_src_h > max_height) {
541 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
542 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
545 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
546 intel_crtc->plane != PLANE_A) {
547 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
548 DRM_DEBUG_KMS("plane not A, disabling compression\n");
552 /* The use of a CPU fence is mandatory in order to detect writes
553 * by the CPU to the scanout and trigger updates to the FBC.
555 if (obj->tiling_mode != I915_TILING_X ||
556 obj->fence_reg == I915_FENCE_REG_NONE) {
557 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
558 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
562 /* If the kernel debugger is active, always disable compression */
566 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
567 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
568 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
572 /* If the scanout has not changed, don't modify the FBC settings.
573 * Note that we make the fundamental assumption that the fb->obj
574 * cannot be unpinned (and have its GTT offset and fence revoked)
575 * without first being decoupled from the scanout and FBC disabled.
577 if (dev_priv->fbc.plane == intel_crtc->plane &&
578 dev_priv->fbc.fb_id == fb->base.id &&
579 dev_priv->fbc.y == crtc->y)
582 if (intel_fbc_enabled(dev)) {
583 /* We update FBC along two paths, after changing fb/crtc
584 * configuration (modeswitching) and after page-flipping
585 * finishes. For the latter, we know that not only did
586 * we disable the FBC at the start of the page-flip
587 * sequence, but also more than one vblank has passed.
589 * For the former case of modeswitching, it is possible
590 * to switch between two FBC valid configurations
591 * instantaneously so we do need to disable the FBC
592 * before we can modify its control registers. We also
593 * have to wait for the next vblank for that to take
594 * effect. However, since we delay enabling FBC we can
595 * assume that a vblank has passed since disabling and
596 * that we can safely alter the registers in the deferred
599 * In the scenario that we go from a valid to invalid
600 * and then back to valid FBC configuration we have
601 * no strict enforcement that a vblank occurred since
602 * disabling the FBC. However, along all current pipe
603 * disabling paths we do need to wait for a vblank at
604 * some point. And we wait before enabling FBC anyway.
606 DRM_DEBUG_KMS("disabling active FBC for update\n");
607 intel_disable_fbc(dev);
610 intel_enable_fbc(crtc);
611 dev_priv->fbc.no_fbc_reason = FBC_OK;
615 /* Multiple disables should be harmless */
616 if (intel_fbc_enabled(dev)) {
617 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
618 intel_disable_fbc(dev);
620 i915_gem_stolen_cleanup_compression(dev);
623 static void i915_pineview_get_mem_freq(struct drm_device *dev)
625 struct drm_i915_private *dev_priv = dev->dev_private;
628 tmp = I915_READ(CLKCFG);
630 switch (tmp & CLKCFG_FSB_MASK) {
632 dev_priv->fsb_freq = 533; /* 133*4 */
635 dev_priv->fsb_freq = 800; /* 200*4 */
638 dev_priv->fsb_freq = 667; /* 167*4 */
641 dev_priv->fsb_freq = 400; /* 100*4 */
645 switch (tmp & CLKCFG_MEM_MASK) {
647 dev_priv->mem_freq = 533;
650 dev_priv->mem_freq = 667;
653 dev_priv->mem_freq = 800;
657 /* detect pineview DDR3 setting */
658 tmp = I915_READ(CSHRDDR3CTL);
659 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
662 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
664 struct drm_i915_private *dev_priv = dev->dev_private;
667 ddrpll = I915_READ16(DDRMPLL1);
668 csipll = I915_READ16(CSIPLL0);
670 switch (ddrpll & 0xff) {
672 dev_priv->mem_freq = 800;
675 dev_priv->mem_freq = 1066;
678 dev_priv->mem_freq = 1333;
681 dev_priv->mem_freq = 1600;
684 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
686 dev_priv->mem_freq = 0;
690 dev_priv->ips.r_t = dev_priv->mem_freq;
692 switch (csipll & 0x3ff) {
694 dev_priv->fsb_freq = 3200;
697 dev_priv->fsb_freq = 3733;
700 dev_priv->fsb_freq = 4266;
703 dev_priv->fsb_freq = 4800;
706 dev_priv->fsb_freq = 5333;
709 dev_priv->fsb_freq = 5866;
712 dev_priv->fsb_freq = 6400;
715 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
717 dev_priv->fsb_freq = 0;
721 if (dev_priv->fsb_freq == 3200) {
722 dev_priv->ips.c_m = 0;
723 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
724 dev_priv->ips.c_m = 1;
726 dev_priv->ips.c_m = 2;
730 static const struct cxsr_latency cxsr_latency_table[] = {
731 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
732 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
733 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
734 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
735 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
737 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
738 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
739 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
740 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
741 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
743 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
744 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
745 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
746 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
747 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
749 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
750 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
751 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
752 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
753 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
755 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
756 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
757 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
758 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
759 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
761 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
762 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
763 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
764 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
765 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
768 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
773 const struct cxsr_latency *latency;
776 if (fsb == 0 || mem == 0)
779 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
780 latency = &cxsr_latency_table[i];
781 if (is_desktop == latency->is_desktop &&
782 is_ddr3 == latency->is_ddr3 &&
783 fsb == latency->fsb_freq && mem == latency->mem_freq)
787 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
792 static void pineview_disable_cxsr(struct drm_device *dev)
794 struct drm_i915_private *dev_priv = dev->dev_private;
796 /* deactivate cxsr */
797 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
801 * Latency for FIFO fetches is dependent on several factors:
802 * - memory configuration (speed, channels)
804 * - current MCH state
805 * It can be fairly high in some situations, so here we assume a fairly
806 * pessimal value. It's a tradeoff between extra memory fetches (if we
807 * set this value too high, the FIFO will fetch frequently to stay full)
808 * and power consumption (set it too low to save power and we might see
809 * FIFO underruns and display "flicker").
811 * A value of 5us seems to be a good balance; safe for very low end
812 * platforms but not overly aggressive on lower latency configs.
814 static const int latency_ns = 5000;
816 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
818 struct drm_i915_private *dev_priv = dev->dev_private;
819 uint32_t dsparb = I915_READ(DSPARB);
822 size = dsparb & 0x7f;
824 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
826 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
827 plane ? "B" : "A", size);
832 static int i830_get_fifo_size(struct drm_device *dev, int plane)
834 struct drm_i915_private *dev_priv = dev->dev_private;
835 uint32_t dsparb = I915_READ(DSPARB);
838 size = dsparb & 0x1ff;
840 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
841 size >>= 1; /* Convert to cachelines */
843 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
844 plane ? "B" : "A", size);
849 static int i845_get_fifo_size(struct drm_device *dev, int plane)
851 struct drm_i915_private *dev_priv = dev->dev_private;
852 uint32_t dsparb = I915_READ(DSPARB);
855 size = dsparb & 0x7f;
856 size >>= 2; /* Convert to cachelines */
858 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
865 /* Pineview has different values for various configs */
866 static const struct intel_watermark_params pineview_display_wm = {
867 PINEVIEW_DISPLAY_FIFO,
871 PINEVIEW_FIFO_LINE_SIZE
873 static const struct intel_watermark_params pineview_display_hplloff_wm = {
874 PINEVIEW_DISPLAY_FIFO,
876 PINEVIEW_DFT_HPLLOFF_WM,
878 PINEVIEW_FIFO_LINE_SIZE
880 static const struct intel_watermark_params pineview_cursor_wm = {
881 PINEVIEW_CURSOR_FIFO,
882 PINEVIEW_CURSOR_MAX_WM,
883 PINEVIEW_CURSOR_DFT_WM,
884 PINEVIEW_CURSOR_GUARD_WM,
885 PINEVIEW_FIFO_LINE_SIZE,
887 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
888 PINEVIEW_CURSOR_FIFO,
889 PINEVIEW_CURSOR_MAX_WM,
890 PINEVIEW_CURSOR_DFT_WM,
891 PINEVIEW_CURSOR_GUARD_WM,
892 PINEVIEW_FIFO_LINE_SIZE
894 static const struct intel_watermark_params g4x_wm_info = {
901 static const struct intel_watermark_params g4x_cursor_wm_info = {
908 static const struct intel_watermark_params valleyview_wm_info = {
909 VALLEYVIEW_FIFO_SIZE,
915 static const struct intel_watermark_params valleyview_cursor_wm_info = {
917 VALLEYVIEW_CURSOR_MAX_WM,
922 static const struct intel_watermark_params i965_cursor_wm_info = {
929 static const struct intel_watermark_params i945_wm_info = {
936 static const struct intel_watermark_params i915_wm_info = {
943 static const struct intel_watermark_params i830_wm_info = {
950 static const struct intel_watermark_params i845_wm_info = {
959 * intel_calculate_wm - calculate watermark level
960 * @clock_in_khz: pixel clock
961 * @wm: chip FIFO params
962 * @pixel_size: display pixel size
963 * @latency_ns: memory latency for the platform
965 * Calculate the watermark level (the level at which the display plane will
966 * start fetching from memory again). Each chip has a different display
967 * FIFO size and allocation, so the caller needs to figure that out and pass
968 * in the correct intel_watermark_params structure.
970 * As the pixel clock runs, the FIFO will be drained at a rate that depends
971 * on the pixel size. When it reaches the watermark level, it'll start
972 * fetching FIFO line sized based chunks from memory until the FIFO fills
973 * past the watermark point. If the FIFO drains completely, a FIFO underrun
974 * will occur, and a display engine hang could result.
976 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
977 const struct intel_watermark_params *wm,
980 unsigned long latency_ns)
982 long entries_required, wm_size;
985 * Note: we need to make sure we don't overflow for various clock &
987 * clocks go from a few thousand to several hundred thousand.
988 * latency is usually a few thousand
990 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
992 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
994 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
996 wm_size = fifo_size - (entries_required + wm->guard_size);
998 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1000 /* Don't promote wm_size to unsigned... */
1001 if (wm_size > (long)wm->max_wm)
1002 wm_size = wm->max_wm;
1004 wm_size = wm->default_wm;
1008 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1010 struct drm_crtc *crtc, *enabled = NULL;
1012 for_each_crtc(dev, crtc) {
1013 if (intel_crtc_active(crtc)) {
1023 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1025 struct drm_device *dev = unused_crtc->dev;
1026 struct drm_i915_private *dev_priv = dev->dev_private;
1027 struct drm_crtc *crtc;
1028 const struct cxsr_latency *latency;
1032 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1033 dev_priv->fsb_freq, dev_priv->mem_freq);
1035 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1036 pineview_disable_cxsr(dev);
1040 crtc = single_enabled_crtc(dev);
1042 const struct drm_display_mode *adjusted_mode;
1043 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1046 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1047 clock = adjusted_mode->crtc_clock;
1050 wm = intel_calculate_wm(clock, &pineview_display_wm,
1051 pineview_display_wm.fifo_size,
1052 pixel_size, latency->display_sr);
1053 reg = I915_READ(DSPFW1);
1054 reg &= ~DSPFW_SR_MASK;
1055 reg |= wm << DSPFW_SR_SHIFT;
1056 I915_WRITE(DSPFW1, reg);
1057 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1060 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1061 pineview_display_wm.fifo_size,
1062 pixel_size, latency->cursor_sr);
1063 reg = I915_READ(DSPFW3);
1064 reg &= ~DSPFW_CURSOR_SR_MASK;
1065 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1066 I915_WRITE(DSPFW3, reg);
1068 /* Display HPLL off SR */
1069 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1070 pineview_display_hplloff_wm.fifo_size,
1071 pixel_size, latency->display_hpll_disable);
1072 reg = I915_READ(DSPFW3);
1073 reg &= ~DSPFW_HPLL_SR_MASK;
1074 reg |= wm & DSPFW_HPLL_SR_MASK;
1075 I915_WRITE(DSPFW3, reg);
1077 /* cursor HPLL off SR */
1078 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1079 pineview_display_hplloff_wm.fifo_size,
1080 pixel_size, latency->cursor_hpll_disable);
1081 reg = I915_READ(DSPFW3);
1082 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1083 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1084 I915_WRITE(DSPFW3, reg);
1085 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1089 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1090 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1092 pineview_disable_cxsr(dev);
1093 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1097 static bool g4x_compute_wm0(struct drm_device *dev,
1099 const struct intel_watermark_params *display,
1100 int display_latency_ns,
1101 const struct intel_watermark_params *cursor,
1102 int cursor_latency_ns,
1106 struct drm_crtc *crtc;
1107 const struct drm_display_mode *adjusted_mode;
1108 int htotal, hdisplay, clock, pixel_size;
1109 int line_time_us, line_count;
1110 int entries, tlb_miss;
1112 crtc = intel_get_crtc_for_plane(dev, plane);
1113 if (!intel_crtc_active(crtc)) {
1114 *cursor_wm = cursor->guard_size;
1115 *plane_wm = display->guard_size;
1119 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1120 clock = adjusted_mode->crtc_clock;
1121 htotal = adjusted_mode->crtc_htotal;
1122 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1123 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1125 /* Use the small buffer method to calculate plane watermark */
1126 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1127 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1129 entries += tlb_miss;
1130 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1131 *plane_wm = entries + display->guard_size;
1132 if (*plane_wm > (int)display->max_wm)
1133 *plane_wm = display->max_wm;
1135 /* Use the large buffer method to calculate cursor watermark */
1136 line_time_us = max(htotal * 1000 / clock, 1);
1137 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1138 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1139 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1141 entries += tlb_miss;
1142 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1143 *cursor_wm = entries + cursor->guard_size;
1144 if (*cursor_wm > (int)cursor->max_wm)
1145 *cursor_wm = (int)cursor->max_wm;
1151 * Check the wm result.
1153 * If any calculated watermark values is larger than the maximum value that
1154 * can be programmed into the associated watermark register, that watermark
1157 static bool g4x_check_srwm(struct drm_device *dev,
1158 int display_wm, int cursor_wm,
1159 const struct intel_watermark_params *display,
1160 const struct intel_watermark_params *cursor)
1162 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1163 display_wm, cursor_wm);
1165 if (display_wm > display->max_wm) {
1166 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1167 display_wm, display->max_wm);
1171 if (cursor_wm > cursor->max_wm) {
1172 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1173 cursor_wm, cursor->max_wm);
1177 if (!(display_wm || cursor_wm)) {
1178 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1185 static bool g4x_compute_srwm(struct drm_device *dev,
1188 const struct intel_watermark_params *display,
1189 const struct intel_watermark_params *cursor,
1190 int *display_wm, int *cursor_wm)
1192 struct drm_crtc *crtc;
1193 const struct drm_display_mode *adjusted_mode;
1194 int hdisplay, htotal, pixel_size, clock;
1195 unsigned long line_time_us;
1196 int line_count, line_size;
1201 *display_wm = *cursor_wm = 0;
1205 crtc = intel_get_crtc_for_plane(dev, plane);
1206 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1207 clock = adjusted_mode->crtc_clock;
1208 htotal = adjusted_mode->crtc_htotal;
1209 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1210 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1212 line_time_us = max(htotal * 1000 / clock, 1);
1213 line_count = (latency_ns / line_time_us + 1000) / 1000;
1214 line_size = hdisplay * pixel_size;
1216 /* Use the minimum of the small and large buffer method for primary */
1217 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1218 large = line_count * line_size;
1220 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1221 *display_wm = entries + display->guard_size;
1223 /* calculate the self-refresh watermark for display cursor */
1224 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1225 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1226 *cursor_wm = entries + cursor->guard_size;
1228 return g4x_check_srwm(dev,
1229 *display_wm, *cursor_wm,
1233 static bool vlv_compute_drain_latency(struct drm_device *dev,
1235 int *plane_prec_mult,
1237 int *cursor_prec_mult,
1240 struct drm_crtc *crtc;
1241 int clock, pixel_size;
1244 crtc = intel_get_crtc_for_plane(dev, plane);
1245 if (!intel_crtc_active(crtc))
1248 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1249 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1251 entries = (clock / 1000) * pixel_size;
1252 *plane_prec_mult = (entries > 256) ?
1253 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1254 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1257 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1258 *cursor_prec_mult = (entries > 256) ?
1259 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1260 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1266 * Update drain latency registers of memory arbiter
1268 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1269 * to be programmed. Each plane has a drain latency multiplier and a drain
1273 static void vlv_update_drain_latency(struct drm_device *dev)
1275 struct drm_i915_private *dev_priv = dev->dev_private;
1276 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1277 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1278 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1281 /* For plane A, Cursor A */
1282 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1283 &cursor_prec_mult, &cursora_dl)) {
1284 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1285 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1286 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1287 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1289 I915_WRITE(VLV_DDL1, cursora_prec |
1290 (cursora_dl << DDL_CURSORA_SHIFT) |
1291 planea_prec | planea_dl);
1294 /* For plane B, Cursor B */
1295 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1296 &cursor_prec_mult, &cursorb_dl)) {
1297 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1298 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1299 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1300 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1302 I915_WRITE(VLV_DDL2, cursorb_prec |
1303 (cursorb_dl << DDL_CURSORB_SHIFT) |
1304 planeb_prec | planeb_dl);
1308 #define single_plane_enabled(mask) is_power_of_2(mask)
1310 static void valleyview_update_wm(struct drm_crtc *crtc)
1312 struct drm_device *dev = crtc->dev;
1313 static const int sr_latency_ns = 12000;
1314 struct drm_i915_private *dev_priv = dev->dev_private;
1315 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1316 int plane_sr, cursor_sr;
1317 int ignore_plane_sr, ignore_cursor_sr;
1318 unsigned int enabled = 0;
1320 vlv_update_drain_latency(dev);
1322 if (g4x_compute_wm0(dev, PIPE_A,
1323 &valleyview_wm_info, latency_ns,
1324 &valleyview_cursor_wm_info, latency_ns,
1325 &planea_wm, &cursora_wm))
1326 enabled |= 1 << PIPE_A;
1328 if (g4x_compute_wm0(dev, PIPE_B,
1329 &valleyview_wm_info, latency_ns,
1330 &valleyview_cursor_wm_info, latency_ns,
1331 &planeb_wm, &cursorb_wm))
1332 enabled |= 1 << PIPE_B;
1334 if (single_plane_enabled(enabled) &&
1335 g4x_compute_srwm(dev, ffs(enabled) - 1,
1337 &valleyview_wm_info,
1338 &valleyview_cursor_wm_info,
1339 &plane_sr, &ignore_cursor_sr) &&
1340 g4x_compute_srwm(dev, ffs(enabled) - 1,
1342 &valleyview_wm_info,
1343 &valleyview_cursor_wm_info,
1344 &ignore_plane_sr, &cursor_sr)) {
1345 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1347 I915_WRITE(FW_BLC_SELF_VLV,
1348 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1349 plane_sr = cursor_sr = 0;
1352 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1353 planea_wm, cursora_wm,
1354 planeb_wm, cursorb_wm,
1355 plane_sr, cursor_sr);
1358 (plane_sr << DSPFW_SR_SHIFT) |
1359 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1360 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1363 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1364 (cursora_wm << DSPFW_CURSORA_SHIFT));
1366 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1367 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1370 static void g4x_update_wm(struct drm_crtc *crtc)
1372 struct drm_device *dev = crtc->dev;
1373 static const int sr_latency_ns = 12000;
1374 struct drm_i915_private *dev_priv = dev->dev_private;
1375 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1376 int plane_sr, cursor_sr;
1377 unsigned int enabled = 0;
1379 if (g4x_compute_wm0(dev, PIPE_A,
1380 &g4x_wm_info, latency_ns,
1381 &g4x_cursor_wm_info, latency_ns,
1382 &planea_wm, &cursora_wm))
1383 enabled |= 1 << PIPE_A;
1385 if (g4x_compute_wm0(dev, PIPE_B,
1386 &g4x_wm_info, latency_ns,
1387 &g4x_cursor_wm_info, latency_ns,
1388 &planeb_wm, &cursorb_wm))
1389 enabled |= 1 << PIPE_B;
1391 if (single_plane_enabled(enabled) &&
1392 g4x_compute_srwm(dev, ffs(enabled) - 1,
1395 &g4x_cursor_wm_info,
1396 &plane_sr, &cursor_sr)) {
1397 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1399 I915_WRITE(FW_BLC_SELF,
1400 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1401 plane_sr = cursor_sr = 0;
1404 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1405 planea_wm, cursora_wm,
1406 planeb_wm, cursorb_wm,
1407 plane_sr, cursor_sr);
1410 (plane_sr << DSPFW_SR_SHIFT) |
1411 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1412 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1415 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1416 (cursora_wm << DSPFW_CURSORA_SHIFT));
1417 /* HPLL off in SR has some issues on G4x... disable it */
1419 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1420 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1423 static void i965_update_wm(struct drm_crtc *unused_crtc)
1425 struct drm_device *dev = unused_crtc->dev;
1426 struct drm_i915_private *dev_priv = dev->dev_private;
1427 struct drm_crtc *crtc;
1431 /* Calc sr entries for one plane configs */
1432 crtc = single_enabled_crtc(dev);
1434 /* self-refresh has much higher latency */
1435 static const int sr_latency_ns = 12000;
1436 const struct drm_display_mode *adjusted_mode =
1437 &to_intel_crtc(crtc)->config.adjusted_mode;
1438 int clock = adjusted_mode->crtc_clock;
1439 int htotal = adjusted_mode->crtc_htotal;
1440 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1441 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1442 unsigned long line_time_us;
1445 line_time_us = max(htotal * 1000 / clock, 1);
1447 /* Use ns/us then divide to preserve precision */
1448 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1449 pixel_size * hdisplay;
1450 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1451 srwm = I965_FIFO_SIZE - entries;
1455 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1458 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1459 pixel_size * to_intel_crtc(crtc)->cursor_width;
1460 entries = DIV_ROUND_UP(entries,
1461 i965_cursor_wm_info.cacheline_size);
1462 cursor_sr = i965_cursor_wm_info.fifo_size -
1463 (entries + i965_cursor_wm_info.guard_size);
1465 if (cursor_sr > i965_cursor_wm_info.max_wm)
1466 cursor_sr = i965_cursor_wm_info.max_wm;
1468 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1469 "cursor %d\n", srwm, cursor_sr);
1471 if (IS_CRESTLINE(dev))
1472 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1474 /* Turn off self refresh if both pipes are enabled */
1475 if (IS_CRESTLINE(dev))
1476 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1480 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1483 /* 965 has limitations... */
1484 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1485 (8 << 16) | (8 << 8) | (8 << 0));
1486 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1487 /* update cursor SR watermark */
1488 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1491 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1493 struct drm_device *dev = unused_crtc->dev;
1494 struct drm_i915_private *dev_priv = dev->dev_private;
1495 const struct intel_watermark_params *wm_info;
1500 int planea_wm, planeb_wm;
1501 struct drm_crtc *crtc, *enabled = NULL;
1504 wm_info = &i945_wm_info;
1505 else if (!IS_GEN2(dev))
1506 wm_info = &i915_wm_info;
1508 wm_info = &i830_wm_info;
1510 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1511 crtc = intel_get_crtc_for_plane(dev, 0);
1512 if (intel_crtc_active(crtc)) {
1513 const struct drm_display_mode *adjusted_mode;
1514 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1518 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1519 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1520 wm_info, fifo_size, cpp,
1524 planea_wm = fifo_size - wm_info->guard_size;
1526 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1527 crtc = intel_get_crtc_for_plane(dev, 1);
1528 if (intel_crtc_active(crtc)) {
1529 const struct drm_display_mode *adjusted_mode;
1530 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1534 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1535 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1536 wm_info, fifo_size, cpp,
1538 if (enabled == NULL)
1543 planeb_wm = fifo_size - wm_info->guard_size;
1545 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547 if (IS_I915GM(dev) && enabled) {
1548 struct intel_framebuffer *fb;
1550 fb = to_intel_framebuffer(enabled->primary->fb);
1552 /* self-refresh seems busted with untiled */
1553 if (fb->obj->tiling_mode == I915_TILING_NONE)
1558 * Overlay gets an aggressive default since video jitter is bad.
1562 /* Play safe and disable self-refresh before adjusting watermarks. */
1563 if (IS_I945G(dev) || IS_I945GM(dev))
1564 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1565 else if (IS_I915GM(dev))
1566 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
1568 /* Calc sr entries for one plane configs */
1569 if (HAS_FW_BLC(dev) && enabled) {
1570 /* self-refresh has much higher latency */
1571 static const int sr_latency_ns = 6000;
1572 const struct drm_display_mode *adjusted_mode =
1573 &to_intel_crtc(enabled)->config.adjusted_mode;
1574 int clock = adjusted_mode->crtc_clock;
1575 int htotal = adjusted_mode->crtc_htotal;
1576 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1577 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1578 unsigned long line_time_us;
1581 line_time_us = max(htotal * 1000 / clock, 1);
1583 /* Use ns/us then divide to preserve precision */
1584 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1585 pixel_size * hdisplay;
1586 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1587 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1588 srwm = wm_info->fifo_size - entries;
1592 if (IS_I945G(dev) || IS_I945GM(dev))
1593 I915_WRITE(FW_BLC_SELF,
1594 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1595 else if (IS_I915GM(dev))
1596 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1599 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1600 planea_wm, planeb_wm, cwm, srwm);
1602 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1603 fwater_hi = (cwm & 0x1f);
1605 /* Set request length to 8 cachelines per fetch */
1606 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1607 fwater_hi = fwater_hi | (1 << 8);
1609 I915_WRITE(FW_BLC, fwater_lo);
1610 I915_WRITE(FW_BLC2, fwater_hi);
1612 if (HAS_FW_BLC(dev)) {
1614 if (IS_I945G(dev) || IS_I945GM(dev))
1615 I915_WRITE(FW_BLC_SELF,
1616 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1617 else if (IS_I915GM(dev))
1618 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
1619 DRM_DEBUG_KMS("memory self refresh enabled\n");
1621 DRM_DEBUG_KMS("memory self refresh disabled\n");
1625 static void i845_update_wm(struct drm_crtc *unused_crtc)
1627 struct drm_device *dev = unused_crtc->dev;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629 struct drm_crtc *crtc;
1630 const struct drm_display_mode *adjusted_mode;
1634 crtc = single_enabled_crtc(dev);
1638 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1639 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1641 dev_priv->display.get_fifo_size(dev, 0),
1643 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1644 fwater_lo |= (3<<8) | planea_wm;
1646 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1648 I915_WRITE(FW_BLC, fwater_lo);
1651 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1652 struct drm_crtc *crtc)
1654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1655 uint32_t pixel_rate;
1657 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1659 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1660 * adjust the pixel_rate here. */
1662 if (intel_crtc->config.pch_pfit.enabled) {
1663 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1664 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1666 pipe_w = intel_crtc->config.pipe_src_w;
1667 pipe_h = intel_crtc->config.pipe_src_h;
1668 pfit_w = (pfit_size >> 16) & 0xFFFF;
1669 pfit_h = pfit_size & 0xFFFF;
1670 if (pipe_w < pfit_w)
1672 if (pipe_h < pfit_h)
1675 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1682 /* latency must be in 0.1us units. */
1683 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1688 if (WARN(latency == 0, "Latency value missing\n"))
1691 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1692 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1697 /* latency must be in 0.1us units. */
1698 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1699 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1704 if (WARN(latency == 0, "Latency value missing\n"))
1707 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1708 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1709 ret = DIV_ROUND_UP(ret, 64) + 2;
1713 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1714 uint8_t bytes_per_pixel)
1716 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1719 struct ilk_pipe_wm_parameters {
1721 uint32_t pipe_htotal;
1722 uint32_t pixel_rate;
1723 struct intel_plane_wm_parameters pri;
1724 struct intel_plane_wm_parameters spr;
1725 struct intel_plane_wm_parameters cur;
1728 struct ilk_wm_maximums {
1735 /* used in computing the new watermarks state */
1736 struct intel_wm_config {
1737 unsigned int num_pipes_active;
1738 bool sprites_enabled;
1739 bool sprites_scaled;
1743 * For both WM_PIPE and WM_LP.
1744 * mem_value must be in 0.1us units.
1746 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1750 uint32_t method1, method2;
1752 if (!params->active || !params->pri.enabled)
1755 method1 = ilk_wm_method1(params->pixel_rate,
1756 params->pri.bytes_per_pixel,
1762 method2 = ilk_wm_method2(params->pixel_rate,
1763 params->pipe_htotal,
1764 params->pri.horiz_pixels,
1765 params->pri.bytes_per_pixel,
1768 return min(method1, method2);
1772 * For both WM_PIPE and WM_LP.
1773 * mem_value must be in 0.1us units.
1775 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1778 uint32_t method1, method2;
1780 if (!params->active || !params->spr.enabled)
1783 method1 = ilk_wm_method1(params->pixel_rate,
1784 params->spr.bytes_per_pixel,
1786 method2 = ilk_wm_method2(params->pixel_rate,
1787 params->pipe_htotal,
1788 params->spr.horiz_pixels,
1789 params->spr.bytes_per_pixel,
1791 return min(method1, method2);
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1798 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1801 if (!params->active || !params->cur.enabled)
1804 return ilk_wm_method2(params->pixel_rate,
1805 params->pipe_htotal,
1806 params->cur.horiz_pixels,
1807 params->cur.bytes_per_pixel,
1811 /* Only for WM_LP. */
1812 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1815 if (!params->active || !params->pri.enabled)
1818 return ilk_wm_fbc(pri_val,
1819 params->pri.horiz_pixels,
1820 params->pri.bytes_per_pixel);
1823 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1825 if (INTEL_INFO(dev)->gen >= 8)
1827 else if (INTEL_INFO(dev)->gen >= 7)
1833 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1834 int level, bool is_sprite)
1836 if (INTEL_INFO(dev)->gen >= 8)
1837 /* BDW primary/sprite plane watermarks */
1838 return level == 0 ? 255 : 2047;
1839 else if (INTEL_INFO(dev)->gen >= 7)
1840 /* IVB/HSW primary/sprite plane watermarks */
1841 return level == 0 ? 127 : 1023;
1842 else if (!is_sprite)
1843 /* ILK/SNB primary plane watermarks */
1844 return level == 0 ? 127 : 511;
1846 /* ILK/SNB sprite plane watermarks */
1847 return level == 0 ? 63 : 255;
1850 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1853 if (INTEL_INFO(dev)->gen >= 7)
1854 return level == 0 ? 63 : 255;
1856 return level == 0 ? 31 : 63;
1859 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1861 if (INTEL_INFO(dev)->gen >= 8)
1867 /* Calculate the maximum primary/sprite plane watermark */
1868 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1870 const struct intel_wm_config *config,
1871 enum intel_ddb_partitioning ddb_partitioning,
1874 unsigned int fifo_size = ilk_display_fifo_size(dev);
1876 /* if sprites aren't enabled, sprites get nothing */
1877 if (is_sprite && !config->sprites_enabled)
1880 /* HSW allows LP1+ watermarks even with multiple pipes */
1881 if (level == 0 || config->num_pipes_active > 1) {
1882 fifo_size /= INTEL_INFO(dev)->num_pipes;
1885 * For some reason the non self refresh
1886 * FIFO size is only half of the self
1887 * refresh FIFO size on ILK/SNB.
1889 if (INTEL_INFO(dev)->gen <= 6)
1893 if (config->sprites_enabled) {
1894 /* level 0 is always calculated with 1:1 split */
1895 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1904 /* clamp to max that the registers can hold */
1905 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1908 /* Calculate the maximum cursor plane watermark */
1909 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1911 const struct intel_wm_config *config)
1913 /* HSW LP1+ watermarks w/ multiple pipes */
1914 if (level > 0 && config->num_pipes_active > 1)
1917 /* otherwise just report max that registers can hold */
1918 return ilk_cursor_wm_reg_max(dev, level);
1921 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1923 const struct intel_wm_config *config,
1924 enum intel_ddb_partitioning ddb_partitioning,
1925 struct ilk_wm_maximums *max)
1927 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1928 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1929 max->cur = ilk_cursor_wm_max(dev, level, config);
1930 max->fbc = ilk_fbc_wm_reg_max(dev);
1933 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1935 struct ilk_wm_maximums *max)
1937 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1938 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1939 max->cur = ilk_cursor_wm_reg_max(dev, level);
1940 max->fbc = ilk_fbc_wm_reg_max(dev);
1943 static bool ilk_validate_wm_level(int level,
1944 const struct ilk_wm_maximums *max,
1945 struct intel_wm_level *result)
1949 /* already determined to be invalid? */
1950 if (!result->enable)
1953 result->enable = result->pri_val <= max->pri &&
1954 result->spr_val <= max->spr &&
1955 result->cur_val <= max->cur;
1957 ret = result->enable;
1960 * HACK until we can pre-compute everything,
1961 * and thus fail gracefully if LP0 watermarks
1964 if (level == 0 && !result->enable) {
1965 if (result->pri_val > max->pri)
1966 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1967 level, result->pri_val, max->pri);
1968 if (result->spr_val > max->spr)
1969 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1970 level, result->spr_val, max->spr);
1971 if (result->cur_val > max->cur)
1972 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1973 level, result->cur_val, max->cur);
1975 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1976 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1977 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1978 result->enable = true;
1984 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1986 const struct ilk_pipe_wm_parameters *p,
1987 struct intel_wm_level *result)
1989 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1990 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1991 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1993 /* WM1+ latency values stored in 0.5us units */
2000 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2001 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2002 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2003 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2004 result->enable = true;
2008 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2010 struct drm_i915_private *dev_priv = dev->dev_private;
2011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2012 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2013 u32 linetime, ips_linetime;
2015 if (!intel_crtc_active(crtc))
2018 /* The WM are computed with base on how long it takes to fill a single
2019 * row at the given clock rate, multiplied by 8.
2021 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2023 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2024 intel_ddi_get_cdclk_freq(dev_priv));
2026 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2027 PIPE_WM_LINETIME_TIME(linetime);
2030 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2032 struct drm_i915_private *dev_priv = dev->dev_private;
2034 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2035 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2037 wm[0] = (sskpd >> 56) & 0xFF;
2039 wm[0] = sskpd & 0xF;
2040 wm[1] = (sskpd >> 4) & 0xFF;
2041 wm[2] = (sskpd >> 12) & 0xFF;
2042 wm[3] = (sskpd >> 20) & 0x1FF;
2043 wm[4] = (sskpd >> 32) & 0x1FF;
2044 } else if (INTEL_INFO(dev)->gen >= 6) {
2045 uint32_t sskpd = I915_READ(MCH_SSKPD);
2047 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2048 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2049 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2050 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2051 } else if (INTEL_INFO(dev)->gen >= 5) {
2052 uint32_t mltr = I915_READ(MLTR_ILK);
2054 /* ILK primary LP0 latency is 700 ns */
2056 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2057 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2061 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2063 /* ILK sprite LP0 latency is 1300 ns */
2064 if (INTEL_INFO(dev)->gen == 5)
2068 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2070 /* ILK cursor LP0 latency is 1300 ns */
2071 if (INTEL_INFO(dev)->gen == 5)
2074 /* WaDoubleCursorLP3Latency:ivb */
2075 if (IS_IVYBRIDGE(dev))
2079 int ilk_wm_max_level(const struct drm_device *dev)
2081 /* how many WM levels are we expecting */
2082 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2084 else if (INTEL_INFO(dev)->gen >= 6)
2090 static void intel_print_wm_latency(struct drm_device *dev,
2092 const uint16_t wm[5])
2094 int level, max_level = ilk_wm_max_level(dev);
2096 for (level = 0; level <= max_level; level++) {
2097 unsigned int latency = wm[level];
2100 DRM_ERROR("%s WM%d latency not provided\n",
2105 /* WM1+ latency values in 0.5us units */
2109 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2110 name, level, wm[level],
2111 latency / 10, latency % 10);
2115 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2116 uint16_t wm[5], uint16_t min)
2118 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2123 wm[0] = max(wm[0], min);
2124 for (level = 1; level <= max_level; level++)
2125 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2130 static void snb_wm_latency_quirk(struct drm_device *dev)
2132 struct drm_i915_private *dev_priv = dev->dev_private;
2136 * The BIOS provided WM memory latency values are often
2137 * inadequate for high resolution displays. Adjust them.
2139 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2140 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2141 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2146 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2147 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2148 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2149 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2152 static void ilk_setup_wm_latency(struct drm_device *dev)
2154 struct drm_i915_private *dev_priv = dev->dev_private;
2156 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2158 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2159 sizeof(dev_priv->wm.pri_latency));
2160 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2161 sizeof(dev_priv->wm.pri_latency));
2163 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2164 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2166 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2167 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2168 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2171 snb_wm_latency_quirk(dev);
2174 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2175 struct ilk_pipe_wm_parameters *p)
2177 struct drm_device *dev = crtc->dev;
2178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2179 enum pipe pipe = intel_crtc->pipe;
2180 struct drm_plane *plane;
2182 if (!intel_crtc_active(crtc))
2186 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2187 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2188 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2189 p->cur.bytes_per_pixel = 4;
2190 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2191 p->cur.horiz_pixels = intel_crtc->cursor_width;
2192 /* TODO: for now, assume primary and cursor planes are always enabled. */
2193 p->pri.enabled = true;
2194 p->cur.enabled = true;
2196 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2197 struct intel_plane *intel_plane = to_intel_plane(plane);
2199 if (intel_plane->pipe == pipe) {
2200 p->spr = intel_plane->wm;
2206 static void ilk_compute_wm_config(struct drm_device *dev,
2207 struct intel_wm_config *config)
2209 struct intel_crtc *intel_crtc;
2211 /* Compute the currently _active_ config */
2212 for_each_intel_crtc(dev, intel_crtc) {
2213 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2215 if (!wm->pipe_enabled)
2218 config->sprites_enabled |= wm->sprites_enabled;
2219 config->sprites_scaled |= wm->sprites_scaled;
2220 config->num_pipes_active++;
2224 /* Compute new watermarks for the pipe */
2225 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2226 const struct ilk_pipe_wm_parameters *params,
2227 struct intel_pipe_wm *pipe_wm)
2229 struct drm_device *dev = crtc->dev;
2230 const struct drm_i915_private *dev_priv = dev->dev_private;
2231 int level, max_level = ilk_wm_max_level(dev);
2232 /* LP0 watermark maximums depend on this pipe alone */
2233 struct intel_wm_config config = {
2234 .num_pipes_active = 1,
2235 .sprites_enabled = params->spr.enabled,
2236 .sprites_scaled = params->spr.scaled,
2238 struct ilk_wm_maximums max;
2240 pipe_wm->pipe_enabled = params->active;
2241 pipe_wm->sprites_enabled = params->spr.enabled;
2242 pipe_wm->sprites_scaled = params->spr.scaled;
2244 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2245 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2248 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2249 if (params->spr.scaled)
2252 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2254 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2255 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2257 /* LP0 watermarks always use 1/2 DDB partitioning */
2258 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2260 /* At least LP0 must be valid */
2261 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2264 ilk_compute_wm_reg_maximums(dev, 1, &max);
2266 for (level = 1; level <= max_level; level++) {
2267 struct intel_wm_level wm = {};
2269 ilk_compute_wm_level(dev_priv, level, params, &wm);
2272 * Disable any watermark level that exceeds the
2273 * register maximums since such watermarks are
2276 if (!ilk_validate_wm_level(level, &max, &wm))
2279 pipe_wm->wm[level] = wm;
2286 * Merge the watermarks from all active pipes for a specific level.
2288 static void ilk_merge_wm_level(struct drm_device *dev,
2290 struct intel_wm_level *ret_wm)
2292 const struct intel_crtc *intel_crtc;
2294 ret_wm->enable = true;
2296 for_each_intel_crtc(dev, intel_crtc) {
2297 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2298 const struct intel_wm_level *wm = &active->wm[level];
2300 if (!active->pipe_enabled)
2304 * The watermark values may have been used in the past,
2305 * so we must maintain them in the registers for some
2306 * time even if the level is now disabled.
2309 ret_wm->enable = false;
2311 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2312 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2313 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2314 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2319 * Merge all low power watermarks for all active pipes.
2321 static void ilk_wm_merge(struct drm_device *dev,
2322 const struct intel_wm_config *config,
2323 const struct ilk_wm_maximums *max,
2324 struct intel_pipe_wm *merged)
2326 int level, max_level = ilk_wm_max_level(dev);
2327 int last_enabled_level = max_level;
2329 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2330 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2331 config->num_pipes_active > 1)
2334 /* ILK: FBC WM must be disabled always */
2335 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2337 /* merge each WM1+ level */
2338 for (level = 1; level <= max_level; level++) {
2339 struct intel_wm_level *wm = &merged->wm[level];
2341 ilk_merge_wm_level(dev, level, wm);
2343 if (level > last_enabled_level)
2345 else if (!ilk_validate_wm_level(level, max, wm))
2346 /* make sure all following levels get disabled */
2347 last_enabled_level = level - 1;
2350 * The spec says it is preferred to disable
2351 * FBC WMs instead of disabling a WM level.
2353 if (wm->fbc_val > max->fbc) {
2355 merged->fbc_wm_enabled = false;
2360 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2362 * FIXME this is racy. FBC might get enabled later.
2363 * What we should check here is whether FBC can be
2364 * enabled sometime later.
2366 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2367 for (level = 2; level <= max_level; level++) {
2368 struct intel_wm_level *wm = &merged->wm[level];
2375 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2377 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2378 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2381 /* The value we need to program into the WM_LPx latency field */
2382 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2384 struct drm_i915_private *dev_priv = dev->dev_private;
2386 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2389 return dev_priv->wm.pri_latency[level];
2392 static void ilk_compute_wm_results(struct drm_device *dev,
2393 const struct intel_pipe_wm *merged,
2394 enum intel_ddb_partitioning partitioning,
2395 struct ilk_wm_values *results)
2397 struct intel_crtc *intel_crtc;
2400 results->enable_fbc_wm = merged->fbc_wm_enabled;
2401 results->partitioning = partitioning;
2403 /* LP1+ register values */
2404 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2405 const struct intel_wm_level *r;
2407 level = ilk_wm_lp_to_level(wm_lp, merged);
2409 r = &merged->wm[level];
2412 * Maintain the watermark values even if the level is
2413 * disabled. Doing otherwise could cause underruns.
2415 results->wm_lp[wm_lp - 1] =
2416 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2417 (r->pri_val << WM1_LP_SR_SHIFT) |
2421 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2423 if (INTEL_INFO(dev)->gen >= 8)
2424 results->wm_lp[wm_lp - 1] |=
2425 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2427 results->wm_lp[wm_lp - 1] |=
2428 r->fbc_val << WM1_LP_FBC_SHIFT;
2431 * Always set WM1S_LP_EN when spr_val != 0, even if the
2432 * level is disabled. Doing otherwise could cause underruns.
2434 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2435 WARN_ON(wm_lp != 1);
2436 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2438 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2441 /* LP0 register values */
2442 for_each_intel_crtc(dev, intel_crtc) {
2443 enum pipe pipe = intel_crtc->pipe;
2444 const struct intel_wm_level *r =
2445 &intel_crtc->wm.active.wm[0];
2447 if (WARN_ON(!r->enable))
2450 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2452 results->wm_pipe[pipe] =
2453 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2454 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2459 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2460 * case both are at the same level. Prefer r1 in case they're the same. */
2461 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2462 struct intel_pipe_wm *r1,
2463 struct intel_pipe_wm *r2)
2465 int level, max_level = ilk_wm_max_level(dev);
2466 int level1 = 0, level2 = 0;
2468 for (level = 1; level <= max_level; level++) {
2469 if (r1->wm[level].enable)
2471 if (r2->wm[level].enable)
2475 if (level1 == level2) {
2476 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2480 } else if (level1 > level2) {
2487 /* dirty bits used to track which watermarks need changes */
2488 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2489 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2490 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2491 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2492 #define WM_DIRTY_FBC (1 << 24)
2493 #define WM_DIRTY_DDB (1 << 25)
2495 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2496 const struct ilk_wm_values *old,
2497 const struct ilk_wm_values *new)
2499 unsigned int dirty = 0;
2503 for_each_pipe(pipe) {
2504 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2505 dirty |= WM_DIRTY_LINETIME(pipe);
2506 /* Must disable LP1+ watermarks too */
2507 dirty |= WM_DIRTY_LP_ALL;
2510 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2511 dirty |= WM_DIRTY_PIPE(pipe);
2512 /* Must disable LP1+ watermarks too */
2513 dirty |= WM_DIRTY_LP_ALL;
2517 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2518 dirty |= WM_DIRTY_FBC;
2519 /* Must disable LP1+ watermarks too */
2520 dirty |= WM_DIRTY_LP_ALL;
2523 if (old->partitioning != new->partitioning) {
2524 dirty |= WM_DIRTY_DDB;
2525 /* Must disable LP1+ watermarks too */
2526 dirty |= WM_DIRTY_LP_ALL;
2529 /* LP1+ watermarks already deemed dirty, no need to continue */
2530 if (dirty & WM_DIRTY_LP_ALL)
2533 /* Find the lowest numbered LP1+ watermark in need of an update... */
2534 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2535 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2536 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2540 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2541 for (; wm_lp <= 3; wm_lp++)
2542 dirty |= WM_DIRTY_LP(wm_lp);
2547 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2550 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2551 bool changed = false;
2553 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2554 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2555 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2558 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2559 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2560 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2563 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2564 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2565 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2570 * Don't touch WM1S_LP_EN here.
2571 * Doing so could cause underruns.
2578 * The spec says we shouldn't write when we don't need, because every write
2579 * causes WMs to be re-evaluated, expending some power.
2581 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2582 struct ilk_wm_values *results)
2584 struct drm_device *dev = dev_priv->dev;
2585 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2589 dirty = ilk_compute_wm_dirty(dev, previous, results);
2593 _ilk_disable_lp_wm(dev_priv, dirty);
2595 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2596 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2597 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2598 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2599 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2600 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2602 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2603 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2604 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2605 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2606 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2607 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2609 if (dirty & WM_DIRTY_DDB) {
2610 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2611 val = I915_READ(WM_MISC);
2612 if (results->partitioning == INTEL_DDB_PART_1_2)
2613 val &= ~WM_MISC_DATA_PARTITION_5_6;
2615 val |= WM_MISC_DATA_PARTITION_5_6;
2616 I915_WRITE(WM_MISC, val);
2618 val = I915_READ(DISP_ARB_CTL2);
2619 if (results->partitioning == INTEL_DDB_PART_1_2)
2620 val &= ~DISP_DATA_PARTITION_5_6;
2622 val |= DISP_DATA_PARTITION_5_6;
2623 I915_WRITE(DISP_ARB_CTL2, val);
2627 if (dirty & WM_DIRTY_FBC) {
2628 val = I915_READ(DISP_ARB_CTL);
2629 if (results->enable_fbc_wm)
2630 val &= ~DISP_FBC_WM_DIS;
2632 val |= DISP_FBC_WM_DIS;
2633 I915_WRITE(DISP_ARB_CTL, val);
2636 if (dirty & WM_DIRTY_LP(1) &&
2637 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2638 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2640 if (INTEL_INFO(dev)->gen >= 7) {
2641 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2642 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2643 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2644 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2647 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2648 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2649 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2650 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2651 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2652 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2654 dev_priv->wm.hw = *results;
2657 static bool ilk_disable_lp_wm(struct drm_device *dev)
2659 struct drm_i915_private *dev_priv = dev->dev_private;
2661 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2664 static void ilk_update_wm(struct drm_crtc *crtc)
2666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2667 struct drm_device *dev = crtc->dev;
2668 struct drm_i915_private *dev_priv = dev->dev_private;
2669 struct ilk_wm_maximums max;
2670 struct ilk_pipe_wm_parameters params = {};
2671 struct ilk_wm_values results = {};
2672 enum intel_ddb_partitioning partitioning;
2673 struct intel_pipe_wm pipe_wm = {};
2674 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2675 struct intel_wm_config config = {};
2677 ilk_compute_wm_parameters(crtc, ¶ms);
2679 intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm);
2681 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2684 intel_crtc->wm.active = pipe_wm;
2686 ilk_compute_wm_config(dev, &config);
2688 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2689 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2691 /* 5/6 split only in single pipe config on IVB+ */
2692 if (INTEL_INFO(dev)->gen >= 7 &&
2693 config.num_pipes_active == 1 && config.sprites_enabled) {
2694 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2695 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2697 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2699 best_lp_wm = &lp_wm_1_2;
2702 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2703 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2705 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2707 ilk_write_wm_values(dev_priv, &results);
2710 static void ilk_update_sprite_wm(struct drm_plane *plane,
2711 struct drm_crtc *crtc,
2712 uint32_t sprite_width, int pixel_size,
2713 bool enabled, bool scaled)
2715 struct drm_device *dev = plane->dev;
2716 struct intel_plane *intel_plane = to_intel_plane(plane);
2718 intel_plane->wm.enabled = enabled;
2719 intel_plane->wm.scaled = scaled;
2720 intel_plane->wm.horiz_pixels = sprite_width;
2721 intel_plane->wm.bytes_per_pixel = pixel_size;
2724 * IVB workaround: must disable low power watermarks for at least
2725 * one frame before enabling scaling. LP watermarks can be re-enabled
2726 * when scaling is disabled.
2728 * WaCxSRDisabledForSpriteScaling:ivb
2730 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2731 intel_wait_for_vblank(dev, intel_plane->pipe);
2733 ilk_update_wm(crtc);
2736 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2738 struct drm_device *dev = crtc->dev;
2739 struct drm_i915_private *dev_priv = dev->dev_private;
2740 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2742 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2743 enum pipe pipe = intel_crtc->pipe;
2744 static const unsigned int wm0_pipe_reg[] = {
2745 [PIPE_A] = WM0_PIPEA_ILK,
2746 [PIPE_B] = WM0_PIPEB_ILK,
2747 [PIPE_C] = WM0_PIPEC_IVB,
2750 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2751 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2752 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2754 active->pipe_enabled = intel_crtc_active(crtc);
2756 if (active->pipe_enabled) {
2757 u32 tmp = hw->wm_pipe[pipe];
2760 * For active pipes LP0 watermark is marked as
2761 * enabled, and LP1+ watermaks as disabled since
2762 * we can't really reverse compute them in case
2763 * multiple pipes are active.
2765 active->wm[0].enable = true;
2766 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2767 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2768 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2769 active->linetime = hw->wm_linetime[pipe];
2771 int level, max_level = ilk_wm_max_level(dev);
2774 * For inactive pipes, all watermark levels
2775 * should be marked as enabled but zeroed,
2776 * which is what we'd compute them to.
2778 for (level = 0; level <= max_level; level++)
2779 active->wm[level].enable = true;
2783 void ilk_wm_get_hw_state(struct drm_device *dev)
2785 struct drm_i915_private *dev_priv = dev->dev_private;
2786 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2787 struct drm_crtc *crtc;
2789 for_each_crtc(dev, crtc)
2790 ilk_pipe_wm_get_hw_state(crtc);
2792 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2793 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2794 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2796 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2797 if (INTEL_INFO(dev)->gen >= 7) {
2798 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2799 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2802 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2803 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2804 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2805 else if (IS_IVYBRIDGE(dev))
2806 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2807 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2810 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2814 * intel_update_watermarks - update FIFO watermark values based on current modes
2816 * Calculate watermark values for the various WM regs based on current mode
2817 * and plane configuration.
2819 * There are several cases to deal with here:
2820 * - normal (i.e. non-self-refresh)
2821 * - self-refresh (SR) mode
2822 * - lines are large relative to FIFO size (buffer can hold up to 2)
2823 * - lines are small relative to FIFO size (buffer can hold more than 2
2824 * lines), so need to account for TLB latency
2826 * The normal calculation is:
2827 * watermark = dotclock * bytes per pixel * latency
2828 * where latency is platform & configuration dependent (we assume pessimal
2831 * The SR calculation is:
2832 * watermark = (trunc(latency/line time)+1) * surface width *
2835 * line time = htotal / dotclock
2836 * surface width = hdisplay for normal plane and 64 for cursor
2837 * and latency is assumed to be high, as above.
2839 * The final value programmed to the register should always be rounded up,
2840 * and include an extra 2 entries to account for clock crossings.
2842 * We don't use the sprite, so we can ignore that. And on Crestline we have
2843 * to set the non-SR watermarks to 8.
2845 void intel_update_watermarks(struct drm_crtc *crtc)
2847 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2849 if (dev_priv->display.update_wm)
2850 dev_priv->display.update_wm(crtc);
2853 void intel_update_sprite_watermarks(struct drm_plane *plane,
2854 struct drm_crtc *crtc,
2855 uint32_t sprite_width, int pixel_size,
2856 bool enabled, bool scaled)
2858 struct drm_i915_private *dev_priv = plane->dev->dev_private;
2860 if (dev_priv->display.update_sprite_wm)
2861 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
2862 pixel_size, enabled, scaled);
2865 static struct drm_i915_gem_object *
2866 intel_alloc_context_page(struct drm_device *dev)
2868 struct drm_i915_gem_object *ctx;
2871 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2873 ctx = i915_gem_alloc_object(dev, 4096);
2875 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2879 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2881 DRM_ERROR("failed to pin power context: %d\n", ret);
2885 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2887 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2894 i915_gem_object_ggtt_unpin(ctx);
2896 drm_gem_object_unreference(&ctx->base);
2901 * Lock protecting IPS related data structures
2903 DEFINE_SPINLOCK(mchdev_lock);
2905 /* Global for IPS driver to get at the current i915 device. Protected by
2907 static struct drm_i915_private *i915_mch_dev;
2909 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2911 struct drm_i915_private *dev_priv = dev->dev_private;
2914 assert_spin_locked(&mchdev_lock);
2916 rgvswctl = I915_READ16(MEMSWCTL);
2917 if (rgvswctl & MEMCTL_CMD_STS) {
2918 DRM_DEBUG("gpu busy, RCS change rejected\n");
2919 return false; /* still busy with another command */
2922 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2923 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2924 I915_WRITE16(MEMSWCTL, rgvswctl);
2925 POSTING_READ16(MEMSWCTL);
2927 rgvswctl |= MEMCTL_CMD_STS;
2928 I915_WRITE16(MEMSWCTL, rgvswctl);
2933 static void ironlake_enable_drps(struct drm_device *dev)
2935 struct drm_i915_private *dev_priv = dev->dev_private;
2936 u32 rgvmodectl = I915_READ(MEMMODECTL);
2937 u8 fmax, fmin, fstart, vstart;
2939 spin_lock_irq(&mchdev_lock);
2941 /* Enable temp reporting */
2942 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2943 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2945 /* 100ms RC evaluation intervals */
2946 I915_WRITE(RCUPEI, 100000);
2947 I915_WRITE(RCDNEI, 100000);
2949 /* Set max/min thresholds to 90ms and 80ms respectively */
2950 I915_WRITE(RCBMAXAVG, 90000);
2951 I915_WRITE(RCBMINAVG, 80000);
2953 I915_WRITE(MEMIHYST, 1);
2955 /* Set up min, max, and cur for interrupt handling */
2956 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2957 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2958 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2959 MEMMODE_FSTART_SHIFT;
2961 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2964 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2965 dev_priv->ips.fstart = fstart;
2967 dev_priv->ips.max_delay = fstart;
2968 dev_priv->ips.min_delay = fmin;
2969 dev_priv->ips.cur_delay = fstart;
2971 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2972 fmax, fmin, fstart);
2974 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2977 * Interrupts will be enabled in ironlake_irq_postinstall
2980 I915_WRITE(VIDSTART, vstart);
2981 POSTING_READ(VIDSTART);
2983 rgvmodectl |= MEMMODE_SWMODE_EN;
2984 I915_WRITE(MEMMODECTL, rgvmodectl);
2986 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2987 DRM_ERROR("stuck trying to change perf mode\n");
2990 ironlake_set_drps(dev, fstart);
2992 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2994 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2995 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2996 dev_priv->ips.last_time2 = ktime_get_raw_ns();
2998 spin_unlock_irq(&mchdev_lock);
3001 static void ironlake_disable_drps(struct drm_device *dev)
3003 struct drm_i915_private *dev_priv = dev->dev_private;
3006 spin_lock_irq(&mchdev_lock);
3008 rgvswctl = I915_READ16(MEMSWCTL);
3010 /* Ack interrupts, disable EFC interrupt */
3011 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3012 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3013 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3014 I915_WRITE(DEIIR, DE_PCU_EVENT);
3015 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3017 /* Go back to the starting frequency */
3018 ironlake_set_drps(dev, dev_priv->ips.fstart);
3020 rgvswctl |= MEMCTL_CMD_STS;
3021 I915_WRITE(MEMSWCTL, rgvswctl);
3024 spin_unlock_irq(&mchdev_lock);
3027 /* There's a funny hw issue where the hw returns all 0 when reading from
3028 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3029 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3030 * all limits and the gpu stuck at whatever frequency it is at atm).
3032 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3036 /* Only set the down limit when we've reached the lowest level to avoid
3037 * getting more interrupts, otherwise leave this clear. This prevents a
3038 * race in the hw when coming out of rc6: There's a tiny window where
3039 * the hw runs at the minimal clock before selecting the desired
3040 * frequency, if the down threshold expires in that window we will not
3041 * receive a down interrupt. */
3042 limits = dev_priv->rps.max_freq_softlimit << 24;
3043 if (val <= dev_priv->rps.min_freq_softlimit)
3044 limits |= dev_priv->rps.min_freq_softlimit << 16;
3049 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3053 new_power = dev_priv->rps.power;
3054 switch (dev_priv->rps.power) {
3056 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3057 new_power = BETWEEN;
3061 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3062 new_power = LOW_POWER;
3063 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3064 new_power = HIGH_POWER;
3068 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3069 new_power = BETWEEN;
3072 /* Max/min bins are special */
3073 if (val == dev_priv->rps.min_freq_softlimit)
3074 new_power = LOW_POWER;
3075 if (val == dev_priv->rps.max_freq_softlimit)
3076 new_power = HIGH_POWER;
3077 if (new_power == dev_priv->rps.power)
3080 /* Note the units here are not exactly 1us, but 1280ns. */
3081 switch (new_power) {
3083 /* Upclock if more than 95% busy over 16ms */
3084 I915_WRITE(GEN6_RP_UP_EI, 12500);
3085 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3087 /* Downclock if less than 85% busy over 32ms */
3088 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3089 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3091 I915_WRITE(GEN6_RP_CONTROL,
3092 GEN6_RP_MEDIA_TURBO |
3093 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3094 GEN6_RP_MEDIA_IS_GFX |
3096 GEN6_RP_UP_BUSY_AVG |
3097 GEN6_RP_DOWN_IDLE_AVG);
3101 /* Upclock if more than 90% busy over 13ms */
3102 I915_WRITE(GEN6_RP_UP_EI, 10250);
3103 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3105 /* Downclock if less than 75% busy over 32ms */
3106 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3107 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3109 I915_WRITE(GEN6_RP_CONTROL,
3110 GEN6_RP_MEDIA_TURBO |
3111 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3112 GEN6_RP_MEDIA_IS_GFX |
3114 GEN6_RP_UP_BUSY_AVG |
3115 GEN6_RP_DOWN_IDLE_AVG);
3119 /* Upclock if more than 85% busy over 10ms */
3120 I915_WRITE(GEN6_RP_UP_EI, 8000);
3121 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3123 /* Downclock if less than 60% busy over 32ms */
3124 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3125 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3127 I915_WRITE(GEN6_RP_CONTROL,
3128 GEN6_RP_MEDIA_TURBO |
3129 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3130 GEN6_RP_MEDIA_IS_GFX |
3132 GEN6_RP_UP_BUSY_AVG |
3133 GEN6_RP_DOWN_IDLE_AVG);
3137 dev_priv->rps.power = new_power;
3138 dev_priv->rps.last_adj = 0;
3141 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3145 if (val > dev_priv->rps.min_freq_softlimit)
3146 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3147 if (val < dev_priv->rps.max_freq_softlimit)
3148 mask |= GEN6_PM_RP_UP_THRESHOLD;
3150 /* IVB and SNB hard hangs on looping batchbuffer
3151 * if GEN6_PM_UP_EI_EXPIRED is masked.
3153 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3154 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3156 if (IS_GEN8(dev_priv->dev))
3157 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3162 /* gen6_set_rps is called to update the frequency request, but should also be
3163 * called when the range (min_delay and max_delay) is modified so that we can
3164 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3165 void gen6_set_rps(struct drm_device *dev, u8 val)
3167 struct drm_i915_private *dev_priv = dev->dev_private;
3169 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3170 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3171 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3173 /* min/max delay may still have been modified so be sure to
3174 * write the limits value.
3176 if (val != dev_priv->rps.cur_freq) {
3177 gen6_set_rps_thresholds(dev_priv, val);
3179 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3180 I915_WRITE(GEN6_RPNSWREQ,
3181 HSW_FREQUENCY(val));
3183 I915_WRITE(GEN6_RPNSWREQ,
3184 GEN6_FREQUENCY(val) |
3186 GEN6_AGGRESSIVE_TURBO);
3189 /* Make sure we continue to get interrupts
3190 * until we hit the minimum or maximum frequencies.
3192 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3193 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3195 POSTING_READ(GEN6_RPNSWREQ);
3197 dev_priv->rps.cur_freq = val;
3198 trace_intel_gpu_freq_change(val * 50);
3201 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3203 * * If Gfx is Idle, then
3204 * 1. Mask Turbo interrupts
3205 * 2. Bring up Gfx clock
3206 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3207 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3208 * 5. Unmask Turbo interrupts
3210 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3212 struct drm_device *dev = dev_priv->dev;
3214 /* Latest VLV doesn't need to force the gfx clock */
3215 if (dev->pdev->revision >= 0xd) {
3216 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3221 * When we are idle. Drop to min voltage state.
3224 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3227 /* Mask turbo interrupt so that they will not come in between */
3228 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3230 vlv_force_gfx_clock(dev_priv, true);
3232 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3234 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3235 dev_priv->rps.min_freq_softlimit);
3237 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3238 & GENFREQSTATUS) == 0, 5))
3239 DRM_ERROR("timed out waiting for Punit\n");
3241 vlv_force_gfx_clock(dev_priv, false);
3243 I915_WRITE(GEN6_PMINTRMSK,
3244 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3247 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3249 struct drm_device *dev = dev_priv->dev;
3251 mutex_lock(&dev_priv->rps.hw_lock);
3252 if (dev_priv->rps.enabled) {
3253 if (IS_VALLEYVIEW(dev))
3254 vlv_set_rps_idle(dev_priv);
3256 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3257 dev_priv->rps.last_adj = 0;
3259 mutex_unlock(&dev_priv->rps.hw_lock);
3262 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3264 struct drm_device *dev = dev_priv->dev;
3266 mutex_lock(&dev_priv->rps.hw_lock);
3267 if (dev_priv->rps.enabled) {
3268 if (IS_VALLEYVIEW(dev))
3269 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3271 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3272 dev_priv->rps.last_adj = 0;
3274 mutex_unlock(&dev_priv->rps.hw_lock);
3277 void valleyview_set_rps(struct drm_device *dev, u8 val)
3279 struct drm_i915_private *dev_priv = dev->dev_private;
3281 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3282 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3283 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3285 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3286 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3287 dev_priv->rps.cur_freq,
3288 vlv_gpu_freq(dev_priv, val), val);
3290 if (val != dev_priv->rps.cur_freq)
3291 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3293 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3295 dev_priv->rps.cur_freq = val;
3296 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3299 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3301 struct drm_i915_private *dev_priv = dev->dev_private;
3303 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3304 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3305 ~dev_priv->pm_rps_events);
3306 /* Complete PM interrupt masking here doesn't race with the rps work
3307 * item again unmasking PM interrupts because that is using a different
3308 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3309 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3310 * gen8_enable_rps will clean up. */
3312 spin_lock_irq(&dev_priv->irq_lock);
3313 dev_priv->rps.pm_iir = 0;
3314 spin_unlock_irq(&dev_priv->irq_lock);
3316 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3319 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3321 struct drm_i915_private *dev_priv = dev->dev_private;
3323 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3324 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3325 ~dev_priv->pm_rps_events);
3326 /* Complete PM interrupt masking here doesn't race with the rps work
3327 * item again unmasking PM interrupts because that is using a different
3328 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3329 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3331 spin_lock_irq(&dev_priv->irq_lock);
3332 dev_priv->rps.pm_iir = 0;
3333 spin_unlock_irq(&dev_priv->irq_lock);
3335 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3338 static void gen6_disable_rps(struct drm_device *dev)
3340 struct drm_i915_private *dev_priv = dev->dev_private;
3342 I915_WRITE(GEN6_RC_CONTROL, 0);
3343 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3345 if (IS_BROADWELL(dev))
3346 gen8_disable_rps_interrupts(dev);
3348 gen6_disable_rps_interrupts(dev);
3351 static void valleyview_disable_rps(struct drm_device *dev)
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3355 I915_WRITE(GEN6_RC_CONTROL, 0);
3357 gen6_disable_rps_interrupts(dev);
3360 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3362 if (IS_VALLEYVIEW(dev)) {
3363 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3364 mode = GEN6_RC_CTL_RC6_ENABLE;
3368 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3369 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3370 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3371 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3374 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3376 /* No RC6 before Ironlake */
3377 if (INTEL_INFO(dev)->gen < 5)
3380 /* RC6 is only on Ironlake mobile not on desktop */
3381 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3384 /* Respect the kernel parameter if it is set */
3385 if (enable_rc6 >= 0) {
3388 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3389 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3392 mask = INTEL_RC6_ENABLE;
3394 if ((enable_rc6 & mask) != enable_rc6)
3395 DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3396 enable_rc6 & mask, enable_rc6, mask);
3398 return enable_rc6 & mask;
3401 /* Disable RC6 on Ironlake */
3402 if (INTEL_INFO(dev)->gen == 5)
3405 if (IS_IVYBRIDGE(dev))
3406 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3408 return INTEL_RC6_ENABLE;
3411 int intel_enable_rc6(const struct drm_device *dev)
3413 return i915.enable_rc6;
3416 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3418 struct drm_i915_private *dev_priv = dev->dev_private;
3420 spin_lock_irq(&dev_priv->irq_lock);
3421 WARN_ON(dev_priv->rps.pm_iir);
3422 bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3423 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3424 spin_unlock_irq(&dev_priv->irq_lock);
3427 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3429 struct drm_i915_private *dev_priv = dev->dev_private;
3431 spin_lock_irq(&dev_priv->irq_lock);
3432 WARN_ON(dev_priv->rps.pm_iir);
3433 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3434 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3435 spin_unlock_irq(&dev_priv->irq_lock);
3438 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3440 /* All of these values are in units of 50MHz */
3441 dev_priv->rps.cur_freq = 0;
3442 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3443 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3444 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3445 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3446 /* XXX: only BYT has a special efficient freq */
3447 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3448 /* hw_max = RP0 until we check for overclocking */
3449 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3451 /* Preserve min/max settings in case of re-init */
3452 if (dev_priv->rps.max_freq_softlimit == 0)
3453 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3455 if (dev_priv->rps.min_freq_softlimit == 0)
3456 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3459 static void gen8_enable_rps(struct drm_device *dev)
3461 struct drm_i915_private *dev_priv = dev->dev_private;
3462 struct intel_engine_cs *ring;
3463 uint32_t rc6_mask = 0, rp_state_cap;
3466 /* 1a: Software RC state - RC0 */
3467 I915_WRITE(GEN6_RC_STATE, 0);
3469 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3470 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3471 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3473 /* 2a: Disable RC states. */
3474 I915_WRITE(GEN6_RC_CONTROL, 0);
3476 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3477 parse_rp_state_cap(dev_priv, rp_state_cap);
3479 /* 2b: Program RC6 thresholds.*/
3480 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3481 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3482 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3483 for_each_ring(ring, dev_priv, unused)
3484 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3485 I915_WRITE(GEN6_RC_SLEEP, 0);
3486 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3489 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3490 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3491 intel_print_rc6_info(dev, rc6_mask);
3492 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3493 GEN6_RC_CTL_EI_MODE(1) |
3496 /* 4 Program defaults and thresholds for RPS*/
3497 I915_WRITE(GEN6_RPNSWREQ,
3498 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3499 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3500 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3501 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3502 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3504 /* Docs recommend 900MHz, and 300 MHz respectively */
3505 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3506 dev_priv->rps.max_freq_softlimit << 24 |
3507 dev_priv->rps.min_freq_softlimit << 16);
3509 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3510 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3511 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3512 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3514 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3517 I915_WRITE(GEN6_RP_CONTROL,
3518 GEN6_RP_MEDIA_TURBO |
3519 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3520 GEN6_RP_MEDIA_IS_GFX |
3522 GEN6_RP_UP_BUSY_AVG |
3523 GEN6_RP_DOWN_IDLE_AVG);
3525 /* 6: Ring frequency + overclocking (our driver does this later */
3527 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3529 gen8_enable_rps_interrupts(dev);
3531 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3534 static void gen6_enable_rps(struct drm_device *dev)
3536 struct drm_i915_private *dev_priv = dev->dev_private;
3537 struct intel_engine_cs *ring;
3540 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3545 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3547 /* Here begins a magic sequence of register writes to enable
3548 * auto-downclocking.
3550 * Perhaps there might be some value in exposing these to
3553 I915_WRITE(GEN6_RC_STATE, 0);
3555 /* Clear the DBG now so we don't confuse earlier errors */
3556 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3557 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3558 I915_WRITE(GTFIFODBG, gtfifodbg);
3561 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3563 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3564 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3566 parse_rp_state_cap(dev_priv, rp_state_cap);
3568 /* disable the counters and set deterministic thresholds */
3569 I915_WRITE(GEN6_RC_CONTROL, 0);
3571 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3572 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3573 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3574 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3575 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3577 for_each_ring(ring, dev_priv, i)
3578 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3580 I915_WRITE(GEN6_RC_SLEEP, 0);
3581 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3582 if (IS_IVYBRIDGE(dev))
3583 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3585 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3586 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3587 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3589 /* Check if we are enabling RC6 */
3590 rc6_mode = intel_enable_rc6(dev_priv->dev);
3591 if (rc6_mode & INTEL_RC6_ENABLE)
3592 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3594 /* We don't use those on Haswell */
3595 if (!IS_HASWELL(dev)) {
3596 if (rc6_mode & INTEL_RC6p_ENABLE)
3597 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3599 if (rc6_mode & INTEL_RC6pp_ENABLE)
3600 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3603 intel_print_rc6_info(dev, rc6_mask);
3605 I915_WRITE(GEN6_RC_CONTROL,
3607 GEN6_RC_CTL_EI_MODE(1) |
3608 GEN6_RC_CTL_HW_ENABLE);
3610 /* Power down if completely idle for over 50ms */
3611 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3612 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3614 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3616 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3618 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3619 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3620 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3621 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3622 (pcu_mbox & 0xff) * 50);
3623 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3626 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3627 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3629 gen6_enable_rps_interrupts(dev);
3632 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3633 if (IS_GEN6(dev) && ret) {
3634 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3635 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3636 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3637 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3638 rc6vids &= 0xffff00;
3639 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3640 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3642 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3645 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3648 static void __gen6_update_ring_freq(struct drm_device *dev)
3650 struct drm_i915_private *dev_priv = dev->dev_private;
3652 unsigned int gpu_freq;
3653 unsigned int max_ia_freq, min_ring_freq;
3654 int scaling_factor = 180;
3655 struct cpufreq_policy *policy;
3657 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3659 policy = cpufreq_cpu_get(0);
3661 max_ia_freq = policy->cpuinfo.max_freq;
3662 cpufreq_cpu_put(policy);
3665 * Default to measured freq if none found, PCU will ensure we
3668 max_ia_freq = tsc_khz;
3671 /* Convert from kHz to MHz */
3672 max_ia_freq /= 1000;
3674 min_ring_freq = I915_READ(DCLK) & 0xf;
3675 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3676 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3679 * For each potential GPU frequency, load a ring frequency we'd like
3680 * to use for memory access. We do this by specifying the IA frequency
3681 * the PCU should use as a reference to determine the ring frequency.
3683 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3685 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3686 unsigned int ia_freq = 0, ring_freq = 0;
3688 if (INTEL_INFO(dev)->gen >= 8) {
3689 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3690 ring_freq = max(min_ring_freq, gpu_freq);
3691 } else if (IS_HASWELL(dev)) {
3692 ring_freq = mult_frac(gpu_freq, 5, 4);
3693 ring_freq = max(min_ring_freq, ring_freq);
3694 /* leave ia_freq as the default, chosen by cpufreq */
3696 /* On older processors, there is no separate ring
3697 * clock domain, so in order to boost the bandwidth
3698 * of the ring, we need to upclock the CPU (ia_freq).
3700 * For GPU frequencies less than 750MHz,
3701 * just use the lowest ring freq.
3703 if (gpu_freq < min_freq)
3706 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3707 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3710 sandybridge_pcode_write(dev_priv,
3711 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3712 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3713 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3718 void gen6_update_ring_freq(struct drm_device *dev)
3720 struct drm_i915_private *dev_priv = dev->dev_private;
3722 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3725 mutex_lock(&dev_priv->rps.hw_lock);
3726 __gen6_update_ring_freq(dev);
3727 mutex_unlock(&dev_priv->rps.hw_lock);
3730 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3734 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3736 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3738 rp0 = min_t(u32, rp0, 0xea);
3743 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3747 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3748 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3749 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3750 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3755 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3757 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3760 /* Check that the pctx buffer wasn't move under us. */
3761 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3763 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3765 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3766 dev_priv->vlv_pctx->stolen->start);
3769 static void valleyview_setup_pctx(struct drm_device *dev)
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772 struct drm_i915_gem_object *pctx;
3773 unsigned long pctx_paddr;
3775 int pctx_size = 24*1024;
3777 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3779 pcbr = I915_READ(VLV_PCBR);
3781 /* BIOS set it up already, grab the pre-alloc'd space */
3784 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3785 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3787 I915_GTT_OFFSET_NONE,
3793 * From the Gunit register HAS:
3794 * The Gfx driver is expected to program this register and ensure
3795 * proper allocation within Gfx stolen memory. For example, this
3796 * register should be programmed such than the PCBR range does not
3797 * overlap with other ranges, such as the frame buffer, protected
3798 * memory, or any other relevant ranges.
3800 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3802 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3806 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3807 I915_WRITE(VLV_PCBR, pctx_paddr);
3810 dev_priv->vlv_pctx = pctx;
3813 static void valleyview_cleanup_pctx(struct drm_device *dev)
3815 struct drm_i915_private *dev_priv = dev->dev_private;
3817 if (WARN_ON(!dev_priv->vlv_pctx))
3820 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3821 dev_priv->vlv_pctx = NULL;
3824 static void valleyview_init_gt_powersave(struct drm_device *dev)
3826 struct drm_i915_private *dev_priv = dev->dev_private;
3828 valleyview_setup_pctx(dev);
3830 mutex_lock(&dev_priv->rps.hw_lock);
3832 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3833 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3834 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3835 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3836 dev_priv->rps.max_freq);
3838 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3839 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3840 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3841 dev_priv->rps.efficient_freq);
3843 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3844 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3845 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3846 dev_priv->rps.min_freq);
3848 /* Preserve min/max settings in case of re-init */
3849 if (dev_priv->rps.max_freq_softlimit == 0)
3850 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3852 if (dev_priv->rps.min_freq_softlimit == 0)
3853 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3855 mutex_unlock(&dev_priv->rps.hw_lock);
3858 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
3860 valleyview_cleanup_pctx(dev);
3863 static void valleyview_enable_rps(struct drm_device *dev)
3865 struct drm_i915_private *dev_priv = dev->dev_private;
3866 struct intel_engine_cs *ring;
3867 u32 gtfifodbg, val, rc6_mode = 0;
3870 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3872 valleyview_check_pctx(dev_priv);
3874 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3875 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3877 I915_WRITE(GTFIFODBG, gtfifodbg);
3880 /* If VLV, Forcewake all wells, else re-direct to regular path */
3881 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3883 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3884 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3885 I915_WRITE(GEN6_RP_UP_EI, 66000);
3886 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3888 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3890 I915_WRITE(GEN6_RP_CONTROL,
3891 GEN6_RP_MEDIA_TURBO |
3892 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3893 GEN6_RP_MEDIA_IS_GFX |
3895 GEN6_RP_UP_BUSY_AVG |
3896 GEN6_RP_DOWN_IDLE_CONT);
3898 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3899 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3900 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3902 for_each_ring(ring, dev_priv, i)
3903 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3905 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
3907 /* allows RC6 residency counter to work */
3908 I915_WRITE(VLV_COUNTER_CONTROL,
3909 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3910 VLV_MEDIA_RC6_COUNT_EN |
3911 VLV_RENDER_RC6_COUNT_EN));
3912 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3913 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
3915 intel_print_rc6_info(dev, rc6_mode);
3917 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3919 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3921 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3922 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3924 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
3925 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3926 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3927 dev_priv->rps.cur_freq);
3929 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3930 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3931 dev_priv->rps.efficient_freq);
3933 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
3935 gen6_enable_rps_interrupts(dev);
3937 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3940 void ironlake_teardown_rc6(struct drm_device *dev)
3942 struct drm_i915_private *dev_priv = dev->dev_private;
3944 if (dev_priv->ips.renderctx) {
3945 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3946 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3947 dev_priv->ips.renderctx = NULL;
3950 if (dev_priv->ips.pwrctx) {
3951 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3952 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3953 dev_priv->ips.pwrctx = NULL;
3957 static void ironlake_disable_rc6(struct drm_device *dev)
3959 struct drm_i915_private *dev_priv = dev->dev_private;
3961 if (I915_READ(PWRCTXA)) {
3962 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3963 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3964 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3967 I915_WRITE(PWRCTXA, 0);
3968 POSTING_READ(PWRCTXA);
3970 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3971 POSTING_READ(RSTDBYCTL);
3975 static int ironlake_setup_rc6(struct drm_device *dev)
3977 struct drm_i915_private *dev_priv = dev->dev_private;
3979 if (dev_priv->ips.renderctx == NULL)
3980 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3981 if (!dev_priv->ips.renderctx)
3984 if (dev_priv->ips.pwrctx == NULL)
3985 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3986 if (!dev_priv->ips.pwrctx) {
3987 ironlake_teardown_rc6(dev);
3994 static void ironlake_enable_rc6(struct drm_device *dev)
3996 struct drm_i915_private *dev_priv = dev->dev_private;
3997 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3998 bool was_interruptible;
4001 /* rc6 disabled by default due to repeated reports of hanging during
4004 if (!intel_enable_rc6(dev))
4007 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4009 ret = ironlake_setup_rc6(dev);
4013 was_interruptible = dev_priv->mm.interruptible;
4014 dev_priv->mm.interruptible = false;
4017 * GPU can automatically power down the render unit if given a page
4020 ret = intel_ring_begin(ring, 6);
4022 ironlake_teardown_rc6(dev);
4023 dev_priv->mm.interruptible = was_interruptible;
4027 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4028 intel_ring_emit(ring, MI_SET_CONTEXT);
4029 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4031 MI_SAVE_EXT_STATE_EN |
4032 MI_RESTORE_EXT_STATE_EN |
4033 MI_RESTORE_INHIBIT);
4034 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4035 intel_ring_emit(ring, MI_NOOP);
4036 intel_ring_emit(ring, MI_FLUSH);
4037 intel_ring_advance(ring);
4040 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4041 * does an implicit flush, combined with MI_FLUSH above, it should be
4042 * safe to assume that renderctx is valid
4044 ret = intel_ring_idle(ring);
4045 dev_priv->mm.interruptible = was_interruptible;
4047 DRM_ERROR("failed to enable ironlake power savings\n");
4048 ironlake_teardown_rc6(dev);
4052 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4053 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4055 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4058 static unsigned long intel_pxfreq(u32 vidfreq)
4061 int div = (vidfreq & 0x3f0000) >> 16;
4062 int post = (vidfreq & 0x3000) >> 12;
4063 int pre = (vidfreq & 0x7);
4068 freq = ((div * 133333) / ((1<<post) * pre));
4073 static const struct cparams {
4079 { 1, 1333, 301, 28664 },
4080 { 1, 1066, 294, 24460 },
4081 { 1, 800, 294, 25192 },
4082 { 0, 1333, 276, 27605 },
4083 { 0, 1066, 276, 27605 },
4084 { 0, 800, 231, 23784 },
4087 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4089 u64 total_count, diff, ret;
4090 u32 count1, count2, count3, m = 0, c = 0;
4091 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4094 assert_spin_locked(&mchdev_lock);
4096 diff1 = now - dev_priv->ips.last_time1;
4098 /* Prevent division-by-zero if we are asking too fast.
4099 * Also, we don't get interesting results if we are polling
4100 * faster than once in 10ms, so just return the saved value
4104 return dev_priv->ips.chipset_power;
4106 count1 = I915_READ(DMIEC);
4107 count2 = I915_READ(DDREC);
4108 count3 = I915_READ(CSIEC);
4110 total_count = count1 + count2 + count3;
4112 /* FIXME: handle per-counter overflow */
4113 if (total_count < dev_priv->ips.last_count1) {
4114 diff = ~0UL - dev_priv->ips.last_count1;
4115 diff += total_count;
4117 diff = total_count - dev_priv->ips.last_count1;
4120 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4121 if (cparams[i].i == dev_priv->ips.c_m &&
4122 cparams[i].t == dev_priv->ips.r_t) {
4129 diff = div_u64(diff, diff1);
4130 ret = ((m * diff) + c);
4131 ret = div_u64(ret, 10);
4133 dev_priv->ips.last_count1 = total_count;
4134 dev_priv->ips.last_time1 = now;
4136 dev_priv->ips.chipset_power = ret;
4141 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4143 struct drm_device *dev = dev_priv->dev;
4146 if (INTEL_INFO(dev)->gen != 5)
4149 spin_lock_irq(&mchdev_lock);
4151 val = __i915_chipset_val(dev_priv);
4153 spin_unlock_irq(&mchdev_lock);
4158 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4160 unsigned long m, x, b;
4163 tsfs = I915_READ(TSFS);
4165 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4166 x = I915_READ8(TR1);
4168 b = tsfs & TSFS_INTR_MASK;
4170 return ((m * x) / 127) - b;
4173 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4175 struct drm_device *dev = dev_priv->dev;
4176 static const struct v_table {
4177 u16 vd; /* in .1 mil */
4178 u16 vm; /* in .1 mil */
4309 if (INTEL_INFO(dev)->is_mobile)
4310 return v_table[pxvid].vm;
4312 return v_table[pxvid].vd;
4315 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4317 u64 now, diff, diffms;
4320 assert_spin_locked(&mchdev_lock);
4322 now = ktime_get_raw_ns();
4323 diffms = now - dev_priv->ips.last_time2;
4324 do_div(diffms, NSEC_PER_MSEC);
4326 /* Don't divide by 0 */
4330 count = I915_READ(GFXEC);
4332 if (count < dev_priv->ips.last_count2) {
4333 diff = ~0UL - dev_priv->ips.last_count2;
4336 diff = count - dev_priv->ips.last_count2;
4339 dev_priv->ips.last_count2 = count;
4340 dev_priv->ips.last_time2 = now;
4342 /* More magic constants... */
4344 diff = div_u64(diff, diffms * 10);
4345 dev_priv->ips.gfx_power = diff;
4348 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4350 struct drm_device *dev = dev_priv->dev;
4352 if (INTEL_INFO(dev)->gen != 5)
4355 spin_lock_irq(&mchdev_lock);
4357 __i915_update_gfx_val(dev_priv);
4359 spin_unlock_irq(&mchdev_lock);
4362 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4364 unsigned long t, corr, state1, corr2, state2;
4367 assert_spin_locked(&mchdev_lock);
4369 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4370 pxvid = (pxvid >> 24) & 0x7f;
4371 ext_v = pvid_to_extvid(dev_priv, pxvid);
4375 t = i915_mch_val(dev_priv);
4377 /* Revel in the empirically derived constants */
4379 /* Correction factor in 1/100000 units */
4381 corr = ((t * 2349) + 135940);
4383 corr = ((t * 964) + 29317);
4385 corr = ((t * 301) + 1004);
4387 corr = corr * ((150142 * state1) / 10000 - 78642);
4389 corr2 = (corr * dev_priv->ips.corr);
4391 state2 = (corr2 * state1) / 10000;
4392 state2 /= 100; /* convert to mW */
4394 __i915_update_gfx_val(dev_priv);
4396 return dev_priv->ips.gfx_power + state2;
4399 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4401 struct drm_device *dev = dev_priv->dev;
4404 if (INTEL_INFO(dev)->gen != 5)
4407 spin_lock_irq(&mchdev_lock);
4409 val = __i915_gfx_val(dev_priv);
4411 spin_unlock_irq(&mchdev_lock);
4417 * i915_read_mch_val - return value for IPS use
4419 * Calculate and return a value for the IPS driver to use when deciding whether
4420 * we have thermal and power headroom to increase CPU or GPU power budget.
4422 unsigned long i915_read_mch_val(void)
4424 struct drm_i915_private *dev_priv;
4425 unsigned long chipset_val, graphics_val, ret = 0;
4427 spin_lock_irq(&mchdev_lock);
4430 dev_priv = i915_mch_dev;
4432 chipset_val = __i915_chipset_val(dev_priv);
4433 graphics_val = __i915_gfx_val(dev_priv);
4435 ret = chipset_val + graphics_val;
4438 spin_unlock_irq(&mchdev_lock);
4442 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4445 * i915_gpu_raise - raise GPU frequency limit
4447 * Raise the limit; IPS indicates we have thermal headroom.
4449 bool i915_gpu_raise(void)
4451 struct drm_i915_private *dev_priv;
4454 spin_lock_irq(&mchdev_lock);
4455 if (!i915_mch_dev) {
4459 dev_priv = i915_mch_dev;
4461 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4462 dev_priv->ips.max_delay--;
4465 spin_unlock_irq(&mchdev_lock);
4469 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4472 * i915_gpu_lower - lower GPU frequency limit
4474 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4475 * frequency maximum.
4477 bool i915_gpu_lower(void)
4479 struct drm_i915_private *dev_priv;
4482 spin_lock_irq(&mchdev_lock);
4483 if (!i915_mch_dev) {
4487 dev_priv = i915_mch_dev;
4489 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4490 dev_priv->ips.max_delay++;
4493 spin_unlock_irq(&mchdev_lock);
4497 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4500 * i915_gpu_busy - indicate GPU business to IPS
4502 * Tell the IPS driver whether or not the GPU is busy.
4504 bool i915_gpu_busy(void)
4506 struct drm_i915_private *dev_priv;
4507 struct intel_engine_cs *ring;
4511 spin_lock_irq(&mchdev_lock);
4514 dev_priv = i915_mch_dev;
4516 for_each_ring(ring, dev_priv, i)
4517 ret |= !list_empty(&ring->request_list);
4520 spin_unlock_irq(&mchdev_lock);
4524 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4527 * i915_gpu_turbo_disable - disable graphics turbo
4529 * Disable graphics turbo by resetting the max frequency and setting the
4530 * current frequency to the default.
4532 bool i915_gpu_turbo_disable(void)
4534 struct drm_i915_private *dev_priv;
4537 spin_lock_irq(&mchdev_lock);
4538 if (!i915_mch_dev) {
4542 dev_priv = i915_mch_dev;
4544 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4546 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4550 spin_unlock_irq(&mchdev_lock);
4554 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4557 * Tells the intel_ips driver that the i915 driver is now loaded, if
4558 * IPS got loaded first.
4560 * This awkward dance is so that neither module has to depend on the
4561 * other in order for IPS to do the appropriate communication of
4562 * GPU turbo limits to i915.
4565 ips_ping_for_i915_load(void)
4569 link = symbol_get(ips_link_to_i915_driver);
4572 symbol_put(ips_link_to_i915_driver);
4576 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4578 /* We only register the i915 ips part with intel-ips once everything is
4579 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4580 spin_lock_irq(&mchdev_lock);
4581 i915_mch_dev = dev_priv;
4582 spin_unlock_irq(&mchdev_lock);
4584 ips_ping_for_i915_load();
4587 void intel_gpu_ips_teardown(void)
4589 spin_lock_irq(&mchdev_lock);
4590 i915_mch_dev = NULL;
4591 spin_unlock_irq(&mchdev_lock);
4594 static void intel_init_emon(struct drm_device *dev)
4596 struct drm_i915_private *dev_priv = dev->dev_private;
4601 /* Disable to program */
4605 /* Program energy weights for various events */
4606 I915_WRITE(SDEW, 0x15040d00);
4607 I915_WRITE(CSIEW0, 0x007f0000);
4608 I915_WRITE(CSIEW1, 0x1e220004);
4609 I915_WRITE(CSIEW2, 0x04000004);
4611 for (i = 0; i < 5; i++)
4612 I915_WRITE(PEW + (i * 4), 0);
4613 for (i = 0; i < 3; i++)
4614 I915_WRITE(DEW + (i * 4), 0);
4616 /* Program P-state weights to account for frequency power adjustment */
4617 for (i = 0; i < 16; i++) {
4618 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4619 unsigned long freq = intel_pxfreq(pxvidfreq);
4620 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4625 val *= (freq / 1000);
4627 val /= (127*127*900);
4629 DRM_ERROR("bad pxval: %ld\n", val);
4632 /* Render standby states get 0 weight */
4636 for (i = 0; i < 4; i++) {
4637 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4638 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4639 I915_WRITE(PXW + (i * 4), val);
4642 /* Adjust magic regs to magic values (more experimental results) */
4643 I915_WRITE(OGW0, 0);
4644 I915_WRITE(OGW1, 0);
4645 I915_WRITE(EG0, 0x00007f00);
4646 I915_WRITE(EG1, 0x0000000e);
4647 I915_WRITE(EG2, 0x000e0000);
4648 I915_WRITE(EG3, 0x68000300);
4649 I915_WRITE(EG4, 0x42000000);
4650 I915_WRITE(EG5, 0x00140031);
4654 for (i = 0; i < 8; i++)
4655 I915_WRITE(PXWL + (i * 4), 0);
4657 /* Enable PMON + select events */
4658 I915_WRITE(ECR, 0x80000019);
4660 lcfuse = I915_READ(LCFUSE02);
4662 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4665 void intel_init_gt_powersave(struct drm_device *dev)
4667 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4669 if (IS_VALLEYVIEW(dev))
4670 valleyview_init_gt_powersave(dev);
4673 void intel_cleanup_gt_powersave(struct drm_device *dev)
4675 if (IS_VALLEYVIEW(dev))
4676 valleyview_cleanup_gt_powersave(dev);
4679 void intel_disable_gt_powersave(struct drm_device *dev)
4681 struct drm_i915_private *dev_priv = dev->dev_private;
4683 /* Interrupts should be disabled already to avoid re-arming. */
4684 WARN_ON(dev->irq_enabled);
4686 if (IS_IRONLAKE_M(dev)) {
4687 ironlake_disable_drps(dev);
4688 ironlake_disable_rc6(dev);
4689 } else if (IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)) {
4690 if (cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work))
4691 intel_runtime_pm_put(dev_priv);
4693 cancel_work_sync(&dev_priv->rps.work);
4694 mutex_lock(&dev_priv->rps.hw_lock);
4695 if (IS_VALLEYVIEW(dev))
4696 valleyview_disable_rps(dev);
4698 gen6_disable_rps(dev);
4699 dev_priv->rps.enabled = false;
4700 mutex_unlock(&dev_priv->rps.hw_lock);
4704 static void intel_gen6_powersave_work(struct work_struct *work)
4706 struct drm_i915_private *dev_priv =
4707 container_of(work, struct drm_i915_private,
4708 rps.delayed_resume_work.work);
4709 struct drm_device *dev = dev_priv->dev;
4711 mutex_lock(&dev_priv->rps.hw_lock);
4713 if (IS_VALLEYVIEW(dev)) {
4714 valleyview_enable_rps(dev);
4715 } else if (IS_BROADWELL(dev)) {
4716 gen8_enable_rps(dev);
4717 __gen6_update_ring_freq(dev);
4719 gen6_enable_rps(dev);
4720 __gen6_update_ring_freq(dev);
4722 dev_priv->rps.enabled = true;
4723 mutex_unlock(&dev_priv->rps.hw_lock);
4725 intel_runtime_pm_put(dev_priv);
4728 void intel_enable_gt_powersave(struct drm_device *dev)
4730 struct drm_i915_private *dev_priv = dev->dev_private;
4732 if (IS_IRONLAKE_M(dev)) {
4733 mutex_lock(&dev->struct_mutex);
4734 ironlake_enable_drps(dev);
4735 ironlake_enable_rc6(dev);
4736 intel_init_emon(dev);
4737 mutex_unlock(&dev->struct_mutex);
4738 } else if (IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)) {
4740 * PCU communication is slow and this doesn't need to be
4741 * done at any specific time, so do this out of our fast path
4742 * to make resume and init faster.
4744 * We depend on the HW RC6 power context save/restore
4745 * mechanism when entering D3 through runtime PM suspend. So
4746 * disable RPM until RPS/RC6 is properly setup. We can only
4747 * get here via the driver load/system resume/runtime resume
4748 * paths, so the _noresume version is enough (and in case of
4749 * runtime resume it's necessary).
4751 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4752 round_jiffies_up_relative(HZ)))
4753 intel_runtime_pm_get_noresume(dev_priv);
4757 void intel_reset_gt_powersave(struct drm_device *dev)
4759 struct drm_i915_private *dev_priv = dev->dev_private;
4761 dev_priv->rps.enabled = false;
4762 intel_enable_gt_powersave(dev);
4765 static void ibx_init_clock_gating(struct drm_device *dev)
4767 struct drm_i915_private *dev_priv = dev->dev_private;
4770 * On Ibex Peak and Cougar Point, we need to disable clock
4771 * gating for the panel power sequencer or it will fail to
4772 * start up when no ports are active.
4774 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4777 static void g4x_disable_trickle_feed(struct drm_device *dev)
4779 struct drm_i915_private *dev_priv = dev->dev_private;
4782 for_each_pipe(pipe) {
4783 I915_WRITE(DSPCNTR(pipe),
4784 I915_READ(DSPCNTR(pipe)) |
4785 DISPPLANE_TRICKLE_FEED_DISABLE);
4786 intel_flush_primary_plane(dev_priv, pipe);
4790 static void ilk_init_lp_watermarks(struct drm_device *dev)
4792 struct drm_i915_private *dev_priv = dev->dev_private;
4794 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4795 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4796 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4799 * Don't touch WM1S_LP_EN here.
4800 * Doing so could cause underruns.
4804 static void ironlake_init_clock_gating(struct drm_device *dev)
4806 struct drm_i915_private *dev_priv = dev->dev_private;
4807 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4811 * WaFbcDisableDpfcClockGating:ilk
4813 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4814 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4815 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4817 I915_WRITE(PCH_3DCGDIS0,
4818 MARIUNIT_CLOCK_GATE_DISABLE |
4819 SVSMUNIT_CLOCK_GATE_DISABLE);
4820 I915_WRITE(PCH_3DCGDIS1,
4821 VFMUNIT_CLOCK_GATE_DISABLE);
4824 * According to the spec the following bits should be set in
4825 * order to enable memory self-refresh
4826 * The bit 22/21 of 0x42004
4827 * The bit 5 of 0x42020
4828 * The bit 15 of 0x45000
4830 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4831 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4832 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4833 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4834 I915_WRITE(DISP_ARB_CTL,
4835 (I915_READ(DISP_ARB_CTL) |
4838 ilk_init_lp_watermarks(dev);
4841 * Based on the document from hardware guys the following bits
4842 * should be set unconditionally in order to enable FBC.
4843 * The bit 22 of 0x42000
4844 * The bit 22 of 0x42004
4845 * The bit 7,8,9 of 0x42020.
4847 if (IS_IRONLAKE_M(dev)) {
4848 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4849 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4850 I915_READ(ILK_DISPLAY_CHICKEN1) |
4852 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4853 I915_READ(ILK_DISPLAY_CHICKEN2) |
4857 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4859 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4860 I915_READ(ILK_DISPLAY_CHICKEN2) |
4861 ILK_ELPIN_409_SELECT);
4862 I915_WRITE(_3D_CHICKEN2,
4863 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4864 _3D_CHICKEN2_WM_READ_PIPELINED);
4866 /* WaDisableRenderCachePipelinedFlush:ilk */
4867 I915_WRITE(CACHE_MODE_0,
4868 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4870 /* WaDisable_RenderCache_OperationalFlush:ilk */
4871 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4873 g4x_disable_trickle_feed(dev);
4875 ibx_init_clock_gating(dev);
4878 static void cpt_init_clock_gating(struct drm_device *dev)
4880 struct drm_i915_private *dev_priv = dev->dev_private;
4885 * On Ibex Peak and Cougar Point, we need to disable clock
4886 * gating for the panel power sequencer or it will fail to
4887 * start up when no ports are active.
4889 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4890 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4891 PCH_CPUNIT_CLOCK_GATE_DISABLE);
4892 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4893 DPLS_EDP_PPS_FIX_DIS);
4894 /* The below fixes the weird display corruption, a few pixels shifted
4895 * downward, on (only) LVDS of some HP laptops with IVY.
4897 for_each_pipe(pipe) {
4898 val = I915_READ(TRANS_CHICKEN2(pipe));
4899 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4900 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4901 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4902 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4903 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4904 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4905 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4906 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4908 /* WADP0ClockGatingDisable */
4909 for_each_pipe(pipe) {
4910 I915_WRITE(TRANS_CHICKEN1(pipe),
4911 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4915 static void gen6_check_mch_setup(struct drm_device *dev)
4917 struct drm_i915_private *dev_priv = dev->dev_private;
4920 tmp = I915_READ(MCH_SSKPD);
4921 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4922 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4923 DRM_INFO("This can cause pipe underruns and display issues.\n");
4924 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4928 static void gen6_init_clock_gating(struct drm_device *dev)
4930 struct drm_i915_private *dev_priv = dev->dev_private;
4931 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4933 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4935 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4936 I915_READ(ILK_DISPLAY_CHICKEN2) |
4937 ILK_ELPIN_409_SELECT);
4939 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4940 I915_WRITE(_3D_CHICKEN,
4941 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4943 /* WaSetupGtModeTdRowDispatch:snb */
4944 if (IS_SNB_GT1(dev))
4945 I915_WRITE(GEN6_GT_MODE,
4946 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4948 /* WaDisable_RenderCache_OperationalFlush:snb */
4949 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4952 * BSpec recoomends 8x4 when MSAA is used,
4953 * however in practice 16x4 seems fastest.
4955 * Note that PS/WM thread counts depend on the WIZ hashing
4956 * disable bit, which we don't touch here, but it's good
4957 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4959 I915_WRITE(GEN6_GT_MODE,
4960 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4962 ilk_init_lp_watermarks(dev);
4964 I915_WRITE(CACHE_MODE_0,
4965 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4967 I915_WRITE(GEN6_UCGCTL1,
4968 I915_READ(GEN6_UCGCTL1) |
4969 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4970 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4972 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4973 * gating disable must be set. Failure to set it results in
4974 * flickering pixels due to Z write ordering failures after
4975 * some amount of runtime in the Mesa "fire" demo, and Unigine
4976 * Sanctuary and Tropics, and apparently anything else with
4977 * alpha test or pixel discard.
4979 * According to the spec, bit 11 (RCCUNIT) must also be set,
4980 * but we didn't debug actual testcases to find it out.
4982 * WaDisableRCCUnitClockGating:snb
4983 * WaDisableRCPBUnitClockGating:snb
4985 I915_WRITE(GEN6_UCGCTL2,
4986 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4987 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4989 /* WaStripsFansDisableFastClipPerformanceFix:snb */
4990 I915_WRITE(_3D_CHICKEN3,
4991 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
4995 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
4996 * 3DSTATE_SF number of SF output attributes is more than 16."
4998 I915_WRITE(_3D_CHICKEN3,
4999 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5002 * According to the spec the following bits should be
5003 * set in order to enable memory self-refresh and fbc:
5004 * The bit21 and bit22 of 0x42000
5005 * The bit21 and bit22 of 0x42004
5006 * The bit5 and bit7 of 0x42020
5007 * The bit14 of 0x70180
5008 * The bit14 of 0x71180
5010 * WaFbcAsynchFlipDisableFbcQueue:snb
5012 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5013 I915_READ(ILK_DISPLAY_CHICKEN1) |
5014 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5015 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5016 I915_READ(ILK_DISPLAY_CHICKEN2) |
5017 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5018 I915_WRITE(ILK_DSPCLK_GATE_D,
5019 I915_READ(ILK_DSPCLK_GATE_D) |
5020 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5021 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5023 g4x_disable_trickle_feed(dev);
5025 cpt_init_clock_gating(dev);
5027 gen6_check_mch_setup(dev);
5030 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5032 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5035 * WaVSThreadDispatchOverride:ivb,vlv
5037 * This actually overrides the dispatch
5038 * mode for all thread types.
5040 reg &= ~GEN7_FF_SCHED_MASK;
5041 reg |= GEN7_FF_TS_SCHED_HW;
5042 reg |= GEN7_FF_VS_SCHED_HW;
5043 reg |= GEN7_FF_DS_SCHED_HW;
5045 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5048 static void lpt_init_clock_gating(struct drm_device *dev)
5050 struct drm_i915_private *dev_priv = dev->dev_private;
5053 * TODO: this bit should only be enabled when really needed, then
5054 * disabled when not needed anymore in order to save power.
5056 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5057 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5058 I915_READ(SOUTH_DSPCLK_GATE_D) |
5059 PCH_LP_PARTITION_LEVEL_DISABLE);
5061 /* WADPOClockGatingDisable:hsw */
5062 I915_WRITE(_TRANSA_CHICKEN1,
5063 I915_READ(_TRANSA_CHICKEN1) |
5064 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5067 static void lpt_suspend_hw(struct drm_device *dev)
5069 struct drm_i915_private *dev_priv = dev->dev_private;
5071 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5072 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5074 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5075 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5079 static void gen8_init_clock_gating(struct drm_device *dev)
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5084 I915_WRITE(WM3_LP_ILK, 0);
5085 I915_WRITE(WM2_LP_ILK, 0);
5086 I915_WRITE(WM1_LP_ILK, 0);
5088 /* FIXME(BDW): Check all the w/a, some might only apply to
5089 * pre-production hw. */
5091 /* WaDisablePartialInstShootdown:bdw */
5092 I915_WRITE(GEN8_ROW_CHICKEN,
5093 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5095 /* WaDisableThreadStallDopClockGating:bdw */
5096 /* FIXME: Unclear whether we really need this on production bdw. */
5097 I915_WRITE(GEN8_ROW_CHICKEN,
5098 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5101 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5102 * pre-production hardware
5104 I915_WRITE(HALF_SLICE_CHICKEN3,
5105 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5106 I915_WRITE(HALF_SLICE_CHICKEN3,
5107 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5108 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5110 I915_WRITE(_3D_CHICKEN3,
5111 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5113 I915_WRITE(COMMON_SLICE_CHICKEN2,
5114 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5116 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5117 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5119 /* WaDisableDopClockGating:bdw May not be needed for production */
5120 I915_WRITE(GEN7_ROW_CHICKEN2,
5121 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5123 /* WaSwitchSolVfFArbitrationPriority:bdw */
5124 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5126 /* WaPsrDPAMaskVBlankInSRD:bdw */
5127 I915_WRITE(CHICKEN_PAR1_1,
5128 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5130 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5131 for_each_pipe(pipe) {
5132 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5133 I915_READ(CHICKEN_PIPESL_1(pipe)) |
5134 BDW_DPRS_MASK_VBLANK_SRD);
5137 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5138 * workaround for for a possible hang in the unlikely event a TLB
5139 * invalidation occurs during a PSD flush.
5141 I915_WRITE(HDC_CHICKEN0,
5142 I915_READ(HDC_CHICKEN0) |
5143 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5145 /* WaVSRefCountFullforceMissDisable:bdw */
5146 /* WaDSRefCountFullforceMissDisable:bdw */
5147 I915_WRITE(GEN7_FF_THREAD_MODE,
5148 I915_READ(GEN7_FF_THREAD_MODE) &
5149 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5152 * BSpec recommends 8x4 when MSAA is used,
5153 * however in practice 16x4 seems fastest.
5155 * Note that PS/WM thread counts depend on the WIZ hashing
5156 * disable bit, which we don't touch here, but it's good
5157 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5159 I915_WRITE(GEN7_GT_MODE,
5160 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5162 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5163 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5165 /* WaDisableSDEUnitClockGating:bdw */
5166 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5167 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5169 /* Wa4x4STCOptimizationDisable:bdw */
5170 I915_WRITE(CACHE_MODE_1,
5171 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
5174 static void haswell_init_clock_gating(struct drm_device *dev)
5176 struct drm_i915_private *dev_priv = dev->dev_private;
5178 ilk_init_lp_watermarks(dev);
5180 /* L3 caching of data atomics doesn't work -- disable it. */
5181 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5182 I915_WRITE(HSW_ROW_CHICKEN3,
5183 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5185 /* This is required by WaCatErrorRejectionIssue:hsw */
5186 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5187 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5188 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5190 /* WaVSRefCountFullforceMissDisable:hsw */
5191 I915_WRITE(GEN7_FF_THREAD_MODE,
5192 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5194 /* WaDisable_RenderCache_OperationalFlush:hsw */
5195 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5197 /* enable HiZ Raw Stall Optimization */
5198 I915_WRITE(CACHE_MODE_0_GEN7,
5199 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5201 /* WaDisable4x2SubspanOptimization:hsw */
5202 I915_WRITE(CACHE_MODE_1,
5203 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5206 * BSpec recommends 8x4 when MSAA is used,
5207 * however in practice 16x4 seems fastest.
5209 * Note that PS/WM thread counts depend on the WIZ hashing
5210 * disable bit, which we don't touch here, but it's good
5211 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5213 I915_WRITE(GEN7_GT_MODE,
5214 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5216 /* WaSwitchSolVfFArbitrationPriority:hsw */
5217 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5219 /* WaRsPkgCStateDisplayPMReq:hsw */
5220 I915_WRITE(CHICKEN_PAR1_1,
5221 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5223 lpt_init_clock_gating(dev);
5226 static void ivybridge_init_clock_gating(struct drm_device *dev)
5228 struct drm_i915_private *dev_priv = dev->dev_private;
5231 ilk_init_lp_watermarks(dev);
5233 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5235 /* WaDisableEarlyCull:ivb */
5236 I915_WRITE(_3D_CHICKEN3,
5237 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5239 /* WaDisableBackToBackFlipFix:ivb */
5240 I915_WRITE(IVB_CHICKEN3,
5241 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5242 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5244 /* WaDisablePSDDualDispatchEnable:ivb */
5245 if (IS_IVB_GT1(dev))
5246 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5247 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5249 /* WaDisable_RenderCache_OperationalFlush:ivb */
5250 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5252 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5253 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5254 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5256 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5257 I915_WRITE(GEN7_L3CNTLREG1,
5258 GEN7_WA_FOR_GEN7_L3_CONTROL);
5259 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5260 GEN7_WA_L3_CHICKEN_MODE);
5261 if (IS_IVB_GT1(dev))
5262 I915_WRITE(GEN7_ROW_CHICKEN2,
5263 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5265 /* must write both registers */
5266 I915_WRITE(GEN7_ROW_CHICKEN2,
5267 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5268 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5269 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5272 /* WaForceL3Serialization:ivb */
5273 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5274 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5277 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5278 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5280 I915_WRITE(GEN6_UCGCTL2,
5281 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5283 /* This is required by WaCatErrorRejectionIssue:ivb */
5284 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5285 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5286 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5288 g4x_disable_trickle_feed(dev);
5290 gen7_setup_fixed_func_scheduler(dev_priv);
5292 if (0) { /* causes HiZ corruption on ivb:gt1 */
5293 /* enable HiZ Raw Stall Optimization */
5294 I915_WRITE(CACHE_MODE_0_GEN7,
5295 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5298 /* WaDisable4x2SubspanOptimization:ivb */
5299 I915_WRITE(CACHE_MODE_1,
5300 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5303 * BSpec recommends 8x4 when MSAA is used,
5304 * however in practice 16x4 seems fastest.
5306 * Note that PS/WM thread counts depend on the WIZ hashing
5307 * disable bit, which we don't touch here, but it's good
5308 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5310 I915_WRITE(GEN7_GT_MODE,
5311 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5313 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5314 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5315 snpcr |= GEN6_MBC_SNPCR_MED;
5316 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5318 if (!HAS_PCH_NOP(dev))
5319 cpt_init_clock_gating(dev);
5321 gen6_check_mch_setup(dev);
5324 static void valleyview_init_clock_gating(struct drm_device *dev)
5326 struct drm_i915_private *dev_priv = dev->dev_private;
5329 mutex_lock(&dev_priv->rps.hw_lock);
5330 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5331 mutex_unlock(&dev_priv->rps.hw_lock);
5332 switch ((val >> 6) & 3) {
5335 dev_priv->mem_freq = 800;
5338 dev_priv->mem_freq = 1066;
5341 dev_priv->mem_freq = 1333;
5344 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5346 dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
5347 DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz",
5348 dev_priv->vlv_cdclk_freq);
5350 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5352 /* WaDisableEarlyCull:vlv */
5353 I915_WRITE(_3D_CHICKEN3,
5354 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5356 /* WaDisableBackToBackFlipFix:vlv */
5357 I915_WRITE(IVB_CHICKEN3,
5358 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5359 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5361 /* WaPsdDispatchEnable:vlv */
5362 /* WaDisablePSDDualDispatchEnable:vlv */
5363 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5364 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5365 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5367 /* WaDisable_RenderCache_OperationalFlush:vlv */
5368 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5370 /* WaForceL3Serialization:vlv */
5371 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5372 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5374 /* WaDisableDopClockGating:vlv */
5375 I915_WRITE(GEN7_ROW_CHICKEN2,
5376 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5378 /* This is required by WaCatErrorRejectionIssue:vlv */
5379 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5380 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5381 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5383 gen7_setup_fixed_func_scheduler(dev_priv);
5386 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5387 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5389 I915_WRITE(GEN6_UCGCTL2,
5390 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5392 /* WaDisableL3Bank2xClockGate:vlv
5393 * Disabling L3 clock gating- MMIO 940c[25] = 1
5394 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5395 I915_WRITE(GEN7_UCGCTL4,
5396 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5398 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5401 * BSpec says this must be set, even though
5402 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5404 I915_WRITE(CACHE_MODE_1,
5405 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5408 * WaIncreaseL3CreditsForVLVB0:vlv
5409 * This is the hardware default actually.
5411 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5414 * WaDisableVLVClockGating_VBIIssue:vlv
5415 * Disable clock gating on th GCFG unit to prevent a delay
5416 * in the reporting of vblank events.
5418 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5421 static void cherryview_init_clock_gating(struct drm_device *dev)
5423 struct drm_i915_private *dev_priv = dev->dev_private;
5425 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5427 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5429 /* WaDisablePartialInstShootdown:chv */
5430 I915_WRITE(GEN8_ROW_CHICKEN,
5431 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5433 /* WaDisableThreadStallDopClockGating:chv */
5434 I915_WRITE(GEN8_ROW_CHICKEN,
5435 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5437 /* WaVSRefCountFullforceMissDisable:chv */
5438 /* WaDSRefCountFullforceMissDisable:chv */
5439 I915_WRITE(GEN7_FF_THREAD_MODE,
5440 I915_READ(GEN7_FF_THREAD_MODE) &
5441 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5443 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5444 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5445 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5447 /* WaDisableCSUnitClockGating:chv */
5448 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5449 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5451 /* WaDisableSDEUnitClockGating:chv */
5452 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5453 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5455 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5456 I915_WRITE(HALF_SLICE_CHICKEN3,
5457 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5459 /* WaDisableGunitClockGating:chv (pre-production hw) */
5460 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5463 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5464 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5465 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5467 /* WaDisableDopClockGating:chv (pre-production hw) */
5468 I915_WRITE(GEN7_ROW_CHICKEN2,
5469 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5470 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5471 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
5474 static void g4x_init_clock_gating(struct drm_device *dev)
5476 struct drm_i915_private *dev_priv = dev->dev_private;
5477 uint32_t dspclk_gate;
5479 I915_WRITE(RENCLK_GATE_D1, 0);
5480 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5481 GS_UNIT_CLOCK_GATE_DISABLE |
5482 CL_UNIT_CLOCK_GATE_DISABLE);
5483 I915_WRITE(RAMCLK_GATE_D, 0);
5484 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5485 OVRUNIT_CLOCK_GATE_DISABLE |
5486 OVCUNIT_CLOCK_GATE_DISABLE;
5488 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5489 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5491 /* WaDisableRenderCachePipelinedFlush */
5492 I915_WRITE(CACHE_MODE_0,
5493 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5495 /* WaDisable_RenderCache_OperationalFlush:g4x */
5496 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5498 g4x_disable_trickle_feed(dev);
5501 static void crestline_init_clock_gating(struct drm_device *dev)
5503 struct drm_i915_private *dev_priv = dev->dev_private;
5505 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5506 I915_WRITE(RENCLK_GATE_D2, 0);
5507 I915_WRITE(DSPCLK_GATE_D, 0);
5508 I915_WRITE(RAMCLK_GATE_D, 0);
5509 I915_WRITE16(DEUC, 0);
5510 I915_WRITE(MI_ARB_STATE,
5511 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5513 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5514 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5517 static void broadwater_init_clock_gating(struct drm_device *dev)
5519 struct drm_i915_private *dev_priv = dev->dev_private;
5521 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5522 I965_RCC_CLOCK_GATE_DISABLE |
5523 I965_RCPB_CLOCK_GATE_DISABLE |
5524 I965_ISC_CLOCK_GATE_DISABLE |
5525 I965_FBC_CLOCK_GATE_DISABLE);
5526 I915_WRITE(RENCLK_GATE_D2, 0);
5527 I915_WRITE(MI_ARB_STATE,
5528 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5530 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5531 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5534 static void gen3_init_clock_gating(struct drm_device *dev)
5536 struct drm_i915_private *dev_priv = dev->dev_private;
5537 u32 dstate = I915_READ(D_STATE);
5539 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5540 DSTATE_DOT_CLOCK_GATING;
5541 I915_WRITE(D_STATE, dstate);
5543 if (IS_PINEVIEW(dev))
5544 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5546 /* IIR "flip pending" means done if this bit is set */
5547 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5549 /* interrupts should cause a wake up from C3 */
5550 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
5552 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5553 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5556 static void i85x_init_clock_gating(struct drm_device *dev)
5558 struct drm_i915_private *dev_priv = dev->dev_private;
5560 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5562 /* interrupts should cause a wake up from C3 */
5563 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
5564 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
5567 static void i830_init_clock_gating(struct drm_device *dev)
5569 struct drm_i915_private *dev_priv = dev->dev_private;
5571 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5574 void intel_init_clock_gating(struct drm_device *dev)
5576 struct drm_i915_private *dev_priv = dev->dev_private;
5578 dev_priv->display.init_clock_gating(dev);
5581 void intel_suspend_hw(struct drm_device *dev)
5583 if (HAS_PCH_LPT(dev))
5584 lpt_suspend_hw(dev);
5587 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
5589 i < (power_domains)->power_well_count && \
5590 ((power_well) = &(power_domains)->power_wells[i]); \
5592 if ((power_well)->domains & (domain_mask))
5594 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5595 for (i = (power_domains)->power_well_count - 1; \
5596 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5598 if ((power_well)->domains & (domain_mask))
5601 * We should only use the power well if we explicitly asked the hardware to
5602 * enable it, so check if it's enabled and also check if we've requested it to
5605 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
5606 struct i915_power_well *power_well)
5608 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5609 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5612 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
5613 enum intel_display_power_domain domain)
5615 struct i915_power_domains *power_domains;
5616 struct i915_power_well *power_well;
5620 if (dev_priv->pm.suspended)
5623 power_domains = &dev_priv->power_domains;
5627 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5628 if (power_well->always_on)
5631 if (!power_well->hw_enabled) {
5640 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
5641 enum intel_display_power_domain domain)
5643 struct i915_power_domains *power_domains;
5646 power_domains = &dev_priv->power_domains;
5648 mutex_lock(&power_domains->lock);
5649 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
5650 mutex_unlock(&power_domains->lock);
5656 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5657 * when not needed anymore. We have 4 registers that can request the power well
5658 * to be enabled, and it will only be disabled if none of the registers is
5659 * requesting it to be enabled.
5661 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5663 struct drm_device *dev = dev_priv->dev;
5664 unsigned long irqflags;
5667 * After we re-enable the power well, if we touch VGA register 0x3d5
5668 * we'll get unclaimed register interrupts. This stops after we write
5669 * anything to the VGA MSR register. The vgacon module uses this
5670 * register all the time, so if we unbind our driver and, as a
5671 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5672 * console_unlock(). So make here we touch the VGA MSR register, making
5673 * sure vgacon can keep working normally without triggering interrupts
5674 * and error messages.
5676 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5677 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5678 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5680 if (IS_BROADWELL(dev)) {
5681 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5682 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5683 dev_priv->de_irq_mask[PIPE_B]);
5684 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5685 ~dev_priv->de_irq_mask[PIPE_B] |
5687 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5688 dev_priv->de_irq_mask[PIPE_C]);
5689 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5690 ~dev_priv->de_irq_mask[PIPE_C] |
5692 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5693 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5697 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
5698 struct i915_power_well *power_well, bool enable)
5700 bool is_enabled, enable_requested;
5703 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5704 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5705 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5708 if (!enable_requested)
5709 I915_WRITE(HSW_PWR_WELL_DRIVER,
5710 HSW_PWR_WELL_ENABLE_REQUEST);
5713 DRM_DEBUG_KMS("Enabling power well\n");
5714 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5715 HSW_PWR_WELL_STATE_ENABLED), 20))
5716 DRM_ERROR("Timeout enabling power well\n");
5719 hsw_power_well_post_enable(dev_priv);
5721 if (enable_requested) {
5722 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5723 POSTING_READ(HSW_PWR_WELL_DRIVER);
5724 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5729 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5730 struct i915_power_well *power_well)
5732 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5735 * We're taking over the BIOS, so clear any requests made by it since
5736 * the driver is in charge now.
5738 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5739 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5742 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5743 struct i915_power_well *power_well)
5745 hsw_set_power_well(dev_priv, power_well, true);
5748 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5749 struct i915_power_well *power_well)
5751 hsw_set_power_well(dev_priv, power_well, false);
5754 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5755 struct i915_power_well *power_well)
5759 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5760 struct i915_power_well *power_well)
5765 void __vlv_set_power_well(struct drm_i915_private *dev_priv,
5766 enum punit_power_well power_well_id, bool enable)
5768 struct drm_device *dev = dev_priv->dev;
5774 if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
5777 * Enable the CRI clock source so we can get at the
5778 * display and the reference clock for VGA
5779 * hotplug / manual detection.
5781 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
5782 DPLL_REFA_CLK_ENABLE_VLV |
5783 DPLL_INTEGRATED_CRI_CLK_VLV);
5784 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
5787 assert_pll_disabled(dev_priv, pipe);
5788 /* Assert common reset */
5789 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) &
5794 mask = PUNIT_PWRGT_MASK(power_well_id);
5795 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
5796 PUNIT_PWRGT_PWR_GATE(power_well_id);
5798 mutex_lock(&dev_priv->rps.hw_lock);
5801 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
5806 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
5809 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
5811 if (wait_for(COND, 100))
5812 DRM_ERROR("timout setting power well state %08x (%08x)\n",
5814 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
5819 mutex_unlock(&dev_priv->rps.hw_lock);
5822 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
5823 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
5824 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
5825 * b. The other bits such as sfr settings / modesel may all
5828 * This should only be done on init and resume from S3 with
5829 * both PLLs disabled, or we risk losing DPIO and PLL
5832 if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC && enable)
5833 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
5836 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5837 struct i915_power_well *power_well, bool enable)
5839 enum punit_power_well power_well_id = power_well->data;
5841 __vlv_set_power_well(dev_priv, power_well_id, enable);
5844 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
5845 struct i915_power_well *power_well)
5847 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
5850 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
5851 struct i915_power_well *power_well)
5853 vlv_set_power_well(dev_priv, power_well, true);
5856 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
5857 struct i915_power_well *power_well)
5859 vlv_set_power_well(dev_priv, power_well, false);
5862 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
5863 struct i915_power_well *power_well)
5865 int power_well_id = power_well->data;
5866 bool enabled = false;
5871 mask = PUNIT_PWRGT_MASK(power_well_id);
5872 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
5874 mutex_lock(&dev_priv->rps.hw_lock);
5876 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
5878 * We only ever set the power-on and power-gate states, anything
5879 * else is unexpected.
5881 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
5882 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
5887 * A transient state at this point would mean some unexpected party
5888 * is poking at the power controls too.
5890 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
5891 WARN_ON(ctrl != state);
5893 mutex_unlock(&dev_priv->rps.hw_lock);
5898 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
5899 struct i915_power_well *power_well)
5901 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5903 vlv_set_power_well(dev_priv, power_well, true);
5905 spin_lock_irq(&dev_priv->irq_lock);
5906 valleyview_enable_display_irqs(dev_priv);
5907 spin_unlock_irq(&dev_priv->irq_lock);
5910 * During driver initialization/resume we can avoid restoring the
5911 * part of the HW/SW state that will be inited anyway explicitly.
5913 if (dev_priv->power_domains.initializing)
5916 intel_hpd_init(dev_priv->dev);
5918 i915_redisable_vga_power_on(dev_priv->dev);
5921 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
5922 struct i915_power_well *power_well)
5924 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5926 spin_lock_irq(&dev_priv->irq_lock);
5927 valleyview_disable_display_irqs(dev_priv);
5928 spin_unlock_irq(&dev_priv->irq_lock);
5930 vlv_set_power_well(dev_priv, power_well, false);
5933 static void check_power_well_state(struct drm_i915_private *dev_priv,
5934 struct i915_power_well *power_well)
5936 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
5938 if (power_well->always_on || !i915.disable_power_well) {
5945 if (enabled != (power_well->count > 0))
5951 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
5952 power_well->name, power_well->always_on, enabled,
5953 power_well->count, i915.disable_power_well);
5956 void intel_display_power_get(struct drm_i915_private *dev_priv,
5957 enum intel_display_power_domain domain)
5959 struct i915_power_domains *power_domains;
5960 struct i915_power_well *power_well;
5963 intel_runtime_pm_get(dev_priv);
5965 power_domains = &dev_priv->power_domains;
5967 mutex_lock(&power_domains->lock);
5969 for_each_power_well(i, power_well, BIT(domain), power_domains) {
5970 if (!power_well->count++) {
5971 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
5972 power_well->ops->enable(dev_priv, power_well);
5973 power_well->hw_enabled = true;
5976 check_power_well_state(dev_priv, power_well);
5979 power_domains->domain_use_count[domain]++;
5981 mutex_unlock(&power_domains->lock);
5984 void intel_display_power_put(struct drm_i915_private *dev_priv,
5985 enum intel_display_power_domain domain)
5987 struct i915_power_domains *power_domains;
5988 struct i915_power_well *power_well;
5991 power_domains = &dev_priv->power_domains;
5993 mutex_lock(&power_domains->lock);
5995 WARN_ON(!power_domains->domain_use_count[domain]);
5996 power_domains->domain_use_count[domain]--;
5998 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5999 WARN_ON(!power_well->count);
6001 if (!--power_well->count && i915.disable_power_well) {
6002 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
6003 power_well->hw_enabled = false;
6004 power_well->ops->disable(dev_priv, power_well);
6007 check_power_well_state(dev_priv, power_well);
6010 mutex_unlock(&power_domains->lock);
6012 intel_runtime_pm_put(dev_priv);
6015 static struct i915_power_domains *hsw_pwr;
6017 /* Display audio driver power well request */
6018 int i915_request_power_well(void)
6020 struct drm_i915_private *dev_priv;
6025 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6027 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6030 EXPORT_SYMBOL_GPL(i915_request_power_well);
6032 /* Display audio driver power well release */
6033 int i915_release_power_well(void)
6035 struct drm_i915_private *dev_priv;
6040 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6042 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6045 EXPORT_SYMBOL_GPL(i915_release_power_well);
6048 * Private interface for the audio driver to get CDCLK in kHz.
6050 * Caller must request power well using i915_request_power_well() prior to
6053 int i915_get_cdclk_freq(void)
6055 struct drm_i915_private *dev_priv;
6060 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6063 return intel_ddi_get_cdclk_freq(dev_priv);
6065 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6068 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6070 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6071 BIT(POWER_DOMAIN_PIPE_A) | \
6072 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6073 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6074 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6075 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6076 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6077 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6078 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6079 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6080 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6081 BIT(POWER_DOMAIN_PORT_CRT) | \
6082 BIT(POWER_DOMAIN_INIT))
6083 #define HSW_DISPLAY_POWER_DOMAINS ( \
6084 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6085 BIT(POWER_DOMAIN_INIT))
6087 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6088 HSW_ALWAYS_ON_POWER_DOMAINS | \
6089 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6090 #define BDW_DISPLAY_POWER_DOMAINS ( \
6091 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6092 BIT(POWER_DOMAIN_INIT))
6094 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6095 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6097 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6098 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6099 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6100 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6101 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6102 BIT(POWER_DOMAIN_PORT_CRT) | \
6103 BIT(POWER_DOMAIN_INIT))
6105 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6106 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6107 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6108 BIT(POWER_DOMAIN_INIT))
6110 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6111 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6112 BIT(POWER_DOMAIN_INIT))
6114 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6115 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6116 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6117 BIT(POWER_DOMAIN_INIT))
6119 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6120 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6121 BIT(POWER_DOMAIN_INIT))
6123 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6124 .sync_hw = i9xx_always_on_power_well_noop,
6125 .enable = i9xx_always_on_power_well_noop,
6126 .disable = i9xx_always_on_power_well_noop,
6127 .is_enabled = i9xx_always_on_power_well_enabled,
6130 static struct i915_power_well i9xx_always_on_power_well[] = {
6132 .name = "always-on",
6134 .domains = POWER_DOMAIN_MASK,
6135 .ops = &i9xx_always_on_power_well_ops,
6139 static const struct i915_power_well_ops hsw_power_well_ops = {
6140 .sync_hw = hsw_power_well_sync_hw,
6141 .enable = hsw_power_well_enable,
6142 .disable = hsw_power_well_disable,
6143 .is_enabled = hsw_power_well_enabled,
6146 static struct i915_power_well hsw_power_wells[] = {
6148 .name = "always-on",
6150 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6151 .ops = &i9xx_always_on_power_well_ops,
6155 .domains = HSW_DISPLAY_POWER_DOMAINS,
6156 .ops = &hsw_power_well_ops,
6160 static struct i915_power_well bdw_power_wells[] = {
6162 .name = "always-on",
6164 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6165 .ops = &i9xx_always_on_power_well_ops,
6169 .domains = BDW_DISPLAY_POWER_DOMAINS,
6170 .ops = &hsw_power_well_ops,
6174 static const struct i915_power_well_ops vlv_display_power_well_ops = {
6175 .sync_hw = vlv_power_well_sync_hw,
6176 .enable = vlv_display_power_well_enable,
6177 .disable = vlv_display_power_well_disable,
6178 .is_enabled = vlv_power_well_enabled,
6181 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6182 .sync_hw = vlv_power_well_sync_hw,
6183 .enable = vlv_power_well_enable,
6184 .disable = vlv_power_well_disable,
6185 .is_enabled = vlv_power_well_enabled,
6188 static struct i915_power_well vlv_power_wells[] = {
6190 .name = "always-on",
6192 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6193 .ops = &i9xx_always_on_power_well_ops,
6197 .domains = VLV_DISPLAY_POWER_DOMAINS,
6198 .data = PUNIT_POWER_WELL_DISP2D,
6199 .ops = &vlv_display_power_well_ops,
6202 .name = "dpio-tx-b-01",
6203 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6204 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6205 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6206 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6207 .ops = &vlv_dpio_power_well_ops,
6208 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6211 .name = "dpio-tx-b-23",
6212 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6213 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6214 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6215 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6216 .ops = &vlv_dpio_power_well_ops,
6217 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6220 .name = "dpio-tx-c-01",
6221 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6222 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6223 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6224 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6225 .ops = &vlv_dpio_power_well_ops,
6226 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6229 .name = "dpio-tx-c-23",
6230 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6231 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6232 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6233 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6234 .ops = &vlv_dpio_power_well_ops,
6235 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6238 .name = "dpio-common",
6239 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6240 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6241 .ops = &vlv_dpio_power_well_ops,
6245 #define set_power_wells(power_domains, __power_wells) ({ \
6246 (power_domains)->power_wells = (__power_wells); \
6247 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6250 int intel_power_domains_init(struct drm_i915_private *dev_priv)
6252 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6254 mutex_init(&power_domains->lock);
6257 * The enabling order will be from lower to higher indexed wells,
6258 * the disabling order is reversed.
6260 if (IS_HASWELL(dev_priv->dev)) {
6261 set_power_wells(power_domains, hsw_power_wells);
6262 hsw_pwr = power_domains;
6263 } else if (IS_BROADWELL(dev_priv->dev)) {
6264 set_power_wells(power_domains, bdw_power_wells);
6265 hsw_pwr = power_domains;
6266 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6267 set_power_wells(power_domains, vlv_power_wells);
6269 set_power_wells(power_domains, i9xx_always_on_power_well);
6275 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
6280 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
6282 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6283 struct i915_power_well *power_well;
6286 mutex_lock(&power_domains->lock);
6287 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
6288 power_well->ops->sync_hw(dev_priv, power_well);
6289 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
6292 mutex_unlock(&power_domains->lock);
6295 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
6297 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6299 power_domains->initializing = true;
6300 /* For now, we need the power well to be always enabled. */
6301 intel_display_set_init_power(dev_priv, true);
6302 intel_power_domains_resume(dev_priv);
6303 power_domains->initializing = false;
6306 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6308 intel_runtime_pm_get(dev_priv);
6311 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6313 intel_runtime_pm_put(dev_priv);
6316 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6318 struct drm_device *dev = dev_priv->dev;
6319 struct device *device = &dev->pdev->dev;
6321 if (!HAS_RUNTIME_PM(dev))
6324 pm_runtime_get_sync(device);
6325 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6328 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6330 struct drm_device *dev = dev_priv->dev;
6331 struct device *device = &dev->pdev->dev;
6333 if (!HAS_RUNTIME_PM(dev))
6336 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6337 pm_runtime_get_noresume(device);
6340 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6342 struct drm_device *dev = dev_priv->dev;
6343 struct device *device = &dev->pdev->dev;
6345 if (!HAS_RUNTIME_PM(dev))
6348 pm_runtime_mark_last_busy(device);
6349 pm_runtime_put_autosuspend(device);
6352 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6354 struct drm_device *dev = dev_priv->dev;
6355 struct device *device = &dev->pdev->dev;
6357 if (!HAS_RUNTIME_PM(dev))
6360 pm_runtime_set_active(device);
6363 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6366 if (!intel_enable_rc6(dev)) {
6367 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6371 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6372 pm_runtime_mark_last_busy(device);
6373 pm_runtime_use_autosuspend(device);
6375 pm_runtime_put_autosuspend(device);
6378 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6380 struct drm_device *dev = dev_priv->dev;
6381 struct device *device = &dev->pdev->dev;
6383 if (!HAS_RUNTIME_PM(dev))
6386 if (!intel_enable_rc6(dev))
6389 /* Make sure we're not suspended first. */
6390 pm_runtime_get_sync(device);
6391 pm_runtime_disable(device);
6394 /* Set up chip specific power management-related functions */
6395 void intel_init_pm(struct drm_device *dev)
6397 struct drm_i915_private *dev_priv = dev->dev_private;
6400 if (INTEL_INFO(dev)->gen >= 7) {
6401 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6402 dev_priv->display.enable_fbc = gen7_enable_fbc;
6403 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6404 } else if (INTEL_INFO(dev)->gen >= 5) {
6405 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6406 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6407 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6408 } else if (IS_GM45(dev)) {
6409 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6410 dev_priv->display.enable_fbc = g4x_enable_fbc;
6411 dev_priv->display.disable_fbc = g4x_disable_fbc;
6413 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6414 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6415 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6417 /* This value was pulled out of someone's hat */
6418 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6423 if (IS_PINEVIEW(dev))
6424 i915_pineview_get_mem_freq(dev);
6425 else if (IS_GEN5(dev))
6426 i915_ironlake_get_mem_freq(dev);
6428 /* For FIFO watermark updates */
6429 if (HAS_PCH_SPLIT(dev)) {
6430 ilk_setup_wm_latency(dev);
6432 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6433 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6434 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6435 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6436 dev_priv->display.update_wm = ilk_update_wm;
6437 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6439 DRM_DEBUG_KMS("Failed to read display plane latency. "
6444 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6445 else if (IS_GEN6(dev))
6446 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6447 else if (IS_IVYBRIDGE(dev))
6448 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6449 else if (IS_HASWELL(dev))
6450 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6451 else if (INTEL_INFO(dev)->gen == 8)
6452 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6453 } else if (IS_CHERRYVIEW(dev)) {
6454 dev_priv->display.update_wm = valleyview_update_wm;
6455 dev_priv->display.init_clock_gating =
6456 cherryview_init_clock_gating;
6457 } else if (IS_VALLEYVIEW(dev)) {
6458 dev_priv->display.update_wm = valleyview_update_wm;
6459 dev_priv->display.init_clock_gating =
6460 valleyview_init_clock_gating;
6461 } else if (IS_PINEVIEW(dev)) {
6462 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6465 dev_priv->mem_freq)) {
6466 DRM_INFO("failed to find known CxSR latency "
6467 "(found ddr%s fsb freq %d, mem freq %d), "
6469 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6470 dev_priv->fsb_freq, dev_priv->mem_freq);
6471 /* Disable CxSR and never update its watermark again */
6472 pineview_disable_cxsr(dev);
6473 dev_priv->display.update_wm = NULL;
6475 dev_priv->display.update_wm = pineview_update_wm;
6476 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6477 } else if (IS_G4X(dev)) {
6478 dev_priv->display.update_wm = g4x_update_wm;
6479 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6480 } else if (IS_GEN4(dev)) {
6481 dev_priv->display.update_wm = i965_update_wm;
6482 if (IS_CRESTLINE(dev))
6483 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6484 else if (IS_BROADWATER(dev))
6485 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6486 } else if (IS_GEN3(dev)) {
6487 dev_priv->display.update_wm = i9xx_update_wm;
6488 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6489 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6490 } else if (IS_GEN2(dev)) {
6491 if (INTEL_INFO(dev)->num_pipes == 1) {
6492 dev_priv->display.update_wm = i845_update_wm;
6493 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6495 dev_priv->display.update_wm = i9xx_update_wm;
6496 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6499 if (IS_I85X(dev) || IS_I865G(dev))
6500 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6502 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6504 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6508 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6510 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6512 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6513 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6517 I915_WRITE(GEN6_PCODE_DATA, *val);
6518 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6520 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6522 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6526 *val = I915_READ(GEN6_PCODE_DATA);
6527 I915_WRITE(GEN6_PCODE_DATA, 0);
6532 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6534 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6536 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6537 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6541 I915_WRITE(GEN6_PCODE_DATA, val);
6542 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6544 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6546 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6550 I915_WRITE(GEN6_PCODE_DATA, 0);
6555 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6560 switch (dev_priv->mem_freq) {
6574 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6577 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6582 switch (dev_priv->mem_freq) {
6596 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6599 void intel_pm_setup(struct drm_device *dev)
6601 struct drm_i915_private *dev_priv = dev->dev_private;
6603 mutex_init(&dev_priv->rps.hw_lock);
6605 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6606 intel_gen6_powersave_work);
6608 dev_priv->pm.suspended = false;
6609 dev_priv->pm.irqs_disabled = false;