2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
69 static void i8xx_disable_fbc(struct drm_device *dev)
71 struct drm_i915_private *dev_priv = dev->dev_private;
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
88 DRM_DEBUG_KMS("disabled FBC\n");
91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->primary->fb;
96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
107 /* FBC_CTL wants 32B or 64B units */
109 cfb_pitch = (cfb_pitch / 32) - 1;
111 cfb_pitch = (cfb_pitch / 64) - 1;
114 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
115 I915_WRITE(FBC_TAG + (i * 4), 0);
121 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
122 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
123 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
124 I915_WRITE(FBC_FENCE_OFF, crtc->y);
128 fbc_ctl = I915_READ(FBC_CONTROL);
129 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
130 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
132 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
133 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
134 fbc_ctl |= obj->fence_reg;
135 I915_WRITE(FBC_CONTROL, fbc_ctl);
137 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
138 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
141 static bool i8xx_fbc_enabled(struct drm_device *dev)
143 struct drm_i915_private *dev_priv = dev->dev_private;
145 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
148 static void g4x_enable_fbc(struct drm_crtc *crtc)
150 struct drm_device *dev = crtc->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private;
152 struct drm_framebuffer *fb = crtc->primary->fb;
153 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
154 struct drm_i915_gem_object *obj = intel_fb->obj;
155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
158 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
159 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
160 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
162 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
163 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
165 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
168 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
170 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
173 static void g4x_disable_fbc(struct drm_device *dev)
175 struct drm_i915_private *dev_priv = dev->dev_private;
178 /* Disable compression */
179 dpfc_ctl = I915_READ(DPFC_CONTROL);
180 if (dpfc_ctl & DPFC_CTL_EN) {
181 dpfc_ctl &= ~DPFC_CTL_EN;
182 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
184 DRM_DEBUG_KMS("disabled FBC\n");
188 static bool g4x_fbc_enabled(struct drm_device *dev)
190 struct drm_i915_private *dev_priv = dev->dev_private;
192 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
195 static void sandybridge_blit_fbc_update(struct drm_device *dev)
197 struct drm_i915_private *dev_priv = dev->dev_private;
200 /* Make sure blitter notifies FBC of writes */
202 /* Blitter is part of Media powerwell on VLV. No impact of
203 * his param in other platforms for now */
204 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
206 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
207 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
208 GEN6_BLITTER_LOCK_SHIFT;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
211 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
212 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
213 GEN6_BLITTER_LOCK_SHIFT);
214 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
215 POSTING_READ(GEN6_BLITTER_ECOSKPD);
217 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
220 static void ironlake_enable_fbc(struct drm_crtc *crtc)
222 struct drm_device *dev = crtc->dev;
223 struct drm_i915_private *dev_priv = dev->dev_private;
224 struct drm_framebuffer *fb = crtc->primary->fb;
225 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
226 struct drm_i915_gem_object *obj = intel_fb->obj;
227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
230 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
231 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
232 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
234 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
237 dpfc_ctl |= obj->fence_reg;
239 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
240 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
245 I915_WRITE(SNB_DPFC_CTL_SA,
246 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
247 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
248 sandybridge_blit_fbc_update(dev);
251 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
254 static void ironlake_disable_fbc(struct drm_device *dev)
256 struct drm_i915_private *dev_priv = dev->dev_private;
259 /* Disable compression */
260 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
261 if (dpfc_ctl & DPFC_CTL_EN) {
262 dpfc_ctl &= ~DPFC_CTL_EN;
263 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
265 DRM_DEBUG_KMS("disabled FBC\n");
269 static bool ironlake_fbc_enabled(struct drm_device *dev)
271 struct drm_i915_private *dev_priv = dev->dev_private;
273 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
276 static void gen7_enable_fbc(struct drm_crtc *crtc)
278 struct drm_device *dev = crtc->dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
280 struct drm_framebuffer *fb = crtc->primary->fb;
281 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
282 struct drm_i915_gem_object *obj = intel_fb->obj;
283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
286 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
287 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
288 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
290 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
291 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
293 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
295 if (IS_IVYBRIDGE(dev)) {
296 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
297 I915_WRITE(ILK_DISPLAY_CHICKEN1,
298 I915_READ(ILK_DISPLAY_CHICKEN1) |
301 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
302 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
303 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
307 I915_WRITE(SNB_DPFC_CTL_SA,
308 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
309 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
311 sandybridge_blit_fbc_update(dev);
313 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
316 bool intel_fbc_enabled(struct drm_device *dev)
318 struct drm_i915_private *dev_priv = dev->dev_private;
320 if (!dev_priv->display.fbc_enabled)
323 return dev_priv->display.fbc_enabled(dev);
326 static void intel_fbc_work_fn(struct work_struct *__work)
328 struct intel_fbc_work *work =
329 container_of(to_delayed_work(__work),
330 struct intel_fbc_work, work);
331 struct drm_device *dev = work->crtc->dev;
332 struct drm_i915_private *dev_priv = dev->dev_private;
334 mutex_lock(&dev->struct_mutex);
335 if (work == dev_priv->fbc.fbc_work) {
336 /* Double check that we haven't switched fb without cancelling
339 if (work->crtc->primary->fb == work->fb) {
340 dev_priv->display.enable_fbc(work->crtc);
342 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
343 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
344 dev_priv->fbc.y = work->crtc->y;
347 dev_priv->fbc.fbc_work = NULL;
349 mutex_unlock(&dev->struct_mutex);
354 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
356 if (dev_priv->fbc.fbc_work == NULL)
359 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
361 /* Synchronisation is provided by struct_mutex and checking of
362 * dev_priv->fbc.fbc_work, so we can perform the cancellation
363 * entirely asynchronously.
365 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
366 /* tasklet was killed before being run, clean up */
367 kfree(dev_priv->fbc.fbc_work);
369 /* Mark the work as no longer wanted so that if it does
370 * wake-up (because the work was already running and waiting
371 * for our mutex), it will discover that is no longer
374 dev_priv->fbc.fbc_work = NULL;
377 static void intel_enable_fbc(struct drm_crtc *crtc)
379 struct intel_fbc_work *work;
380 struct drm_device *dev = crtc->dev;
381 struct drm_i915_private *dev_priv = dev->dev_private;
383 if (!dev_priv->display.enable_fbc)
386 intel_cancel_fbc_work(dev_priv);
388 work = kzalloc(sizeof(*work), GFP_KERNEL);
390 DRM_ERROR("Failed to allocate FBC work structure\n");
391 dev_priv->display.enable_fbc(crtc);
396 work->fb = crtc->primary->fb;
397 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
399 dev_priv->fbc.fbc_work = work;
401 /* Delay the actual enabling to let pageflipping cease and the
402 * display to settle before starting the compression. Note that
403 * this delay also serves a second purpose: it allows for a
404 * vblank to pass after disabling the FBC before we attempt
405 * to modify the control registers.
407 * A more complicated solution would involve tracking vblanks
408 * following the termination of the page-flipping sequence
409 * and indeed performing the enable as a co-routine and not
410 * waiting synchronously upon the vblank.
412 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
414 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
417 void intel_disable_fbc(struct drm_device *dev)
419 struct drm_i915_private *dev_priv = dev->dev_private;
421 intel_cancel_fbc_work(dev_priv);
423 if (!dev_priv->display.disable_fbc)
426 dev_priv->display.disable_fbc(dev);
427 dev_priv->fbc.plane = -1;
430 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
431 enum no_fbc_reason reason)
433 if (dev_priv->fbc.no_fbc_reason == reason)
436 dev_priv->fbc.no_fbc_reason = reason;
441 * intel_update_fbc - enable/disable FBC as needed
442 * @dev: the drm_device
444 * Set up the framebuffer compression hardware at mode set time. We
445 * enable it if possible:
446 * - plane A only (on pre-965)
447 * - no pixel mulitply/line duplication
448 * - no alpha buffer discard
450 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
452 * We can't assume that any compression will take place (worst case),
453 * so the compressed buffer has to be the same size as the uncompressed
454 * one. It also must reside (along with the line length buffer) in
457 * We need to enable/disable FBC on a global basis.
459 void intel_update_fbc(struct drm_device *dev)
461 struct drm_i915_private *dev_priv = dev->dev_private;
462 struct drm_crtc *crtc = NULL, *tmp_crtc;
463 struct intel_crtc *intel_crtc;
464 struct drm_framebuffer *fb;
465 struct intel_framebuffer *intel_fb;
466 struct drm_i915_gem_object *obj;
467 const struct drm_display_mode *adjusted_mode;
468 unsigned int max_width, max_height;
471 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
475 if (!i915.powersave) {
476 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
477 DRM_DEBUG_KMS("fbc disabled per module param\n");
482 * If FBC is already on, we just have to verify that we can
483 * keep it that way...
484 * Need to disable if:
485 * - more than one pipe is active
486 * - changing FBC params (stride, fence, mode)
487 * - new fb is too large to fit in compressed buffer
488 * - going to an unsupported config (interlace, pixel multiply, etc.)
490 for_each_crtc(dev, tmp_crtc) {
491 if (intel_crtc_active(tmp_crtc) &&
492 to_intel_crtc(tmp_crtc)->primary_enabled) {
494 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
495 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
502 if (!crtc || crtc->primary->fb == NULL) {
503 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
504 DRM_DEBUG_KMS("no output, disabling\n");
508 intel_crtc = to_intel_crtc(crtc);
509 fb = crtc->primary->fb;
510 intel_fb = to_intel_framebuffer(fb);
512 adjusted_mode = &intel_crtc->config.adjusted_mode;
514 if (i915.enable_fbc < 0 &&
515 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
516 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
517 DRM_DEBUG_KMS("disabled per chip default\n");
520 if (!i915.enable_fbc) {
521 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
522 DRM_DEBUG_KMS("fbc disabled per module param\n");
525 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
526 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
527 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
528 DRM_DEBUG_KMS("mode incompatible with compression, "
533 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
540 if (intel_crtc->config.pipe_src_w > max_width ||
541 intel_crtc->config.pipe_src_h > max_height) {
542 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
543 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
546 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
547 intel_crtc->plane != PLANE_A) {
548 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
549 DRM_DEBUG_KMS("plane not A, disabling compression\n");
553 /* The use of a CPU fence is mandatory in order to detect writes
554 * by the CPU to the scanout and trigger updates to the FBC.
556 if (obj->tiling_mode != I915_TILING_X ||
557 obj->fence_reg == I915_FENCE_REG_NONE) {
558 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
559 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
563 /* If the kernel debugger is active, always disable compression */
567 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
568 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
569 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
573 /* If the scanout has not changed, don't modify the FBC settings.
574 * Note that we make the fundamental assumption that the fb->obj
575 * cannot be unpinned (and have its GTT offset and fence revoked)
576 * without first being decoupled from the scanout and FBC disabled.
578 if (dev_priv->fbc.plane == intel_crtc->plane &&
579 dev_priv->fbc.fb_id == fb->base.id &&
580 dev_priv->fbc.y == crtc->y)
583 if (intel_fbc_enabled(dev)) {
584 /* We update FBC along two paths, after changing fb/crtc
585 * configuration (modeswitching) and after page-flipping
586 * finishes. For the latter, we know that not only did
587 * we disable the FBC at the start of the page-flip
588 * sequence, but also more than one vblank has passed.
590 * For the former case of modeswitching, it is possible
591 * to switch between two FBC valid configurations
592 * instantaneously so we do need to disable the FBC
593 * before we can modify its control registers. We also
594 * have to wait for the next vblank for that to take
595 * effect. However, since we delay enabling FBC we can
596 * assume that a vblank has passed since disabling and
597 * that we can safely alter the registers in the deferred
600 * In the scenario that we go from a valid to invalid
601 * and then back to valid FBC configuration we have
602 * no strict enforcement that a vblank occurred since
603 * disabling the FBC. However, along all current pipe
604 * disabling paths we do need to wait for a vblank at
605 * some point. And we wait before enabling FBC anyway.
607 DRM_DEBUG_KMS("disabling active FBC for update\n");
608 intel_disable_fbc(dev);
611 intel_enable_fbc(crtc);
612 dev_priv->fbc.no_fbc_reason = FBC_OK;
616 /* Multiple disables should be harmless */
617 if (intel_fbc_enabled(dev)) {
618 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
619 intel_disable_fbc(dev);
621 i915_gem_stolen_cleanup_compression(dev);
624 static void i915_pineview_get_mem_freq(struct drm_device *dev)
626 struct drm_i915_private *dev_priv = dev->dev_private;
629 tmp = I915_READ(CLKCFG);
631 switch (tmp & CLKCFG_FSB_MASK) {
633 dev_priv->fsb_freq = 533; /* 133*4 */
636 dev_priv->fsb_freq = 800; /* 200*4 */
639 dev_priv->fsb_freq = 667; /* 167*4 */
642 dev_priv->fsb_freq = 400; /* 100*4 */
646 switch (tmp & CLKCFG_MEM_MASK) {
648 dev_priv->mem_freq = 533;
651 dev_priv->mem_freq = 667;
654 dev_priv->mem_freq = 800;
658 /* detect pineview DDR3 setting */
659 tmp = I915_READ(CSHRDDR3CTL);
660 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
663 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
665 struct drm_i915_private *dev_priv = dev->dev_private;
668 ddrpll = I915_READ16(DDRMPLL1);
669 csipll = I915_READ16(CSIPLL0);
671 switch (ddrpll & 0xff) {
673 dev_priv->mem_freq = 800;
676 dev_priv->mem_freq = 1066;
679 dev_priv->mem_freq = 1333;
682 dev_priv->mem_freq = 1600;
685 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
687 dev_priv->mem_freq = 0;
691 dev_priv->ips.r_t = dev_priv->mem_freq;
693 switch (csipll & 0x3ff) {
695 dev_priv->fsb_freq = 3200;
698 dev_priv->fsb_freq = 3733;
701 dev_priv->fsb_freq = 4266;
704 dev_priv->fsb_freq = 4800;
707 dev_priv->fsb_freq = 5333;
710 dev_priv->fsb_freq = 5866;
713 dev_priv->fsb_freq = 6400;
716 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
718 dev_priv->fsb_freq = 0;
722 if (dev_priv->fsb_freq == 3200) {
723 dev_priv->ips.c_m = 0;
724 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
725 dev_priv->ips.c_m = 1;
727 dev_priv->ips.c_m = 2;
731 static const struct cxsr_latency cxsr_latency_table[] = {
732 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
733 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
734 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
735 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
736 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
738 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
739 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
740 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
741 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
742 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
744 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
745 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
746 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
747 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
748 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
750 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
751 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
752 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
753 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
754 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
756 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
757 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
758 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
759 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
760 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
762 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
763 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
764 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
765 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
766 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
769 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
774 const struct cxsr_latency *latency;
777 if (fsb == 0 || mem == 0)
780 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
781 latency = &cxsr_latency_table[i];
782 if (is_desktop == latency->is_desktop &&
783 is_ddr3 == latency->is_ddr3 &&
784 fsb == latency->fsb_freq && mem == latency->mem_freq)
788 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
793 static void pineview_disable_cxsr(struct drm_device *dev)
795 struct drm_i915_private *dev_priv = dev->dev_private;
797 /* deactivate cxsr */
798 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
802 * Latency for FIFO fetches is dependent on several factors:
803 * - memory configuration (speed, channels)
805 * - current MCH state
806 * It can be fairly high in some situations, so here we assume a fairly
807 * pessimal value. It's a tradeoff between extra memory fetches (if we
808 * set this value too high, the FIFO will fetch frequently to stay full)
809 * and power consumption (set it too low to save power and we might see
810 * FIFO underruns and display "flicker").
812 * A value of 5us seems to be a good balance; safe for very low end
813 * platforms but not overly aggressive on lower latency configs.
815 static const int latency_ns = 5000;
817 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
819 struct drm_i915_private *dev_priv = dev->dev_private;
820 uint32_t dsparb = I915_READ(DSPARB);
823 size = dsparb & 0x7f;
825 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
827 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
828 plane ? "B" : "A", size);
833 static int i830_get_fifo_size(struct drm_device *dev, int plane)
835 struct drm_i915_private *dev_priv = dev->dev_private;
836 uint32_t dsparb = I915_READ(DSPARB);
839 size = dsparb & 0x1ff;
841 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
842 size >>= 1; /* Convert to cachelines */
844 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
845 plane ? "B" : "A", size);
850 static int i845_get_fifo_size(struct drm_device *dev, int plane)
852 struct drm_i915_private *dev_priv = dev->dev_private;
853 uint32_t dsparb = I915_READ(DSPARB);
856 size = dsparb & 0x7f;
857 size >>= 2; /* Convert to cachelines */
859 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
866 /* Pineview has different values for various configs */
867 static const struct intel_watermark_params pineview_display_wm = {
868 PINEVIEW_DISPLAY_FIFO,
872 PINEVIEW_FIFO_LINE_SIZE
874 static const struct intel_watermark_params pineview_display_hplloff_wm = {
875 PINEVIEW_DISPLAY_FIFO,
877 PINEVIEW_DFT_HPLLOFF_WM,
879 PINEVIEW_FIFO_LINE_SIZE
881 static const struct intel_watermark_params pineview_cursor_wm = {
882 PINEVIEW_CURSOR_FIFO,
883 PINEVIEW_CURSOR_MAX_WM,
884 PINEVIEW_CURSOR_DFT_WM,
885 PINEVIEW_CURSOR_GUARD_WM,
886 PINEVIEW_FIFO_LINE_SIZE,
888 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
889 PINEVIEW_CURSOR_FIFO,
890 PINEVIEW_CURSOR_MAX_WM,
891 PINEVIEW_CURSOR_DFT_WM,
892 PINEVIEW_CURSOR_GUARD_WM,
893 PINEVIEW_FIFO_LINE_SIZE
895 static const struct intel_watermark_params g4x_wm_info = {
902 static const struct intel_watermark_params g4x_cursor_wm_info = {
909 static const struct intel_watermark_params valleyview_wm_info = {
910 VALLEYVIEW_FIFO_SIZE,
916 static const struct intel_watermark_params valleyview_cursor_wm_info = {
918 VALLEYVIEW_CURSOR_MAX_WM,
923 static const struct intel_watermark_params i965_cursor_wm_info = {
930 static const struct intel_watermark_params i945_wm_info = {
937 static const struct intel_watermark_params i915_wm_info = {
944 static const struct intel_watermark_params i830_wm_info = {
951 static const struct intel_watermark_params i845_wm_info = {
960 * intel_calculate_wm - calculate watermark level
961 * @clock_in_khz: pixel clock
962 * @wm: chip FIFO params
963 * @pixel_size: display pixel size
964 * @latency_ns: memory latency for the platform
966 * Calculate the watermark level (the level at which the display plane will
967 * start fetching from memory again). Each chip has a different display
968 * FIFO size and allocation, so the caller needs to figure that out and pass
969 * in the correct intel_watermark_params structure.
971 * As the pixel clock runs, the FIFO will be drained at a rate that depends
972 * on the pixel size. When it reaches the watermark level, it'll start
973 * fetching FIFO line sized based chunks from memory until the FIFO fills
974 * past the watermark point. If the FIFO drains completely, a FIFO underrun
975 * will occur, and a display engine hang could result.
977 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
978 const struct intel_watermark_params *wm,
981 unsigned long latency_ns)
983 long entries_required, wm_size;
986 * Note: we need to make sure we don't overflow for various clock &
988 * clocks go from a few thousand to several hundred thousand.
989 * latency is usually a few thousand
991 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
993 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
995 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
997 wm_size = fifo_size - (entries_required + wm->guard_size);
999 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1001 /* Don't promote wm_size to unsigned... */
1002 if (wm_size > (long)wm->max_wm)
1003 wm_size = wm->max_wm;
1005 wm_size = wm->default_wm;
1009 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1011 struct drm_crtc *crtc, *enabled = NULL;
1013 for_each_crtc(dev, crtc) {
1014 if (intel_crtc_active(crtc)) {
1024 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1026 struct drm_device *dev = unused_crtc->dev;
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 struct drm_crtc *crtc;
1029 const struct cxsr_latency *latency;
1033 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1034 dev_priv->fsb_freq, dev_priv->mem_freq);
1036 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1037 pineview_disable_cxsr(dev);
1041 crtc = single_enabled_crtc(dev);
1043 const struct drm_display_mode *adjusted_mode;
1044 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1047 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1048 clock = adjusted_mode->crtc_clock;
1051 wm = intel_calculate_wm(clock, &pineview_display_wm,
1052 pineview_display_wm.fifo_size,
1053 pixel_size, latency->display_sr);
1054 reg = I915_READ(DSPFW1);
1055 reg &= ~DSPFW_SR_MASK;
1056 reg |= wm << DSPFW_SR_SHIFT;
1057 I915_WRITE(DSPFW1, reg);
1058 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1061 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1062 pineview_display_wm.fifo_size,
1063 pixel_size, latency->cursor_sr);
1064 reg = I915_READ(DSPFW3);
1065 reg &= ~DSPFW_CURSOR_SR_MASK;
1066 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1067 I915_WRITE(DSPFW3, reg);
1069 /* Display HPLL off SR */
1070 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1071 pineview_display_hplloff_wm.fifo_size,
1072 pixel_size, latency->display_hpll_disable);
1073 reg = I915_READ(DSPFW3);
1074 reg &= ~DSPFW_HPLL_SR_MASK;
1075 reg |= wm & DSPFW_HPLL_SR_MASK;
1076 I915_WRITE(DSPFW3, reg);
1078 /* cursor HPLL off SR */
1079 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1080 pineview_display_hplloff_wm.fifo_size,
1081 pixel_size, latency->cursor_hpll_disable);
1082 reg = I915_READ(DSPFW3);
1083 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1084 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1085 I915_WRITE(DSPFW3, reg);
1086 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1090 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1091 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1093 pineview_disable_cxsr(dev);
1094 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1098 static bool g4x_compute_wm0(struct drm_device *dev,
1100 const struct intel_watermark_params *display,
1101 int display_latency_ns,
1102 const struct intel_watermark_params *cursor,
1103 int cursor_latency_ns,
1107 struct drm_crtc *crtc;
1108 const struct drm_display_mode *adjusted_mode;
1109 int htotal, hdisplay, clock, pixel_size;
1110 int line_time_us, line_count;
1111 int entries, tlb_miss;
1113 crtc = intel_get_crtc_for_plane(dev, plane);
1114 if (!intel_crtc_active(crtc)) {
1115 *cursor_wm = cursor->guard_size;
1116 *plane_wm = display->guard_size;
1120 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1121 clock = adjusted_mode->crtc_clock;
1122 htotal = adjusted_mode->crtc_htotal;
1123 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1124 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1126 /* Use the small buffer method to calculate plane watermark */
1127 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1128 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1130 entries += tlb_miss;
1131 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1132 *plane_wm = entries + display->guard_size;
1133 if (*plane_wm > (int)display->max_wm)
1134 *plane_wm = display->max_wm;
1136 /* Use the large buffer method to calculate cursor watermark */
1137 line_time_us = max(htotal * 1000 / clock, 1);
1138 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1139 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1140 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1142 entries += tlb_miss;
1143 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1144 *cursor_wm = entries + cursor->guard_size;
1145 if (*cursor_wm > (int)cursor->max_wm)
1146 *cursor_wm = (int)cursor->max_wm;
1152 * Check the wm result.
1154 * If any calculated watermark values is larger than the maximum value that
1155 * can be programmed into the associated watermark register, that watermark
1158 static bool g4x_check_srwm(struct drm_device *dev,
1159 int display_wm, int cursor_wm,
1160 const struct intel_watermark_params *display,
1161 const struct intel_watermark_params *cursor)
1163 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1164 display_wm, cursor_wm);
1166 if (display_wm > display->max_wm) {
1167 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1168 display_wm, display->max_wm);
1172 if (cursor_wm > cursor->max_wm) {
1173 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1174 cursor_wm, cursor->max_wm);
1178 if (!(display_wm || cursor_wm)) {
1179 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1186 static bool g4x_compute_srwm(struct drm_device *dev,
1189 const struct intel_watermark_params *display,
1190 const struct intel_watermark_params *cursor,
1191 int *display_wm, int *cursor_wm)
1193 struct drm_crtc *crtc;
1194 const struct drm_display_mode *adjusted_mode;
1195 int hdisplay, htotal, pixel_size, clock;
1196 unsigned long line_time_us;
1197 int line_count, line_size;
1202 *display_wm = *cursor_wm = 0;
1206 crtc = intel_get_crtc_for_plane(dev, plane);
1207 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1208 clock = adjusted_mode->crtc_clock;
1209 htotal = adjusted_mode->crtc_htotal;
1210 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1211 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1213 line_time_us = max(htotal * 1000 / clock, 1);
1214 line_count = (latency_ns / line_time_us + 1000) / 1000;
1215 line_size = hdisplay * pixel_size;
1217 /* Use the minimum of the small and large buffer method for primary */
1218 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1219 large = line_count * line_size;
1221 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1222 *display_wm = entries + display->guard_size;
1224 /* calculate the self-refresh watermark for display cursor */
1225 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1226 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1227 *cursor_wm = entries + cursor->guard_size;
1229 return g4x_check_srwm(dev,
1230 *display_wm, *cursor_wm,
1234 static bool vlv_compute_drain_latency(struct drm_device *dev,
1236 int *plane_prec_mult,
1238 int *cursor_prec_mult,
1241 struct drm_crtc *crtc;
1242 int clock, pixel_size;
1245 crtc = intel_get_crtc_for_plane(dev, plane);
1246 if (!intel_crtc_active(crtc))
1249 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1250 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1252 entries = (clock / 1000) * pixel_size;
1253 *plane_prec_mult = (entries > 256) ?
1254 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1255 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1258 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1259 *cursor_prec_mult = (entries > 256) ?
1260 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1261 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1267 * Update drain latency registers of memory arbiter
1269 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1270 * to be programmed. Each plane has a drain latency multiplier and a drain
1274 static void vlv_update_drain_latency(struct drm_device *dev)
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1277 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1278 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1279 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1282 /* For plane A, Cursor A */
1283 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1284 &cursor_prec_mult, &cursora_dl)) {
1285 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1286 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1287 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1288 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1290 I915_WRITE(VLV_DDL1, cursora_prec |
1291 (cursora_dl << DDL_CURSORA_SHIFT) |
1292 planea_prec | planea_dl);
1295 /* For plane B, Cursor B */
1296 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1297 &cursor_prec_mult, &cursorb_dl)) {
1298 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1299 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1300 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1301 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1303 I915_WRITE(VLV_DDL2, cursorb_prec |
1304 (cursorb_dl << DDL_CURSORB_SHIFT) |
1305 planeb_prec | planeb_dl);
1309 #define single_plane_enabled(mask) is_power_of_2(mask)
1311 static void valleyview_update_wm(struct drm_crtc *crtc)
1313 struct drm_device *dev = crtc->dev;
1314 static const int sr_latency_ns = 12000;
1315 struct drm_i915_private *dev_priv = dev->dev_private;
1316 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1317 int plane_sr, cursor_sr;
1318 int ignore_plane_sr, ignore_cursor_sr;
1319 unsigned int enabled = 0;
1321 vlv_update_drain_latency(dev);
1323 if (g4x_compute_wm0(dev, PIPE_A,
1324 &valleyview_wm_info, latency_ns,
1325 &valleyview_cursor_wm_info, latency_ns,
1326 &planea_wm, &cursora_wm))
1327 enabled |= 1 << PIPE_A;
1329 if (g4x_compute_wm0(dev, PIPE_B,
1330 &valleyview_wm_info, latency_ns,
1331 &valleyview_cursor_wm_info, latency_ns,
1332 &planeb_wm, &cursorb_wm))
1333 enabled |= 1 << PIPE_B;
1335 if (single_plane_enabled(enabled) &&
1336 g4x_compute_srwm(dev, ffs(enabled) - 1,
1338 &valleyview_wm_info,
1339 &valleyview_cursor_wm_info,
1340 &plane_sr, &ignore_cursor_sr) &&
1341 g4x_compute_srwm(dev, ffs(enabled) - 1,
1343 &valleyview_wm_info,
1344 &valleyview_cursor_wm_info,
1345 &ignore_plane_sr, &cursor_sr)) {
1346 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1348 I915_WRITE(FW_BLC_SELF_VLV,
1349 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1350 plane_sr = cursor_sr = 0;
1353 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1354 planea_wm, cursora_wm,
1355 planeb_wm, cursorb_wm,
1356 plane_sr, cursor_sr);
1359 (plane_sr << DSPFW_SR_SHIFT) |
1360 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1361 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1364 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1365 (cursora_wm << DSPFW_CURSORA_SHIFT));
1367 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1368 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1371 static void g4x_update_wm(struct drm_crtc *crtc)
1373 struct drm_device *dev = crtc->dev;
1374 static const int sr_latency_ns = 12000;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377 int plane_sr, cursor_sr;
1378 unsigned int enabled = 0;
1380 if (g4x_compute_wm0(dev, PIPE_A,
1381 &g4x_wm_info, latency_ns,
1382 &g4x_cursor_wm_info, latency_ns,
1383 &planea_wm, &cursora_wm))
1384 enabled |= 1 << PIPE_A;
1386 if (g4x_compute_wm0(dev, PIPE_B,
1387 &g4x_wm_info, latency_ns,
1388 &g4x_cursor_wm_info, latency_ns,
1389 &planeb_wm, &cursorb_wm))
1390 enabled |= 1 << PIPE_B;
1392 if (single_plane_enabled(enabled) &&
1393 g4x_compute_srwm(dev, ffs(enabled) - 1,
1396 &g4x_cursor_wm_info,
1397 &plane_sr, &cursor_sr)) {
1398 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1400 I915_WRITE(FW_BLC_SELF,
1401 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1402 plane_sr = cursor_sr = 0;
1405 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1406 planea_wm, cursora_wm,
1407 planeb_wm, cursorb_wm,
1408 plane_sr, cursor_sr);
1411 (plane_sr << DSPFW_SR_SHIFT) |
1412 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1413 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1416 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1417 (cursora_wm << DSPFW_CURSORA_SHIFT));
1418 /* HPLL off in SR has some issues on G4x... disable it */
1420 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1421 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1424 static void i965_update_wm(struct drm_crtc *unused_crtc)
1426 struct drm_device *dev = unused_crtc->dev;
1427 struct drm_i915_private *dev_priv = dev->dev_private;
1428 struct drm_crtc *crtc;
1432 /* Calc sr entries for one plane configs */
1433 crtc = single_enabled_crtc(dev);
1435 /* self-refresh has much higher latency */
1436 static const int sr_latency_ns = 12000;
1437 const struct drm_display_mode *adjusted_mode =
1438 &to_intel_crtc(crtc)->config.adjusted_mode;
1439 int clock = adjusted_mode->crtc_clock;
1440 int htotal = adjusted_mode->crtc_htotal;
1441 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1442 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1443 unsigned long line_time_us;
1446 line_time_us = max(htotal * 1000 / clock, 1);
1448 /* Use ns/us then divide to preserve precision */
1449 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450 pixel_size * hdisplay;
1451 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1452 srwm = I965_FIFO_SIZE - entries;
1456 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1459 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1460 pixel_size * to_intel_crtc(crtc)->cursor_width;
1461 entries = DIV_ROUND_UP(entries,
1462 i965_cursor_wm_info.cacheline_size);
1463 cursor_sr = i965_cursor_wm_info.fifo_size -
1464 (entries + i965_cursor_wm_info.guard_size);
1466 if (cursor_sr > i965_cursor_wm_info.max_wm)
1467 cursor_sr = i965_cursor_wm_info.max_wm;
1469 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470 "cursor %d\n", srwm, cursor_sr);
1472 if (IS_CRESTLINE(dev))
1473 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1475 /* Turn off self refresh if both pipes are enabled */
1476 if (IS_CRESTLINE(dev))
1477 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1481 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1484 /* 965 has limitations... */
1485 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1486 (8 << 16) | (8 << 8) | (8 << 0));
1487 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1488 /* update cursor SR watermark */
1489 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1492 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1494 struct drm_device *dev = unused_crtc->dev;
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 const struct intel_watermark_params *wm_info;
1501 int planea_wm, planeb_wm;
1502 struct drm_crtc *crtc, *enabled = NULL;
1505 wm_info = &i945_wm_info;
1506 else if (!IS_GEN2(dev))
1507 wm_info = &i915_wm_info;
1509 wm_info = &i830_wm_info;
1511 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1512 crtc = intel_get_crtc_for_plane(dev, 0);
1513 if (intel_crtc_active(crtc)) {
1514 const struct drm_display_mode *adjusted_mode;
1515 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1519 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1520 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1521 wm_info, fifo_size, cpp,
1525 planea_wm = fifo_size - wm_info->guard_size;
1527 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1528 crtc = intel_get_crtc_for_plane(dev, 1);
1529 if (intel_crtc_active(crtc)) {
1530 const struct drm_display_mode *adjusted_mode;
1531 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1535 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1536 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1537 wm_info, fifo_size, cpp,
1539 if (enabled == NULL)
1544 planeb_wm = fifo_size - wm_info->guard_size;
1546 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1548 if (IS_I915GM(dev) && enabled) {
1549 struct intel_framebuffer *fb;
1551 fb = to_intel_framebuffer(enabled->primary->fb);
1553 /* self-refresh seems busted with untiled */
1554 if (fb->obj->tiling_mode == I915_TILING_NONE)
1559 * Overlay gets an aggressive default since video jitter is bad.
1563 /* Play safe and disable self-refresh before adjusting watermarks. */
1564 if (IS_I945G(dev) || IS_I945GM(dev))
1565 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1566 else if (IS_I915GM(dev))
1567 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
1569 /* Calc sr entries for one plane configs */
1570 if (HAS_FW_BLC(dev) && enabled) {
1571 /* self-refresh has much higher latency */
1572 static const int sr_latency_ns = 6000;
1573 const struct drm_display_mode *adjusted_mode =
1574 &to_intel_crtc(enabled)->config.adjusted_mode;
1575 int clock = adjusted_mode->crtc_clock;
1576 int htotal = adjusted_mode->crtc_htotal;
1577 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1578 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1579 unsigned long line_time_us;
1582 line_time_us = max(htotal * 1000 / clock, 1);
1584 /* Use ns/us then divide to preserve precision */
1585 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1586 pixel_size * hdisplay;
1587 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1588 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1589 srwm = wm_info->fifo_size - entries;
1593 if (IS_I945G(dev) || IS_I945GM(dev))
1594 I915_WRITE(FW_BLC_SELF,
1595 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1596 else if (IS_I915GM(dev))
1597 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1600 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1601 planea_wm, planeb_wm, cwm, srwm);
1603 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1604 fwater_hi = (cwm & 0x1f);
1606 /* Set request length to 8 cachelines per fetch */
1607 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1608 fwater_hi = fwater_hi | (1 << 8);
1610 I915_WRITE(FW_BLC, fwater_lo);
1611 I915_WRITE(FW_BLC2, fwater_hi);
1613 if (HAS_FW_BLC(dev)) {
1615 if (IS_I945G(dev) || IS_I945GM(dev))
1616 I915_WRITE(FW_BLC_SELF,
1617 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1618 else if (IS_I915GM(dev))
1619 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
1620 DRM_DEBUG_KMS("memory self refresh enabled\n");
1622 DRM_DEBUG_KMS("memory self refresh disabled\n");
1626 static void i845_update_wm(struct drm_crtc *unused_crtc)
1628 struct drm_device *dev = unused_crtc->dev;
1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 struct drm_crtc *crtc;
1631 const struct drm_display_mode *adjusted_mode;
1635 crtc = single_enabled_crtc(dev);
1639 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1640 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1642 dev_priv->display.get_fifo_size(dev, 0),
1644 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1645 fwater_lo |= (3<<8) | planea_wm;
1647 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1649 I915_WRITE(FW_BLC, fwater_lo);
1652 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1653 struct drm_crtc *crtc)
1655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1656 uint32_t pixel_rate;
1658 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1660 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1661 * adjust the pixel_rate here. */
1663 if (intel_crtc->config.pch_pfit.enabled) {
1664 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1665 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1667 pipe_w = intel_crtc->config.pipe_src_w;
1668 pipe_h = intel_crtc->config.pipe_src_h;
1669 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670 pfit_h = pfit_size & 0xFFFF;
1671 if (pipe_w < pfit_w)
1673 if (pipe_h < pfit_h)
1676 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1683 /* latency must be in 0.1us units. */
1684 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1689 if (WARN(latency == 0, "Latency value missing\n"))
1692 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1693 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1698 /* latency must be in 0.1us units. */
1699 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1700 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1705 if (WARN(latency == 0, "Latency value missing\n"))
1708 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1709 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1710 ret = DIV_ROUND_UP(ret, 64) + 2;
1714 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1715 uint8_t bytes_per_pixel)
1717 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1720 struct ilk_pipe_wm_parameters {
1722 uint32_t pipe_htotal;
1723 uint32_t pixel_rate;
1724 struct intel_plane_wm_parameters pri;
1725 struct intel_plane_wm_parameters spr;
1726 struct intel_plane_wm_parameters cur;
1729 struct ilk_wm_maximums {
1736 /* used in computing the new watermarks state */
1737 struct intel_wm_config {
1738 unsigned int num_pipes_active;
1739 bool sprites_enabled;
1740 bool sprites_scaled;
1744 * For both WM_PIPE and WM_LP.
1745 * mem_value must be in 0.1us units.
1747 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1751 uint32_t method1, method2;
1753 if (!params->active || !params->pri.enabled)
1756 method1 = ilk_wm_method1(params->pixel_rate,
1757 params->pri.bytes_per_pixel,
1763 method2 = ilk_wm_method2(params->pixel_rate,
1764 params->pipe_htotal,
1765 params->pri.horiz_pixels,
1766 params->pri.bytes_per_pixel,
1769 return min(method1, method2);
1773 * For both WM_PIPE and WM_LP.
1774 * mem_value must be in 0.1us units.
1776 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1779 uint32_t method1, method2;
1781 if (!params->active || !params->spr.enabled)
1784 method1 = ilk_wm_method1(params->pixel_rate,
1785 params->spr.bytes_per_pixel,
1787 method2 = ilk_wm_method2(params->pixel_rate,
1788 params->pipe_htotal,
1789 params->spr.horiz_pixels,
1790 params->spr.bytes_per_pixel,
1792 return min(method1, method2);
1796 * For both WM_PIPE and WM_LP.
1797 * mem_value must be in 0.1us units.
1799 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1802 if (!params->active || !params->cur.enabled)
1805 return ilk_wm_method2(params->pixel_rate,
1806 params->pipe_htotal,
1807 params->cur.horiz_pixels,
1808 params->cur.bytes_per_pixel,
1812 /* Only for WM_LP. */
1813 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1816 if (!params->active || !params->pri.enabled)
1819 return ilk_wm_fbc(pri_val,
1820 params->pri.horiz_pixels,
1821 params->pri.bytes_per_pixel);
1824 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1826 if (INTEL_INFO(dev)->gen >= 8)
1828 else if (INTEL_INFO(dev)->gen >= 7)
1834 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1835 int level, bool is_sprite)
1837 if (INTEL_INFO(dev)->gen >= 8)
1838 /* BDW primary/sprite plane watermarks */
1839 return level == 0 ? 255 : 2047;
1840 else if (INTEL_INFO(dev)->gen >= 7)
1841 /* IVB/HSW primary/sprite plane watermarks */
1842 return level == 0 ? 127 : 1023;
1843 else if (!is_sprite)
1844 /* ILK/SNB primary plane watermarks */
1845 return level == 0 ? 127 : 511;
1847 /* ILK/SNB sprite plane watermarks */
1848 return level == 0 ? 63 : 255;
1851 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1854 if (INTEL_INFO(dev)->gen >= 7)
1855 return level == 0 ? 63 : 255;
1857 return level == 0 ? 31 : 63;
1860 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1862 if (INTEL_INFO(dev)->gen >= 8)
1868 /* Calculate the maximum primary/sprite plane watermark */
1869 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1871 const struct intel_wm_config *config,
1872 enum intel_ddb_partitioning ddb_partitioning,
1875 unsigned int fifo_size = ilk_display_fifo_size(dev);
1877 /* if sprites aren't enabled, sprites get nothing */
1878 if (is_sprite && !config->sprites_enabled)
1881 /* HSW allows LP1+ watermarks even with multiple pipes */
1882 if (level == 0 || config->num_pipes_active > 1) {
1883 fifo_size /= INTEL_INFO(dev)->num_pipes;
1886 * For some reason the non self refresh
1887 * FIFO size is only half of the self
1888 * refresh FIFO size on ILK/SNB.
1890 if (INTEL_INFO(dev)->gen <= 6)
1894 if (config->sprites_enabled) {
1895 /* level 0 is always calculated with 1:1 split */
1896 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1905 /* clamp to max that the registers can hold */
1906 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1909 /* Calculate the maximum cursor plane watermark */
1910 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1912 const struct intel_wm_config *config)
1914 /* HSW LP1+ watermarks w/ multiple pipes */
1915 if (level > 0 && config->num_pipes_active > 1)
1918 /* otherwise just report max that registers can hold */
1919 return ilk_cursor_wm_reg_max(dev, level);
1922 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1924 const struct intel_wm_config *config,
1925 enum intel_ddb_partitioning ddb_partitioning,
1926 struct ilk_wm_maximums *max)
1928 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1929 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1930 max->cur = ilk_cursor_wm_max(dev, level, config);
1931 max->fbc = ilk_fbc_wm_reg_max(dev);
1934 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1936 struct ilk_wm_maximums *max)
1938 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1939 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1940 max->cur = ilk_cursor_wm_reg_max(dev, level);
1941 max->fbc = ilk_fbc_wm_reg_max(dev);
1944 static bool ilk_validate_wm_level(int level,
1945 const struct ilk_wm_maximums *max,
1946 struct intel_wm_level *result)
1950 /* already determined to be invalid? */
1951 if (!result->enable)
1954 result->enable = result->pri_val <= max->pri &&
1955 result->spr_val <= max->spr &&
1956 result->cur_val <= max->cur;
1958 ret = result->enable;
1961 * HACK until we can pre-compute everything,
1962 * and thus fail gracefully if LP0 watermarks
1965 if (level == 0 && !result->enable) {
1966 if (result->pri_val > max->pri)
1967 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1968 level, result->pri_val, max->pri);
1969 if (result->spr_val > max->spr)
1970 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1971 level, result->spr_val, max->spr);
1972 if (result->cur_val > max->cur)
1973 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1974 level, result->cur_val, max->cur);
1976 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1977 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1978 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1979 result->enable = true;
1985 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1987 const struct ilk_pipe_wm_parameters *p,
1988 struct intel_wm_level *result)
1990 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1991 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1992 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1994 /* WM1+ latency values stored in 0.5us units */
2001 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2002 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2003 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2004 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2005 result->enable = true;
2009 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2011 struct drm_i915_private *dev_priv = dev->dev_private;
2012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2013 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2014 u32 linetime, ips_linetime;
2016 if (!intel_crtc_active(crtc))
2019 /* The WM are computed with base on how long it takes to fill a single
2020 * row at the given clock rate, multiplied by 8.
2022 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2024 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2025 intel_ddi_get_cdclk_freq(dev_priv));
2027 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2028 PIPE_WM_LINETIME_TIME(linetime);
2031 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2033 struct drm_i915_private *dev_priv = dev->dev_private;
2035 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2036 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2038 wm[0] = (sskpd >> 56) & 0xFF;
2040 wm[0] = sskpd & 0xF;
2041 wm[1] = (sskpd >> 4) & 0xFF;
2042 wm[2] = (sskpd >> 12) & 0xFF;
2043 wm[3] = (sskpd >> 20) & 0x1FF;
2044 wm[4] = (sskpd >> 32) & 0x1FF;
2045 } else if (INTEL_INFO(dev)->gen >= 6) {
2046 uint32_t sskpd = I915_READ(MCH_SSKPD);
2048 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2049 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2050 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2051 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2052 } else if (INTEL_INFO(dev)->gen >= 5) {
2053 uint32_t mltr = I915_READ(MLTR_ILK);
2055 /* ILK primary LP0 latency is 700 ns */
2057 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2058 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2062 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2064 /* ILK sprite LP0 latency is 1300 ns */
2065 if (INTEL_INFO(dev)->gen == 5)
2069 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2071 /* ILK cursor LP0 latency is 1300 ns */
2072 if (INTEL_INFO(dev)->gen == 5)
2075 /* WaDoubleCursorLP3Latency:ivb */
2076 if (IS_IVYBRIDGE(dev))
2080 int ilk_wm_max_level(const struct drm_device *dev)
2082 /* how many WM levels are we expecting */
2083 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2085 else if (INTEL_INFO(dev)->gen >= 6)
2091 static void intel_print_wm_latency(struct drm_device *dev,
2093 const uint16_t wm[5])
2095 int level, max_level = ilk_wm_max_level(dev);
2097 for (level = 0; level <= max_level; level++) {
2098 unsigned int latency = wm[level];
2101 DRM_ERROR("%s WM%d latency not provided\n",
2106 /* WM1+ latency values in 0.5us units */
2110 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2111 name, level, wm[level],
2112 latency / 10, latency % 10);
2116 static void ilk_setup_wm_latency(struct drm_device *dev)
2118 struct drm_i915_private *dev_priv = dev->dev_private;
2120 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2122 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2123 sizeof(dev_priv->wm.pri_latency));
2124 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2125 sizeof(dev_priv->wm.pri_latency));
2127 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2128 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2130 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2131 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2132 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2135 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2136 struct ilk_pipe_wm_parameters *p)
2138 struct drm_device *dev = crtc->dev;
2139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2140 enum pipe pipe = intel_crtc->pipe;
2141 struct drm_plane *plane;
2143 if (!intel_crtc_active(crtc))
2147 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2148 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2149 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2150 p->cur.bytes_per_pixel = 4;
2151 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2152 p->cur.horiz_pixels = intel_crtc->cursor_width;
2153 /* TODO: for now, assume primary and cursor planes are always enabled. */
2154 p->pri.enabled = true;
2155 p->cur.enabled = true;
2157 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2158 struct intel_plane *intel_plane = to_intel_plane(plane);
2160 if (intel_plane->pipe == pipe) {
2161 p->spr = intel_plane->wm;
2167 static void ilk_compute_wm_config(struct drm_device *dev,
2168 struct intel_wm_config *config)
2170 struct intel_crtc *intel_crtc;
2172 /* Compute the currently _active_ config */
2173 for_each_intel_crtc(dev, intel_crtc) {
2174 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2176 if (!wm->pipe_enabled)
2179 config->sprites_enabled |= wm->sprites_enabled;
2180 config->sprites_scaled |= wm->sprites_scaled;
2181 config->num_pipes_active++;
2185 /* Compute new watermarks for the pipe */
2186 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2187 const struct ilk_pipe_wm_parameters *params,
2188 struct intel_pipe_wm *pipe_wm)
2190 struct drm_device *dev = crtc->dev;
2191 const struct drm_i915_private *dev_priv = dev->dev_private;
2192 int level, max_level = ilk_wm_max_level(dev);
2193 /* LP0 watermark maximums depend on this pipe alone */
2194 struct intel_wm_config config = {
2195 .num_pipes_active = 1,
2196 .sprites_enabled = params->spr.enabled,
2197 .sprites_scaled = params->spr.scaled,
2199 struct ilk_wm_maximums max;
2201 pipe_wm->pipe_enabled = params->active;
2202 pipe_wm->sprites_enabled = params->spr.enabled;
2203 pipe_wm->sprites_scaled = params->spr.scaled;
2205 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2206 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2209 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2210 if (params->spr.scaled)
2213 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2215 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2216 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2218 /* LP0 watermarks always use 1/2 DDB partitioning */
2219 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2221 /* At least LP0 must be valid */
2222 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2225 ilk_compute_wm_reg_maximums(dev, 1, &max);
2227 for (level = 1; level <= max_level; level++) {
2228 struct intel_wm_level wm = {};
2230 ilk_compute_wm_level(dev_priv, level, params, &wm);
2233 * Disable any watermark level that exceeds the
2234 * register maximums since such watermarks are
2237 if (!ilk_validate_wm_level(level, &max, &wm))
2240 pipe_wm->wm[level] = wm;
2247 * Merge the watermarks from all active pipes for a specific level.
2249 static void ilk_merge_wm_level(struct drm_device *dev,
2251 struct intel_wm_level *ret_wm)
2253 const struct intel_crtc *intel_crtc;
2255 ret_wm->enable = true;
2257 for_each_intel_crtc(dev, intel_crtc) {
2258 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2259 const struct intel_wm_level *wm = &active->wm[level];
2261 if (!active->pipe_enabled)
2265 * The watermark values may have been used in the past,
2266 * so we must maintain them in the registers for some
2267 * time even if the level is now disabled.
2270 ret_wm->enable = false;
2272 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2273 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2274 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2275 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2280 * Merge all low power watermarks for all active pipes.
2282 static void ilk_wm_merge(struct drm_device *dev,
2283 const struct intel_wm_config *config,
2284 const struct ilk_wm_maximums *max,
2285 struct intel_pipe_wm *merged)
2287 int level, max_level = ilk_wm_max_level(dev);
2288 int last_enabled_level = max_level;
2290 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2291 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2292 config->num_pipes_active > 1)
2295 /* ILK: FBC WM must be disabled always */
2296 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2298 /* merge each WM1+ level */
2299 for (level = 1; level <= max_level; level++) {
2300 struct intel_wm_level *wm = &merged->wm[level];
2302 ilk_merge_wm_level(dev, level, wm);
2304 if (level > last_enabled_level)
2306 else if (!ilk_validate_wm_level(level, max, wm))
2307 /* make sure all following levels get disabled */
2308 last_enabled_level = level - 1;
2311 * The spec says it is preferred to disable
2312 * FBC WMs instead of disabling a WM level.
2314 if (wm->fbc_val > max->fbc) {
2316 merged->fbc_wm_enabled = false;
2321 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2323 * FIXME this is racy. FBC might get enabled later.
2324 * What we should check here is whether FBC can be
2325 * enabled sometime later.
2327 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2328 for (level = 2; level <= max_level; level++) {
2329 struct intel_wm_level *wm = &merged->wm[level];
2336 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2338 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2339 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2342 /* The value we need to program into the WM_LPx latency field */
2343 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2345 struct drm_i915_private *dev_priv = dev->dev_private;
2347 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2350 return dev_priv->wm.pri_latency[level];
2353 static void ilk_compute_wm_results(struct drm_device *dev,
2354 const struct intel_pipe_wm *merged,
2355 enum intel_ddb_partitioning partitioning,
2356 struct ilk_wm_values *results)
2358 struct intel_crtc *intel_crtc;
2361 results->enable_fbc_wm = merged->fbc_wm_enabled;
2362 results->partitioning = partitioning;
2364 /* LP1+ register values */
2365 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2366 const struct intel_wm_level *r;
2368 level = ilk_wm_lp_to_level(wm_lp, merged);
2370 r = &merged->wm[level];
2373 * Maintain the watermark values even if the level is
2374 * disabled. Doing otherwise could cause underruns.
2376 results->wm_lp[wm_lp - 1] =
2377 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2378 (r->pri_val << WM1_LP_SR_SHIFT) |
2382 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2384 if (INTEL_INFO(dev)->gen >= 8)
2385 results->wm_lp[wm_lp - 1] |=
2386 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2388 results->wm_lp[wm_lp - 1] |=
2389 r->fbc_val << WM1_LP_FBC_SHIFT;
2392 * Always set WM1S_LP_EN when spr_val != 0, even if the
2393 * level is disabled. Doing otherwise could cause underruns.
2395 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2396 WARN_ON(wm_lp != 1);
2397 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2399 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2402 /* LP0 register values */
2403 for_each_intel_crtc(dev, intel_crtc) {
2404 enum pipe pipe = intel_crtc->pipe;
2405 const struct intel_wm_level *r =
2406 &intel_crtc->wm.active.wm[0];
2408 if (WARN_ON(!r->enable))
2411 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2413 results->wm_pipe[pipe] =
2414 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2415 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2420 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2421 * case both are at the same level. Prefer r1 in case they're the same. */
2422 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2423 struct intel_pipe_wm *r1,
2424 struct intel_pipe_wm *r2)
2426 int level, max_level = ilk_wm_max_level(dev);
2427 int level1 = 0, level2 = 0;
2429 for (level = 1; level <= max_level; level++) {
2430 if (r1->wm[level].enable)
2432 if (r2->wm[level].enable)
2436 if (level1 == level2) {
2437 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2441 } else if (level1 > level2) {
2448 /* dirty bits used to track which watermarks need changes */
2449 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2450 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2451 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2452 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2453 #define WM_DIRTY_FBC (1 << 24)
2454 #define WM_DIRTY_DDB (1 << 25)
2456 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2457 const struct ilk_wm_values *old,
2458 const struct ilk_wm_values *new)
2460 unsigned int dirty = 0;
2464 for_each_pipe(pipe) {
2465 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2466 dirty |= WM_DIRTY_LINETIME(pipe);
2467 /* Must disable LP1+ watermarks too */
2468 dirty |= WM_DIRTY_LP_ALL;
2471 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2472 dirty |= WM_DIRTY_PIPE(pipe);
2473 /* Must disable LP1+ watermarks too */
2474 dirty |= WM_DIRTY_LP_ALL;
2478 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2479 dirty |= WM_DIRTY_FBC;
2480 /* Must disable LP1+ watermarks too */
2481 dirty |= WM_DIRTY_LP_ALL;
2484 if (old->partitioning != new->partitioning) {
2485 dirty |= WM_DIRTY_DDB;
2486 /* Must disable LP1+ watermarks too */
2487 dirty |= WM_DIRTY_LP_ALL;
2490 /* LP1+ watermarks already deemed dirty, no need to continue */
2491 if (dirty & WM_DIRTY_LP_ALL)
2494 /* Find the lowest numbered LP1+ watermark in need of an update... */
2495 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2496 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2497 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2501 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2502 for (; wm_lp <= 3; wm_lp++)
2503 dirty |= WM_DIRTY_LP(wm_lp);
2508 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2511 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2512 bool changed = false;
2514 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2515 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2516 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2519 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2520 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2521 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2524 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2525 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2526 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2531 * Don't touch WM1S_LP_EN here.
2532 * Doing so could cause underruns.
2539 * The spec says we shouldn't write when we don't need, because every write
2540 * causes WMs to be re-evaluated, expending some power.
2542 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2543 struct ilk_wm_values *results)
2545 struct drm_device *dev = dev_priv->dev;
2546 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2550 dirty = ilk_compute_wm_dirty(dev, previous, results);
2554 _ilk_disable_lp_wm(dev_priv, dirty);
2556 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2557 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2558 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2559 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2560 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2561 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2563 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2564 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2565 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2566 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2567 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2568 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2570 if (dirty & WM_DIRTY_DDB) {
2571 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2572 val = I915_READ(WM_MISC);
2573 if (results->partitioning == INTEL_DDB_PART_1_2)
2574 val &= ~WM_MISC_DATA_PARTITION_5_6;
2576 val |= WM_MISC_DATA_PARTITION_5_6;
2577 I915_WRITE(WM_MISC, val);
2579 val = I915_READ(DISP_ARB_CTL2);
2580 if (results->partitioning == INTEL_DDB_PART_1_2)
2581 val &= ~DISP_DATA_PARTITION_5_6;
2583 val |= DISP_DATA_PARTITION_5_6;
2584 I915_WRITE(DISP_ARB_CTL2, val);
2588 if (dirty & WM_DIRTY_FBC) {
2589 val = I915_READ(DISP_ARB_CTL);
2590 if (results->enable_fbc_wm)
2591 val &= ~DISP_FBC_WM_DIS;
2593 val |= DISP_FBC_WM_DIS;
2594 I915_WRITE(DISP_ARB_CTL, val);
2597 if (dirty & WM_DIRTY_LP(1) &&
2598 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2599 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2601 if (INTEL_INFO(dev)->gen >= 7) {
2602 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2603 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2604 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2605 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2608 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2609 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2610 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2611 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2612 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2613 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2615 dev_priv->wm.hw = *results;
2618 static bool ilk_disable_lp_wm(struct drm_device *dev)
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2622 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2625 static void ilk_update_wm(struct drm_crtc *crtc)
2627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2628 struct drm_device *dev = crtc->dev;
2629 struct drm_i915_private *dev_priv = dev->dev_private;
2630 struct ilk_wm_maximums max;
2631 struct ilk_pipe_wm_parameters params = {};
2632 struct ilk_wm_values results = {};
2633 enum intel_ddb_partitioning partitioning;
2634 struct intel_pipe_wm pipe_wm = {};
2635 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2636 struct intel_wm_config config = {};
2638 ilk_compute_wm_parameters(crtc, ¶ms);
2640 intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm);
2642 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2645 intel_crtc->wm.active = pipe_wm;
2647 ilk_compute_wm_config(dev, &config);
2649 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2650 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2652 /* 5/6 split only in single pipe config on IVB+ */
2653 if (INTEL_INFO(dev)->gen >= 7 &&
2654 config.num_pipes_active == 1 && config.sprites_enabled) {
2655 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2656 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2658 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2660 best_lp_wm = &lp_wm_1_2;
2663 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2664 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2666 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2668 ilk_write_wm_values(dev_priv, &results);
2671 static void ilk_update_sprite_wm(struct drm_plane *plane,
2672 struct drm_crtc *crtc,
2673 uint32_t sprite_width, int pixel_size,
2674 bool enabled, bool scaled)
2676 struct drm_device *dev = plane->dev;
2677 struct intel_plane *intel_plane = to_intel_plane(plane);
2679 intel_plane->wm.enabled = enabled;
2680 intel_plane->wm.scaled = scaled;
2681 intel_plane->wm.horiz_pixels = sprite_width;
2682 intel_plane->wm.bytes_per_pixel = pixel_size;
2685 * IVB workaround: must disable low power watermarks for at least
2686 * one frame before enabling scaling. LP watermarks can be re-enabled
2687 * when scaling is disabled.
2689 * WaCxSRDisabledForSpriteScaling:ivb
2691 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2692 intel_wait_for_vblank(dev, intel_plane->pipe);
2694 ilk_update_wm(crtc);
2697 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2699 struct drm_device *dev = crtc->dev;
2700 struct drm_i915_private *dev_priv = dev->dev_private;
2701 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2703 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2704 enum pipe pipe = intel_crtc->pipe;
2705 static const unsigned int wm0_pipe_reg[] = {
2706 [PIPE_A] = WM0_PIPEA_ILK,
2707 [PIPE_B] = WM0_PIPEB_ILK,
2708 [PIPE_C] = WM0_PIPEC_IVB,
2711 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2712 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2713 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2715 active->pipe_enabled = intel_crtc_active(crtc);
2717 if (active->pipe_enabled) {
2718 u32 tmp = hw->wm_pipe[pipe];
2721 * For active pipes LP0 watermark is marked as
2722 * enabled, and LP1+ watermaks as disabled since
2723 * we can't really reverse compute them in case
2724 * multiple pipes are active.
2726 active->wm[0].enable = true;
2727 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2728 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2729 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2730 active->linetime = hw->wm_linetime[pipe];
2732 int level, max_level = ilk_wm_max_level(dev);
2735 * For inactive pipes, all watermark levels
2736 * should be marked as enabled but zeroed,
2737 * which is what we'd compute them to.
2739 for (level = 0; level <= max_level; level++)
2740 active->wm[level].enable = true;
2744 void ilk_wm_get_hw_state(struct drm_device *dev)
2746 struct drm_i915_private *dev_priv = dev->dev_private;
2747 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2748 struct drm_crtc *crtc;
2750 for_each_crtc(dev, crtc)
2751 ilk_pipe_wm_get_hw_state(crtc);
2753 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2754 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2755 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2757 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2758 if (INTEL_INFO(dev)->gen >= 7) {
2759 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2760 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2763 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2764 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2765 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2766 else if (IS_IVYBRIDGE(dev))
2767 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2768 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2771 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2775 * intel_update_watermarks - update FIFO watermark values based on current modes
2777 * Calculate watermark values for the various WM regs based on current mode
2778 * and plane configuration.
2780 * There are several cases to deal with here:
2781 * - normal (i.e. non-self-refresh)
2782 * - self-refresh (SR) mode
2783 * - lines are large relative to FIFO size (buffer can hold up to 2)
2784 * - lines are small relative to FIFO size (buffer can hold more than 2
2785 * lines), so need to account for TLB latency
2787 * The normal calculation is:
2788 * watermark = dotclock * bytes per pixel * latency
2789 * where latency is platform & configuration dependent (we assume pessimal
2792 * The SR calculation is:
2793 * watermark = (trunc(latency/line time)+1) * surface width *
2796 * line time = htotal / dotclock
2797 * surface width = hdisplay for normal plane and 64 for cursor
2798 * and latency is assumed to be high, as above.
2800 * The final value programmed to the register should always be rounded up,
2801 * and include an extra 2 entries to account for clock crossings.
2803 * We don't use the sprite, so we can ignore that. And on Crestline we have
2804 * to set the non-SR watermarks to 8.
2806 void intel_update_watermarks(struct drm_crtc *crtc)
2808 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2810 if (dev_priv->display.update_wm)
2811 dev_priv->display.update_wm(crtc);
2814 void intel_update_sprite_watermarks(struct drm_plane *plane,
2815 struct drm_crtc *crtc,
2816 uint32_t sprite_width, int pixel_size,
2817 bool enabled, bool scaled)
2819 struct drm_i915_private *dev_priv = plane->dev->dev_private;
2821 if (dev_priv->display.update_sprite_wm)
2822 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
2823 pixel_size, enabled, scaled);
2826 static struct drm_i915_gem_object *
2827 intel_alloc_context_page(struct drm_device *dev)
2829 struct drm_i915_gem_object *ctx;
2832 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2834 ctx = i915_gem_alloc_object(dev, 4096);
2836 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2840 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2842 DRM_ERROR("failed to pin power context: %d\n", ret);
2846 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2848 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2855 i915_gem_object_ggtt_unpin(ctx);
2857 drm_gem_object_unreference(&ctx->base);
2862 * Lock protecting IPS related data structures
2864 DEFINE_SPINLOCK(mchdev_lock);
2866 /* Global for IPS driver to get at the current i915 device. Protected by
2868 static struct drm_i915_private *i915_mch_dev;
2870 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2872 struct drm_i915_private *dev_priv = dev->dev_private;
2875 assert_spin_locked(&mchdev_lock);
2877 rgvswctl = I915_READ16(MEMSWCTL);
2878 if (rgvswctl & MEMCTL_CMD_STS) {
2879 DRM_DEBUG("gpu busy, RCS change rejected\n");
2880 return false; /* still busy with another command */
2883 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2884 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2885 I915_WRITE16(MEMSWCTL, rgvswctl);
2886 POSTING_READ16(MEMSWCTL);
2888 rgvswctl |= MEMCTL_CMD_STS;
2889 I915_WRITE16(MEMSWCTL, rgvswctl);
2894 static void ironlake_enable_drps(struct drm_device *dev)
2896 struct drm_i915_private *dev_priv = dev->dev_private;
2897 u32 rgvmodectl = I915_READ(MEMMODECTL);
2898 u8 fmax, fmin, fstart, vstart;
2900 spin_lock_irq(&mchdev_lock);
2902 /* Enable temp reporting */
2903 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2904 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2906 /* 100ms RC evaluation intervals */
2907 I915_WRITE(RCUPEI, 100000);
2908 I915_WRITE(RCDNEI, 100000);
2910 /* Set max/min thresholds to 90ms and 80ms respectively */
2911 I915_WRITE(RCBMAXAVG, 90000);
2912 I915_WRITE(RCBMINAVG, 80000);
2914 I915_WRITE(MEMIHYST, 1);
2916 /* Set up min, max, and cur for interrupt handling */
2917 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2918 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2919 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2920 MEMMODE_FSTART_SHIFT;
2922 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2925 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2926 dev_priv->ips.fstart = fstart;
2928 dev_priv->ips.max_delay = fstart;
2929 dev_priv->ips.min_delay = fmin;
2930 dev_priv->ips.cur_delay = fstart;
2932 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2933 fmax, fmin, fstart);
2935 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2938 * Interrupts will be enabled in ironlake_irq_postinstall
2941 I915_WRITE(VIDSTART, vstart);
2942 POSTING_READ(VIDSTART);
2944 rgvmodectl |= MEMMODE_SWMODE_EN;
2945 I915_WRITE(MEMMODECTL, rgvmodectl);
2947 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2948 DRM_ERROR("stuck trying to change perf mode\n");
2951 ironlake_set_drps(dev, fstart);
2953 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2955 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2956 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2957 getrawmonotonic(&dev_priv->ips.last_time2);
2959 spin_unlock_irq(&mchdev_lock);
2962 static void ironlake_disable_drps(struct drm_device *dev)
2964 struct drm_i915_private *dev_priv = dev->dev_private;
2967 spin_lock_irq(&mchdev_lock);
2969 rgvswctl = I915_READ16(MEMSWCTL);
2971 /* Ack interrupts, disable EFC interrupt */
2972 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2973 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2974 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2975 I915_WRITE(DEIIR, DE_PCU_EVENT);
2976 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2978 /* Go back to the starting frequency */
2979 ironlake_set_drps(dev, dev_priv->ips.fstart);
2981 rgvswctl |= MEMCTL_CMD_STS;
2982 I915_WRITE(MEMSWCTL, rgvswctl);
2985 spin_unlock_irq(&mchdev_lock);
2988 /* There's a funny hw issue where the hw returns all 0 when reading from
2989 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2990 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2991 * all limits and the gpu stuck at whatever frequency it is at atm).
2993 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2997 /* Only set the down limit when we've reached the lowest level to avoid
2998 * getting more interrupts, otherwise leave this clear. This prevents a
2999 * race in the hw when coming out of rc6: There's a tiny window where
3000 * the hw runs at the minimal clock before selecting the desired
3001 * frequency, if the down threshold expires in that window we will not
3002 * receive a down interrupt. */
3003 limits = dev_priv->rps.max_freq_softlimit << 24;
3004 if (val <= dev_priv->rps.min_freq_softlimit)
3005 limits |= dev_priv->rps.min_freq_softlimit << 16;
3010 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3014 new_power = dev_priv->rps.power;
3015 switch (dev_priv->rps.power) {
3017 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3018 new_power = BETWEEN;
3022 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3023 new_power = LOW_POWER;
3024 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3025 new_power = HIGH_POWER;
3029 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3030 new_power = BETWEEN;
3033 /* Max/min bins are special */
3034 if (val == dev_priv->rps.min_freq_softlimit)
3035 new_power = LOW_POWER;
3036 if (val == dev_priv->rps.max_freq_softlimit)
3037 new_power = HIGH_POWER;
3038 if (new_power == dev_priv->rps.power)
3041 /* Note the units here are not exactly 1us, but 1280ns. */
3042 switch (new_power) {
3044 /* Upclock if more than 95% busy over 16ms */
3045 I915_WRITE(GEN6_RP_UP_EI, 12500);
3046 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3048 /* Downclock if less than 85% busy over 32ms */
3049 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3050 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3052 I915_WRITE(GEN6_RP_CONTROL,
3053 GEN6_RP_MEDIA_TURBO |
3054 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3055 GEN6_RP_MEDIA_IS_GFX |
3057 GEN6_RP_UP_BUSY_AVG |
3058 GEN6_RP_DOWN_IDLE_AVG);
3062 /* Upclock if more than 90% busy over 13ms */
3063 I915_WRITE(GEN6_RP_UP_EI, 10250);
3064 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3066 /* Downclock if less than 75% busy over 32ms */
3067 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3068 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3070 I915_WRITE(GEN6_RP_CONTROL,
3071 GEN6_RP_MEDIA_TURBO |
3072 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3073 GEN6_RP_MEDIA_IS_GFX |
3075 GEN6_RP_UP_BUSY_AVG |
3076 GEN6_RP_DOWN_IDLE_AVG);
3080 /* Upclock if more than 85% busy over 10ms */
3081 I915_WRITE(GEN6_RP_UP_EI, 8000);
3082 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3084 /* Downclock if less than 60% busy over 32ms */
3085 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3086 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3088 I915_WRITE(GEN6_RP_CONTROL,
3089 GEN6_RP_MEDIA_TURBO |
3090 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3091 GEN6_RP_MEDIA_IS_GFX |
3093 GEN6_RP_UP_BUSY_AVG |
3094 GEN6_RP_DOWN_IDLE_AVG);
3098 dev_priv->rps.power = new_power;
3099 dev_priv->rps.last_adj = 0;
3102 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3106 if (val > dev_priv->rps.min_freq_softlimit)
3107 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3108 if (val < dev_priv->rps.max_freq_softlimit)
3109 mask |= GEN6_PM_RP_UP_THRESHOLD;
3111 /* IVB and SNB hard hangs on looping batchbuffer
3112 * if GEN6_PM_UP_EI_EXPIRED is masked.
3114 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3115 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3117 if (IS_GEN8(dev_priv->dev))
3118 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3123 /* gen6_set_rps is called to update the frequency request, but should also be
3124 * called when the range (min_delay and max_delay) is modified so that we can
3125 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3126 void gen6_set_rps(struct drm_device *dev, u8 val)
3128 struct drm_i915_private *dev_priv = dev->dev_private;
3130 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3131 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3132 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3134 /* min/max delay may still have been modified so be sure to
3135 * write the limits value.
3137 if (val != dev_priv->rps.cur_freq) {
3138 gen6_set_rps_thresholds(dev_priv, val);
3140 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3141 I915_WRITE(GEN6_RPNSWREQ,
3142 HSW_FREQUENCY(val));
3144 I915_WRITE(GEN6_RPNSWREQ,
3145 GEN6_FREQUENCY(val) |
3147 GEN6_AGGRESSIVE_TURBO);
3150 /* Make sure we continue to get interrupts
3151 * until we hit the minimum or maximum frequencies.
3153 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3154 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3156 POSTING_READ(GEN6_RPNSWREQ);
3158 dev_priv->rps.cur_freq = val;
3159 trace_intel_gpu_freq_change(val * 50);
3162 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3164 * * If Gfx is Idle, then
3165 * 1. Mask Turbo interrupts
3166 * 2. Bring up Gfx clock
3167 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3168 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3169 * 5. Unmask Turbo interrupts
3171 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3174 * When we are idle. Drop to min voltage state.
3177 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3180 /* Mask turbo interrupt so that they will not come in between */
3181 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3183 vlv_force_gfx_clock(dev_priv, true);
3185 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3187 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3188 dev_priv->rps.min_freq_softlimit);
3190 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3191 & GENFREQSTATUS) == 0, 5))
3192 DRM_ERROR("timed out waiting for Punit\n");
3194 vlv_force_gfx_clock(dev_priv, false);
3196 I915_WRITE(GEN6_PMINTRMSK,
3197 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3200 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3202 struct drm_device *dev = dev_priv->dev;
3204 mutex_lock(&dev_priv->rps.hw_lock);
3205 if (dev_priv->rps.enabled) {
3206 if (IS_VALLEYVIEW(dev))
3207 vlv_set_rps_idle(dev_priv);
3209 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3210 dev_priv->rps.last_adj = 0;
3212 mutex_unlock(&dev_priv->rps.hw_lock);
3215 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3217 struct drm_device *dev = dev_priv->dev;
3219 mutex_lock(&dev_priv->rps.hw_lock);
3220 if (dev_priv->rps.enabled) {
3221 if (IS_VALLEYVIEW(dev))
3222 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3224 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3225 dev_priv->rps.last_adj = 0;
3227 mutex_unlock(&dev_priv->rps.hw_lock);
3230 void valleyview_set_rps(struct drm_device *dev, u8 val)
3232 struct drm_i915_private *dev_priv = dev->dev_private;
3234 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3235 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3236 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3238 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3239 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3240 dev_priv->rps.cur_freq,
3241 vlv_gpu_freq(dev_priv, val), val);
3243 if (val != dev_priv->rps.cur_freq)
3244 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3246 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3248 dev_priv->rps.cur_freq = val;
3249 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3252 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3254 struct drm_i915_private *dev_priv = dev->dev_private;
3256 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3257 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3258 ~dev_priv->pm_rps_events);
3259 /* Complete PM interrupt masking here doesn't race with the rps work
3260 * item again unmasking PM interrupts because that is using a different
3261 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3262 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3263 * gen8_enable_rps will clean up. */
3265 spin_lock_irq(&dev_priv->irq_lock);
3266 dev_priv->rps.pm_iir = 0;
3267 spin_unlock_irq(&dev_priv->irq_lock);
3269 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3272 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3274 struct drm_i915_private *dev_priv = dev->dev_private;
3276 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3277 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3278 ~dev_priv->pm_rps_events);
3279 /* Complete PM interrupt masking here doesn't race with the rps work
3280 * item again unmasking PM interrupts because that is using a different
3281 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3282 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3284 spin_lock_irq(&dev_priv->irq_lock);
3285 dev_priv->rps.pm_iir = 0;
3286 spin_unlock_irq(&dev_priv->irq_lock);
3288 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3291 static void gen6_disable_rps(struct drm_device *dev)
3293 struct drm_i915_private *dev_priv = dev->dev_private;
3295 I915_WRITE(GEN6_RC_CONTROL, 0);
3296 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3298 if (IS_BROADWELL(dev))
3299 gen8_disable_rps_interrupts(dev);
3301 gen6_disable_rps_interrupts(dev);
3304 static void valleyview_disable_rps(struct drm_device *dev)
3306 struct drm_i915_private *dev_priv = dev->dev_private;
3308 I915_WRITE(GEN6_RC_CONTROL, 0);
3310 gen6_disable_rps_interrupts(dev);
3313 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3315 if (IS_VALLEYVIEW(dev)) {
3316 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3317 mode = GEN6_RC_CTL_RC6_ENABLE;
3321 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3322 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3323 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3324 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3327 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3329 /* No RC6 before Ironlake */
3330 if (INTEL_INFO(dev)->gen < 5)
3333 /* RC6 is only on Ironlake mobile not on desktop */
3334 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3337 /* Respect the kernel parameter if it is set */
3338 if (enable_rc6 >= 0) {
3341 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3342 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3345 mask = INTEL_RC6_ENABLE;
3347 if ((enable_rc6 & mask) != enable_rc6)
3348 DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3349 enable_rc6 & mask, enable_rc6, mask);
3351 return enable_rc6 & mask;
3354 /* Disable RC6 on Ironlake */
3355 if (INTEL_INFO(dev)->gen == 5)
3358 if (IS_IVYBRIDGE(dev))
3359 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3361 return INTEL_RC6_ENABLE;
3364 int intel_enable_rc6(const struct drm_device *dev)
3366 return i915.enable_rc6;
3369 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3371 struct drm_i915_private *dev_priv = dev->dev_private;
3373 spin_lock_irq(&dev_priv->irq_lock);
3374 WARN_ON(dev_priv->rps.pm_iir);
3375 bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3376 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3377 spin_unlock_irq(&dev_priv->irq_lock);
3380 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3384 spin_lock_irq(&dev_priv->irq_lock);
3385 WARN_ON(dev_priv->rps.pm_iir);
3386 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3387 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3388 spin_unlock_irq(&dev_priv->irq_lock);
3391 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3393 /* All of these values are in units of 50MHz */
3394 dev_priv->rps.cur_freq = 0;
3395 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3396 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3397 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3398 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3399 /* XXX: only BYT has a special efficient freq */
3400 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3401 /* hw_max = RP0 until we check for overclocking */
3402 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3404 /* Preserve min/max settings in case of re-init */
3405 if (dev_priv->rps.max_freq_softlimit == 0)
3406 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3408 if (dev_priv->rps.min_freq_softlimit == 0)
3409 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3412 static void gen8_enable_rps(struct drm_device *dev)
3414 struct drm_i915_private *dev_priv = dev->dev_private;
3415 struct intel_engine_cs *ring;
3416 uint32_t rc6_mask = 0, rp_state_cap;
3419 /* 1a: Software RC state - RC0 */
3420 I915_WRITE(GEN6_RC_STATE, 0);
3422 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3423 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3424 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3426 /* 2a: Disable RC states. */
3427 I915_WRITE(GEN6_RC_CONTROL, 0);
3429 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3430 parse_rp_state_cap(dev_priv, rp_state_cap);
3432 /* 2b: Program RC6 thresholds.*/
3433 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3434 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3435 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3436 for_each_ring(ring, dev_priv, unused)
3437 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3438 I915_WRITE(GEN6_RC_SLEEP, 0);
3439 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3442 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3443 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3444 intel_print_rc6_info(dev, rc6_mask);
3445 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3446 GEN6_RC_CTL_EI_MODE(1) |
3449 /* 4 Program defaults and thresholds for RPS*/
3450 I915_WRITE(GEN6_RPNSWREQ,
3451 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3452 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3453 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3454 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3455 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3457 /* Docs recommend 900MHz, and 300 MHz respectively */
3458 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3459 dev_priv->rps.max_freq_softlimit << 24 |
3460 dev_priv->rps.min_freq_softlimit << 16);
3462 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3463 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3464 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3465 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3467 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3469 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
3470 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
3471 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
3474 I915_WRITE(GEN6_RP_CONTROL,
3475 GEN6_RP_MEDIA_TURBO |
3476 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3477 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
3479 GEN6_RP_UP_BUSY_AVG |
3480 GEN6_RP_DOWN_IDLE_AVG);
3482 /* 6: Ring frequency + overclocking (our driver does this later */
3484 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3486 gen8_enable_rps_interrupts(dev);
3488 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3491 static void gen6_enable_rps(struct drm_device *dev)
3493 struct drm_i915_private *dev_priv = dev->dev_private;
3494 struct intel_engine_cs *ring;
3497 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3502 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3504 /* Here begins a magic sequence of register writes to enable
3505 * auto-downclocking.
3507 * Perhaps there might be some value in exposing these to
3510 I915_WRITE(GEN6_RC_STATE, 0);
3512 /* Clear the DBG now so we don't confuse earlier errors */
3513 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3514 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3515 I915_WRITE(GTFIFODBG, gtfifodbg);
3518 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3520 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3521 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3523 parse_rp_state_cap(dev_priv, rp_state_cap);
3525 /* disable the counters and set deterministic thresholds */
3526 I915_WRITE(GEN6_RC_CONTROL, 0);
3528 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3529 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3530 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3531 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3532 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3534 for_each_ring(ring, dev_priv, i)
3535 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3537 I915_WRITE(GEN6_RC_SLEEP, 0);
3538 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3539 if (IS_IVYBRIDGE(dev))
3540 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3542 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3543 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3544 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3546 /* Check if we are enabling RC6 */
3547 rc6_mode = intel_enable_rc6(dev_priv->dev);
3548 if (rc6_mode & INTEL_RC6_ENABLE)
3549 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3551 /* We don't use those on Haswell */
3552 if (!IS_HASWELL(dev)) {
3553 if (rc6_mode & INTEL_RC6p_ENABLE)
3554 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3556 if (rc6_mode & INTEL_RC6pp_ENABLE)
3557 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3560 intel_print_rc6_info(dev, rc6_mask);
3562 I915_WRITE(GEN6_RC_CONTROL,
3564 GEN6_RC_CTL_EI_MODE(1) |
3565 GEN6_RC_CTL_HW_ENABLE);
3567 /* Power down if completely idle for over 50ms */
3568 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3569 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3571 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3573 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3575 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3576 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3577 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3578 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3579 (pcu_mbox & 0xff) * 50);
3580 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3583 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3584 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3586 gen6_enable_rps_interrupts(dev);
3589 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3590 if (IS_GEN6(dev) && ret) {
3591 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3592 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3593 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3594 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3595 rc6vids &= 0xffff00;
3596 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3597 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3599 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3602 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3605 static void __gen6_update_ring_freq(struct drm_device *dev)
3607 struct drm_i915_private *dev_priv = dev->dev_private;
3609 unsigned int gpu_freq;
3610 unsigned int max_ia_freq, min_ring_freq;
3611 int scaling_factor = 180;
3612 struct cpufreq_policy *policy;
3614 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3616 policy = cpufreq_cpu_get(0);
3618 max_ia_freq = policy->cpuinfo.max_freq;
3619 cpufreq_cpu_put(policy);
3622 * Default to measured freq if none found, PCU will ensure we
3625 max_ia_freq = tsc_khz;
3628 /* Convert from kHz to MHz */
3629 max_ia_freq /= 1000;
3631 min_ring_freq = I915_READ(DCLK) & 0xf;
3632 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3633 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3636 * For each potential GPU frequency, load a ring frequency we'd like
3637 * to use for memory access. We do this by specifying the IA frequency
3638 * the PCU should use as a reference to determine the ring frequency.
3640 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3642 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3643 unsigned int ia_freq = 0, ring_freq = 0;
3645 if (INTEL_INFO(dev)->gen >= 8) {
3646 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3647 ring_freq = max(min_ring_freq, gpu_freq);
3648 } else if (IS_HASWELL(dev)) {
3649 ring_freq = mult_frac(gpu_freq, 5, 4);
3650 ring_freq = max(min_ring_freq, ring_freq);
3651 /* leave ia_freq as the default, chosen by cpufreq */
3653 /* On older processors, there is no separate ring
3654 * clock domain, so in order to boost the bandwidth
3655 * of the ring, we need to upclock the CPU (ia_freq).
3657 * For GPU frequencies less than 750MHz,
3658 * just use the lowest ring freq.
3660 if (gpu_freq < min_freq)
3663 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3664 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3667 sandybridge_pcode_write(dev_priv,
3668 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3669 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3670 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3675 void gen6_update_ring_freq(struct drm_device *dev)
3677 struct drm_i915_private *dev_priv = dev->dev_private;
3679 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3682 mutex_lock(&dev_priv->rps.hw_lock);
3683 __gen6_update_ring_freq(dev);
3684 mutex_unlock(&dev_priv->rps.hw_lock);
3687 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3691 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3693 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3695 rp0 = min_t(u32, rp0, 0xea);
3700 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3704 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3705 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3706 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3707 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3712 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3714 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3717 /* Check that the pctx buffer wasn't move under us. */
3718 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3720 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3722 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3723 dev_priv->vlv_pctx->stolen->start);
3726 static void valleyview_setup_pctx(struct drm_device *dev)
3728 struct drm_i915_private *dev_priv = dev->dev_private;
3729 struct drm_i915_gem_object *pctx;
3730 unsigned long pctx_paddr;
3732 int pctx_size = 24*1024;
3734 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3736 pcbr = I915_READ(VLV_PCBR);
3738 /* BIOS set it up already, grab the pre-alloc'd space */
3741 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3742 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3744 I915_GTT_OFFSET_NONE,
3750 * From the Gunit register HAS:
3751 * The Gfx driver is expected to program this register and ensure
3752 * proper allocation within Gfx stolen memory. For example, this
3753 * register should be programmed such than the PCBR range does not
3754 * overlap with other ranges, such as the frame buffer, protected
3755 * memory, or any other relevant ranges.
3757 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3759 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3763 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3764 I915_WRITE(VLV_PCBR, pctx_paddr);
3767 dev_priv->vlv_pctx = pctx;
3770 static void valleyview_cleanup_pctx(struct drm_device *dev)
3772 struct drm_i915_private *dev_priv = dev->dev_private;
3774 if (WARN_ON(!dev_priv->vlv_pctx))
3777 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3778 dev_priv->vlv_pctx = NULL;
3781 static void valleyview_init_gt_powersave(struct drm_device *dev)
3783 struct drm_i915_private *dev_priv = dev->dev_private;
3785 valleyview_setup_pctx(dev);
3787 mutex_lock(&dev_priv->rps.hw_lock);
3789 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3790 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3791 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3792 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3793 dev_priv->rps.max_freq);
3795 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3796 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3797 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3798 dev_priv->rps.efficient_freq);
3800 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3801 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3802 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3803 dev_priv->rps.min_freq);
3805 /* Preserve min/max settings in case of re-init */
3806 if (dev_priv->rps.max_freq_softlimit == 0)
3807 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3809 if (dev_priv->rps.min_freq_softlimit == 0)
3810 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3812 mutex_unlock(&dev_priv->rps.hw_lock);
3815 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
3817 valleyview_cleanup_pctx(dev);
3820 static void valleyview_enable_rps(struct drm_device *dev)
3822 struct drm_i915_private *dev_priv = dev->dev_private;
3823 struct intel_engine_cs *ring;
3824 u32 gtfifodbg, val, rc6_mode = 0;
3827 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3829 valleyview_check_pctx(dev_priv);
3831 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3832 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3834 I915_WRITE(GTFIFODBG, gtfifodbg);
3837 /* If VLV, Forcewake all wells, else re-direct to regular path */
3838 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3840 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3841 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3842 I915_WRITE(GEN6_RP_UP_EI, 66000);
3843 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3845 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3847 I915_WRITE(GEN6_RP_CONTROL,
3848 GEN6_RP_MEDIA_TURBO |
3849 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3850 GEN6_RP_MEDIA_IS_GFX |
3852 GEN6_RP_UP_BUSY_AVG |
3853 GEN6_RP_DOWN_IDLE_CONT);
3855 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3856 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3857 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3859 for_each_ring(ring, dev_priv, i)
3860 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3862 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
3864 /* allows RC6 residency counter to work */
3865 I915_WRITE(VLV_COUNTER_CONTROL,
3866 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3867 VLV_MEDIA_RC6_COUNT_EN |
3868 VLV_RENDER_RC6_COUNT_EN));
3869 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3870 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
3872 intel_print_rc6_info(dev, rc6_mode);
3874 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3876 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3878 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3879 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3881 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
3882 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3883 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3884 dev_priv->rps.cur_freq);
3886 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3887 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3888 dev_priv->rps.efficient_freq);
3890 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
3892 gen6_enable_rps_interrupts(dev);
3894 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3897 void ironlake_teardown_rc6(struct drm_device *dev)
3899 struct drm_i915_private *dev_priv = dev->dev_private;
3901 if (dev_priv->ips.renderctx) {
3902 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3903 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3904 dev_priv->ips.renderctx = NULL;
3907 if (dev_priv->ips.pwrctx) {
3908 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3909 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3910 dev_priv->ips.pwrctx = NULL;
3914 static void ironlake_disable_rc6(struct drm_device *dev)
3916 struct drm_i915_private *dev_priv = dev->dev_private;
3918 if (I915_READ(PWRCTXA)) {
3919 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3920 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3921 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3924 I915_WRITE(PWRCTXA, 0);
3925 POSTING_READ(PWRCTXA);
3927 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3928 POSTING_READ(RSTDBYCTL);
3932 static int ironlake_setup_rc6(struct drm_device *dev)
3934 struct drm_i915_private *dev_priv = dev->dev_private;
3936 if (dev_priv->ips.renderctx == NULL)
3937 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3938 if (!dev_priv->ips.renderctx)
3941 if (dev_priv->ips.pwrctx == NULL)
3942 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3943 if (!dev_priv->ips.pwrctx) {
3944 ironlake_teardown_rc6(dev);
3951 static void ironlake_enable_rc6(struct drm_device *dev)
3953 struct drm_i915_private *dev_priv = dev->dev_private;
3954 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3955 bool was_interruptible;
3958 /* rc6 disabled by default due to repeated reports of hanging during
3961 if (!intel_enable_rc6(dev))
3964 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3966 ret = ironlake_setup_rc6(dev);
3970 was_interruptible = dev_priv->mm.interruptible;
3971 dev_priv->mm.interruptible = false;
3974 * GPU can automatically power down the render unit if given a page
3977 ret = intel_ring_begin(ring, 6);
3979 ironlake_teardown_rc6(dev);
3980 dev_priv->mm.interruptible = was_interruptible;
3984 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3985 intel_ring_emit(ring, MI_SET_CONTEXT);
3986 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
3988 MI_SAVE_EXT_STATE_EN |
3989 MI_RESTORE_EXT_STATE_EN |
3990 MI_RESTORE_INHIBIT);
3991 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3992 intel_ring_emit(ring, MI_NOOP);
3993 intel_ring_emit(ring, MI_FLUSH);
3994 intel_ring_advance(ring);
3997 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3998 * does an implicit flush, combined with MI_FLUSH above, it should be
3999 * safe to assume that renderctx is valid
4001 ret = intel_ring_idle(ring);
4002 dev_priv->mm.interruptible = was_interruptible;
4004 DRM_ERROR("failed to enable ironlake power savings\n");
4005 ironlake_teardown_rc6(dev);
4009 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4010 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4012 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4015 static unsigned long intel_pxfreq(u32 vidfreq)
4018 int div = (vidfreq & 0x3f0000) >> 16;
4019 int post = (vidfreq & 0x3000) >> 12;
4020 int pre = (vidfreq & 0x7);
4025 freq = ((div * 133333) / ((1<<post) * pre));
4030 static const struct cparams {
4036 { 1, 1333, 301, 28664 },
4037 { 1, 1066, 294, 24460 },
4038 { 1, 800, 294, 25192 },
4039 { 0, 1333, 276, 27605 },
4040 { 0, 1066, 276, 27605 },
4041 { 0, 800, 231, 23784 },
4044 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4046 u64 total_count, diff, ret;
4047 u32 count1, count2, count3, m = 0, c = 0;
4048 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4051 assert_spin_locked(&mchdev_lock);
4053 diff1 = now - dev_priv->ips.last_time1;
4055 /* Prevent division-by-zero if we are asking too fast.
4056 * Also, we don't get interesting results if we are polling
4057 * faster than once in 10ms, so just return the saved value
4061 return dev_priv->ips.chipset_power;
4063 count1 = I915_READ(DMIEC);
4064 count2 = I915_READ(DDREC);
4065 count3 = I915_READ(CSIEC);
4067 total_count = count1 + count2 + count3;
4069 /* FIXME: handle per-counter overflow */
4070 if (total_count < dev_priv->ips.last_count1) {
4071 diff = ~0UL - dev_priv->ips.last_count1;
4072 diff += total_count;
4074 diff = total_count - dev_priv->ips.last_count1;
4077 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4078 if (cparams[i].i == dev_priv->ips.c_m &&
4079 cparams[i].t == dev_priv->ips.r_t) {
4086 diff = div_u64(diff, diff1);
4087 ret = ((m * diff) + c);
4088 ret = div_u64(ret, 10);
4090 dev_priv->ips.last_count1 = total_count;
4091 dev_priv->ips.last_time1 = now;
4093 dev_priv->ips.chipset_power = ret;
4098 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4100 struct drm_device *dev = dev_priv->dev;
4103 if (INTEL_INFO(dev)->gen != 5)
4106 spin_lock_irq(&mchdev_lock);
4108 val = __i915_chipset_val(dev_priv);
4110 spin_unlock_irq(&mchdev_lock);
4115 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4117 unsigned long m, x, b;
4120 tsfs = I915_READ(TSFS);
4122 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4123 x = I915_READ8(TR1);
4125 b = tsfs & TSFS_INTR_MASK;
4127 return ((m * x) / 127) - b;
4130 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4132 struct drm_device *dev = dev_priv->dev;
4133 static const struct v_table {
4134 u16 vd; /* in .1 mil */
4135 u16 vm; /* in .1 mil */
4266 if (INTEL_INFO(dev)->is_mobile)
4267 return v_table[pxvid].vm;
4269 return v_table[pxvid].vd;
4272 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4274 struct timespec now, diff1;
4276 unsigned long diffms;
4279 assert_spin_locked(&mchdev_lock);
4281 getrawmonotonic(&now);
4282 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4284 /* Don't divide by 0 */
4285 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4289 count = I915_READ(GFXEC);
4291 if (count < dev_priv->ips.last_count2) {
4292 diff = ~0UL - dev_priv->ips.last_count2;
4295 diff = count - dev_priv->ips.last_count2;
4298 dev_priv->ips.last_count2 = count;
4299 dev_priv->ips.last_time2 = now;
4301 /* More magic constants... */
4303 diff = div_u64(diff, diffms * 10);
4304 dev_priv->ips.gfx_power = diff;
4307 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4309 struct drm_device *dev = dev_priv->dev;
4311 if (INTEL_INFO(dev)->gen != 5)
4314 spin_lock_irq(&mchdev_lock);
4316 __i915_update_gfx_val(dev_priv);
4318 spin_unlock_irq(&mchdev_lock);
4321 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4323 unsigned long t, corr, state1, corr2, state2;
4326 assert_spin_locked(&mchdev_lock);
4328 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4329 pxvid = (pxvid >> 24) & 0x7f;
4330 ext_v = pvid_to_extvid(dev_priv, pxvid);
4334 t = i915_mch_val(dev_priv);
4336 /* Revel in the empirically derived constants */
4338 /* Correction factor in 1/100000 units */
4340 corr = ((t * 2349) + 135940);
4342 corr = ((t * 964) + 29317);
4344 corr = ((t * 301) + 1004);
4346 corr = corr * ((150142 * state1) / 10000 - 78642);
4348 corr2 = (corr * dev_priv->ips.corr);
4350 state2 = (corr2 * state1) / 10000;
4351 state2 /= 100; /* convert to mW */
4353 __i915_update_gfx_val(dev_priv);
4355 return dev_priv->ips.gfx_power + state2;
4358 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4360 struct drm_device *dev = dev_priv->dev;
4363 if (INTEL_INFO(dev)->gen != 5)
4366 spin_lock_irq(&mchdev_lock);
4368 val = __i915_gfx_val(dev_priv);
4370 spin_unlock_irq(&mchdev_lock);
4376 * i915_read_mch_val - return value for IPS use
4378 * Calculate and return a value for the IPS driver to use when deciding whether
4379 * we have thermal and power headroom to increase CPU or GPU power budget.
4381 unsigned long i915_read_mch_val(void)
4383 struct drm_i915_private *dev_priv;
4384 unsigned long chipset_val, graphics_val, ret = 0;
4386 spin_lock_irq(&mchdev_lock);
4389 dev_priv = i915_mch_dev;
4391 chipset_val = __i915_chipset_val(dev_priv);
4392 graphics_val = __i915_gfx_val(dev_priv);
4394 ret = chipset_val + graphics_val;
4397 spin_unlock_irq(&mchdev_lock);
4401 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4404 * i915_gpu_raise - raise GPU frequency limit
4406 * Raise the limit; IPS indicates we have thermal headroom.
4408 bool i915_gpu_raise(void)
4410 struct drm_i915_private *dev_priv;
4413 spin_lock_irq(&mchdev_lock);
4414 if (!i915_mch_dev) {
4418 dev_priv = i915_mch_dev;
4420 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4421 dev_priv->ips.max_delay--;
4424 spin_unlock_irq(&mchdev_lock);
4428 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4431 * i915_gpu_lower - lower GPU frequency limit
4433 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4434 * frequency maximum.
4436 bool i915_gpu_lower(void)
4438 struct drm_i915_private *dev_priv;
4441 spin_lock_irq(&mchdev_lock);
4442 if (!i915_mch_dev) {
4446 dev_priv = i915_mch_dev;
4448 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4449 dev_priv->ips.max_delay++;
4452 spin_unlock_irq(&mchdev_lock);
4456 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4459 * i915_gpu_busy - indicate GPU business to IPS
4461 * Tell the IPS driver whether or not the GPU is busy.
4463 bool i915_gpu_busy(void)
4465 struct drm_i915_private *dev_priv;
4466 struct intel_engine_cs *ring;
4470 spin_lock_irq(&mchdev_lock);
4473 dev_priv = i915_mch_dev;
4475 for_each_ring(ring, dev_priv, i)
4476 ret |= !list_empty(&ring->request_list);
4479 spin_unlock_irq(&mchdev_lock);
4483 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4486 * i915_gpu_turbo_disable - disable graphics turbo
4488 * Disable graphics turbo by resetting the max frequency and setting the
4489 * current frequency to the default.
4491 bool i915_gpu_turbo_disable(void)
4493 struct drm_i915_private *dev_priv;
4496 spin_lock_irq(&mchdev_lock);
4497 if (!i915_mch_dev) {
4501 dev_priv = i915_mch_dev;
4503 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4505 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4509 spin_unlock_irq(&mchdev_lock);
4513 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4516 * Tells the intel_ips driver that the i915 driver is now loaded, if
4517 * IPS got loaded first.
4519 * This awkward dance is so that neither module has to depend on the
4520 * other in order for IPS to do the appropriate communication of
4521 * GPU turbo limits to i915.
4524 ips_ping_for_i915_load(void)
4528 link = symbol_get(ips_link_to_i915_driver);
4531 symbol_put(ips_link_to_i915_driver);
4535 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4537 /* We only register the i915 ips part with intel-ips once everything is
4538 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4539 spin_lock_irq(&mchdev_lock);
4540 i915_mch_dev = dev_priv;
4541 spin_unlock_irq(&mchdev_lock);
4543 ips_ping_for_i915_load();
4546 void intel_gpu_ips_teardown(void)
4548 spin_lock_irq(&mchdev_lock);
4549 i915_mch_dev = NULL;
4550 spin_unlock_irq(&mchdev_lock);
4553 static void intel_init_emon(struct drm_device *dev)
4555 struct drm_i915_private *dev_priv = dev->dev_private;
4560 /* Disable to program */
4564 /* Program energy weights for various events */
4565 I915_WRITE(SDEW, 0x15040d00);
4566 I915_WRITE(CSIEW0, 0x007f0000);
4567 I915_WRITE(CSIEW1, 0x1e220004);
4568 I915_WRITE(CSIEW2, 0x04000004);
4570 for (i = 0; i < 5; i++)
4571 I915_WRITE(PEW + (i * 4), 0);
4572 for (i = 0; i < 3; i++)
4573 I915_WRITE(DEW + (i * 4), 0);
4575 /* Program P-state weights to account for frequency power adjustment */
4576 for (i = 0; i < 16; i++) {
4577 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4578 unsigned long freq = intel_pxfreq(pxvidfreq);
4579 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4584 val *= (freq / 1000);
4586 val /= (127*127*900);
4588 DRM_ERROR("bad pxval: %ld\n", val);
4591 /* Render standby states get 0 weight */
4595 for (i = 0; i < 4; i++) {
4596 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4597 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4598 I915_WRITE(PXW + (i * 4), val);
4601 /* Adjust magic regs to magic values (more experimental results) */
4602 I915_WRITE(OGW0, 0);
4603 I915_WRITE(OGW1, 0);
4604 I915_WRITE(EG0, 0x00007f00);
4605 I915_WRITE(EG1, 0x0000000e);
4606 I915_WRITE(EG2, 0x000e0000);
4607 I915_WRITE(EG3, 0x68000300);
4608 I915_WRITE(EG4, 0x42000000);
4609 I915_WRITE(EG5, 0x00140031);
4613 for (i = 0; i < 8; i++)
4614 I915_WRITE(PXWL + (i * 4), 0);
4616 /* Enable PMON + select events */
4617 I915_WRITE(ECR, 0x80000019);
4619 lcfuse = I915_READ(LCFUSE02);
4621 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4624 void intel_init_gt_powersave(struct drm_device *dev)
4626 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4628 if (IS_VALLEYVIEW(dev))
4629 valleyview_init_gt_powersave(dev);
4632 void intel_cleanup_gt_powersave(struct drm_device *dev)
4634 if (IS_VALLEYVIEW(dev))
4635 valleyview_cleanup_gt_powersave(dev);
4638 void intel_disable_gt_powersave(struct drm_device *dev)
4640 struct drm_i915_private *dev_priv = dev->dev_private;
4642 /* Interrupts should be disabled already to avoid re-arming. */
4643 WARN_ON(dev->irq_enabled);
4645 if (IS_IRONLAKE_M(dev)) {
4646 ironlake_disable_drps(dev);
4647 ironlake_disable_rc6(dev);
4648 } else if (IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)) {
4649 if (cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work))
4650 intel_runtime_pm_put(dev_priv);
4652 cancel_work_sync(&dev_priv->rps.work);
4653 mutex_lock(&dev_priv->rps.hw_lock);
4654 if (IS_VALLEYVIEW(dev))
4655 valleyview_disable_rps(dev);
4657 gen6_disable_rps(dev);
4658 dev_priv->rps.enabled = false;
4659 mutex_unlock(&dev_priv->rps.hw_lock);
4663 static void intel_gen6_powersave_work(struct work_struct *work)
4665 struct drm_i915_private *dev_priv =
4666 container_of(work, struct drm_i915_private,
4667 rps.delayed_resume_work.work);
4668 struct drm_device *dev = dev_priv->dev;
4670 mutex_lock(&dev_priv->rps.hw_lock);
4672 if (IS_VALLEYVIEW(dev)) {
4673 valleyview_enable_rps(dev);
4674 } else if (IS_BROADWELL(dev)) {
4675 gen8_enable_rps(dev);
4676 __gen6_update_ring_freq(dev);
4678 gen6_enable_rps(dev);
4679 __gen6_update_ring_freq(dev);
4681 dev_priv->rps.enabled = true;
4682 mutex_unlock(&dev_priv->rps.hw_lock);
4684 intel_runtime_pm_put(dev_priv);
4687 void intel_enable_gt_powersave(struct drm_device *dev)
4689 struct drm_i915_private *dev_priv = dev->dev_private;
4691 if (IS_IRONLAKE_M(dev)) {
4692 mutex_lock(&dev->struct_mutex);
4693 ironlake_enable_drps(dev);
4694 ironlake_enable_rc6(dev);
4695 intel_init_emon(dev);
4696 mutex_unlock(&dev->struct_mutex);
4697 } else if (IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)) {
4699 * PCU communication is slow and this doesn't need to be
4700 * done at any specific time, so do this out of our fast path
4701 * to make resume and init faster.
4703 * We depend on the HW RC6 power context save/restore
4704 * mechanism when entering D3 through runtime PM suspend. So
4705 * disable RPM until RPS/RC6 is properly setup. We can only
4706 * get here via the driver load/system resume/runtime resume
4707 * paths, so the _noresume version is enough (and in case of
4708 * runtime resume it's necessary).
4710 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4711 round_jiffies_up_relative(HZ)))
4712 intel_runtime_pm_get_noresume(dev_priv);
4716 void intel_reset_gt_powersave(struct drm_device *dev)
4718 struct drm_i915_private *dev_priv = dev->dev_private;
4720 dev_priv->rps.enabled = false;
4721 intel_enable_gt_powersave(dev);
4724 static void ibx_init_clock_gating(struct drm_device *dev)
4726 struct drm_i915_private *dev_priv = dev->dev_private;
4729 * On Ibex Peak and Cougar Point, we need to disable clock
4730 * gating for the panel power sequencer or it will fail to
4731 * start up when no ports are active.
4733 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4736 static void g4x_disable_trickle_feed(struct drm_device *dev)
4738 struct drm_i915_private *dev_priv = dev->dev_private;
4741 for_each_pipe(pipe) {
4742 I915_WRITE(DSPCNTR(pipe),
4743 I915_READ(DSPCNTR(pipe)) |
4744 DISPPLANE_TRICKLE_FEED_DISABLE);
4745 intel_flush_primary_plane(dev_priv, pipe);
4749 static void ilk_init_lp_watermarks(struct drm_device *dev)
4751 struct drm_i915_private *dev_priv = dev->dev_private;
4753 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4754 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4755 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4758 * Don't touch WM1S_LP_EN here.
4759 * Doing so could cause underruns.
4763 static void ironlake_init_clock_gating(struct drm_device *dev)
4765 struct drm_i915_private *dev_priv = dev->dev_private;
4766 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4770 * WaFbcDisableDpfcClockGating:ilk
4772 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4773 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4774 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4776 I915_WRITE(PCH_3DCGDIS0,
4777 MARIUNIT_CLOCK_GATE_DISABLE |
4778 SVSMUNIT_CLOCK_GATE_DISABLE);
4779 I915_WRITE(PCH_3DCGDIS1,
4780 VFMUNIT_CLOCK_GATE_DISABLE);
4783 * According to the spec the following bits should be set in
4784 * order to enable memory self-refresh
4785 * The bit 22/21 of 0x42004
4786 * The bit 5 of 0x42020
4787 * The bit 15 of 0x45000
4789 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4790 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4791 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4792 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4793 I915_WRITE(DISP_ARB_CTL,
4794 (I915_READ(DISP_ARB_CTL) |
4797 ilk_init_lp_watermarks(dev);
4800 * Based on the document from hardware guys the following bits
4801 * should be set unconditionally in order to enable FBC.
4802 * The bit 22 of 0x42000
4803 * The bit 22 of 0x42004
4804 * The bit 7,8,9 of 0x42020.
4806 if (IS_IRONLAKE_M(dev)) {
4807 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4808 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4809 I915_READ(ILK_DISPLAY_CHICKEN1) |
4811 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4812 I915_READ(ILK_DISPLAY_CHICKEN2) |
4816 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4818 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4819 I915_READ(ILK_DISPLAY_CHICKEN2) |
4820 ILK_ELPIN_409_SELECT);
4821 I915_WRITE(_3D_CHICKEN2,
4822 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4823 _3D_CHICKEN2_WM_READ_PIPELINED);
4825 /* WaDisableRenderCachePipelinedFlush:ilk */
4826 I915_WRITE(CACHE_MODE_0,
4827 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4829 /* WaDisable_RenderCache_OperationalFlush:ilk */
4830 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4832 g4x_disable_trickle_feed(dev);
4834 ibx_init_clock_gating(dev);
4837 static void cpt_init_clock_gating(struct drm_device *dev)
4839 struct drm_i915_private *dev_priv = dev->dev_private;
4844 * On Ibex Peak and Cougar Point, we need to disable clock
4845 * gating for the panel power sequencer or it will fail to
4846 * start up when no ports are active.
4848 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4849 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4850 PCH_CPUNIT_CLOCK_GATE_DISABLE);
4851 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4852 DPLS_EDP_PPS_FIX_DIS);
4853 /* The below fixes the weird display corruption, a few pixels shifted
4854 * downward, on (only) LVDS of some HP laptops with IVY.
4856 for_each_pipe(pipe) {
4857 val = I915_READ(TRANS_CHICKEN2(pipe));
4858 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4859 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4860 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4861 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4862 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4863 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4864 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4865 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4867 /* WADP0ClockGatingDisable */
4868 for_each_pipe(pipe) {
4869 I915_WRITE(TRANS_CHICKEN1(pipe),
4870 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4874 static void gen6_check_mch_setup(struct drm_device *dev)
4876 struct drm_i915_private *dev_priv = dev->dev_private;
4879 tmp = I915_READ(MCH_SSKPD);
4880 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4881 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4882 DRM_INFO("This can cause pipe underruns and display issues.\n");
4883 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4887 static void gen6_init_clock_gating(struct drm_device *dev)
4889 struct drm_i915_private *dev_priv = dev->dev_private;
4890 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4892 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4894 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4895 I915_READ(ILK_DISPLAY_CHICKEN2) |
4896 ILK_ELPIN_409_SELECT);
4898 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4899 I915_WRITE(_3D_CHICKEN,
4900 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4902 /* WaSetupGtModeTdRowDispatch:snb */
4903 if (IS_SNB_GT1(dev))
4904 I915_WRITE(GEN6_GT_MODE,
4905 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4907 /* WaDisable_RenderCache_OperationalFlush:snb */
4908 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4911 * BSpec recoomends 8x4 when MSAA is used,
4912 * however in practice 16x4 seems fastest.
4914 * Note that PS/WM thread counts depend on the WIZ hashing
4915 * disable bit, which we don't touch here, but it's good
4916 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4918 I915_WRITE(GEN6_GT_MODE,
4919 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4921 ilk_init_lp_watermarks(dev);
4923 I915_WRITE(CACHE_MODE_0,
4924 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4926 I915_WRITE(GEN6_UCGCTL1,
4927 I915_READ(GEN6_UCGCTL1) |
4928 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4929 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4931 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4932 * gating disable must be set. Failure to set it results in
4933 * flickering pixels due to Z write ordering failures after
4934 * some amount of runtime in the Mesa "fire" demo, and Unigine
4935 * Sanctuary and Tropics, and apparently anything else with
4936 * alpha test or pixel discard.
4938 * According to the spec, bit 11 (RCCUNIT) must also be set,
4939 * but we didn't debug actual testcases to find it out.
4941 * WaDisableRCCUnitClockGating:snb
4942 * WaDisableRCPBUnitClockGating:snb
4944 I915_WRITE(GEN6_UCGCTL2,
4945 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4946 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4948 /* WaStripsFansDisableFastClipPerformanceFix:snb */
4949 I915_WRITE(_3D_CHICKEN3,
4950 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
4954 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
4955 * 3DSTATE_SF number of SF output attributes is more than 16."
4957 I915_WRITE(_3D_CHICKEN3,
4958 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
4961 * According to the spec the following bits should be
4962 * set in order to enable memory self-refresh and fbc:
4963 * The bit21 and bit22 of 0x42000
4964 * The bit21 and bit22 of 0x42004
4965 * The bit5 and bit7 of 0x42020
4966 * The bit14 of 0x70180
4967 * The bit14 of 0x71180
4969 * WaFbcAsynchFlipDisableFbcQueue:snb
4971 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4972 I915_READ(ILK_DISPLAY_CHICKEN1) |
4973 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4974 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4975 I915_READ(ILK_DISPLAY_CHICKEN2) |
4976 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4977 I915_WRITE(ILK_DSPCLK_GATE_D,
4978 I915_READ(ILK_DSPCLK_GATE_D) |
4979 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4980 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4982 g4x_disable_trickle_feed(dev);
4984 cpt_init_clock_gating(dev);
4986 gen6_check_mch_setup(dev);
4989 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4991 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4994 * WaVSThreadDispatchOverride:ivb,vlv
4996 * This actually overrides the dispatch
4997 * mode for all thread types.
4999 reg &= ~GEN7_FF_SCHED_MASK;
5000 reg |= GEN7_FF_TS_SCHED_HW;
5001 reg |= GEN7_FF_VS_SCHED_HW;
5002 reg |= GEN7_FF_DS_SCHED_HW;
5004 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5007 static void lpt_init_clock_gating(struct drm_device *dev)
5009 struct drm_i915_private *dev_priv = dev->dev_private;
5012 * TODO: this bit should only be enabled when really needed, then
5013 * disabled when not needed anymore in order to save power.
5015 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5016 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5017 I915_READ(SOUTH_DSPCLK_GATE_D) |
5018 PCH_LP_PARTITION_LEVEL_DISABLE);
5020 /* WADPOClockGatingDisable:hsw */
5021 I915_WRITE(_TRANSA_CHICKEN1,
5022 I915_READ(_TRANSA_CHICKEN1) |
5023 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5026 static void lpt_suspend_hw(struct drm_device *dev)
5028 struct drm_i915_private *dev_priv = dev->dev_private;
5030 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5031 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5033 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5034 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5038 static void gen8_init_clock_gating(struct drm_device *dev)
5040 struct drm_i915_private *dev_priv = dev->dev_private;
5043 I915_WRITE(WM3_LP_ILK, 0);
5044 I915_WRITE(WM2_LP_ILK, 0);
5045 I915_WRITE(WM1_LP_ILK, 0);
5047 /* FIXME(BDW): Check all the w/a, some might only apply to
5048 * pre-production hw. */
5050 /* WaDisablePartialInstShootdown:bdw */
5051 I915_WRITE(GEN8_ROW_CHICKEN,
5052 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5054 /* WaDisableThreadStallDopClockGating:bdw */
5055 /* FIXME: Unclear whether we really need this on production bdw. */
5056 I915_WRITE(GEN8_ROW_CHICKEN,
5057 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5060 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5061 * pre-production hardware
5063 I915_WRITE(HALF_SLICE_CHICKEN3,
5064 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5065 I915_WRITE(HALF_SLICE_CHICKEN3,
5066 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5067 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5069 I915_WRITE(_3D_CHICKEN3,
5070 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5072 I915_WRITE(COMMON_SLICE_CHICKEN2,
5073 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5075 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5076 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5078 /* WaDisableDopClockGating:bdw May not be needed for production */
5079 I915_WRITE(GEN7_ROW_CHICKEN2,
5080 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5082 /* WaSwitchSolVfFArbitrationPriority:bdw */
5083 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5085 /* WaPsrDPAMaskVBlankInSRD:bdw */
5086 I915_WRITE(CHICKEN_PAR1_1,
5087 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5089 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5090 for_each_pipe(pipe) {
5091 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5092 I915_READ(CHICKEN_PIPESL_1(pipe)) |
5093 BDW_DPRS_MASK_VBLANK_SRD);
5096 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5097 * workaround for for a possible hang in the unlikely event a TLB
5098 * invalidation occurs during a PSD flush.
5100 I915_WRITE(HDC_CHICKEN0,
5101 I915_READ(HDC_CHICKEN0) |
5102 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5104 /* WaVSRefCountFullforceMissDisable:bdw */
5105 /* WaDSRefCountFullforceMissDisable:bdw */
5106 I915_WRITE(GEN7_FF_THREAD_MODE,
5107 I915_READ(GEN7_FF_THREAD_MODE) &
5108 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5111 * BSpec recommends 8x4 when MSAA is used,
5112 * however in practice 16x4 seems fastest.
5114 * Note that PS/WM thread counts depend on the WIZ hashing
5115 * disable bit, which we don't touch here, but it's good
5116 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5118 I915_WRITE(GEN7_GT_MODE,
5119 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5121 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5122 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5124 /* WaDisableSDEUnitClockGating:bdw */
5125 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5126 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5128 /* Wa4x4STCOptimizationDisable:bdw */
5129 I915_WRITE(CACHE_MODE_1,
5130 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
5133 static void haswell_init_clock_gating(struct drm_device *dev)
5135 struct drm_i915_private *dev_priv = dev->dev_private;
5137 ilk_init_lp_watermarks(dev);
5139 /* L3 caching of data atomics doesn't work -- disable it. */
5140 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5141 I915_WRITE(HSW_ROW_CHICKEN3,
5142 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5144 /* This is required by WaCatErrorRejectionIssue:hsw */
5145 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5146 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5147 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5149 /* WaVSRefCountFullforceMissDisable:hsw */
5150 I915_WRITE(GEN7_FF_THREAD_MODE,
5151 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5153 /* WaDisable_RenderCache_OperationalFlush:hsw */
5154 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5156 /* enable HiZ Raw Stall Optimization */
5157 I915_WRITE(CACHE_MODE_0_GEN7,
5158 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5160 /* WaDisable4x2SubspanOptimization:hsw */
5161 I915_WRITE(CACHE_MODE_1,
5162 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5165 * BSpec recommends 8x4 when MSAA is used,
5166 * however in practice 16x4 seems fastest.
5168 * Note that PS/WM thread counts depend on the WIZ hashing
5169 * disable bit, which we don't touch here, but it's good
5170 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5172 I915_WRITE(GEN7_GT_MODE,
5173 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5175 /* WaSwitchSolVfFArbitrationPriority:hsw */
5176 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5178 /* WaRsPkgCStateDisplayPMReq:hsw */
5179 I915_WRITE(CHICKEN_PAR1_1,
5180 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5182 lpt_init_clock_gating(dev);
5185 static void ivybridge_init_clock_gating(struct drm_device *dev)
5187 struct drm_i915_private *dev_priv = dev->dev_private;
5190 ilk_init_lp_watermarks(dev);
5192 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5194 /* WaDisableEarlyCull:ivb */
5195 I915_WRITE(_3D_CHICKEN3,
5196 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5198 /* WaDisableBackToBackFlipFix:ivb */
5199 I915_WRITE(IVB_CHICKEN3,
5200 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5201 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5203 /* WaDisablePSDDualDispatchEnable:ivb */
5204 if (IS_IVB_GT1(dev))
5205 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5206 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5208 /* WaDisable_RenderCache_OperationalFlush:ivb */
5209 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5211 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5212 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5213 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5215 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5216 I915_WRITE(GEN7_L3CNTLREG1,
5217 GEN7_WA_FOR_GEN7_L3_CONTROL);
5218 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5219 GEN7_WA_L3_CHICKEN_MODE);
5220 if (IS_IVB_GT1(dev))
5221 I915_WRITE(GEN7_ROW_CHICKEN2,
5222 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5224 /* must write both registers */
5225 I915_WRITE(GEN7_ROW_CHICKEN2,
5226 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5227 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5228 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5231 /* WaForceL3Serialization:ivb */
5232 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5233 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5236 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5237 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5239 I915_WRITE(GEN6_UCGCTL2,
5240 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5242 /* This is required by WaCatErrorRejectionIssue:ivb */
5243 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5244 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5245 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5247 g4x_disable_trickle_feed(dev);
5249 gen7_setup_fixed_func_scheduler(dev_priv);
5251 if (0) { /* causes HiZ corruption on ivb:gt1 */
5252 /* enable HiZ Raw Stall Optimization */
5253 I915_WRITE(CACHE_MODE_0_GEN7,
5254 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5257 /* WaDisable4x2SubspanOptimization:ivb */
5258 I915_WRITE(CACHE_MODE_1,
5259 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5262 * BSpec recommends 8x4 when MSAA is used,
5263 * however in practice 16x4 seems fastest.
5265 * Note that PS/WM thread counts depend on the WIZ hashing
5266 * disable bit, which we don't touch here, but it's good
5267 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5269 I915_WRITE(GEN7_GT_MODE,
5270 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5272 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5273 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5274 snpcr |= GEN6_MBC_SNPCR_MED;
5275 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5277 if (!HAS_PCH_NOP(dev))
5278 cpt_init_clock_gating(dev);
5280 gen6_check_mch_setup(dev);
5283 static void valleyview_init_clock_gating(struct drm_device *dev)
5285 struct drm_i915_private *dev_priv = dev->dev_private;
5288 mutex_lock(&dev_priv->rps.hw_lock);
5289 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5290 mutex_unlock(&dev_priv->rps.hw_lock);
5291 switch ((val >> 6) & 3) {
5294 dev_priv->mem_freq = 800;
5297 dev_priv->mem_freq = 1066;
5300 dev_priv->mem_freq = 1333;
5303 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5305 dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
5306 DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz",
5307 dev_priv->vlv_cdclk_freq);
5309 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5311 /* WaDisableEarlyCull:vlv */
5312 I915_WRITE(_3D_CHICKEN3,
5313 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5315 /* WaDisableBackToBackFlipFix:vlv */
5316 I915_WRITE(IVB_CHICKEN3,
5317 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5318 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5320 /* WaPsdDispatchEnable:vlv */
5321 /* WaDisablePSDDualDispatchEnable:vlv */
5322 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5323 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5324 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5326 /* WaDisable_RenderCache_OperationalFlush:vlv */
5327 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5329 /* WaForceL3Serialization:vlv */
5330 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5331 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5333 /* WaDisableDopClockGating:vlv */
5334 I915_WRITE(GEN7_ROW_CHICKEN2,
5335 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5337 /* This is required by WaCatErrorRejectionIssue:vlv */
5338 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5339 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5340 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5342 gen7_setup_fixed_func_scheduler(dev_priv);
5345 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5346 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5348 I915_WRITE(GEN6_UCGCTL2,
5349 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5351 /* WaDisableL3Bank2xClockGate:vlv */
5352 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5354 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5357 * BSpec says this must be set, even though
5358 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5360 I915_WRITE(CACHE_MODE_1,
5361 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5364 * WaIncreaseL3CreditsForVLVB0:vlv
5365 * This is the hardware default actually.
5367 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5370 * WaDisableVLVClockGating_VBIIssue:vlv
5371 * Disable clock gating on th GCFG unit to prevent a delay
5372 * in the reporting of vblank events.
5374 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5377 static void cherryview_init_clock_gating(struct drm_device *dev)
5379 struct drm_i915_private *dev_priv = dev->dev_private;
5381 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5383 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5385 /* WaDisablePartialInstShootdown:chv */
5386 I915_WRITE(GEN8_ROW_CHICKEN,
5387 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5389 /* WaDisableThreadStallDopClockGating:chv */
5390 I915_WRITE(GEN8_ROW_CHICKEN,
5391 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5393 /* WaVSRefCountFullforceMissDisable:chv */
5394 /* WaDSRefCountFullforceMissDisable:chv */
5395 I915_WRITE(GEN7_FF_THREAD_MODE,
5396 I915_READ(GEN7_FF_THREAD_MODE) &
5397 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5399 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5400 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5401 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5403 /* WaDisableCSUnitClockGating:chv */
5404 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5405 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5407 /* WaDisableSDEUnitClockGating:chv */
5408 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5409 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5411 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5412 I915_WRITE(HALF_SLICE_CHICKEN3,
5413 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5415 /* WaDisableGunitClockGating:chv (pre-production hw) */
5416 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5419 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5420 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5421 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5423 /* WaDisableDopClockGating:chv (pre-production hw) */
5424 I915_WRITE(GEN7_ROW_CHICKEN2,
5425 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5426 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5427 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
5430 static void g4x_init_clock_gating(struct drm_device *dev)
5432 struct drm_i915_private *dev_priv = dev->dev_private;
5433 uint32_t dspclk_gate;
5435 I915_WRITE(RENCLK_GATE_D1, 0);
5436 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5437 GS_UNIT_CLOCK_GATE_DISABLE |
5438 CL_UNIT_CLOCK_GATE_DISABLE);
5439 I915_WRITE(RAMCLK_GATE_D, 0);
5440 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5441 OVRUNIT_CLOCK_GATE_DISABLE |
5442 OVCUNIT_CLOCK_GATE_DISABLE;
5444 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5445 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5447 /* WaDisableRenderCachePipelinedFlush */
5448 I915_WRITE(CACHE_MODE_0,
5449 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5451 /* WaDisable_RenderCache_OperationalFlush:g4x */
5452 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5454 g4x_disable_trickle_feed(dev);
5457 static void crestline_init_clock_gating(struct drm_device *dev)
5459 struct drm_i915_private *dev_priv = dev->dev_private;
5461 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5462 I915_WRITE(RENCLK_GATE_D2, 0);
5463 I915_WRITE(DSPCLK_GATE_D, 0);
5464 I915_WRITE(RAMCLK_GATE_D, 0);
5465 I915_WRITE16(DEUC, 0);
5466 I915_WRITE(MI_ARB_STATE,
5467 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5469 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5470 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5473 static void broadwater_init_clock_gating(struct drm_device *dev)
5475 struct drm_i915_private *dev_priv = dev->dev_private;
5477 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5478 I965_RCC_CLOCK_GATE_DISABLE |
5479 I965_RCPB_CLOCK_GATE_DISABLE |
5480 I965_ISC_CLOCK_GATE_DISABLE |
5481 I965_FBC_CLOCK_GATE_DISABLE);
5482 I915_WRITE(RENCLK_GATE_D2, 0);
5483 I915_WRITE(MI_ARB_STATE,
5484 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5486 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5487 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5490 static void gen3_init_clock_gating(struct drm_device *dev)
5492 struct drm_i915_private *dev_priv = dev->dev_private;
5493 u32 dstate = I915_READ(D_STATE);
5495 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5496 DSTATE_DOT_CLOCK_GATING;
5497 I915_WRITE(D_STATE, dstate);
5499 if (IS_PINEVIEW(dev))
5500 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5502 /* IIR "flip pending" means done if this bit is set */
5503 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5506 static void i85x_init_clock_gating(struct drm_device *dev)
5508 struct drm_i915_private *dev_priv = dev->dev_private;
5510 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5513 static void i830_init_clock_gating(struct drm_device *dev)
5515 struct drm_i915_private *dev_priv = dev->dev_private;
5517 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5520 void intel_init_clock_gating(struct drm_device *dev)
5522 struct drm_i915_private *dev_priv = dev->dev_private;
5524 dev_priv->display.init_clock_gating(dev);
5527 void intel_suspend_hw(struct drm_device *dev)
5529 if (HAS_PCH_LPT(dev))
5530 lpt_suspend_hw(dev);
5533 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
5535 i < (power_domains)->power_well_count && \
5536 ((power_well) = &(power_domains)->power_wells[i]); \
5538 if ((power_well)->domains & (domain_mask))
5540 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5541 for (i = (power_domains)->power_well_count - 1; \
5542 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5544 if ((power_well)->domains & (domain_mask))
5547 * We should only use the power well if we explicitly asked the hardware to
5548 * enable it, so check if it's enabled and also check if we've requested it to
5551 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
5552 struct i915_power_well *power_well)
5554 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5555 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5558 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
5559 enum intel_display_power_domain domain)
5561 struct i915_power_domains *power_domains;
5563 power_domains = &dev_priv->power_domains;
5565 return power_domains->domain_use_count[domain];
5568 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
5569 enum intel_display_power_domain domain)
5571 struct i915_power_domains *power_domains;
5572 struct i915_power_well *power_well;
5576 if (dev_priv->pm.suspended)
5579 power_domains = &dev_priv->power_domains;
5583 mutex_lock(&power_domains->lock);
5584 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5585 if (power_well->always_on)
5588 if (!power_well->ops->is_enabled(dev_priv, power_well)) {
5593 mutex_unlock(&power_domains->lock);
5599 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5600 * when not needed anymore. We have 4 registers that can request the power well
5601 * to be enabled, and it will only be disabled if none of the registers is
5602 * requesting it to be enabled.
5604 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5606 struct drm_device *dev = dev_priv->dev;
5607 unsigned long irqflags;
5610 * After we re-enable the power well, if we touch VGA register 0x3d5
5611 * we'll get unclaimed register interrupts. This stops after we write
5612 * anything to the VGA MSR register. The vgacon module uses this
5613 * register all the time, so if we unbind our driver and, as a
5614 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5615 * console_unlock(). So make here we touch the VGA MSR register, making
5616 * sure vgacon can keep working normally without triggering interrupts
5617 * and error messages.
5619 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5620 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5621 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5623 if (IS_BROADWELL(dev)) {
5624 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5625 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5626 dev_priv->de_irq_mask[PIPE_B]);
5627 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5628 ~dev_priv->de_irq_mask[PIPE_B] |
5630 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5631 dev_priv->de_irq_mask[PIPE_C]);
5632 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5633 ~dev_priv->de_irq_mask[PIPE_C] |
5635 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5636 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5640 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
5641 struct i915_power_well *power_well, bool enable)
5643 bool is_enabled, enable_requested;
5646 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5647 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5648 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5651 if (!enable_requested)
5652 I915_WRITE(HSW_PWR_WELL_DRIVER,
5653 HSW_PWR_WELL_ENABLE_REQUEST);
5656 DRM_DEBUG_KMS("Enabling power well\n");
5657 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5658 HSW_PWR_WELL_STATE_ENABLED), 20))
5659 DRM_ERROR("Timeout enabling power well\n");
5662 hsw_power_well_post_enable(dev_priv);
5664 if (enable_requested) {
5665 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5666 POSTING_READ(HSW_PWR_WELL_DRIVER);
5667 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5672 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5673 struct i915_power_well *power_well)
5675 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5678 * We're taking over the BIOS, so clear any requests made by it since
5679 * the driver is in charge now.
5681 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5682 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5685 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5686 struct i915_power_well *power_well)
5688 hsw_set_power_well(dev_priv, power_well, true);
5691 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5692 struct i915_power_well *power_well)
5694 hsw_set_power_well(dev_priv, power_well, false);
5697 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5698 struct i915_power_well *power_well)
5702 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5703 struct i915_power_well *power_well)
5708 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5709 struct i915_power_well *power_well, bool enable)
5711 enum punit_power_well power_well_id = power_well->data;
5716 mask = PUNIT_PWRGT_MASK(power_well_id);
5717 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
5718 PUNIT_PWRGT_PWR_GATE(power_well_id);
5720 mutex_lock(&dev_priv->rps.hw_lock);
5723 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
5728 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
5731 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
5733 if (wait_for(COND, 100))
5734 DRM_ERROR("timout setting power well state %08x (%08x)\n",
5736 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
5741 mutex_unlock(&dev_priv->rps.hw_lock);
5744 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
5745 struct i915_power_well *power_well)
5747 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
5750 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
5751 struct i915_power_well *power_well)
5753 vlv_set_power_well(dev_priv, power_well, true);
5756 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
5757 struct i915_power_well *power_well)
5759 vlv_set_power_well(dev_priv, power_well, false);
5762 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
5763 struct i915_power_well *power_well)
5765 int power_well_id = power_well->data;
5766 bool enabled = false;
5771 mask = PUNIT_PWRGT_MASK(power_well_id);
5772 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
5774 mutex_lock(&dev_priv->rps.hw_lock);
5776 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
5778 * We only ever set the power-on and power-gate states, anything
5779 * else is unexpected.
5781 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
5782 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
5787 * A transient state at this point would mean some unexpected party
5788 * is poking at the power controls too.
5790 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
5791 WARN_ON(ctrl != state);
5793 mutex_unlock(&dev_priv->rps.hw_lock);
5798 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
5799 struct i915_power_well *power_well)
5801 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5803 vlv_set_power_well(dev_priv, power_well, true);
5805 spin_lock_irq(&dev_priv->irq_lock);
5806 valleyview_enable_display_irqs(dev_priv);
5807 spin_unlock_irq(&dev_priv->irq_lock);
5810 * During driver initialization/resume we can avoid restoring the
5811 * part of the HW/SW state that will be inited anyway explicitly.
5813 if (dev_priv->power_domains.initializing)
5816 intel_hpd_init(dev_priv->dev);
5818 i915_redisable_vga_power_on(dev_priv->dev);
5821 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
5822 struct i915_power_well *power_well)
5824 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5826 spin_lock_irq(&dev_priv->irq_lock);
5827 valleyview_disable_display_irqs(dev_priv);
5828 spin_unlock_irq(&dev_priv->irq_lock);
5830 vlv_set_power_well(dev_priv, power_well, false);
5833 static void check_power_well_state(struct drm_i915_private *dev_priv,
5834 struct i915_power_well *power_well)
5836 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
5838 if (power_well->always_on || !i915.disable_power_well) {
5845 if (enabled != (power_well->count > 0))
5851 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
5852 power_well->name, power_well->always_on, enabled,
5853 power_well->count, i915.disable_power_well);
5856 void intel_display_power_get(struct drm_i915_private *dev_priv,
5857 enum intel_display_power_domain domain)
5859 struct i915_power_domains *power_domains;
5860 struct i915_power_well *power_well;
5863 intel_runtime_pm_get(dev_priv);
5865 power_domains = &dev_priv->power_domains;
5867 mutex_lock(&power_domains->lock);
5869 for_each_power_well(i, power_well, BIT(domain), power_domains) {
5870 if (!power_well->count++) {
5871 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
5872 power_well->ops->enable(dev_priv, power_well);
5875 check_power_well_state(dev_priv, power_well);
5878 power_domains->domain_use_count[domain]++;
5880 mutex_unlock(&power_domains->lock);
5883 void intel_display_power_put(struct drm_i915_private *dev_priv,
5884 enum intel_display_power_domain domain)
5886 struct i915_power_domains *power_domains;
5887 struct i915_power_well *power_well;
5890 power_domains = &dev_priv->power_domains;
5892 mutex_lock(&power_domains->lock);
5894 WARN_ON(!power_domains->domain_use_count[domain]);
5895 power_domains->domain_use_count[domain]--;
5897 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5898 WARN_ON(!power_well->count);
5900 if (!--power_well->count && i915.disable_power_well) {
5901 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
5902 power_well->ops->disable(dev_priv, power_well);
5905 check_power_well_state(dev_priv, power_well);
5908 mutex_unlock(&power_domains->lock);
5910 intel_runtime_pm_put(dev_priv);
5913 static struct i915_power_domains *hsw_pwr;
5915 /* Display audio driver power well request */
5916 void i915_request_power_well(void)
5918 struct drm_i915_private *dev_priv;
5920 if (WARN_ON(!hsw_pwr))
5923 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5925 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
5927 EXPORT_SYMBOL_GPL(i915_request_power_well);
5929 /* Display audio driver power well release */
5930 void i915_release_power_well(void)
5932 struct drm_i915_private *dev_priv;
5934 if (WARN_ON(!hsw_pwr))
5937 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5939 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
5941 EXPORT_SYMBOL_GPL(i915_release_power_well);
5943 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
5945 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
5946 BIT(POWER_DOMAIN_PIPE_A) | \
5947 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
5948 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
5949 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
5950 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5951 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5952 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5953 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5954 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
5955 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
5956 BIT(POWER_DOMAIN_PORT_CRT) | \
5957 BIT(POWER_DOMAIN_INIT))
5958 #define HSW_DISPLAY_POWER_DOMAINS ( \
5959 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
5960 BIT(POWER_DOMAIN_INIT))
5962 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
5963 HSW_ALWAYS_ON_POWER_DOMAINS | \
5964 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
5965 #define BDW_DISPLAY_POWER_DOMAINS ( \
5966 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
5967 BIT(POWER_DOMAIN_INIT))
5969 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
5970 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
5972 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
5973 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5974 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5975 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5976 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5977 BIT(POWER_DOMAIN_PORT_CRT) | \
5978 BIT(POWER_DOMAIN_INIT))
5980 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
5981 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5982 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5983 BIT(POWER_DOMAIN_INIT))
5985 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
5986 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5987 BIT(POWER_DOMAIN_INIT))
5989 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
5990 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5991 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5992 BIT(POWER_DOMAIN_INIT))
5994 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
5995 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5996 BIT(POWER_DOMAIN_INIT))
5998 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
5999 .sync_hw = i9xx_always_on_power_well_noop,
6000 .enable = i9xx_always_on_power_well_noop,
6001 .disable = i9xx_always_on_power_well_noop,
6002 .is_enabled = i9xx_always_on_power_well_enabled,
6005 static struct i915_power_well i9xx_always_on_power_well[] = {
6007 .name = "always-on",
6009 .domains = POWER_DOMAIN_MASK,
6010 .ops = &i9xx_always_on_power_well_ops,
6014 static const struct i915_power_well_ops hsw_power_well_ops = {
6015 .sync_hw = hsw_power_well_sync_hw,
6016 .enable = hsw_power_well_enable,
6017 .disable = hsw_power_well_disable,
6018 .is_enabled = hsw_power_well_enabled,
6021 static struct i915_power_well hsw_power_wells[] = {
6023 .name = "always-on",
6025 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6026 .ops = &i9xx_always_on_power_well_ops,
6030 .domains = HSW_DISPLAY_POWER_DOMAINS,
6031 .ops = &hsw_power_well_ops,
6035 static struct i915_power_well bdw_power_wells[] = {
6037 .name = "always-on",
6039 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6040 .ops = &i9xx_always_on_power_well_ops,
6044 .domains = BDW_DISPLAY_POWER_DOMAINS,
6045 .ops = &hsw_power_well_ops,
6049 static const struct i915_power_well_ops vlv_display_power_well_ops = {
6050 .sync_hw = vlv_power_well_sync_hw,
6051 .enable = vlv_display_power_well_enable,
6052 .disable = vlv_display_power_well_disable,
6053 .is_enabled = vlv_power_well_enabled,
6056 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6057 .sync_hw = vlv_power_well_sync_hw,
6058 .enable = vlv_power_well_enable,
6059 .disable = vlv_power_well_disable,
6060 .is_enabled = vlv_power_well_enabled,
6063 static struct i915_power_well vlv_power_wells[] = {
6065 .name = "always-on",
6067 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6068 .ops = &i9xx_always_on_power_well_ops,
6072 .domains = VLV_DISPLAY_POWER_DOMAINS,
6073 .data = PUNIT_POWER_WELL_DISP2D,
6074 .ops = &vlv_display_power_well_ops,
6077 .name = "dpio-common",
6078 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6079 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6080 .ops = &vlv_dpio_power_well_ops,
6083 .name = "dpio-tx-b-01",
6084 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6085 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6086 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6087 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6088 .ops = &vlv_dpio_power_well_ops,
6089 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6092 .name = "dpio-tx-b-23",
6093 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6094 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6095 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6096 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6097 .ops = &vlv_dpio_power_well_ops,
6098 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6101 .name = "dpio-tx-c-01",
6102 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6103 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6104 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6105 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6106 .ops = &vlv_dpio_power_well_ops,
6107 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6110 .name = "dpio-tx-c-23",
6111 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6112 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6113 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6114 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6115 .ops = &vlv_dpio_power_well_ops,
6116 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6120 #define set_power_wells(power_domains, __power_wells) ({ \
6121 (power_domains)->power_wells = (__power_wells); \
6122 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6125 int intel_power_domains_init(struct drm_i915_private *dev_priv)
6127 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6129 mutex_init(&power_domains->lock);
6132 * The enabling order will be from lower to higher indexed wells,
6133 * the disabling order is reversed.
6135 if (IS_HASWELL(dev_priv->dev)) {
6136 set_power_wells(power_domains, hsw_power_wells);
6137 hsw_pwr = power_domains;
6138 } else if (IS_BROADWELL(dev_priv->dev)) {
6139 set_power_wells(power_domains, bdw_power_wells);
6140 hsw_pwr = power_domains;
6141 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6142 set_power_wells(power_domains, vlv_power_wells);
6144 set_power_wells(power_domains, i9xx_always_on_power_well);
6150 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
6155 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
6157 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6158 struct i915_power_well *power_well;
6161 mutex_lock(&power_domains->lock);
6162 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
6163 power_well->ops->sync_hw(dev_priv, power_well);
6164 mutex_unlock(&power_domains->lock);
6167 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
6169 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6171 power_domains->initializing = true;
6172 /* For now, we need the power well to be always enabled. */
6173 intel_display_set_init_power(dev_priv, true);
6174 intel_power_domains_resume(dev_priv);
6175 power_domains->initializing = false;
6178 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6180 intel_runtime_pm_get(dev_priv);
6183 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6185 intel_runtime_pm_put(dev_priv);
6188 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6190 struct drm_device *dev = dev_priv->dev;
6191 struct device *device = &dev->pdev->dev;
6193 if (!HAS_RUNTIME_PM(dev))
6196 pm_runtime_get_sync(device);
6197 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6200 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6202 struct drm_device *dev = dev_priv->dev;
6203 struct device *device = &dev->pdev->dev;
6205 if (!HAS_RUNTIME_PM(dev))
6208 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6209 pm_runtime_get_noresume(device);
6212 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6214 struct drm_device *dev = dev_priv->dev;
6215 struct device *device = &dev->pdev->dev;
6217 if (!HAS_RUNTIME_PM(dev))
6220 pm_runtime_mark_last_busy(device);
6221 pm_runtime_put_autosuspend(device);
6224 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6226 struct drm_device *dev = dev_priv->dev;
6227 struct device *device = &dev->pdev->dev;
6229 if (!HAS_RUNTIME_PM(dev))
6232 pm_runtime_set_active(device);
6235 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6238 if (!intel_enable_rc6(dev)) {
6239 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6243 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6244 pm_runtime_mark_last_busy(device);
6245 pm_runtime_use_autosuspend(device);
6247 pm_runtime_put_autosuspend(device);
6250 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6252 struct drm_device *dev = dev_priv->dev;
6253 struct device *device = &dev->pdev->dev;
6255 if (!HAS_RUNTIME_PM(dev))
6258 if (!intel_enable_rc6(dev))
6261 /* Make sure we're not suspended first. */
6262 pm_runtime_get_sync(device);
6263 pm_runtime_disable(device);
6266 /* Set up chip specific power management-related functions */
6267 void intel_init_pm(struct drm_device *dev)
6269 struct drm_i915_private *dev_priv = dev->dev_private;
6272 if (INTEL_INFO(dev)->gen >= 7) {
6273 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6274 dev_priv->display.enable_fbc = gen7_enable_fbc;
6275 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6276 } else if (INTEL_INFO(dev)->gen >= 5) {
6277 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6278 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6279 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6280 } else if (IS_GM45(dev)) {
6281 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6282 dev_priv->display.enable_fbc = g4x_enable_fbc;
6283 dev_priv->display.disable_fbc = g4x_disable_fbc;
6285 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6286 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6287 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6289 /* This value was pulled out of someone's hat */
6290 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6295 if (IS_PINEVIEW(dev))
6296 i915_pineview_get_mem_freq(dev);
6297 else if (IS_GEN5(dev))
6298 i915_ironlake_get_mem_freq(dev);
6300 /* For FIFO watermark updates */
6301 if (HAS_PCH_SPLIT(dev)) {
6302 ilk_setup_wm_latency(dev);
6304 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6305 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6306 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6307 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6308 dev_priv->display.update_wm = ilk_update_wm;
6309 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6311 DRM_DEBUG_KMS("Failed to read display plane latency. "
6316 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6317 else if (IS_GEN6(dev))
6318 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6319 else if (IS_IVYBRIDGE(dev))
6320 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6321 else if (IS_HASWELL(dev))
6322 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6323 else if (INTEL_INFO(dev)->gen == 8)
6324 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6325 } else if (IS_CHERRYVIEW(dev)) {
6326 dev_priv->display.update_wm = valleyview_update_wm;
6327 dev_priv->display.init_clock_gating =
6328 cherryview_init_clock_gating;
6329 } else if (IS_VALLEYVIEW(dev)) {
6330 dev_priv->display.update_wm = valleyview_update_wm;
6331 dev_priv->display.init_clock_gating =
6332 valleyview_init_clock_gating;
6333 } else if (IS_PINEVIEW(dev)) {
6334 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6337 dev_priv->mem_freq)) {
6338 DRM_INFO("failed to find known CxSR latency "
6339 "(found ddr%s fsb freq %d, mem freq %d), "
6341 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6342 dev_priv->fsb_freq, dev_priv->mem_freq);
6343 /* Disable CxSR and never update its watermark again */
6344 pineview_disable_cxsr(dev);
6345 dev_priv->display.update_wm = NULL;
6347 dev_priv->display.update_wm = pineview_update_wm;
6348 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6349 } else if (IS_G4X(dev)) {
6350 dev_priv->display.update_wm = g4x_update_wm;
6351 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6352 } else if (IS_GEN4(dev)) {
6353 dev_priv->display.update_wm = i965_update_wm;
6354 if (IS_CRESTLINE(dev))
6355 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6356 else if (IS_BROADWATER(dev))
6357 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6358 } else if (IS_GEN3(dev)) {
6359 dev_priv->display.update_wm = i9xx_update_wm;
6360 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6361 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6362 } else if (IS_GEN2(dev)) {
6363 if (INTEL_INFO(dev)->num_pipes == 1) {
6364 dev_priv->display.update_wm = i845_update_wm;
6365 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6367 dev_priv->display.update_wm = i9xx_update_wm;
6368 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6371 if (IS_I85X(dev) || IS_I865G(dev))
6372 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6374 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6376 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6380 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6382 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6384 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6385 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6389 I915_WRITE(GEN6_PCODE_DATA, *val);
6390 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6392 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6394 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6398 *val = I915_READ(GEN6_PCODE_DATA);
6399 I915_WRITE(GEN6_PCODE_DATA, 0);
6404 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6406 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6408 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6409 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6413 I915_WRITE(GEN6_PCODE_DATA, val);
6414 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6416 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6418 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6422 I915_WRITE(GEN6_PCODE_DATA, 0);
6427 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6432 switch (dev_priv->mem_freq) {
6446 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6449 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6454 switch (dev_priv->mem_freq) {
6468 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6471 void intel_pm_setup(struct drm_device *dev)
6473 struct drm_i915_private *dev_priv = dev->dev_private;
6475 mutex_init(&dev_priv->rps.hw_lock);
6477 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6478 intel_gen6_powersave_work);
6480 dev_priv->pm.suspended = false;
6481 dev_priv->pm.irqs_disabled = false;