drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/i915_powerwell.h>
  35 #include <linux/pm_runtime.h>
  36
  37 /**
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  59  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  60  * during in-memory transfers and, therefore, reduce the power packet.
  61  *
  62  * The benefits of FBC are mostly visible with solid backgrounds and
  63  * variation-less patterns.
  64  *
  65  * FBC-related functionality can be enabled by the means of the
  66  * i915.i915_enable_fbc parameter
  67  */
  68
  69 static void i8xx_disable_fbc(struct drm_device *dev)
  70 {
  71         struct drm_i915_private *dev_priv = dev->dev_private;
  72         u32 fbc_ctl;
  73
  74         /* Disable compression */
  75         fbc_ctl = I915_READ(FBC_CONTROL);
  76         if ((fbc_ctl & FBC_CTL_EN) == 0)
  77                 return;
  78
  79         fbc_ctl &= ~FBC_CTL_EN;
  80         I915_WRITE(FBC_CONTROL, fbc_ctl);
  81
  82         /* Wait for compressing bit to clear */
  83         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  84                 DRM_DEBUG_KMS("FBC idle timed out\n");
  85                 return;
  86         }
  87
  88         DRM_DEBUG_KMS("disabled FBC\n");
  89 }
  90
  91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
  92 {
  93         struct drm_device *dev = crtc->dev;
  94         struct drm_i915_private *dev_priv = dev->dev_private;
  95         struct drm_framebuffer *fb = crtc->primary->fb;
  96         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  97         struct drm_i915_gem_object *obj = intel_fb->obj;
  98         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  99         int cfb_pitch;
 100         int i;
 101         u32 fbc_ctl;
 102
 103         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
 104         if (fb->pitches[0] < cfb_pitch)
 105                 cfb_pitch = fb->pitches[0];
 106
 107         /* FBC_CTL wants 32B or 64B units */
 108         if (IS_GEN2(dev))
 109                 cfb_pitch = (cfb_pitch / 32) - 1;
 110         else
 111                 cfb_pitch = (cfb_pitch / 64) - 1;
 112
 113         /* Clear old tags */
 114         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 115                 I915_WRITE(FBC_TAG + (i * 4), 0);
 116
 117         if (IS_GEN4(dev)) {
 118                 u32 fbc_ctl2;
 119
 120                 /* Set it up... */
 121                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 122                 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
 123                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 124                 I915_WRITE(FBC_FENCE_OFF, crtc->y);
 125         }
 126
 127         /* enable it... */
 128         fbc_ctl = I915_READ(FBC_CONTROL);
 129         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 130         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 131         if (IS_I945GM(dev))
 132                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 133         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 134         fbc_ctl |= obj->fence_reg;
 135         I915_WRITE(FBC_CONTROL, fbc_ctl);
 136
 137         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
 138                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 139 }
 140
 141 static bool i8xx_fbc_enabled(struct drm_device *dev)
 142 {
 143         struct drm_i915_private *dev_priv = dev->dev_private;
 144
 145         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 146 }
 147
 148 static void g4x_enable_fbc(struct drm_crtc *crtc)
 149 {
 150         struct drm_device *dev = crtc->dev;
 151         struct drm_i915_private *dev_priv = dev->dev_private;
 152         struct drm_framebuffer *fb = crtc->primary->fb;
 153         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 154         struct drm_i915_gem_object *obj = intel_fb->obj;
 155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 156         u32 dpfc_ctl;
 157
 158         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
 159         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 160                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 161         else
 162                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 163         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 164
 165         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 166
 167         /* enable it... */
 168         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 169
 170         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 171 }
 172
 173 static void g4x_disable_fbc(struct drm_device *dev)
 174 {
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176         u32 dpfc_ctl;
 177
 178         /* Disable compression */
 179         dpfc_ctl = I915_READ(DPFC_CONTROL);
 180         if (dpfc_ctl & DPFC_CTL_EN) {
 181                 dpfc_ctl &= ~DPFC_CTL_EN;
 182                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 183
 184                 DRM_DEBUG_KMS("disabled FBC\n");
 185         }
 186 }
 187
 188 static bool g4x_fbc_enabled(struct drm_device *dev)
 189 {
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191
 192         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 193 }
 194
 195 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 196 {
 197         struct drm_i915_private *dev_priv = dev->dev_private;
 198         u32 blt_ecoskpd;
 199
 200         /* Make sure blitter notifies FBC of writes */
 201
 202         /* Blitter is part of Media powerwell on VLV. No impact of
 203          * his param in other platforms for now */
 204         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
 205
 206         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 207         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 208                 GEN6_BLITTER_LOCK_SHIFT;
 209         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 210         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 211         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 212         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 213                          GEN6_BLITTER_LOCK_SHIFT);
 214         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 215         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 216
 217         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
 218 }
 219
 220 static void ironlake_enable_fbc(struct drm_crtc *crtc)
 221 {
 222         struct drm_device *dev = crtc->dev;
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         struct drm_framebuffer *fb = crtc->primary->fb;
 225         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 226         struct drm_i915_gem_object *obj = intel_fb->obj;
 227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 228         u32 dpfc_ctl;
 229
 230         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
 231         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 232                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 233         else
 234                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 235         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 236         if (IS_GEN5(dev))
 237                 dpfc_ctl |= obj->fence_reg;
 238
 239         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 240         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 241         /* enable it... */
 242         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 243
 244         if (IS_GEN6(dev)) {
 245                 I915_WRITE(SNB_DPFC_CTL_SA,
 246                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 247                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 248                 sandybridge_blit_fbc_update(dev);
 249         }
 250
 251         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 252 }
 253
 254 static void ironlake_disable_fbc(struct drm_device *dev)
 255 {
 256         struct drm_i915_private *dev_priv = dev->dev_private;
 257         u32 dpfc_ctl;
 258
 259         /* Disable compression */
 260         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 261         if (dpfc_ctl & DPFC_CTL_EN) {
 262                 dpfc_ctl &= ~DPFC_CTL_EN;
 263                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 264
 265                 DRM_DEBUG_KMS("disabled FBC\n");
 266         }
 267 }
 268
 269 static bool ironlake_fbc_enabled(struct drm_device *dev)
 270 {
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272
 273         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 274 }
 275
 276 static void gen7_enable_fbc(struct drm_crtc *crtc)
 277 {
 278         struct drm_device *dev = crtc->dev;
 279         struct drm_i915_private *dev_priv = dev->dev_private;
 280         struct drm_framebuffer *fb = crtc->primary->fb;
 281         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 282         struct drm_i915_gem_object *obj = intel_fb->obj;
 283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 284         u32 dpfc_ctl;
 285
 286         dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
 287         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 288                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 289         else
 290                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 291         dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 292
 293         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 294
 295         if (IS_IVYBRIDGE(dev)) {
 296                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 297                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 298                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 299                            ILK_FBCQ_DIS);
 300         } else {
 301                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 302                 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
 303                            I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
 304                            HSW_FBCQ_DIS);
 305         }
 306
 307         I915_WRITE(SNB_DPFC_CTL_SA,
 308                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 309         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 310
 311         sandybridge_blit_fbc_update(dev);
 312
 313         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 314 }
 315
 316 bool intel_fbc_enabled(struct drm_device *dev)
 317 {
 318         struct drm_i915_private *dev_priv = dev->dev_private;
 319
 320         if (!dev_priv->display.fbc_enabled)
 321                 return false;
 322
 323         return dev_priv->display.fbc_enabled(dev);
 324 }
 325
 326 static void intel_fbc_work_fn(struct work_struct *__work)
 327 {
 328         struct intel_fbc_work *work =
 329                 container_of(to_delayed_work(__work),
 330                              struct intel_fbc_work, work);
 331         struct drm_device *dev = work->crtc->dev;
 332         struct drm_i915_private *dev_priv = dev->dev_private;
 333
 334         mutex_lock(&dev->struct_mutex);
 335         if (work == dev_priv->fbc.fbc_work) {
 336                 /* Double check that we haven't switched fb without cancelling
 337                  * the prior work.
 338                  */
 339                 if (work->crtc->primary->fb == work->fb) {
 340                         dev_priv->display.enable_fbc(work->crtc);
 341
 342                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 343                         dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
 344                         dev_priv->fbc.y = work->crtc->y;
 345                 }
 346
 347                 dev_priv->fbc.fbc_work = NULL;
 348         }
 349         mutex_unlock(&dev->struct_mutex);
 350
 351         kfree(work);
 352 }
 353
 354 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 355 {
 356         if (dev_priv->fbc.fbc_work == NULL)
 357                 return;
 358
 359         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 360
 361         /* Synchronisation is provided by struct_mutex and checking of
 362          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 363          * entirely asynchronously.
 364          */
 365         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 366                 /* tasklet was killed before being run, clean up */
 367                 kfree(dev_priv->fbc.fbc_work);
 368
 369         /* Mark the work as no longer wanted so that if it does
 370          * wake-up (because the work was already running and waiting
 371          * for our mutex), it will discover that is no longer
 372          * necessary to run.
 373          */
 374         dev_priv->fbc.fbc_work = NULL;
 375 }
 376
 377 static void intel_enable_fbc(struct drm_crtc *crtc)
 378 {
 379         struct intel_fbc_work *work;
 380         struct drm_device *dev = crtc->dev;
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382
 383         if (!dev_priv->display.enable_fbc)
 384                 return;
 385
 386         intel_cancel_fbc_work(dev_priv);
 387
 388         work = kzalloc(sizeof(*work), GFP_KERNEL);
 389         if (work == NULL) {
 390                 DRM_ERROR("Failed to allocate FBC work structure\n");
 391                 dev_priv->display.enable_fbc(crtc);
 392                 return;
 393         }
 394
 395         work->crtc = crtc;
 396         work->fb = crtc->primary->fb;
 397         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 398
 399         dev_priv->fbc.fbc_work = work;
 400
 401         /* Delay the actual enabling to let pageflipping cease and the
 402          * display to settle before starting the compression. Note that
 403          * this delay also serves a second purpose: it allows for a
 404          * vblank to pass after disabling the FBC before we attempt
 405          * to modify the control registers.
 406          *
 407          * A more complicated solution would involve tracking vblanks
 408          * following the termination of the page-flipping sequence
 409          * and indeed performing the enable as a co-routine and not
 410          * waiting synchronously upon the vblank.
 411          *
 412          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 413          */
 414         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 415 }
 416
 417 void intel_disable_fbc(struct drm_device *dev)
 418 {
 419         struct drm_i915_private *dev_priv = dev->dev_private;
 420
 421         intel_cancel_fbc_work(dev_priv);
 422
 423         if (!dev_priv->display.disable_fbc)
 424                 return;
 425
 426         dev_priv->display.disable_fbc(dev);
 427         dev_priv->fbc.plane = -1;
 428 }
 429
 430 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 431                               enum no_fbc_reason reason)
 432 {
 433         if (dev_priv->fbc.no_fbc_reason == reason)
 434                 return false;
 435
 436         dev_priv->fbc.no_fbc_reason = reason;
 437         return true;
 438 }
 439
 440 /**
 441  * intel_update_fbc - enable/disable FBC as needed
 442  * @dev: the drm_device
 443  *
 444  * Set up the framebuffer compression hardware at mode set time.  We
 445  * enable it if possible:
 446  *   - plane A only (on pre-965)
 447  *   - no pixel mulitply/line duplication
 448  *   - no alpha buffer discard
 449  *   - no dual wide
 450  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 451  *
 452  * We can't assume that any compression will take place (worst case),
 453  * so the compressed buffer has to be the same size as the uncompressed
 454  * one.  It also must reside (along with the line length buffer) in
 455  * stolen memory.
 456  *
 457  * We need to enable/disable FBC on a global basis.
 458  */
 459 void intel_update_fbc(struct drm_device *dev)
 460 {
 461         struct drm_i915_private *dev_priv = dev->dev_private;
 462         struct drm_crtc *crtc = NULL, *tmp_crtc;
 463         struct intel_crtc *intel_crtc;
 464         struct drm_framebuffer *fb;
 465         struct intel_framebuffer *intel_fb;
 466         struct drm_i915_gem_object *obj;
 467         const struct drm_display_mode *adjusted_mode;
 468         unsigned int max_width, max_height;
 469
 470         if (!HAS_FBC(dev)) {
 471                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 472                 return;
 473         }
 474
 475         if (!i915.powersave) {
 476                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 477                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 478                 return;
 479         }
 480
 481         /*
 482          * If FBC is already on, we just have to verify that we can
 483          * keep it that way...
 484          * Need to disable if:
 485          *   - more than one pipe is active
 486          *   - changing FBC params (stride, fence, mode)
 487          *   - new fb is too large to fit in compressed buffer
 488          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 489          */
 490         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 491                 if (intel_crtc_active(tmp_crtc) &&
 492                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 493                         if (crtc) {
 494                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 495                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 496                                 goto out_disable;
 497                         }
 498                         crtc = tmp_crtc;
 499                 }
 500         }
 501
 502         if (!crtc || crtc->primary->fb == NULL) {
 503                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 504                         DRM_DEBUG_KMS("no output, disabling\n");
 505                 goto out_disable;
 506         }
 507
 508         intel_crtc = to_intel_crtc(crtc);
 509         fb = crtc->primary->fb;
 510         intel_fb = to_intel_framebuffer(fb);
 511         obj = intel_fb->obj;
 512         adjusted_mode = &intel_crtc->config.adjusted_mode;
 513
 514         if (i915.enable_fbc < 0 &&
 515             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
 516                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 517                         DRM_DEBUG_KMS("disabled per chip default\n");
 518                 goto out_disable;
 519         }
 520         if (!i915.enable_fbc) {
 521                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 522                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 523                 goto out_disable;
 524         }
 525         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 526             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 527                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 528                         DRM_DEBUG_KMS("mode incompatible with compression, "
 529                                       "disabling\n");
 530                 goto out_disable;
 531         }
 532
 533         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 534                 max_width = 4096;
 535                 max_height = 2048;
 536         } else {
 537                 max_width = 2048;
 538                 max_height = 1536;
 539         }
 540         if (intel_crtc->config.pipe_src_w > max_width ||
 541             intel_crtc->config.pipe_src_h > max_height) {
 542                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 543                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 544                 goto out_disable;
 545         }
 546         if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
 547             intel_crtc->plane != PLANE_A) {
 548                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 549                         DRM_DEBUG_KMS("plane not A, disabling compression\n");
 550                 goto out_disable;
 551         }
 552
 553         /* The use of a CPU fence is mandatory in order to detect writes
 554          * by the CPU to the scanout and trigger updates to the FBC.
 555          */
 556         if (obj->tiling_mode != I915_TILING_X ||
 557             obj->fence_reg == I915_FENCE_REG_NONE) {
 558                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 559                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 560                 goto out_disable;
 561         }
 562
 563         /* If the kernel debugger is active, always disable compression */
 564         if (in_dbg_master())
 565                 goto out_disable;
 566
 567         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 568                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 569                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 570                 goto out_disable;
 571         }
 572
 573         /* If the scanout has not changed, don't modify the FBC settings.
 574          * Note that we make the fundamental assumption that the fb->obj
 575          * cannot be unpinned (and have its GTT offset and fence revoked)
 576          * without first being decoupled from the scanout and FBC disabled.
 577          */
 578         if (dev_priv->fbc.plane == intel_crtc->plane &&
 579             dev_priv->fbc.fb_id == fb->base.id &&
 580             dev_priv->fbc.y == crtc->y)
 581                 return;
 582
 583         if (intel_fbc_enabled(dev)) {
 584                 /* We update FBC along two paths, after changing fb/crtc
 585                  * configuration (modeswitching) and after page-flipping
 586                  * finishes. For the latter, we know that not only did
 587                  * we disable the FBC at the start of the page-flip
 588                  * sequence, but also more than one vblank has passed.
 589                  *
 590                  * For the former case of modeswitching, it is possible
 591                  * to switch between two FBC valid configurations
 592                  * instantaneously so we do need to disable the FBC
 593                  * before we can modify its control registers. We also
 594                  * have to wait for the next vblank for that to take
 595                  * effect. However, since we delay enabling FBC we can
 596                  * assume that a vblank has passed since disabling and
 597                  * that we can safely alter the registers in the deferred
 598                  * callback.
 599                  *
 600                  * In the scenario that we go from a valid to invalid
 601                  * and then back to valid FBC configuration we have
 602                  * no strict enforcement that a vblank occurred since
 603                  * disabling the FBC. However, along all current pipe
 604                  * disabling paths we do need to wait for a vblank at
 605                  * some point. And we wait before enabling FBC anyway.
 606                  */
 607                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 608                 intel_disable_fbc(dev);
 609         }
 610
 611         intel_enable_fbc(crtc);
 612         dev_priv->fbc.no_fbc_reason = FBC_OK;
 613         return;
 614
 615 out_disable:
 616         /* Multiple disables should be harmless */
 617         if (intel_fbc_enabled(dev)) {
 618                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 619                 intel_disable_fbc(dev);
 620         }
 621         i915_gem_stolen_cleanup_compression(dev);
 622 }
 623
 624 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 625 {
 626         struct drm_i915_private *dev_priv = dev->dev_private;
 627         u32 tmp;
 628
 629         tmp = I915_READ(CLKCFG);
 630
 631         switch (tmp & CLKCFG_FSB_MASK) {
 632         case CLKCFG_FSB_533:
 633                 dev_priv->fsb_freq = 533; /* 133*4 */
 634                 break;
 635         case CLKCFG_FSB_800:
 636                 dev_priv->fsb_freq = 800; /* 200*4 */
 637                 break;
 638         case CLKCFG_FSB_667:
 639                 dev_priv->fsb_freq =  667; /* 167*4 */
 640                 break;
 641         case CLKCFG_FSB_400:
 642                 dev_priv->fsb_freq = 400; /* 100*4 */
 643                 break;
 644         }
 645
 646         switch (tmp & CLKCFG_MEM_MASK) {
 647         case CLKCFG_MEM_533:
 648                 dev_priv->mem_freq = 533;
 649                 break;
 650         case CLKCFG_MEM_667:
 651                 dev_priv->mem_freq = 667;
 652                 break;
 653         case CLKCFG_MEM_800:
 654                 dev_priv->mem_freq = 800;
 655                 break;
 656         }
 657
 658         /* detect pineview DDR3 setting */
 659         tmp = I915_READ(CSHRDDR3CTL);
 660         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 661 }
 662
 663 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 664 {
 665         struct drm_i915_private *dev_priv = dev->dev_private;
 666         u16 ddrpll, csipll;
 667
 668         ddrpll = I915_READ16(DDRMPLL1);
 669         csipll = I915_READ16(CSIPLL0);
 670
 671         switch (ddrpll & 0xff) {
 672         case 0xc:
 673                 dev_priv->mem_freq = 800;
 674                 break;
 675         case 0x10:
 676                 dev_priv->mem_freq = 1066;
 677                 break;
 678         case 0x14:
 679                 dev_priv->mem_freq = 1333;
 680                 break;
 681         case 0x18:
 682                 dev_priv->mem_freq = 1600;
 683                 break;
 684         default:
 685                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 686                                  ddrpll & 0xff);
 687                 dev_priv->mem_freq = 0;
 688                 break;
 689         }
 690
 691         dev_priv->ips.r_t = dev_priv->mem_freq;
 692
 693         switch (csipll & 0x3ff) {
 694         case 0x00c:
 695                 dev_priv->fsb_freq = 3200;
 696                 break;
 697         case 0x00e:
 698                 dev_priv->fsb_freq = 3733;
 699                 break;
 700         case 0x010:
 701                 dev_priv->fsb_freq = 4266;
 702                 break;
 703         case 0x012:
 704                 dev_priv->fsb_freq = 4800;
 705                 break;
 706         case 0x014:
 707                 dev_priv->fsb_freq = 5333;
 708                 break;
 709         case 0x016:
 710                 dev_priv->fsb_freq = 5866;
 711                 break;
 712         case 0x018:
 713                 dev_priv->fsb_freq = 6400;
 714                 break;
 715         default:
 716                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 717                                  csipll & 0x3ff);
 718                 dev_priv->fsb_freq = 0;
 719                 break;
 720         }
 721
 722         if (dev_priv->fsb_freq == 3200) {
 723                 dev_priv->ips.c_m = 0;
 724         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 725                 dev_priv->ips.c_m = 1;
 726         } else {
 727                 dev_priv->ips.c_m = 2;
 728         }
 729 }
 730
 731 static const struct cxsr_latency cxsr_latency_table[] = {
 732         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 733         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 734         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 735         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 736         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 737
 738         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 739         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 740         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 741         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 742         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 743
 744         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 745         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 746         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 747         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 748         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 749
 750         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 751         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 752         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 753         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 754         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 755
 756         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 757         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 758         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 759         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 760         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 761
 762         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 763         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 764         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 765         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 766         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 767 };
 768
 769 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 770                                                          int is_ddr3,
 771                                                          int fsb,
 772                                                          int mem)
 773 {
 774         const struct cxsr_latency *latency;
 775         int i;
 776
 777         if (fsb == 0 || mem == 0)
 778                 return NULL;
 779
 780         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 781                 latency = &cxsr_latency_table[i];
 782                 if (is_desktop == latency->is_desktop &&
 783                     is_ddr3 == latency->is_ddr3 &&
 784                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 785                         return latency;
 786         }
 787
 788         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 789
 790         return NULL;
 791 }
 792
 793 static void pineview_disable_cxsr(struct drm_device *dev)
 794 {
 795         struct drm_i915_private *dev_priv = dev->dev_private;
 796
 797         /* deactivate cxsr */
 798         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 799 }
 800
 801 /*
 802  * Latency for FIFO fetches is dependent on several factors:
 803  *   - memory configuration (speed, channels)
 804  *   - chipset
 805  *   - current MCH state
 806  * It can be fairly high in some situations, so here we assume a fairly
 807  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 808  * set this value too high, the FIFO will fetch frequently to stay full)
 809  * and power consumption (set it too low to save power and we might see
 810  * FIFO underruns and display "flicker").
 811  *
 812  * A value of 5us seems to be a good balance; safe for very low end
 813  * platforms but not overly aggressive on lower latency configs.
 814  */
 815 static const int latency_ns = 5000;
 816
 817 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 818 {
 819         struct drm_i915_private *dev_priv = dev->dev_private;
 820         uint32_t dsparb = I915_READ(DSPARB);
 821         int size;
 822
 823         size = dsparb & 0x7f;
 824         if (plane)
 825                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 826
 827         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 828                       plane ? "B" : "A", size);
 829
 830         return size;
 831 }
 832
 833 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 834 {
 835         struct drm_i915_private *dev_priv = dev->dev_private;
 836         uint32_t dsparb = I915_READ(DSPARB);
 837         int size;
 838
 839         size = dsparb & 0x1ff;
 840         if (plane)
 841                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 842         size >>= 1; /* Convert to cachelines */
 843
 844         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 845                       plane ? "B" : "A", size);
 846
 847         return size;
 848 }
 849
 850 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 851 {
 852         struct drm_i915_private *dev_priv = dev->dev_private;
 853         uint32_t dsparb = I915_READ(DSPARB);
 854         int size;
 855
 856         size = dsparb & 0x7f;
 857         size >>= 2; /* Convert to cachelines */
 858
 859         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 860                       plane ? "B" : "A",
 861                       size);
 862
 863         return size;
 864 }
 865
 866 /* Pineview has different values for various configs */
 867 static const struct intel_watermark_params pineview_display_wm = {
 868         PINEVIEW_DISPLAY_FIFO,
 869         PINEVIEW_MAX_WM,
 870         PINEVIEW_DFT_WM,
 871         PINEVIEW_GUARD_WM,
 872         PINEVIEW_FIFO_LINE_SIZE
 873 };
 874 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 875         PINEVIEW_DISPLAY_FIFO,
 876         PINEVIEW_MAX_WM,
 877         PINEVIEW_DFT_HPLLOFF_WM,
 878         PINEVIEW_GUARD_WM,
 879         PINEVIEW_FIFO_LINE_SIZE
 880 };
 881 static const struct intel_watermark_params pineview_cursor_wm = {
 882         PINEVIEW_CURSOR_FIFO,
 883         PINEVIEW_CURSOR_MAX_WM,
 884         PINEVIEW_CURSOR_DFT_WM,
 885         PINEVIEW_CURSOR_GUARD_WM,
 886         PINEVIEW_FIFO_LINE_SIZE,
 887 };
 888 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 889         PINEVIEW_CURSOR_FIFO,
 890         PINEVIEW_CURSOR_MAX_WM,
 891         PINEVIEW_CURSOR_DFT_WM,
 892         PINEVIEW_CURSOR_GUARD_WM,
 893         PINEVIEW_FIFO_LINE_SIZE
 894 };
 895 static const struct intel_watermark_params g4x_wm_info = {
 896         G4X_FIFO_SIZE,
 897         G4X_MAX_WM,
 898         G4X_MAX_WM,
 899         2,
 900         G4X_FIFO_LINE_SIZE,
 901 };
 902 static const struct intel_watermark_params g4x_cursor_wm_info = {
 903         I965_CURSOR_FIFO,
 904         I965_CURSOR_MAX_WM,
 905         I965_CURSOR_DFT_WM,
 906         2,
 907         G4X_FIFO_LINE_SIZE,
 908 };
 909 static const struct intel_watermark_params valleyview_wm_info = {
 910         VALLEYVIEW_FIFO_SIZE,
 911         VALLEYVIEW_MAX_WM,
 912         VALLEYVIEW_MAX_WM,
 913         2,
 914         G4X_FIFO_LINE_SIZE,
 915 };
 916 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 917         I965_CURSOR_FIFO,
 918         VALLEYVIEW_CURSOR_MAX_WM,
 919         I965_CURSOR_DFT_WM,
 920         2,
 921         G4X_FIFO_LINE_SIZE,
 922 };
 923 static const struct intel_watermark_params i965_cursor_wm_info = {
 924         I965_CURSOR_FIFO,
 925         I965_CURSOR_MAX_WM,
 926         I965_CURSOR_DFT_WM,
 927         2,
 928         I915_FIFO_LINE_SIZE,
 929 };
 930 static const struct intel_watermark_params i945_wm_info = {
 931         I945_FIFO_SIZE,
 932         I915_MAX_WM,
 933         1,
 934         2,
 935         I915_FIFO_LINE_SIZE
 936 };
 937 static const struct intel_watermark_params i915_wm_info = {
 938         I915_FIFO_SIZE,
 939         I915_MAX_WM,
 940         1,
 941         2,
 942         I915_FIFO_LINE_SIZE
 943 };
 944 static const struct intel_watermark_params i830_wm_info = {
 945         I855GM_FIFO_SIZE,
 946         I915_MAX_WM,
 947         1,
 948         2,
 949         I830_FIFO_LINE_SIZE
 950 };
 951 static const struct intel_watermark_params i845_wm_info = {
 952         I830_FIFO_SIZE,
 953         I915_MAX_WM,
 954         1,
 955         2,
 956         I830_FIFO_LINE_SIZE
 957 };
 958
 959 /**
 960  * intel_calculate_wm - calculate watermark level
 961  * @clock_in_khz: pixel clock
 962  * @wm: chip FIFO params
 963  * @pixel_size: display pixel size
 964  * @latency_ns: memory latency for the platform
 965  *
 966  * Calculate the watermark level (the level at which the display plane will
 967  * start fetching from memory again).  Each chip has a different display
 968  * FIFO size and allocation, so the caller needs to figure that out and pass
 969  * in the correct intel_watermark_params structure.
 970  *
 971  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 972  * on the pixel size.  When it reaches the watermark level, it'll start
 973  * fetching FIFO line sized based chunks from memory until the FIFO fills
 974  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 975  * will occur, and a display engine hang could result.
 976  */
 977 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 978                                         const struct intel_watermark_params *wm,
 979                                         int fifo_size,
 980                                         int pixel_size,
 981                                         unsigned long latency_ns)
 982 {
 983         long entries_required, wm_size;
 984
 985         /*
 986          * Note: we need to make sure we don't overflow for various clock &
 987          * latency values.
 988          * clocks go from a few thousand to several hundred thousand.
 989          * latency is usually a few thousand
 990          */
 991         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 992                 1000;
 993         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 994
 995         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 996
 997         wm_size = fifo_size - (entries_required + wm->guard_size);
 998
 999         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1000
1001         /* Don't promote wm_size to unsigned... */
1002         if (wm_size > (long)wm->max_wm)
1003                 wm_size = wm->max_wm;
1004         if (wm_size <= 0)
1005                 wm_size = wm->default_wm;
1006         return wm_size;
1007 }
1008
1009 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1010 {
1011         struct drm_crtc *crtc, *enabled = NULL;
1012
1013         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1014                 if (intel_crtc_active(crtc)) {
1015                         if (enabled)
1016                                 return NULL;
1017                         enabled = crtc;
1018                 }
1019         }
1020
1021         return enabled;
1022 }
1023
1024 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1025 {
1026         struct drm_device *dev = unused_crtc->dev;
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028         struct drm_crtc *crtc;
1029         const struct cxsr_latency *latency;
1030         u32 reg;
1031         unsigned long wm;
1032
1033         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1034                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1035         if (!latency) {
1036                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1037                 pineview_disable_cxsr(dev);
1038                 return;
1039         }
1040
1041         crtc = single_enabled_crtc(dev);
1042         if (crtc) {
1043                 const struct drm_display_mode *adjusted_mode;
1044                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1045                 int clock;
1046
1047                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1048                 clock = adjusted_mode->crtc_clock;
1049
1050                 /* Display SR */
1051                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1052                                         pineview_display_wm.fifo_size,
1053                                         pixel_size, latency->display_sr);
1054                 reg = I915_READ(DSPFW1);
1055                 reg &= ~DSPFW_SR_MASK;
1056                 reg |= wm << DSPFW_SR_SHIFT;
1057                 I915_WRITE(DSPFW1, reg);
1058                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1059
1060                 /* cursor SR */
1061                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1062                                         pineview_display_wm.fifo_size,
1063                                         pixel_size, latency->cursor_sr);
1064                 reg = I915_READ(DSPFW3);
1065                 reg &= ~DSPFW_CURSOR_SR_MASK;
1066                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1067                 I915_WRITE(DSPFW3, reg);
1068
1069                 /* Display HPLL off SR */
1070                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1071                                         pineview_display_hplloff_wm.fifo_size,
1072                                         pixel_size, latency->display_hpll_disable);
1073                 reg = I915_READ(DSPFW3);
1074                 reg &= ~DSPFW_HPLL_SR_MASK;
1075                 reg |= wm & DSPFW_HPLL_SR_MASK;
1076                 I915_WRITE(DSPFW3, reg);
1077
1078                 /* cursor HPLL off SR */
1079                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1080                                         pineview_display_hplloff_wm.fifo_size,
1081                                         pixel_size, latency->cursor_hpll_disable);
1082                 reg = I915_READ(DSPFW3);
1083                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1084                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1085                 I915_WRITE(DSPFW3, reg);
1086                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1087
1088                 /* activate cxsr */
1089                 I915_WRITE(DSPFW3,
1090                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1091                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1092         } else {
1093                 pineview_disable_cxsr(dev);
1094                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1095         }
1096 }
1097
1098 static bool g4x_compute_wm0(struct drm_device *dev,
1099                             int plane,
1100                             const struct intel_watermark_params *display,
1101                             int display_latency_ns,
1102                             const struct intel_watermark_params *cursor,
1103                             int cursor_latency_ns,
1104                             int *plane_wm,
1105                             int *cursor_wm)
1106 {
1107         struct drm_crtc *crtc;
1108         const struct drm_display_mode *adjusted_mode;
1109         int htotal, hdisplay, clock, pixel_size;
1110         int line_time_us, line_count;
1111         int entries, tlb_miss;
1112
1113         crtc = intel_get_crtc_for_plane(dev, plane);
1114         if (!intel_crtc_active(crtc)) {
1115                 *cursor_wm = cursor->guard_size;
1116                 *plane_wm = display->guard_size;
1117                 return false;
1118         }
1119
1120         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1121         clock = adjusted_mode->crtc_clock;
1122         htotal = adjusted_mode->crtc_htotal;
1123         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1124         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1125
1126         /* Use the small buffer method to calculate plane watermark */
1127         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1128         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1129         if (tlb_miss > 0)
1130                 entries += tlb_miss;
1131         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1132         *plane_wm = entries + display->guard_size;
1133         if (*plane_wm > (int)display->max_wm)
1134                 *plane_wm = display->max_wm;
1135
1136         /* Use the large buffer method to calculate cursor watermark */
1137         line_time_us = max(htotal * 1000 / clock, 1);
1138         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1139         entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1140         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1141         if (tlb_miss > 0)
1142                 entries += tlb_miss;
1143         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1144         *cursor_wm = entries + cursor->guard_size;
1145         if (*cursor_wm > (int)cursor->max_wm)
1146                 *cursor_wm = (int)cursor->max_wm;
1147
1148         return true;
1149 }
1150
1151 /*
1152  * Check the wm result.
1153  *
1154  * If any calculated watermark values is larger than the maximum value that
1155  * can be programmed into the associated watermark register, that watermark
1156  * must be disabled.
1157  */
1158 static bool g4x_check_srwm(struct drm_device *dev,
1159                            int display_wm, int cursor_wm,
1160                            const struct intel_watermark_params *display,
1161                            const struct intel_watermark_params *cursor)
1162 {
1163         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1164                       display_wm, cursor_wm);
1165
1166         if (display_wm > display->max_wm) {
1167                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1168                               display_wm, display->max_wm);
1169                 return false;
1170         }
1171
1172         if (cursor_wm > cursor->max_wm) {
1173                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1174                               cursor_wm, cursor->max_wm);
1175                 return false;
1176         }
1177
1178         if (!(display_wm || cursor_wm)) {
1179                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1180                 return false;
1181         }
1182
1183         return true;
1184 }
1185
1186 static bool g4x_compute_srwm(struct drm_device *dev,
1187                              int plane,
1188                              int latency_ns,
1189                              const struct intel_watermark_params *display,
1190                              const struct intel_watermark_params *cursor,
1191                              int *display_wm, int *cursor_wm)
1192 {
1193         struct drm_crtc *crtc;
1194         const struct drm_display_mode *adjusted_mode;
1195         int hdisplay, htotal, pixel_size, clock;
1196         unsigned long line_time_us;
1197         int line_count, line_size;
1198         int small, large;
1199         int entries;
1200
1201         if (!latency_ns) {
1202                 *display_wm = *cursor_wm = 0;
1203                 return false;
1204         }
1205
1206         crtc = intel_get_crtc_for_plane(dev, plane);
1207         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1208         clock = adjusted_mode->crtc_clock;
1209         htotal = adjusted_mode->crtc_htotal;
1210         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1211         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1212
1213         line_time_us = max(htotal * 1000 / clock, 1);
1214         line_count = (latency_ns / line_time_us + 1000) / 1000;
1215         line_size = hdisplay * pixel_size;
1216
1217         /* Use the minimum of the small and large buffer method for primary */
1218         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1219         large = line_count * line_size;
1220
1221         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1222         *display_wm = entries + display->guard_size;
1223
1224         /* calculate the self-refresh watermark for display cursor */
1225         entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1226         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1227         *cursor_wm = entries + cursor->guard_size;
1228
1229         return g4x_check_srwm(dev,
1230                               *display_wm, *cursor_wm,
1231                               display, cursor);
1232 }
1233
1234 static bool vlv_compute_drain_latency(struct drm_device *dev,
1235                                      int plane,
1236                                      int *plane_prec_mult,
1237                                      int *plane_dl,
1238                                      int *cursor_prec_mult,
1239                                      int *cursor_dl)
1240 {
1241         struct drm_crtc *crtc;
1242         int clock, pixel_size;
1243         int entries;
1244
1245         crtc = intel_get_crtc_for_plane(dev, plane);
1246         if (!intel_crtc_active(crtc))
1247                 return false;
1248
1249         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1250         pixel_size = crtc->primary->fb->bits_per_pixel / 8;     /* BPP */
1251
1252         entries = (clock / 1000) * pixel_size;
1253         *plane_prec_mult = (entries > 256) ?
1254                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1255         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1256                                                      pixel_size);
1257
1258         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1259         *cursor_prec_mult = (entries > 256) ?
1260                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1261         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1262
1263         return true;
1264 }
1265
1266 /*
1267  * Update drain latency registers of memory arbiter
1268  *
1269  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1270  * to be programmed. Each plane has a drain latency multiplier and a drain
1271  * latency value.
1272  */
1273
1274 static void vlv_update_drain_latency(struct drm_device *dev)
1275 {
1276         struct drm_i915_private *dev_priv = dev->dev_private;
1277         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1278         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1279         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1280                                                         either 16 or 32 */
1281
1282         /* For plane A, Cursor A */
1283         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1284                                       &cursor_prec_mult, &cursora_dl)) {
1285                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1286                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1287                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1288                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1289
1290                 I915_WRITE(VLV_DDL1, cursora_prec |
1291                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1292                                 planea_prec | planea_dl);
1293         }
1294
1295         /* For plane B, Cursor B */
1296         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1297                                       &cursor_prec_mult, &cursorb_dl)) {
1298                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1299                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1300                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1301                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1302
1303                 I915_WRITE(VLV_DDL2, cursorb_prec |
1304                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1305                                 planeb_prec | planeb_dl);
1306         }
1307 }
1308
1309 #define single_plane_enabled(mask) is_power_of_2(mask)
1310
1311 static void valleyview_update_wm(struct drm_crtc *crtc)
1312 {
1313         struct drm_device *dev = crtc->dev;
1314         static const int sr_latency_ns = 12000;
1315         struct drm_i915_private *dev_priv = dev->dev_private;
1316         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1317         int plane_sr, cursor_sr;
1318         int ignore_plane_sr, ignore_cursor_sr;
1319         unsigned int enabled = 0;
1320
1321         vlv_update_drain_latency(dev);
1322
1323         if (g4x_compute_wm0(dev, PIPE_A,
1324                             &valleyview_wm_info, latency_ns,
1325                             &valleyview_cursor_wm_info, latency_ns,
1326                             &planea_wm, &cursora_wm))
1327                 enabled |= 1 << PIPE_A;
1328
1329         if (g4x_compute_wm0(dev, PIPE_B,
1330                             &valleyview_wm_info, latency_ns,
1331                             &valleyview_cursor_wm_info, latency_ns,
1332                             &planeb_wm, &cursorb_wm))
1333                 enabled |= 1 << PIPE_B;
1334
1335         if (single_plane_enabled(enabled) &&
1336             g4x_compute_srwm(dev, ffs(enabled) - 1,
1337                              sr_latency_ns,
1338                              &valleyview_wm_info,
1339                              &valleyview_cursor_wm_info,
1340                              &plane_sr, &ignore_cursor_sr) &&
1341             g4x_compute_srwm(dev, ffs(enabled) - 1,
1342                              2*sr_latency_ns,
1343                              &valleyview_wm_info,
1344                              &valleyview_cursor_wm_info,
1345                              &ignore_plane_sr, &cursor_sr)) {
1346                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1347         } else {
1348                 I915_WRITE(FW_BLC_SELF_VLV,
1349                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1350                 plane_sr = cursor_sr = 0;
1351         }
1352
1353         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1354                       planea_wm, cursora_wm,
1355                       planeb_wm, cursorb_wm,
1356                       plane_sr, cursor_sr);
1357
1358         I915_WRITE(DSPFW1,
1359                    (plane_sr << DSPFW_SR_SHIFT) |
1360                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1361                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1362                    planea_wm);
1363         I915_WRITE(DSPFW2,
1364                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1365                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1366         I915_WRITE(DSPFW3,
1367                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1368                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1369 }
1370
1371 static void g4x_update_wm(struct drm_crtc *crtc)
1372 {
1373         struct drm_device *dev = crtc->dev;
1374         static const int sr_latency_ns = 12000;
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377         int plane_sr, cursor_sr;
1378         unsigned int enabled = 0;
1379
1380         if (g4x_compute_wm0(dev, PIPE_A,
1381                             &g4x_wm_info, latency_ns,
1382                             &g4x_cursor_wm_info, latency_ns,
1383                             &planea_wm, &cursora_wm))
1384                 enabled |= 1 << PIPE_A;
1385
1386         if (g4x_compute_wm0(dev, PIPE_B,
1387                             &g4x_wm_info, latency_ns,
1388                             &g4x_cursor_wm_info, latency_ns,
1389                             &planeb_wm, &cursorb_wm))
1390                 enabled |= 1 << PIPE_B;
1391
1392         if (single_plane_enabled(enabled) &&
1393             g4x_compute_srwm(dev, ffs(enabled) - 1,
1394                              sr_latency_ns,
1395                              &g4x_wm_info,
1396                              &g4x_cursor_wm_info,
1397                              &plane_sr, &cursor_sr)) {
1398                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1399         } else {
1400                 I915_WRITE(FW_BLC_SELF,
1401                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1402                 plane_sr = cursor_sr = 0;
1403         }
1404
1405         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1406                       planea_wm, cursora_wm,
1407                       planeb_wm, cursorb_wm,
1408                       plane_sr, cursor_sr);
1409
1410         I915_WRITE(DSPFW1,
1411                    (plane_sr << DSPFW_SR_SHIFT) |
1412                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1413                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1414                    planea_wm);
1415         I915_WRITE(DSPFW2,
1416                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1417                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1418         /* HPLL off in SR has some issues on G4x... disable it */
1419         I915_WRITE(DSPFW3,
1420                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1421                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1422 }
1423
1424 static void i965_update_wm(struct drm_crtc *unused_crtc)
1425 {
1426         struct drm_device *dev = unused_crtc->dev;
1427         struct drm_i915_private *dev_priv = dev->dev_private;
1428         struct drm_crtc *crtc;
1429         int srwm = 1;
1430         int cursor_sr = 16;
1431
1432         /* Calc sr entries for one plane configs */
1433         crtc = single_enabled_crtc(dev);
1434         if (crtc) {
1435                 /* self-refresh has much higher latency */
1436                 static const int sr_latency_ns = 12000;
1437                 const struct drm_display_mode *adjusted_mode =
1438                         &to_intel_crtc(crtc)->config.adjusted_mode;
1439                 int clock = adjusted_mode->crtc_clock;
1440                 int htotal = adjusted_mode->crtc_htotal;
1441                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1442                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1443                 unsigned long line_time_us;
1444                 int entries;
1445
1446                 line_time_us = max(htotal * 1000 / clock, 1);
1447
1448                 /* Use ns/us then divide to preserve precision */
1449                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450                         pixel_size * hdisplay;
1451                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1452                 srwm = I965_FIFO_SIZE - entries;
1453                 if (srwm < 0)
1454                         srwm = 1;
1455                 srwm &= 0x1ff;
1456                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1457                               entries, srwm);
1458
1459                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1460                         pixel_size * to_intel_crtc(crtc)->cursor_width;
1461                 entries = DIV_ROUND_UP(entries,
1462                                           i965_cursor_wm_info.cacheline_size);
1463                 cursor_sr = i965_cursor_wm_info.fifo_size -
1464                         (entries + i965_cursor_wm_info.guard_size);
1465
1466                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1467                         cursor_sr = i965_cursor_wm_info.max_wm;
1468
1469                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470                               "cursor %d\n", srwm, cursor_sr);
1471
1472                 if (IS_CRESTLINE(dev))
1473                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1474         } else {
1475                 /* Turn off self refresh if both pipes are enabled */
1476                 if (IS_CRESTLINE(dev))
1477                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1478                                    & ~FW_BLC_SELF_EN);
1479         }
1480
1481         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1482                       srwm);
1483
1484         /* 965 has limitations... */
1485         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1486                    (8 << 16) | (8 << 8) | (8 << 0));
1487         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1488         /* update cursor SR watermark */
1489         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490 }
1491
1492 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1493 {
1494         struct drm_device *dev = unused_crtc->dev;
1495         struct drm_i915_private *dev_priv = dev->dev_private;
1496         const struct intel_watermark_params *wm_info;
1497         uint32_t fwater_lo;
1498         uint32_t fwater_hi;
1499         int cwm, srwm = 1;
1500         int fifo_size;
1501         int planea_wm, planeb_wm;
1502         struct drm_crtc *crtc, *enabled = NULL;
1503
1504         if (IS_I945GM(dev))
1505                 wm_info = &i945_wm_info;
1506         else if (!IS_GEN2(dev))
1507                 wm_info = &i915_wm_info;
1508         else
1509                 wm_info = &i830_wm_info;
1510
1511         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1512         crtc = intel_get_crtc_for_plane(dev, 0);
1513         if (intel_crtc_active(crtc)) {
1514                 const struct drm_display_mode *adjusted_mode;
1515                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1516                 if (IS_GEN2(dev))
1517                         cpp = 4;
1518
1519                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1520                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1521                                                wm_info, fifo_size, cpp,
1522                                                latency_ns);
1523                 enabled = crtc;
1524         } else
1525                 planea_wm = fifo_size - wm_info->guard_size;
1526
1527         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1528         crtc = intel_get_crtc_for_plane(dev, 1);
1529         if (intel_crtc_active(crtc)) {
1530                 const struct drm_display_mode *adjusted_mode;
1531                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1532                 if (IS_GEN2(dev))
1533                         cpp = 4;
1534
1535                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1536                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1537                                                wm_info, fifo_size, cpp,
1538                                                latency_ns);
1539                 if (enabled == NULL)
1540                         enabled = crtc;
1541                 else
1542                         enabled = NULL;
1543         } else
1544                 planeb_wm = fifo_size - wm_info->guard_size;
1545
1546         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
1548         if (IS_I915GM(dev) && enabled) {
1549                 struct intel_framebuffer *fb;
1550
1551                 fb = to_intel_framebuffer(enabled->primary->fb);
1552
1553                 /* self-refresh seems busted with untiled */
1554                 if (fb->obj->tiling_mode == I915_TILING_NONE)
1555                         enabled = NULL;
1556         }
1557
1558         /*
1559          * Overlay gets an aggressive default since video jitter is bad.
1560          */
1561         cwm = 2;
1562
1563         /* Play safe and disable self-refresh before adjusting watermarks. */
1564         if (IS_I945G(dev) || IS_I945GM(dev))
1565                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1566         else if (IS_I915GM(dev))
1567                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
1568
1569         /* Calc sr entries for one plane configs */
1570         if (HAS_FW_BLC(dev) && enabled) {
1571                 /* self-refresh has much higher latency */
1572                 static const int sr_latency_ns = 6000;
1573                 const struct drm_display_mode *adjusted_mode =
1574                         &to_intel_crtc(enabled)->config.adjusted_mode;
1575                 int clock = adjusted_mode->crtc_clock;
1576                 int htotal = adjusted_mode->crtc_htotal;
1577                 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1578                 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1579                 unsigned long line_time_us;
1580                 int entries;
1581
1582                 line_time_us = max(htotal * 1000 / clock, 1);
1583
1584                 /* Use ns/us then divide to preserve precision */
1585                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1586                         pixel_size * hdisplay;
1587                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1588                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1589                 srwm = wm_info->fifo_size - entries;
1590                 if (srwm < 0)
1591                         srwm = 1;
1592
1593                 if (IS_I945G(dev) || IS_I945GM(dev))
1594                         I915_WRITE(FW_BLC_SELF,
1595                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1596                 else if (IS_I915GM(dev))
1597                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1598         }
1599
1600         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1601                       planea_wm, planeb_wm, cwm, srwm);
1602
1603         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1604         fwater_hi = (cwm & 0x1f);
1605
1606         /* Set request length to 8 cachelines per fetch */
1607         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1608         fwater_hi = fwater_hi | (1 << 8);
1609
1610         I915_WRITE(FW_BLC, fwater_lo);
1611         I915_WRITE(FW_BLC2, fwater_hi);
1612
1613         if (HAS_FW_BLC(dev)) {
1614                 if (enabled) {
1615                         if (IS_I945G(dev) || IS_I945GM(dev))
1616                                 I915_WRITE(FW_BLC_SELF,
1617                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1618                         else if (IS_I915GM(dev))
1619                                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
1620                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1621                 } else
1622                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1623         }
1624 }
1625
1626 static void i845_update_wm(struct drm_crtc *unused_crtc)
1627 {
1628         struct drm_device *dev = unused_crtc->dev;
1629         struct drm_i915_private *dev_priv = dev->dev_private;
1630         struct drm_crtc *crtc;
1631         const struct drm_display_mode *adjusted_mode;
1632         uint32_t fwater_lo;
1633         int planea_wm;
1634
1635         crtc = single_enabled_crtc(dev);
1636         if (crtc == NULL)
1637                 return;
1638
1639         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1640         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1641                                        &i845_wm_info,
1642                                        dev_priv->display.get_fifo_size(dev, 0),
1643                                        4, latency_ns);
1644         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1645         fwater_lo |= (3<<8) | planea_wm;
1646
1647         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1648
1649         I915_WRITE(FW_BLC, fwater_lo);
1650 }
1651
1652 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1653                                     struct drm_crtc *crtc)
1654 {
1655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1656         uint32_t pixel_rate;
1657
1658         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1659
1660         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1661          * adjust the pixel_rate here. */
1662
1663         if (intel_crtc->config.pch_pfit.enabled) {
1664                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1665                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1666
1667                 pipe_w = intel_crtc->config.pipe_src_w;
1668                 pipe_h = intel_crtc->config.pipe_src_h;
1669                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670                 pfit_h = pfit_size & 0xFFFF;
1671                 if (pipe_w < pfit_w)
1672                         pipe_w = pfit_w;
1673                 if (pipe_h < pfit_h)
1674                         pipe_h = pfit_h;
1675
1676                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1677                                      pfit_w * pfit_h);
1678         }
1679
1680         return pixel_rate;
1681 }
1682
1683 /* latency must be in 0.1us units. */
1684 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1685                                uint32_t latency)
1686 {
1687         uint64_t ret;
1688
1689         if (WARN(latency == 0, "Latency value missing\n"))
1690                 return UINT_MAX;
1691
1692         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1693         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1694
1695         return ret;
1696 }
1697
1698 /* latency must be in 0.1us units. */
1699 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1700                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1701                                uint32_t latency)
1702 {
1703         uint32_t ret;
1704
1705         if (WARN(latency == 0, "Latency value missing\n"))
1706                 return UINT_MAX;
1707
1708         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1709         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1710         ret = DIV_ROUND_UP(ret, 64) + 2;
1711         return ret;
1712 }
1713
1714 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1715                            uint8_t bytes_per_pixel)
1716 {
1717         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1718 }
1719
1720 struct ilk_pipe_wm_parameters {
1721         bool active;
1722         uint32_t pipe_htotal;
1723         uint32_t pixel_rate;
1724         struct intel_plane_wm_parameters pri;
1725         struct intel_plane_wm_parameters spr;
1726         struct intel_plane_wm_parameters cur;
1727 };
1728
1729 struct ilk_wm_maximums {
1730         uint16_t pri;
1731         uint16_t spr;
1732         uint16_t cur;
1733         uint16_t fbc;
1734 };
1735
1736 /* used in computing the new watermarks state */
1737 struct intel_wm_config {
1738         unsigned int num_pipes_active;
1739         bool sprites_enabled;
1740         bool sprites_scaled;
1741 };
1742
1743 /*
1744  * For both WM_PIPE and WM_LP.
1745  * mem_value must be in 0.1us units.
1746  */
1747 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1748                                    uint32_t mem_value,
1749                                    bool is_lp)
1750 {
1751         uint32_t method1, method2;
1752
1753         if (!params->active || !params->pri.enabled)
1754                 return 0;
1755
1756         method1 = ilk_wm_method1(params->pixel_rate,
1757                                  params->pri.bytes_per_pixel,
1758                                  mem_value);
1759
1760         if (!is_lp)
1761                 return method1;
1762
1763         method2 = ilk_wm_method2(params->pixel_rate,
1764                                  params->pipe_htotal,
1765                                  params->pri.horiz_pixels,
1766                                  params->pri.bytes_per_pixel,
1767                                  mem_value);
1768
1769         return min(method1, method2);
1770 }
1771
1772 /*
1773  * For both WM_PIPE and WM_LP.
1774  * mem_value must be in 0.1us units.
1775  */
1776 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1777                                    uint32_t mem_value)
1778 {
1779         uint32_t method1, method2;
1780
1781         if (!params->active || !params->spr.enabled)
1782                 return 0;
1783
1784         method1 = ilk_wm_method1(params->pixel_rate,
1785                                  params->spr.bytes_per_pixel,
1786                                  mem_value);
1787         method2 = ilk_wm_method2(params->pixel_rate,
1788                                  params->pipe_htotal,
1789                                  params->spr.horiz_pixels,
1790                                  params->spr.bytes_per_pixel,
1791                                  mem_value);
1792         return min(method1, method2);
1793 }
1794
1795 /*
1796  * For both WM_PIPE and WM_LP.
1797  * mem_value must be in 0.1us units.
1798  */
1799 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1800                                    uint32_t mem_value)
1801 {
1802         if (!params->active || !params->cur.enabled)
1803                 return 0;
1804
1805         return ilk_wm_method2(params->pixel_rate,
1806                               params->pipe_htotal,
1807                               params->cur.horiz_pixels,
1808                               params->cur.bytes_per_pixel,
1809                               mem_value);
1810 }
1811
1812 /* Only for WM_LP. */
1813 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1814                                    uint32_t pri_val)
1815 {
1816         if (!params->active || !params->pri.enabled)
1817                 return 0;
1818
1819         return ilk_wm_fbc(pri_val,
1820                           params->pri.horiz_pixels,
1821                           params->pri.bytes_per_pixel);
1822 }
1823
1824 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1825 {
1826         if (INTEL_INFO(dev)->gen >= 8)
1827                 return 3072;
1828         else if (INTEL_INFO(dev)->gen >= 7)
1829                 return 768;
1830         else
1831                 return 512;
1832 }
1833
1834 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1835                                          int level, bool is_sprite)
1836 {
1837         if (INTEL_INFO(dev)->gen >= 8)
1838                 /* BDW primary/sprite plane watermarks */
1839                 return level == 0 ? 255 : 2047;
1840         else if (INTEL_INFO(dev)->gen >= 7)
1841                 /* IVB/HSW primary/sprite plane watermarks */
1842                 return level == 0 ? 127 : 1023;
1843         else if (!is_sprite)
1844                 /* ILK/SNB primary plane watermarks */
1845                 return level == 0 ? 127 : 511;
1846         else
1847                 /* ILK/SNB sprite plane watermarks */
1848                 return level == 0 ? 63 : 255;
1849 }
1850
1851 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1852                                           int level)
1853 {
1854         if (INTEL_INFO(dev)->gen >= 7)
1855                 return level == 0 ? 63 : 255;
1856         else
1857                 return level == 0 ? 31 : 63;
1858 }
1859
1860 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1861 {
1862         if (INTEL_INFO(dev)->gen >= 8)
1863                 return 31;
1864         else
1865                 return 15;
1866 }
1867
1868 /* Calculate the maximum primary/sprite plane watermark */
1869 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1870                                      int level,
1871                                      const struct intel_wm_config *config,
1872                                      enum intel_ddb_partitioning ddb_partitioning,
1873                                      bool is_sprite)
1874 {
1875         unsigned int fifo_size = ilk_display_fifo_size(dev);
1876
1877         /* if sprites aren't enabled, sprites get nothing */
1878         if (is_sprite && !config->sprites_enabled)
1879                 return 0;
1880
1881         /* HSW allows LP1+ watermarks even with multiple pipes */
1882         if (level == 0 || config->num_pipes_active > 1) {
1883                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1884
1885                 /*
1886                  * For some reason the non self refresh
1887                  * FIFO size is only half of the self
1888                  * refresh FIFO size on ILK/SNB.
1889                  */
1890                 if (INTEL_INFO(dev)->gen <= 6)
1891                         fifo_size /= 2;
1892         }
1893
1894         if (config->sprites_enabled) {
1895                 /* level 0 is always calculated with 1:1 split */
1896                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1897                         if (is_sprite)
1898                                 fifo_size *= 5;
1899                         fifo_size /= 6;
1900                 } else {
1901                         fifo_size /= 2;
1902                 }
1903         }
1904
1905         /* clamp to max that the registers can hold */
1906         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1907 }
1908
1909 /* Calculate the maximum cursor plane watermark */
1910 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1911                                       int level,
1912                                       const struct intel_wm_config *config)
1913 {
1914         /* HSW LP1+ watermarks w/ multiple pipes */
1915         if (level > 0 && config->num_pipes_active > 1)
1916                 return 64;
1917
1918         /* otherwise just report max that registers can hold */
1919         return ilk_cursor_wm_reg_max(dev, level);
1920 }
1921
1922 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1923                                     int level,
1924                                     const struct intel_wm_config *config,
1925                                     enum intel_ddb_partitioning ddb_partitioning,
1926                                     struct ilk_wm_maximums *max)
1927 {
1928         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1929         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1930         max->cur = ilk_cursor_wm_max(dev, level, config);
1931         max->fbc = ilk_fbc_wm_reg_max(dev);
1932 }
1933
1934 static bool ilk_validate_wm_level(int level,
1935                                   const struct ilk_wm_maximums *max,
1936                                   struct intel_wm_level *result)
1937 {
1938         bool ret;
1939
1940         /* already determined to be invalid? */
1941         if (!result->enable)
1942                 return false;
1943
1944         result->enable = result->pri_val <= max->pri &&
1945                          result->spr_val <= max->spr &&
1946                          result->cur_val <= max->cur;
1947
1948         ret = result->enable;
1949
1950         /*
1951          * HACK until we can pre-compute everything,
1952          * and thus fail gracefully if LP0 watermarks
1953          * are exceeded...
1954          */
1955         if (level == 0 && !result->enable) {
1956                 if (result->pri_val > max->pri)
1957                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1958                                       level, result->pri_val, max->pri);
1959                 if (result->spr_val > max->spr)
1960                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1961                                       level, result->spr_val, max->spr);
1962                 if (result->cur_val > max->cur)
1963                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1964                                       level, result->cur_val, max->cur);
1965
1966                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1967                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1968                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1969                 result->enable = true;
1970         }
1971
1972         return ret;
1973 }
1974
1975 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1976                                  int level,
1977                                  const struct ilk_pipe_wm_parameters *p,
1978                                  struct intel_wm_level *result)
1979 {
1980         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1981         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1982         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1983
1984         /* WM1+ latency values stored in 0.5us units */
1985         if (level > 0) {
1986                 pri_latency *= 5;
1987                 spr_latency *= 5;
1988                 cur_latency *= 5;
1989         }
1990
1991         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1992         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1993         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1994         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1995         result->enable = true;
1996 }
1997
1998 static uint32_t
1999 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2000 {
2001         struct drm_i915_private *dev_priv = dev->dev_private;
2002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2003         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2004         u32 linetime, ips_linetime;
2005
2006         if (!intel_crtc_active(crtc))
2007                 return 0;
2008
2009         /* The WM are computed with base on how long it takes to fill a single
2010          * row at the given clock rate, multiplied by 8.
2011          * */
2012         linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2013                                      mode->crtc_clock);
2014         ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2015                                          intel_ddi_get_cdclk_freq(dev_priv));
2016
2017         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2018                PIPE_WM_LINETIME_TIME(linetime);
2019 }
2020
2021 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2022 {
2023         struct drm_i915_private *dev_priv = dev->dev_private;
2024
2025         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2026                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2027
2028                 wm[0] = (sskpd >> 56) & 0xFF;
2029                 if (wm[0] == 0)
2030                         wm[0] = sskpd & 0xF;
2031                 wm[1] = (sskpd >> 4) & 0xFF;
2032                 wm[2] = (sskpd >> 12) & 0xFF;
2033                 wm[3] = (sskpd >> 20) & 0x1FF;
2034                 wm[4] = (sskpd >> 32) & 0x1FF;
2035         } else if (INTEL_INFO(dev)->gen >= 6) {
2036                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2037
2038                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2039                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2040                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2041                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2042         } else if (INTEL_INFO(dev)->gen >= 5) {
2043                 uint32_t mltr = I915_READ(MLTR_ILK);
2044
2045                 /* ILK primary LP0 latency is 700 ns */
2046                 wm[0] = 7;
2047                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2048                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2049         }
2050 }
2051
2052 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2053 {
2054         /* ILK sprite LP0 latency is 1300 ns */
2055         if (INTEL_INFO(dev)->gen == 5)
2056                 wm[0] = 13;
2057 }
2058
2059 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2060 {
2061         /* ILK cursor LP0 latency is 1300 ns */
2062         if (INTEL_INFO(dev)->gen == 5)
2063                 wm[0] = 13;
2064
2065         /* WaDoubleCursorLP3Latency:ivb */
2066         if (IS_IVYBRIDGE(dev))
2067                 wm[3] *= 2;
2068 }
2069
2070 static int ilk_wm_max_level(const struct drm_device *dev)
2071 {
2072         /* how many WM levels are we expecting */
2073         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2074                 return 4;
2075         else if (INTEL_INFO(dev)->gen >= 6)
2076                 return 3;
2077         else
2078                 return 2;
2079 }
2080
2081 static void intel_print_wm_latency(struct drm_device *dev,
2082                                    const char *name,
2083                                    const uint16_t wm[5])
2084 {
2085         int level, max_level = ilk_wm_max_level(dev);
2086
2087         for (level = 0; level <= max_level; level++) {
2088                 unsigned int latency = wm[level];
2089
2090                 if (latency == 0) {
2091                         DRM_ERROR("%s WM%d latency not provided\n",
2092                                   name, level);
2093                         continue;
2094                 }
2095
2096                 /* WM1+ latency values in 0.5us units */
2097                 if (level > 0)
2098                         latency *= 5;
2099
2100                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2101                               name, level, wm[level],
2102                               latency / 10, latency % 10);
2103         }
2104 }
2105
2106 static void ilk_setup_wm_latency(struct drm_device *dev)
2107 {
2108         struct drm_i915_private *dev_priv = dev->dev_private;
2109
2110         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2111
2112         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2113                sizeof(dev_priv->wm.pri_latency));
2114         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2115                sizeof(dev_priv->wm.pri_latency));
2116
2117         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2118         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2119
2120         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2121         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2122         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2123 }
2124
2125 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2126                                       struct ilk_pipe_wm_parameters *p)
2127 {
2128         struct drm_device *dev = crtc->dev;
2129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2130         enum pipe pipe = intel_crtc->pipe;
2131         struct drm_plane *plane;
2132
2133         if (!intel_crtc_active(crtc))
2134                 return;
2135
2136         p->active = true;
2137         p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2138         p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2139         p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2140         p->cur.bytes_per_pixel = 4;
2141         p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2142         p->cur.horiz_pixels = intel_crtc->cursor_width;
2143         /* TODO: for now, assume primary and cursor planes are always enabled. */
2144         p->pri.enabled = true;
2145         p->cur.enabled = true;
2146
2147         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2148                 struct intel_plane *intel_plane = to_intel_plane(plane);
2149
2150                 if (intel_plane->pipe == pipe) {
2151                         p->spr = intel_plane->wm;
2152                         break;
2153                 }
2154         }
2155 }
2156
2157 static void ilk_compute_wm_config(struct drm_device *dev,
2158                                   struct intel_wm_config *config)
2159 {
2160         struct intel_crtc *intel_crtc;
2161
2162         /* Compute the currently _active_ config */
2163         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2164                 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2165
2166                 if (!wm->pipe_enabled)
2167                         continue;
2168
2169                 config->sprites_enabled |= wm->sprites_enabled;
2170                 config->sprites_scaled |= wm->sprites_scaled;
2171                 config->num_pipes_active++;
2172         }
2173 }
2174
2175 /* Compute new watermarks for the pipe */
2176 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2177                                   const struct ilk_pipe_wm_parameters *params,
2178                                   struct intel_pipe_wm *pipe_wm)
2179 {
2180         struct drm_device *dev = crtc->dev;
2181         const struct drm_i915_private *dev_priv = dev->dev_private;
2182         int level, max_level = ilk_wm_max_level(dev);
2183         /* LP0 watermark maximums depend on this pipe alone */
2184         struct intel_wm_config config = {
2185                 .num_pipes_active = 1,
2186                 .sprites_enabled = params->spr.enabled,
2187                 .sprites_scaled = params->spr.scaled,
2188         };
2189         struct ilk_wm_maximums max;
2190
2191         /* LP0 watermarks always use 1/2 DDB partitioning */
2192         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2193
2194         pipe_wm->pipe_enabled = params->active;
2195         pipe_wm->sprites_enabled = params->spr.enabled;
2196         pipe_wm->sprites_scaled = params->spr.scaled;
2197
2198         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2199         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2200                 max_level = 1;
2201
2202         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2203         if (params->spr.scaled)
2204                 max_level = 0;
2205
2206         for (level = 0; level <= max_level; level++)
2207                 ilk_compute_wm_level(dev_priv, level, params,
2208                                      &pipe_wm->wm[level]);
2209
2210         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2211                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2212
2213         /* At least LP0 must be valid */
2214         return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2215 }
2216
2217 /*
2218  * Merge the watermarks from all active pipes for a specific level.
2219  */
2220 static void ilk_merge_wm_level(struct drm_device *dev,
2221                                int level,
2222                                struct intel_wm_level *ret_wm)
2223 {
2224         const struct intel_crtc *intel_crtc;
2225
2226         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2227                 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2228                 const struct intel_wm_level *wm = &active->wm[level];
2229
2230                 if (!active->pipe_enabled)
2231                         continue;
2232
2233                 if (!wm->enable)
2234                         return;
2235
2236                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2237                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2238                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2239                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2240         }
2241
2242         ret_wm->enable = true;
2243 }
2244
2245 /*
2246  * Merge all low power watermarks for all active pipes.
2247  */
2248 static void ilk_wm_merge(struct drm_device *dev,
2249                          const struct intel_wm_config *config,
2250                          const struct ilk_wm_maximums *max,
2251                          struct intel_pipe_wm *merged)
2252 {
2253         int level, max_level = ilk_wm_max_level(dev);
2254
2255         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2256         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2257             config->num_pipes_active > 1)
2258                 return;
2259
2260         /* ILK: FBC WM must be disabled always */
2261         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2262
2263         /* merge each WM1+ level */
2264         for (level = 1; level <= max_level; level++) {
2265                 struct intel_wm_level *wm = &merged->wm[level];
2266
2267                 ilk_merge_wm_level(dev, level, wm);
2268
2269                 if (!ilk_validate_wm_level(level, max, wm))
2270                         break;
2271
2272                 /*
2273                  * The spec says it is preferred to disable
2274                  * FBC WMs instead of disabling a WM level.
2275                  */
2276                 if (wm->fbc_val > max->fbc) {
2277                         merged->fbc_wm_enabled = false;
2278                         wm->fbc_val = 0;
2279                 }
2280         }
2281
2282         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2283         /*
2284          * FIXME this is racy. FBC might get enabled later.
2285          * What we should check here is whether FBC can be
2286          * enabled sometime later.
2287          */
2288         if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2289                 for (level = 2; level <= max_level; level++) {
2290                         struct intel_wm_level *wm = &merged->wm[level];
2291
2292                         wm->enable = false;
2293                 }
2294         }
2295 }
2296
2297 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2298 {
2299         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2300         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2301 }
2302
2303 /* The value we need to program into the WM_LPx latency field */
2304 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2305 {
2306         struct drm_i915_private *dev_priv = dev->dev_private;
2307
2308         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2309                 return 2 * level;
2310         else
2311                 return dev_priv->wm.pri_latency[level];
2312 }
2313
2314 static void ilk_compute_wm_results(struct drm_device *dev,
2315                                    const struct intel_pipe_wm *merged,
2316                                    enum intel_ddb_partitioning partitioning,
2317                                    struct ilk_wm_values *results)
2318 {
2319         struct intel_crtc *intel_crtc;
2320         int level, wm_lp;
2321
2322         results->enable_fbc_wm = merged->fbc_wm_enabled;
2323         results->partitioning = partitioning;
2324
2325         /* LP1+ register values */
2326         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2327                 const struct intel_wm_level *r;
2328
2329                 level = ilk_wm_lp_to_level(wm_lp, merged);
2330
2331                 r = &merged->wm[level];
2332                 if (!r->enable)
2333                         break;
2334
2335                 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2336                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2337                         (r->pri_val << WM1_LP_SR_SHIFT) |
2338                         r->cur_val;
2339
2340                 if (INTEL_INFO(dev)->gen >= 8)
2341                         results->wm_lp[wm_lp - 1] |=
2342                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2343                 else
2344                         results->wm_lp[wm_lp - 1] |=
2345                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2346
2347                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2348                         WARN_ON(wm_lp != 1);
2349                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2350                 } else
2351                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2352         }
2353
2354         /* LP0 register values */
2355         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2356                 enum pipe pipe = intel_crtc->pipe;
2357                 const struct intel_wm_level *r =
2358                         &intel_crtc->wm.active.wm[0];
2359
2360                 if (WARN_ON(!r->enable))
2361                         continue;
2362
2363                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2364
2365                 results->wm_pipe[pipe] =
2366                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2367                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2368                         r->cur_val;
2369         }
2370 }
2371
2372 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2373  * case both are at the same level. Prefer r1 in case they're the same. */
2374 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2375                                                   struct intel_pipe_wm *r1,
2376                                                   struct intel_pipe_wm *r2)
2377 {
2378         int level, max_level = ilk_wm_max_level(dev);
2379         int level1 = 0, level2 = 0;
2380
2381         for (level = 1; level <= max_level; level++) {
2382                 if (r1->wm[level].enable)
2383                         level1 = level;
2384                 if (r2->wm[level].enable)
2385                         level2 = level;
2386         }
2387
2388         if (level1 == level2) {
2389                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2390                         return r2;
2391                 else
2392                         return r1;
2393         } else if (level1 > level2) {
2394                 return r1;
2395         } else {
2396                 return r2;
2397         }
2398 }
2399
2400 /* dirty bits used to track which watermarks need changes */
2401 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2402 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2403 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2404 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2405 #define WM_DIRTY_FBC (1 << 24)
2406 #define WM_DIRTY_DDB (1 << 25)
2407
2408 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2409                                          const struct ilk_wm_values *old,
2410                                          const struct ilk_wm_values *new)
2411 {
2412         unsigned int dirty = 0;
2413         enum pipe pipe;
2414         int wm_lp;
2415
2416         for_each_pipe(pipe) {
2417                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2418                         dirty |= WM_DIRTY_LINETIME(pipe);
2419                         /* Must disable LP1+ watermarks too */
2420                         dirty |= WM_DIRTY_LP_ALL;
2421                 }
2422
2423                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2424                         dirty |= WM_DIRTY_PIPE(pipe);
2425                         /* Must disable LP1+ watermarks too */
2426                         dirty |= WM_DIRTY_LP_ALL;
2427                 }
2428         }
2429
2430         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2431                 dirty |= WM_DIRTY_FBC;
2432                 /* Must disable LP1+ watermarks too */
2433                 dirty |= WM_DIRTY_LP_ALL;
2434         }
2435
2436         if (old->partitioning != new->partitioning) {
2437                 dirty |= WM_DIRTY_DDB;
2438                 /* Must disable LP1+ watermarks too */
2439                 dirty |= WM_DIRTY_LP_ALL;
2440         }
2441
2442         /* LP1+ watermarks already deemed dirty, no need to continue */
2443         if (dirty & WM_DIRTY_LP_ALL)
2444                 return dirty;
2445
2446         /* Find the lowest numbered LP1+ watermark in need of an update... */
2447         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2448                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2449                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2450                         break;
2451         }
2452
2453         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2454         for (; wm_lp <= 3; wm_lp++)
2455                 dirty |= WM_DIRTY_LP(wm_lp);
2456
2457         return dirty;
2458 }
2459
2460 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2461                                unsigned int dirty)
2462 {
2463         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2464         bool changed = false;
2465
2466         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2467                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2468                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2469                 changed = true;
2470         }
2471         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2472                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2473                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2474                 changed = true;
2475         }
2476         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2477                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2478                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2479                 changed = true;
2480         }
2481
2482         /*
2483          * Don't touch WM1S_LP_EN here.
2484          * Doing so could cause underruns.
2485          */
2486
2487         return changed;
2488 }
2489
2490 /*
2491  * The spec says we shouldn't write when we don't need, because every write
2492  * causes WMs to be re-evaluated, expending some power.
2493  */
2494 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2495                                 struct ilk_wm_values *results)
2496 {
2497         struct drm_device *dev = dev_priv->dev;
2498         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2499         unsigned int dirty;
2500         uint32_t val;
2501
2502         dirty = ilk_compute_wm_dirty(dev, previous, results);
2503         if (!dirty)
2504                 return;
2505
2506         _ilk_disable_lp_wm(dev_priv, dirty);
2507
2508         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2509                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2510         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2511                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2512         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2513                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2514
2515         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2516                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2517         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2518                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2519         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2520                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2521
2522         if (dirty & WM_DIRTY_DDB) {
2523                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2524                         val = I915_READ(WM_MISC);
2525                         if (results->partitioning == INTEL_DDB_PART_1_2)
2526                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2527                         else
2528                                 val |= WM_MISC_DATA_PARTITION_5_6;
2529                         I915_WRITE(WM_MISC, val);
2530                 } else {
2531                         val = I915_READ(DISP_ARB_CTL2);
2532                         if (results->partitioning == INTEL_DDB_PART_1_2)
2533                                 val &= ~DISP_DATA_PARTITION_5_6;
2534                         else
2535                                 val |= DISP_DATA_PARTITION_5_6;
2536                         I915_WRITE(DISP_ARB_CTL2, val);
2537                 }
2538         }
2539
2540         if (dirty & WM_DIRTY_FBC) {
2541                 val = I915_READ(DISP_ARB_CTL);
2542                 if (results->enable_fbc_wm)
2543                         val &= ~DISP_FBC_WM_DIS;
2544                 else
2545                         val |= DISP_FBC_WM_DIS;
2546                 I915_WRITE(DISP_ARB_CTL, val);
2547         }
2548
2549         if (dirty & WM_DIRTY_LP(1) &&
2550             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2551                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2552
2553         if (INTEL_INFO(dev)->gen >= 7) {
2554                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2555                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2556                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2557                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2558         }
2559
2560         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2561                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2562         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2563                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2564         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2565                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2566
2567         dev_priv->wm.hw = *results;
2568 }
2569
2570 static bool ilk_disable_lp_wm(struct drm_device *dev)
2571 {
2572         struct drm_i915_private *dev_priv = dev->dev_private;
2573
2574         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2575 }
2576
2577 static void ilk_update_wm(struct drm_crtc *crtc)
2578 {
2579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2580         struct drm_device *dev = crtc->dev;
2581         struct drm_i915_private *dev_priv = dev->dev_private;
2582         struct ilk_wm_maximums max;
2583         struct ilk_pipe_wm_parameters params = {};
2584         struct ilk_wm_values results = {};
2585         enum intel_ddb_partitioning partitioning;
2586         struct intel_pipe_wm pipe_wm = {};
2587         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2588         struct intel_wm_config config = {};
2589
2590         ilk_compute_wm_parameters(crtc, &params);
2591
2592         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2593
2594         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2595                 return;
2596
2597         intel_crtc->wm.active = pipe_wm;
2598
2599         ilk_compute_wm_config(dev, &config);
2600
2601         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2602         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2603
2604         /* 5/6 split only in single pipe config on IVB+ */
2605         if (INTEL_INFO(dev)->gen >= 7 &&
2606             config.num_pipes_active == 1 && config.sprites_enabled) {
2607                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2608                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2609
2610                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2611         } else {
2612                 best_lp_wm = &lp_wm_1_2;
2613         }
2614
2615         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2616                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2617
2618         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2619
2620         ilk_write_wm_values(dev_priv, &results);
2621 }
2622
2623 static void ilk_update_sprite_wm(struct drm_plane *plane,
2624                                      struct drm_crtc *crtc,
2625                                      uint32_t sprite_width, int pixel_size,
2626                                      bool enabled, bool scaled)
2627 {
2628         struct drm_device *dev = plane->dev;
2629         struct intel_plane *intel_plane = to_intel_plane(plane);
2630
2631         intel_plane->wm.enabled = enabled;
2632         intel_plane->wm.scaled = scaled;
2633         intel_plane->wm.horiz_pixels = sprite_width;
2634         intel_plane->wm.bytes_per_pixel = pixel_size;
2635
2636         /*
2637          * IVB workaround: must disable low power watermarks for at least
2638          * one frame before enabling scaling.  LP watermarks can be re-enabled
2639          * when scaling is disabled.
2640          *
2641          * WaCxSRDisabledForSpriteScaling:ivb
2642          */
2643         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2644                 intel_wait_for_vblank(dev, intel_plane->pipe);
2645
2646         ilk_update_wm(crtc);
2647 }
2648
2649 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2650 {
2651         struct drm_device *dev = crtc->dev;
2652         struct drm_i915_private *dev_priv = dev->dev_private;
2653         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2655         struct intel_pipe_wm *active = &intel_crtc->wm.active;
2656         enum pipe pipe = intel_crtc->pipe;
2657         static const unsigned int wm0_pipe_reg[] = {
2658                 [PIPE_A] = WM0_PIPEA_ILK,
2659                 [PIPE_B] = WM0_PIPEB_ILK,
2660                 [PIPE_C] = WM0_PIPEC_IVB,
2661         };
2662
2663         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2664         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2665                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2666
2667         active->pipe_enabled = intel_crtc_active(crtc);
2668
2669         if (active->pipe_enabled) {
2670                 u32 tmp = hw->wm_pipe[pipe];
2671
2672                 /*
2673                  * For active pipes LP0 watermark is marked as
2674                  * enabled, and LP1+ watermaks as disabled since
2675                  * we can't really reverse compute them in case
2676                  * multiple pipes are active.
2677                  */
2678                 active->wm[0].enable = true;
2679                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2680                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2681                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2682                 active->linetime = hw->wm_linetime[pipe];
2683         } else {
2684                 int level, max_level = ilk_wm_max_level(dev);
2685
2686                 /*
2687                  * For inactive pipes, all watermark levels
2688                  * should be marked as enabled but zeroed,
2689                  * which is what we'd compute them to.
2690                  */
2691                 for (level = 0; level <= max_level; level++)
2692                         active->wm[level].enable = true;
2693         }
2694 }
2695
2696 void ilk_wm_get_hw_state(struct drm_device *dev)
2697 {
2698         struct drm_i915_private *dev_priv = dev->dev_private;
2699         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2700         struct drm_crtc *crtc;
2701
2702         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2703                 ilk_pipe_wm_get_hw_state(crtc);
2704
2705         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2706         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2707         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2708
2709         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2710         if (INTEL_INFO(dev)->gen >= 7) {
2711                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2712                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2713         }
2714
2715         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2716                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2717                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2718         else if (IS_IVYBRIDGE(dev))
2719                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2720                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2721
2722         hw->enable_fbc_wm =
2723                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2724 }
2725
2726 /**
2727  * intel_update_watermarks - update FIFO watermark values based on current modes
2728  *
2729  * Calculate watermark values for the various WM regs based on current mode
2730  * and plane configuration.
2731  *
2732  * There are several cases to deal with here:
2733  *   - normal (i.e. non-self-refresh)
2734  *   - self-refresh (SR) mode
2735  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2736  *   - lines are small relative to FIFO size (buffer can hold more than 2
2737  *     lines), so need to account for TLB latency
2738  *
2739  *   The normal calculation is:
2740  *     watermark = dotclock * bytes per pixel * latency
2741  *   where latency is platform & configuration dependent (we assume pessimal
2742  *   values here).
2743  *
2744  *   The SR calculation is:
2745  *     watermark = (trunc(latency/line time)+1) * surface width *
2746  *       bytes per pixel
2747  *   where
2748  *     line time = htotal / dotclock
2749  *     surface width = hdisplay for normal plane and 64 for cursor
2750  *   and latency is assumed to be high, as above.
2751  *
2752  * The final value programmed to the register should always be rounded up,
2753  * and include an extra 2 entries to account for clock crossings.
2754  *
2755  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2756  * to set the non-SR watermarks to 8.
2757  */
2758 void intel_update_watermarks(struct drm_crtc *crtc)
2759 {
2760         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2761
2762         if (dev_priv->display.update_wm)
2763                 dev_priv->display.update_wm(crtc);
2764 }
2765
2766 void intel_update_sprite_watermarks(struct drm_plane *plane,
2767                                     struct drm_crtc *crtc,
2768                                     uint32_t sprite_width, int pixel_size,
2769                                     bool enabled, bool scaled)
2770 {
2771         struct drm_i915_private *dev_priv = plane->dev->dev_private;
2772
2773         if (dev_priv->display.update_sprite_wm)
2774                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
2775                                                    pixel_size, enabled, scaled);
2776 }
2777
2778 static struct drm_i915_gem_object *
2779 intel_alloc_context_page(struct drm_device *dev)
2780 {
2781         struct drm_i915_gem_object *ctx;
2782         int ret;
2783
2784         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2785
2786         ctx = i915_gem_alloc_object(dev, 4096);
2787         if (!ctx) {
2788                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2789                 return NULL;
2790         }
2791
2792         ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2793         if (ret) {
2794                 DRM_ERROR("failed to pin power context: %d\n", ret);
2795                 goto err_unref;
2796         }
2797
2798         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2799         if (ret) {
2800                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2801                 goto err_unpin;
2802         }
2803
2804         return ctx;
2805
2806 err_unpin:
2807         i915_gem_object_ggtt_unpin(ctx);
2808 err_unref:
2809         drm_gem_object_unreference(&ctx->base);
2810         return NULL;
2811 }
2812
2813 /**
2814  * Lock protecting IPS related data structures
2815  */
2816 DEFINE_SPINLOCK(mchdev_lock);
2817
2818 /* Global for IPS driver to get at the current i915 device. Protected by
2819  * mchdev_lock. */
2820 static struct drm_i915_private *i915_mch_dev;
2821
2822 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2823 {
2824         struct drm_i915_private *dev_priv = dev->dev_private;
2825         u16 rgvswctl;
2826
2827         assert_spin_locked(&mchdev_lock);
2828
2829         rgvswctl = I915_READ16(MEMSWCTL);
2830         if (rgvswctl & MEMCTL_CMD_STS) {
2831                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2832                 return false; /* still busy with another command */
2833         }
2834
2835         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2836                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2837         I915_WRITE16(MEMSWCTL, rgvswctl);
2838         POSTING_READ16(MEMSWCTL);
2839
2840         rgvswctl |= MEMCTL_CMD_STS;
2841         I915_WRITE16(MEMSWCTL, rgvswctl);
2842
2843         return true;
2844 }
2845
2846 static void ironlake_enable_drps(struct drm_device *dev)
2847 {
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849         u32 rgvmodectl = I915_READ(MEMMODECTL);
2850         u8 fmax, fmin, fstart, vstart;
2851
2852         spin_lock_irq(&mchdev_lock);
2853
2854         /* Enable temp reporting */
2855         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2856         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2857
2858         /* 100ms RC evaluation intervals */
2859         I915_WRITE(RCUPEI, 100000);
2860         I915_WRITE(RCDNEI, 100000);
2861
2862         /* Set max/min thresholds to 90ms and 80ms respectively */
2863         I915_WRITE(RCBMAXAVG, 90000);
2864         I915_WRITE(RCBMINAVG, 80000);
2865
2866         I915_WRITE(MEMIHYST, 1);
2867
2868         /* Set up min, max, and cur for interrupt handling */
2869         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2870         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2871         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2872                 MEMMODE_FSTART_SHIFT;
2873
2874         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2875                 PXVFREQ_PX_SHIFT;
2876
2877         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2878         dev_priv->ips.fstart = fstart;
2879
2880         dev_priv->ips.max_delay = fstart;
2881         dev_priv->ips.min_delay = fmin;
2882         dev_priv->ips.cur_delay = fstart;
2883
2884         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2885                          fmax, fmin, fstart);
2886
2887         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2888
2889         /*
2890          * Interrupts will be enabled in ironlake_irq_postinstall
2891          */
2892
2893         I915_WRITE(VIDSTART, vstart);
2894         POSTING_READ(VIDSTART);
2895
2896         rgvmodectl |= MEMMODE_SWMODE_EN;
2897         I915_WRITE(MEMMODECTL, rgvmodectl);
2898
2899         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2900                 DRM_ERROR("stuck trying to change perf mode\n");
2901         mdelay(1);
2902
2903         ironlake_set_drps(dev, fstart);
2904
2905         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2906                 I915_READ(0x112e0);
2907         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2908         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2909         getrawmonotonic(&dev_priv->ips.last_time2);
2910
2911         spin_unlock_irq(&mchdev_lock);
2912 }
2913
2914 static void ironlake_disable_drps(struct drm_device *dev)
2915 {
2916         struct drm_i915_private *dev_priv = dev->dev_private;
2917         u16 rgvswctl;
2918
2919         spin_lock_irq(&mchdev_lock);
2920
2921         rgvswctl = I915_READ16(MEMSWCTL);
2922
2923         /* Ack interrupts, disable EFC interrupt */
2924         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2925         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2926         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2927         I915_WRITE(DEIIR, DE_PCU_EVENT);
2928         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2929
2930         /* Go back to the starting frequency */
2931         ironlake_set_drps(dev, dev_priv->ips.fstart);
2932         mdelay(1);
2933         rgvswctl |= MEMCTL_CMD_STS;
2934         I915_WRITE(MEMSWCTL, rgvswctl);
2935         mdelay(1);
2936
2937         spin_unlock_irq(&mchdev_lock);
2938 }
2939
2940 /* There's a funny hw issue where the hw returns all 0 when reading from
2941  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2942  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2943  * all limits and the gpu stuck at whatever frequency it is at atm).
2944  */
2945 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2946 {
2947         u32 limits;
2948
2949         /* Only set the down limit when we've reached the lowest level to avoid
2950          * getting more interrupts, otherwise leave this clear. This prevents a
2951          * race in the hw when coming out of rc6: There's a tiny window where
2952          * the hw runs at the minimal clock before selecting the desired
2953          * frequency, if the down threshold expires in that window we will not
2954          * receive a down interrupt. */
2955         limits = dev_priv->rps.max_freq_softlimit << 24;
2956         if (val <= dev_priv->rps.min_freq_softlimit)
2957                 limits |= dev_priv->rps.min_freq_softlimit << 16;
2958
2959         return limits;
2960 }
2961
2962 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
2963 {
2964         int new_power;
2965
2966         new_power = dev_priv->rps.power;
2967         switch (dev_priv->rps.power) {
2968         case LOW_POWER:
2969                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
2970                         new_power = BETWEEN;
2971                 break;
2972
2973         case BETWEEN:
2974                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
2975                         new_power = LOW_POWER;
2976                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
2977                         new_power = HIGH_POWER;
2978                 break;
2979
2980         case HIGH_POWER:
2981                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
2982                         new_power = BETWEEN;
2983                 break;
2984         }
2985         /* Max/min bins are special */
2986         if (val == dev_priv->rps.min_freq_softlimit)
2987                 new_power = LOW_POWER;
2988         if (val == dev_priv->rps.max_freq_softlimit)
2989                 new_power = HIGH_POWER;
2990         if (new_power == dev_priv->rps.power)
2991                 return;
2992
2993         /* Note the units here are not exactly 1us, but 1280ns. */
2994         switch (new_power) {
2995         case LOW_POWER:
2996                 /* Upclock if more than 95% busy over 16ms */
2997                 I915_WRITE(GEN6_RP_UP_EI, 12500);
2998                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
2999
3000                 /* Downclock if less than 85% busy over 32ms */
3001                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3002                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3003
3004                 I915_WRITE(GEN6_RP_CONTROL,
3005                            GEN6_RP_MEDIA_TURBO |
3006                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3007                            GEN6_RP_MEDIA_IS_GFX |
3008                            GEN6_RP_ENABLE |
3009                            GEN6_RP_UP_BUSY_AVG |
3010                            GEN6_RP_DOWN_IDLE_AVG);
3011                 break;
3012
3013         case BETWEEN:
3014                 /* Upclock if more than 90% busy over 13ms */
3015                 I915_WRITE(GEN6_RP_UP_EI, 10250);
3016                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3017
3018                 /* Downclock if less than 75% busy over 32ms */
3019                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3020                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3021
3022                 I915_WRITE(GEN6_RP_CONTROL,
3023                            GEN6_RP_MEDIA_TURBO |
3024                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3025                            GEN6_RP_MEDIA_IS_GFX |
3026                            GEN6_RP_ENABLE |
3027                            GEN6_RP_UP_BUSY_AVG |
3028                            GEN6_RP_DOWN_IDLE_AVG);
3029                 break;
3030
3031         case HIGH_POWER:
3032                 /* Upclock if more than 85% busy over 10ms */
3033                 I915_WRITE(GEN6_RP_UP_EI, 8000);
3034                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3035
3036                 /* Downclock if less than 60% busy over 32ms */
3037                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3038                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3039
3040                 I915_WRITE(GEN6_RP_CONTROL,
3041                            GEN6_RP_MEDIA_TURBO |
3042                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3043                            GEN6_RP_MEDIA_IS_GFX |
3044                            GEN6_RP_ENABLE |
3045                            GEN6_RP_UP_BUSY_AVG |
3046                            GEN6_RP_DOWN_IDLE_AVG);
3047                 break;
3048         }
3049
3050         dev_priv->rps.power = new_power;
3051         dev_priv->rps.last_adj = 0;
3052 }
3053
3054 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3055 {
3056         u32 mask = 0;
3057
3058         if (val > dev_priv->rps.min_freq_softlimit)
3059                 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3060         if (val < dev_priv->rps.max_freq_softlimit)
3061                 mask |= GEN6_PM_RP_UP_THRESHOLD;
3062
3063         /* IVB and SNB hard hangs on looping batchbuffer
3064          * if GEN6_PM_UP_EI_EXPIRED is masked.
3065          */
3066         if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3067                 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3068
3069         return ~mask;
3070 }
3071
3072 /* gen6_set_rps is called to update the frequency request, but should also be
3073  * called when the range (min_delay and max_delay) is modified so that we can
3074  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3075 void gen6_set_rps(struct drm_device *dev, u8 val)
3076 {
3077         struct drm_i915_private *dev_priv = dev->dev_private;
3078
3079         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3080         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3081         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3082
3083         /* min/max delay may still have been modified so be sure to
3084          * write the limits value.
3085          */
3086         if (val != dev_priv->rps.cur_freq) {
3087                 gen6_set_rps_thresholds(dev_priv, val);
3088
3089                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3090                         I915_WRITE(GEN6_RPNSWREQ,
3091                                    HSW_FREQUENCY(val));
3092                 else
3093                         I915_WRITE(GEN6_RPNSWREQ,
3094                                    GEN6_FREQUENCY(val) |
3095                                    GEN6_OFFSET(0) |
3096                                    GEN6_AGGRESSIVE_TURBO);
3097         }
3098
3099         /* Make sure we continue to get interrupts
3100          * until we hit the minimum or maximum frequencies.
3101          */
3102         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3103         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3104
3105         POSTING_READ(GEN6_RPNSWREQ);
3106
3107         dev_priv->rps.cur_freq = val;
3108         trace_intel_gpu_freq_change(val * 50);
3109 }
3110
3111 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3112  *
3113  * * If Gfx is Idle, then
3114  * 1. Mask Turbo interrupts
3115  * 2. Bring up Gfx clock
3116  * 3. Change the freq to Rpn and wait till P-Unit updates freq
3117  * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3118  * 5. Unmask Turbo interrupts
3119 */
3120 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3121 {
3122         /*
3123          * When we are idle.  Drop to min voltage state.
3124          */
3125
3126         if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3127                 return;
3128
3129         /* Mask turbo interrupt so that they will not come in between */
3130         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3131
3132         vlv_force_gfx_clock(dev_priv, true);
3133
3134         dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3135
3136         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3137                                         dev_priv->rps.min_freq_softlimit);
3138
3139         if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3140                                 & GENFREQSTATUS) == 0, 5))
3141                 DRM_ERROR("timed out waiting for Punit\n");
3142
3143         vlv_force_gfx_clock(dev_priv, false);
3144
3145         I915_WRITE(GEN6_PMINTRMSK,
3146                    gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3147 }
3148
3149 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3150 {
3151         struct drm_device *dev = dev_priv->dev;
3152
3153         mutex_lock(&dev_priv->rps.hw_lock);
3154         if (dev_priv->rps.enabled) {
3155                 if (IS_VALLEYVIEW(dev))
3156                         vlv_set_rps_idle(dev_priv);
3157                 else
3158                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3159                 dev_priv->rps.last_adj = 0;
3160         }
3161         mutex_unlock(&dev_priv->rps.hw_lock);
3162 }
3163
3164 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3165 {
3166         struct drm_device *dev = dev_priv->dev;
3167
3168         mutex_lock(&dev_priv->rps.hw_lock);
3169         if (dev_priv->rps.enabled) {
3170                 if (IS_VALLEYVIEW(dev))
3171                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3172                 else
3173                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3174                 dev_priv->rps.last_adj = 0;
3175         }
3176         mutex_unlock(&dev_priv->rps.hw_lock);
3177 }
3178
3179 void valleyview_set_rps(struct drm_device *dev, u8 val)
3180 {
3181         struct drm_i915_private *dev_priv = dev->dev_private;
3182
3183         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3184         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3185         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3186
3187         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3188                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3189                          dev_priv->rps.cur_freq,
3190                          vlv_gpu_freq(dev_priv, val), val);
3191
3192         if (val != dev_priv->rps.cur_freq)
3193                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3194
3195         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3196
3197         dev_priv->rps.cur_freq = val;
3198         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3199 }
3200
3201 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3202 {
3203         struct drm_i915_private *dev_priv = dev->dev_private;
3204
3205         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3206         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3207                                 ~dev_priv->pm_rps_events);
3208         /* Complete PM interrupt masking here doesn't race with the rps work
3209          * item again unmasking PM interrupts because that is using a different
3210          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3211          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3212
3213         spin_lock_irq(&dev_priv->irq_lock);
3214         dev_priv->rps.pm_iir = 0;
3215         spin_unlock_irq(&dev_priv->irq_lock);
3216
3217         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3218 }
3219
3220 static void gen6_disable_rps(struct drm_device *dev)
3221 {
3222         struct drm_i915_private *dev_priv = dev->dev_private;
3223
3224         I915_WRITE(GEN6_RC_CONTROL, 0);
3225         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3226
3227         gen6_disable_rps_interrupts(dev);
3228 }
3229
3230 static void valleyview_disable_rps(struct drm_device *dev)
3231 {
3232         struct drm_i915_private *dev_priv = dev->dev_private;
3233
3234         I915_WRITE(GEN6_RC_CONTROL, 0);
3235
3236         gen6_disable_rps_interrupts(dev);
3237 }
3238
3239 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3240 {
3241         if (IS_VALLEYVIEW(dev)) {
3242                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3243                         mode = GEN6_RC_CTL_RC6_ENABLE;
3244                 else
3245                         mode = 0;
3246         }
3247         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3248                  (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3249                  (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3250                  (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3251 }
3252
3253 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3254 {
3255         /* No RC6 before Ironlake */
3256         if (INTEL_INFO(dev)->gen < 5)
3257                 return 0;
3258
3259         /* RC6 is only on Ironlake mobile not on desktop */
3260         if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3261                 return 0;
3262
3263         /* Respect the kernel parameter if it is set */
3264         if (enable_rc6 >= 0) {
3265                 int mask;
3266
3267                 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3268                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3269                                INTEL_RC6pp_ENABLE;
3270                 else
3271                         mask = INTEL_RC6_ENABLE;
3272
3273                 if ((enable_rc6 & mask) != enable_rc6)
3274                         DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3275                                  enable_rc6, enable_rc6 & mask, mask);
3276
3277                 return enable_rc6 & mask;
3278         }
3279
3280         /* Disable RC6 on Ironlake */
3281         if (INTEL_INFO(dev)->gen == 5)
3282                 return 0;
3283
3284         if (IS_IVYBRIDGE(dev))
3285                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3286
3287         return INTEL_RC6_ENABLE;
3288 }
3289
3290 int intel_enable_rc6(const struct drm_device *dev)
3291 {
3292         return i915.enable_rc6;
3293 }
3294
3295 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3296 {
3297         struct drm_i915_private *dev_priv = dev->dev_private;
3298
3299         spin_lock_irq(&dev_priv->irq_lock);
3300         WARN_ON(dev_priv->rps.pm_iir);
3301         snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3302         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3303         spin_unlock_irq(&dev_priv->irq_lock);
3304 }
3305
3306 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3307 {
3308         /* All of these values are in units of 50MHz */
3309         dev_priv->rps.cur_freq          = 0;
3310         /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3311         dev_priv->rps.rp1_freq          = (rp_state_cap >>  8) & 0xff;
3312         dev_priv->rps.rp0_freq          = (rp_state_cap >>  0) & 0xff;
3313         dev_priv->rps.min_freq          = (rp_state_cap >> 16) & 0xff;
3314         /* XXX: only BYT has a special efficient freq */
3315         dev_priv->rps.efficient_freq    = dev_priv->rps.rp1_freq;
3316         /* hw_max = RP0 until we check for overclocking */
3317         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
3318
3319         /* Preserve min/max settings in case of re-init */
3320         if (dev_priv->rps.max_freq_softlimit == 0)
3321                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3322
3323         if (dev_priv->rps.min_freq_softlimit == 0)
3324                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3325 }
3326
3327 static void gen8_enable_rps(struct drm_device *dev)
3328 {
3329         struct drm_i915_private *dev_priv = dev->dev_private;
3330         struct intel_ring_buffer *ring;
3331         uint32_t rc6_mask = 0, rp_state_cap;
3332         int unused;
3333
3334         /* 1a: Software RC state - RC0 */
3335         I915_WRITE(GEN6_RC_STATE, 0);
3336
3337         /* 1c & 1d: Get forcewake during program sequence. Although the driver
3338          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3339         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3340
3341         /* 2a: Disable RC states. */
3342         I915_WRITE(GEN6_RC_CONTROL, 0);
3343
3344         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3345         parse_rp_state_cap(dev_priv, rp_state_cap);
3346
3347         /* 2b: Program RC6 thresholds.*/
3348         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3349         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3350         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3351         for_each_ring(ring, dev_priv, unused)
3352                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3353         I915_WRITE(GEN6_RC_SLEEP, 0);
3354         I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3355
3356         /* 3: Enable RC6 */
3357         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3358                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3359         intel_print_rc6_info(dev, rc6_mask);
3360         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3361                                     GEN6_RC_CTL_EI_MODE(1) |
3362                                     rc6_mask);
3363
3364         /* 4 Program defaults and thresholds for RPS*/
3365         I915_WRITE(GEN6_RPNSWREQ,
3366                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3367         I915_WRITE(GEN6_RC_VIDEO_FREQ,
3368                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3369         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3370         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3371
3372         /* Docs recommend 900MHz, and 300 MHz respectively */
3373         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3374                    dev_priv->rps.max_freq_softlimit << 24 |
3375                    dev_priv->rps.min_freq_softlimit << 16);
3376
3377         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3378         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3379         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3380         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3381
3382         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3383
3384         /* 5: Enable RPS */
3385         I915_WRITE(GEN6_RP_CONTROL,
3386                    GEN6_RP_MEDIA_TURBO |
3387                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3388                    GEN6_RP_MEDIA_IS_GFX |
3389                    GEN6_RP_ENABLE |
3390                    GEN6_RP_UP_BUSY_AVG |
3391                    GEN6_RP_DOWN_IDLE_AVG);
3392
3393         /* 6: Ring frequency + overclocking (our driver does this later */
3394
3395         gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3396
3397         gen6_enable_rps_interrupts(dev);
3398
3399         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3400 }
3401
3402 static void gen6_enable_rps(struct drm_device *dev)
3403 {
3404         struct drm_i915_private *dev_priv = dev->dev_private;
3405         struct intel_ring_buffer *ring;
3406         u32 rp_state_cap;
3407         u32 gt_perf_status;
3408         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3409         u32 gtfifodbg;
3410         int rc6_mode;
3411         int i, ret;
3412
3413         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3414
3415         /* Here begins a magic sequence of register writes to enable
3416          * auto-downclocking.
3417          *
3418          * Perhaps there might be some value in exposing these to
3419          * userspace...
3420          */
3421         I915_WRITE(GEN6_RC_STATE, 0);
3422
3423         /* Clear the DBG now so we don't confuse earlier errors */
3424         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3425                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3426                 I915_WRITE(GTFIFODBG, gtfifodbg);
3427         }
3428
3429         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3430
3431         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3432         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3433
3434         parse_rp_state_cap(dev_priv, rp_state_cap);
3435
3436         /* disable the counters and set deterministic thresholds */
3437         I915_WRITE(GEN6_RC_CONTROL, 0);
3438
3439         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3440         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3441         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3442         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3443         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3444
3445         for_each_ring(ring, dev_priv, i)
3446                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3447
3448         I915_WRITE(GEN6_RC_SLEEP, 0);
3449         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3450         if (IS_IVYBRIDGE(dev))
3451                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3452         else
3453                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3454         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3455         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3456
3457         /* Check if we are enabling RC6 */
3458         rc6_mode = intel_enable_rc6(dev_priv->dev);
3459         if (rc6_mode & INTEL_RC6_ENABLE)
3460                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3461
3462         /* We don't use those on Haswell */
3463         if (!IS_HASWELL(dev)) {
3464                 if (rc6_mode & INTEL_RC6p_ENABLE)
3465                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3466
3467                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3468                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3469         }
3470
3471         intel_print_rc6_info(dev, rc6_mask);
3472
3473         I915_WRITE(GEN6_RC_CONTROL,
3474                    rc6_mask |
3475                    GEN6_RC_CTL_EI_MODE(1) |
3476                    GEN6_RC_CTL_HW_ENABLE);
3477
3478         /* Power down if completely idle for over 50ms */
3479         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3480         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3481
3482         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3483         if (ret)
3484                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3485
3486         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3487         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3488                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3489                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3490                                  (pcu_mbox & 0xff) * 50);
3491                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3492         }
3493
3494         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3495         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3496
3497         gen6_enable_rps_interrupts(dev);
3498
3499         rc6vids = 0;
3500         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3501         if (IS_GEN6(dev) && ret) {
3502                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3503         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3504                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3505                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3506                 rc6vids &= 0xffff00;
3507                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3508                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3509                 if (ret)
3510                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3511         }
3512
3513         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3514 }
3515
3516 static void __gen6_update_ring_freq(struct drm_device *dev)
3517 {
3518         struct drm_i915_private *dev_priv = dev->dev_private;
3519         int min_freq = 15;
3520         unsigned int gpu_freq;
3521         unsigned int max_ia_freq, min_ring_freq;
3522         int scaling_factor = 180;
3523         struct cpufreq_policy *policy;
3524
3525         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3526
3527         policy = cpufreq_cpu_get(0);
3528         if (policy) {
3529                 max_ia_freq = policy->cpuinfo.max_freq;
3530                 cpufreq_cpu_put(policy);
3531         } else {
3532                 /*
3533                  * Default to measured freq if none found, PCU will ensure we
3534                  * don't go over
3535                  */
3536                 max_ia_freq = tsc_khz;
3537         }
3538
3539         /* Convert from kHz to MHz */
3540         max_ia_freq /= 1000;
3541
3542         min_ring_freq = I915_READ(DCLK) & 0xf;
3543         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3544         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3545
3546         /*
3547          * For each potential GPU frequency, load a ring frequency we'd like
3548          * to use for memory access.  We do this by specifying the IA frequency
3549          * the PCU should use as a reference to determine the ring frequency.
3550          */
3551         for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3552              gpu_freq--) {
3553                 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3554                 unsigned int ia_freq = 0, ring_freq = 0;
3555
3556                 if (INTEL_INFO(dev)->gen >= 8) {
3557                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
3558                         ring_freq = max(min_ring_freq, gpu_freq);
3559                 } else if (IS_HASWELL(dev)) {
3560                         ring_freq = mult_frac(gpu_freq, 5, 4);
3561                         ring_freq = max(min_ring_freq, ring_freq);
3562                         /* leave ia_freq as the default, chosen by cpufreq */
3563                 } else {
3564                         /* On older processors, there is no separate ring
3565                          * clock domain, so in order to boost the bandwidth
3566                          * of the ring, we need to upclock the CPU (ia_freq).
3567                          *
3568                          * For GPU frequencies less than 750MHz,
3569                          * just use the lowest ring freq.
3570                          */
3571                         if (gpu_freq < min_freq)
3572                                 ia_freq = 800;
3573                         else
3574                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3575                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3576                 }
3577
3578                 sandybridge_pcode_write(dev_priv,
3579                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3580                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3581                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3582                                         gpu_freq);
3583         }
3584 }
3585
3586 void gen6_update_ring_freq(struct drm_device *dev)
3587 {
3588         struct drm_i915_private *dev_priv = dev->dev_private;
3589
3590         if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3591                 return;
3592
3593         mutex_lock(&dev_priv->rps.hw_lock);
3594         __gen6_update_ring_freq(dev);
3595         mutex_unlock(&dev_priv->rps.hw_lock);
3596 }
3597
3598 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3599 {
3600         u32 val, rp0;
3601
3602         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3603
3604         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3605         /* Clamp to max */
3606         rp0 = min_t(u32, rp0, 0xea);
3607
3608         return rp0;
3609 }
3610
3611 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3612 {
3613         u32 val, rpe;
3614
3615         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3616         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3617         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3618         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3619
3620         return rpe;
3621 }
3622
3623 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3624 {
3625         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3626 }
3627
3628 /* Check that the pctx buffer wasn't move under us. */
3629 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3630 {
3631         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3632
3633         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3634                              dev_priv->vlv_pctx->stolen->start);
3635 }
3636
3637 static void valleyview_setup_pctx(struct drm_device *dev)
3638 {
3639         struct drm_i915_private *dev_priv = dev->dev_private;
3640         struct drm_i915_gem_object *pctx;
3641         unsigned long pctx_paddr;
3642         u32 pcbr;
3643         int pctx_size = 24*1024;
3644
3645         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3646
3647         pcbr = I915_READ(VLV_PCBR);
3648         if (pcbr) {
3649                 /* BIOS set it up already, grab the pre-alloc'd space */
3650                 int pcbr_offset;
3651
3652                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3653                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3654                                                                       pcbr_offset,
3655                                                                       I915_GTT_OFFSET_NONE,
3656                                                                       pctx_size);
3657                 goto out;
3658         }
3659
3660         /*
3661          * From the Gunit register HAS:
3662          * The Gfx driver is expected to program this register and ensure
3663          * proper allocation within Gfx stolen memory.  For example, this
3664          * register should be programmed such than the PCBR range does not
3665          * overlap with other ranges, such as the frame buffer, protected
3666          * memory, or any other relevant ranges.
3667          */
3668         pctx = i915_gem_object_create_stolen(dev, pctx_size);
3669         if (!pctx) {
3670                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3671                 return;
3672         }
3673
3674         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3675         I915_WRITE(VLV_PCBR, pctx_paddr);
3676
3677 out:
3678         dev_priv->vlv_pctx = pctx;
3679 }
3680
3681 static void valleyview_cleanup_pctx(struct drm_device *dev)
3682 {
3683         struct drm_i915_private *dev_priv = dev->dev_private;
3684
3685         if (WARN_ON(!dev_priv->vlv_pctx))
3686                 return;
3687
3688         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3689         dev_priv->vlv_pctx = NULL;
3690 }
3691
3692 static void valleyview_init_gt_powersave(struct drm_device *dev)
3693 {
3694         struct drm_i915_private *dev_priv = dev->dev_private;
3695
3696         valleyview_setup_pctx(dev);
3697
3698         mutex_lock(&dev_priv->rps.hw_lock);
3699
3700         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3701         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3702         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3703                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3704                          dev_priv->rps.max_freq);
3705
3706         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3707         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3708                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3709                          dev_priv->rps.efficient_freq);
3710
3711         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3712         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3713                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3714                          dev_priv->rps.min_freq);
3715
3716         /* Preserve min/max settings in case of re-init */
3717         if (dev_priv->rps.max_freq_softlimit == 0)
3718                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3719
3720         if (dev_priv->rps.min_freq_softlimit == 0)
3721                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3722
3723         mutex_unlock(&dev_priv->rps.hw_lock);
3724 }
3725
3726 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
3727 {
3728         valleyview_cleanup_pctx(dev);
3729 }
3730
3731 static void valleyview_enable_rps(struct drm_device *dev)
3732 {
3733         struct drm_i915_private *dev_priv = dev->dev_private;
3734         struct intel_ring_buffer *ring;
3735         u32 gtfifodbg, val, rc6_mode = 0;
3736         int i;
3737
3738         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3739
3740         valleyview_check_pctx(dev_priv);
3741
3742         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3743                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3744                                  gtfifodbg);
3745                 I915_WRITE(GTFIFODBG, gtfifodbg);
3746         }
3747
3748         /* If VLV, Forcewake all wells, else re-direct to regular path */
3749         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3750
3751         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3752         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3753         I915_WRITE(GEN6_RP_UP_EI, 66000);
3754         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3755
3756         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3757
3758         I915_WRITE(GEN6_RP_CONTROL,
3759                    GEN6_RP_MEDIA_TURBO |
3760                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3761                    GEN6_RP_MEDIA_IS_GFX |
3762                    GEN6_RP_ENABLE |
3763                    GEN6_RP_UP_BUSY_AVG |
3764                    GEN6_RP_DOWN_IDLE_CONT);
3765
3766         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3767         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3768         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3769
3770         for_each_ring(ring, dev_priv, i)
3771                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3772
3773         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
3774
3775         /* allows RC6 residency counter to work */
3776         I915_WRITE(VLV_COUNTER_CONTROL,
3777                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3778                                       VLV_MEDIA_RC6_COUNT_EN |
3779                                       VLV_RENDER_RC6_COUNT_EN));
3780         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3781                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
3782
3783         intel_print_rc6_info(dev, rc6_mode);
3784
3785         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3786
3787         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3788
3789         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3790         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3791
3792         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
3793         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3794                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3795                          dev_priv->rps.cur_freq);
3796
3797         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3798                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3799                          dev_priv->rps.efficient_freq);
3800
3801         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
3802
3803         gen6_enable_rps_interrupts(dev);
3804
3805         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3806 }
3807
3808 void ironlake_teardown_rc6(struct drm_device *dev)
3809 {
3810         struct drm_i915_private *dev_priv = dev->dev_private;
3811
3812         if (dev_priv->ips.renderctx) {
3813                 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3814                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3815                 dev_priv->ips.renderctx = NULL;
3816         }
3817
3818         if (dev_priv->ips.pwrctx) {
3819                 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3820                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3821                 dev_priv->ips.pwrctx = NULL;
3822         }
3823 }
3824
3825 static void ironlake_disable_rc6(struct drm_device *dev)
3826 {
3827         struct drm_i915_private *dev_priv = dev->dev_private;
3828
3829         if (I915_READ(PWRCTXA)) {
3830                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3831                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3832                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3833                          50);
3834
3835                 I915_WRITE(PWRCTXA, 0);
3836                 POSTING_READ(PWRCTXA);
3837
3838                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3839                 POSTING_READ(RSTDBYCTL);
3840         }
3841 }
3842
3843 static int ironlake_setup_rc6(struct drm_device *dev)
3844 {
3845         struct drm_i915_private *dev_priv = dev->dev_private;
3846
3847         if (dev_priv->ips.renderctx == NULL)
3848                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3849         if (!dev_priv->ips.renderctx)
3850                 return -ENOMEM;
3851
3852         if (dev_priv->ips.pwrctx == NULL)
3853                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3854         if (!dev_priv->ips.pwrctx) {
3855                 ironlake_teardown_rc6(dev);
3856                 return -ENOMEM;
3857         }
3858
3859         return 0;
3860 }
3861
3862 static void ironlake_enable_rc6(struct drm_device *dev)
3863 {
3864         struct drm_i915_private *dev_priv = dev->dev_private;
3865         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3866         bool was_interruptible;
3867         int ret;
3868
3869         /* rc6 disabled by default due to repeated reports of hanging during
3870          * boot and resume.
3871          */
3872         if (!intel_enable_rc6(dev))
3873                 return;
3874
3875         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3876
3877         ret = ironlake_setup_rc6(dev);
3878         if (ret)
3879                 return;
3880
3881         was_interruptible = dev_priv->mm.interruptible;
3882         dev_priv->mm.interruptible = false;
3883
3884         /*
3885          * GPU can automatically power down the render unit if given a page
3886          * to save state.
3887          */
3888         ret = intel_ring_begin(ring, 6);
3889         if (ret) {
3890                 ironlake_teardown_rc6(dev);
3891                 dev_priv->mm.interruptible = was_interruptible;
3892                 return;
3893         }
3894
3895         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3896         intel_ring_emit(ring, MI_SET_CONTEXT);
3897         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
3898                         MI_MM_SPACE_GTT |
3899                         MI_SAVE_EXT_STATE_EN |
3900                         MI_RESTORE_EXT_STATE_EN |
3901                         MI_RESTORE_INHIBIT);
3902         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3903         intel_ring_emit(ring, MI_NOOP);
3904         intel_ring_emit(ring, MI_FLUSH);
3905         intel_ring_advance(ring);
3906
3907         /*
3908          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3909          * does an implicit flush, combined with MI_FLUSH above, it should be
3910          * safe to assume that renderctx is valid
3911          */
3912         ret = intel_ring_idle(ring);
3913         dev_priv->mm.interruptible = was_interruptible;
3914         if (ret) {
3915                 DRM_ERROR("failed to enable ironlake power savings\n");
3916                 ironlake_teardown_rc6(dev);
3917                 return;
3918         }
3919
3920         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
3921         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3922
3923         intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
3924 }
3925
3926 static unsigned long intel_pxfreq(u32 vidfreq)
3927 {
3928         unsigned long freq;
3929         int div = (vidfreq & 0x3f0000) >> 16;
3930         int post = (vidfreq & 0x3000) >> 12;
3931         int pre = (vidfreq & 0x7);
3932
3933         if (!pre)
3934                 return 0;
3935
3936         freq = ((div * 133333) / ((1<<post) * pre));
3937
3938         return freq;
3939 }
3940
3941 static const struct cparams {
3942         u16 i;
3943         u16 t;
3944         u16 m;
3945         u16 c;
3946 } cparams[] = {
3947         { 1, 1333, 301, 28664 },
3948         { 1, 1066, 294, 24460 },
3949         { 1, 800, 294, 25192 },
3950         { 0, 1333, 276, 27605 },
3951         { 0, 1066, 276, 27605 },
3952         { 0, 800, 231, 23784 },
3953 };
3954
3955 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3956 {
3957         u64 total_count, diff, ret;
3958         u32 count1, count2, count3, m = 0, c = 0;
3959         unsigned long now = jiffies_to_msecs(jiffies), diff1;
3960         int i;
3961
3962         assert_spin_locked(&mchdev_lock);
3963
3964         diff1 = now - dev_priv->ips.last_time1;
3965
3966         /* Prevent division-by-zero if we are asking too fast.
3967          * Also, we don't get interesting results if we are polling
3968          * faster than once in 10ms, so just return the saved value
3969          * in such cases.
3970          */
3971         if (diff1 <= 10)
3972                 return dev_priv->ips.chipset_power;
3973
3974         count1 = I915_READ(DMIEC);
3975         count2 = I915_READ(DDREC);
3976         count3 = I915_READ(CSIEC);
3977
3978         total_count = count1 + count2 + count3;
3979
3980         /* FIXME: handle per-counter overflow */
3981         if (total_count < dev_priv->ips.last_count1) {
3982                 diff = ~0UL - dev_priv->ips.last_count1;
3983                 diff += total_count;
3984         } else {
3985                 diff = total_count - dev_priv->ips.last_count1;
3986         }
3987
3988         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3989                 if (cparams[i].i == dev_priv->ips.c_m &&
3990                     cparams[i].t == dev_priv->ips.r_t) {
3991                         m = cparams[i].m;
3992                         c = cparams[i].c;
3993                         break;
3994                 }
3995         }
3996
3997         diff = div_u64(diff, diff1);
3998         ret = ((m * diff) + c);
3999         ret = div_u64(ret, 10);
4000
4001         dev_priv->ips.last_count1 = total_count;
4002         dev_priv->ips.last_time1 = now;
4003
4004         dev_priv->ips.chipset_power = ret;
4005
4006         return ret;
4007 }
4008
4009 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4010 {
4011         struct drm_device *dev = dev_priv->dev;
4012         unsigned long val;
4013
4014         if (INTEL_INFO(dev)->gen != 5)
4015                 return 0;
4016
4017         spin_lock_irq(&mchdev_lock);
4018
4019         val = __i915_chipset_val(dev_priv);
4020
4021         spin_unlock_irq(&mchdev_lock);
4022
4023         return val;
4024 }
4025
4026 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4027 {
4028         unsigned long m, x, b;
4029         u32 tsfs;
4030
4031         tsfs = I915_READ(TSFS);
4032
4033         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4034         x = I915_READ8(TR1);
4035
4036         b = tsfs & TSFS_INTR_MASK;
4037
4038         return ((m * x) / 127) - b;
4039 }
4040
4041 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4042 {
4043         struct drm_device *dev = dev_priv->dev;
4044         static const struct v_table {
4045                 u16 vd; /* in .1 mil */
4046                 u16 vm; /* in .1 mil */
4047         } v_table[] = {
4048                 { 0, 0, },
4049                 { 375, 0, },
4050                 { 500, 0, },
4051                 { 625, 0, },
4052                 { 750, 0, },
4053                 { 875, 0, },
4054                 { 1000, 0, },
4055                 { 1125, 0, },
4056                 { 4125, 3000, },
4057                 { 4125, 3000, },
4058                 { 4125, 3000, },
4059                 { 4125, 3000, },
4060                 { 4125, 3000, },
4061                 { 4125, 3000, },
4062                 { 4125, 3000, },
4063                 { 4125, 3000, },
4064                 { 4125, 3000, },
4065                 { 4125, 3000, },
4066                 { 4125, 3000, },
4067                 { 4125, 3000, },
4068                 { 4125, 3000, },
4069                 { 4125, 3000, },
4070                 { 4125, 3000, },
4071                 { 4125, 3000, },
4072                 { 4125, 3000, },
4073                 { 4125, 3000, },
4074                 { 4125, 3000, },
4075                 { 4125, 3000, },
4076                 { 4125, 3000, },
4077                 { 4125, 3000, },
4078                 { 4125, 3000, },
4079                 { 4125, 3000, },
4080                 { 4250, 3125, },
4081                 { 4375, 3250, },
4082                 { 4500, 3375, },
4083                 { 4625, 3500, },
4084                 { 4750, 3625, },
4085                 { 4875, 3750, },
4086                 { 5000, 3875, },
4087                 { 5125, 4000, },
4088                 { 5250, 4125, },
4089                 { 5375, 4250, },
4090                 { 5500, 4375, },
4091                 { 5625, 4500, },
4092                 { 5750, 4625, },
4093                 { 5875, 4750, },
4094                 { 6000, 4875, },
4095                 { 6125, 5000, },
4096                 { 6250, 5125, },
4097                 { 6375, 5250, },
4098                 { 6500, 5375, },
4099                 { 6625, 5500, },
4100                 { 6750, 5625, },
4101                 { 6875, 5750, },
4102                 { 7000, 5875, },
4103                 { 7125, 6000, },
4104                 { 7250, 6125, },
4105                 { 7375, 6250, },
4106                 { 7500, 6375, },
4107                 { 7625, 6500, },
4108                 { 7750, 6625, },
4109                 { 7875, 6750, },
4110                 { 8000, 6875, },
4111                 { 8125, 7000, },
4112                 { 8250, 7125, },
4113                 { 8375, 7250, },
4114                 { 8500, 7375, },
4115                 { 8625, 7500, },
4116                 { 8750, 7625, },
4117                 { 8875, 7750, },
4118                 { 9000, 7875, },
4119                 { 9125, 8000, },
4120                 { 9250, 8125, },
4121                 { 9375, 8250, },
4122                 { 9500, 8375, },
4123                 { 9625, 8500, },
4124                 { 9750, 8625, },
4125                 { 9875, 8750, },
4126                 { 10000, 8875, },
4127                 { 10125, 9000, },
4128                 { 10250, 9125, },
4129                 { 10375, 9250, },
4130                 { 10500, 9375, },
4131                 { 10625, 9500, },
4132                 { 10750, 9625, },
4133                 { 10875, 9750, },
4134                 { 11000, 9875, },
4135                 { 11125, 10000, },
4136                 { 11250, 10125, },
4137                 { 11375, 10250, },
4138                 { 11500, 10375, },
4139                 { 11625, 10500, },
4140                 { 11750, 10625, },
4141                 { 11875, 10750, },
4142                 { 12000, 10875, },
4143                 { 12125, 11000, },
4144                 { 12250, 11125, },
4145                 { 12375, 11250, },
4146                 { 12500, 11375, },
4147                 { 12625, 11500, },
4148                 { 12750, 11625, },
4149                 { 12875, 11750, },
4150                 { 13000, 11875, },
4151                 { 13125, 12000, },
4152                 { 13250, 12125, },
4153                 { 13375, 12250, },
4154                 { 13500, 12375, },
4155                 { 13625, 12500, },
4156                 { 13750, 12625, },
4157                 { 13875, 12750, },
4158                 { 14000, 12875, },
4159                 { 14125, 13000, },
4160                 { 14250, 13125, },
4161                 { 14375, 13250, },
4162                 { 14500, 13375, },
4163                 { 14625, 13500, },
4164                 { 14750, 13625, },
4165                 { 14875, 13750, },
4166                 { 15000, 13875, },
4167                 { 15125, 14000, },
4168                 { 15250, 14125, },
4169                 { 15375, 14250, },
4170                 { 15500, 14375, },
4171                 { 15625, 14500, },
4172                 { 15750, 14625, },
4173                 { 15875, 14750, },
4174                 { 16000, 14875, },
4175                 { 16125, 15000, },
4176         };
4177         if (INTEL_INFO(dev)->is_mobile)
4178                 return v_table[pxvid].vm;
4179         else
4180                 return v_table[pxvid].vd;
4181 }
4182
4183 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4184 {
4185         struct timespec now, diff1;
4186         u64 diff;
4187         unsigned long diffms;
4188         u32 count;
4189
4190         assert_spin_locked(&mchdev_lock);
4191
4192         getrawmonotonic(&now);
4193         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4194
4195         /* Don't divide by 0 */
4196         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4197         if (!diffms)
4198                 return;
4199
4200         count = I915_READ(GFXEC);
4201
4202         if (count < dev_priv->ips.last_count2) {
4203                 diff = ~0UL - dev_priv->ips.last_count2;
4204                 diff += count;
4205         } else {
4206                 diff = count - dev_priv->ips.last_count2;
4207         }
4208
4209         dev_priv->ips.last_count2 = count;
4210         dev_priv->ips.last_time2 = now;
4211
4212         /* More magic constants... */
4213         diff = diff * 1181;
4214         diff = div_u64(diff, diffms * 10);
4215         dev_priv->ips.gfx_power = diff;
4216 }
4217
4218 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4219 {
4220         struct drm_device *dev = dev_priv->dev;
4221
4222         if (INTEL_INFO(dev)->gen != 5)
4223                 return;
4224
4225         spin_lock_irq(&mchdev_lock);
4226
4227         __i915_update_gfx_val(dev_priv);
4228
4229         spin_unlock_irq(&mchdev_lock);
4230 }
4231
4232 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4233 {
4234         unsigned long t, corr, state1, corr2, state2;
4235         u32 pxvid, ext_v;
4236
4237         assert_spin_locked(&mchdev_lock);
4238
4239         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4240         pxvid = (pxvid >> 24) & 0x7f;
4241         ext_v = pvid_to_extvid(dev_priv, pxvid);
4242
4243         state1 = ext_v;
4244
4245         t = i915_mch_val(dev_priv);
4246
4247         /* Revel in the empirically derived constants */
4248
4249         /* Correction factor in 1/100000 units */
4250         if (t > 80)
4251                 corr = ((t * 2349) + 135940);
4252         else if (t >= 50)
4253                 corr = ((t * 964) + 29317);
4254         else /* < 50 */
4255                 corr = ((t * 301) + 1004);
4256
4257         corr = corr * ((150142 * state1) / 10000 - 78642);
4258         corr /= 100000;
4259         corr2 = (corr * dev_priv->ips.corr);
4260
4261         state2 = (corr2 * state1) / 10000;
4262         state2 /= 100; /* convert to mW */
4263
4264         __i915_update_gfx_val(dev_priv);
4265
4266         return dev_priv->ips.gfx_power + state2;
4267 }
4268
4269 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4270 {
4271         struct drm_device *dev = dev_priv->dev;
4272         unsigned long val;
4273
4274         if (INTEL_INFO(dev)->gen != 5)
4275                 return 0;
4276
4277         spin_lock_irq(&mchdev_lock);
4278
4279         val = __i915_gfx_val(dev_priv);
4280
4281         spin_unlock_irq(&mchdev_lock);
4282
4283         return val;
4284 }
4285
4286 /**
4287  * i915_read_mch_val - return value for IPS use
4288  *
4289  * Calculate and return a value for the IPS driver to use when deciding whether
4290  * we have thermal and power headroom to increase CPU or GPU power budget.
4291  */
4292 unsigned long i915_read_mch_val(void)
4293 {
4294         struct drm_i915_private *dev_priv;
4295         unsigned long chipset_val, graphics_val, ret = 0;
4296
4297         spin_lock_irq(&mchdev_lock);
4298         if (!i915_mch_dev)
4299                 goto out_unlock;
4300         dev_priv = i915_mch_dev;
4301
4302         chipset_val = __i915_chipset_val(dev_priv);
4303         graphics_val = __i915_gfx_val(dev_priv);
4304
4305         ret = chipset_val + graphics_val;
4306
4307 out_unlock:
4308         spin_unlock_irq(&mchdev_lock);
4309
4310         return ret;
4311 }
4312 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4313
4314 /**
4315  * i915_gpu_raise - raise GPU frequency limit
4316  *
4317  * Raise the limit; IPS indicates we have thermal headroom.
4318  */
4319 bool i915_gpu_raise(void)
4320 {
4321         struct drm_i915_private *dev_priv;
4322         bool ret = true;
4323
4324         spin_lock_irq(&mchdev_lock);
4325         if (!i915_mch_dev) {
4326                 ret = false;
4327                 goto out_unlock;
4328         }
4329         dev_priv = i915_mch_dev;
4330
4331         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4332                 dev_priv->ips.max_delay--;
4333
4334 out_unlock:
4335         spin_unlock_irq(&mchdev_lock);
4336
4337         return ret;
4338 }
4339 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4340
4341 /**
4342  * i915_gpu_lower - lower GPU frequency limit
4343  *
4344  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4345  * frequency maximum.
4346  */
4347 bool i915_gpu_lower(void)
4348 {
4349         struct drm_i915_private *dev_priv;
4350         bool ret = true;
4351
4352         spin_lock_irq(&mchdev_lock);
4353         if (!i915_mch_dev) {
4354                 ret = false;
4355                 goto out_unlock;
4356         }
4357         dev_priv = i915_mch_dev;
4358
4359         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4360                 dev_priv->ips.max_delay++;
4361
4362 out_unlock:
4363         spin_unlock_irq(&mchdev_lock);
4364
4365         return ret;
4366 }
4367 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4368
4369 /**
4370  * i915_gpu_busy - indicate GPU business to IPS
4371  *
4372  * Tell the IPS driver whether or not the GPU is busy.
4373  */
4374 bool i915_gpu_busy(void)
4375 {
4376         struct drm_i915_private *dev_priv;
4377         struct intel_ring_buffer *ring;
4378         bool ret = false;
4379         int i;
4380
4381         spin_lock_irq(&mchdev_lock);
4382         if (!i915_mch_dev)
4383                 goto out_unlock;
4384         dev_priv = i915_mch_dev;
4385
4386         for_each_ring(ring, dev_priv, i)
4387                 ret |= !list_empty(&ring->request_list);
4388
4389 out_unlock:
4390         spin_unlock_irq(&mchdev_lock);
4391
4392         return ret;
4393 }
4394 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4395
4396 /**
4397  * i915_gpu_turbo_disable - disable graphics turbo
4398  *
4399  * Disable graphics turbo by resetting the max frequency and setting the
4400  * current frequency to the default.
4401  */
4402 bool i915_gpu_turbo_disable(void)
4403 {
4404         struct drm_i915_private *dev_priv;
4405         bool ret = true;
4406
4407         spin_lock_irq(&mchdev_lock);
4408         if (!i915_mch_dev) {
4409                 ret = false;
4410                 goto out_unlock;
4411         }
4412         dev_priv = i915_mch_dev;
4413
4414         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4415
4416         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4417                 ret = false;
4418
4419 out_unlock:
4420         spin_unlock_irq(&mchdev_lock);
4421
4422         return ret;
4423 }
4424 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4425
4426 /**
4427  * Tells the intel_ips driver that the i915 driver is now loaded, if
4428  * IPS got loaded first.
4429  *
4430  * This awkward dance is so that neither module has to depend on the
4431  * other in order for IPS to do the appropriate communication of
4432  * GPU turbo limits to i915.
4433  */
4434 static void
4435 ips_ping_for_i915_load(void)
4436 {
4437         void (*link)(void);
4438
4439         link = symbol_get(ips_link_to_i915_driver);
4440         if (link) {
4441                 link();
4442                 symbol_put(ips_link_to_i915_driver);
4443         }
4444 }
4445
4446 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4447 {
4448         /* We only register the i915 ips part with intel-ips once everything is
4449          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4450         spin_lock_irq(&mchdev_lock);
4451         i915_mch_dev = dev_priv;
4452         spin_unlock_irq(&mchdev_lock);
4453
4454         ips_ping_for_i915_load();
4455 }
4456
4457 void intel_gpu_ips_teardown(void)
4458 {
4459         spin_lock_irq(&mchdev_lock);
4460         i915_mch_dev = NULL;
4461         spin_unlock_irq(&mchdev_lock);
4462 }
4463
4464 static void intel_init_emon(struct drm_device *dev)
4465 {
4466         struct drm_i915_private *dev_priv = dev->dev_private;
4467         u32 lcfuse;
4468         u8 pxw[16];
4469         int i;
4470
4471         /* Disable to program */
4472         I915_WRITE(ECR, 0);
4473         POSTING_READ(ECR);
4474
4475         /* Program energy weights for various events */
4476         I915_WRITE(SDEW, 0x15040d00);
4477         I915_WRITE(CSIEW0, 0x007f0000);
4478         I915_WRITE(CSIEW1, 0x1e220004);
4479         I915_WRITE(CSIEW2, 0x04000004);
4480
4481         for (i = 0; i < 5; i++)
4482                 I915_WRITE(PEW + (i * 4), 0);
4483         for (i = 0; i < 3; i++)
4484                 I915_WRITE(DEW + (i * 4), 0);
4485
4486         /* Program P-state weights to account for frequency power adjustment */
4487         for (i = 0; i < 16; i++) {
4488                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4489                 unsigned long freq = intel_pxfreq(pxvidfreq);
4490                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4491                         PXVFREQ_PX_SHIFT;
4492                 unsigned long val;
4493
4494                 val = vid * vid;
4495                 val *= (freq / 1000);
4496                 val *= 255;
4497                 val /= (127*127*900);
4498                 if (val > 0xff)
4499                         DRM_ERROR("bad pxval: %ld\n", val);
4500                 pxw[i] = val;
4501         }
4502         /* Render standby states get 0 weight */
4503         pxw[14] = 0;
4504         pxw[15] = 0;
4505
4506         for (i = 0; i < 4; i++) {
4507                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4508                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4509                 I915_WRITE(PXW + (i * 4), val);
4510         }
4511
4512         /* Adjust magic regs to magic values (more experimental results) */
4513         I915_WRITE(OGW0, 0);
4514         I915_WRITE(OGW1, 0);
4515         I915_WRITE(EG0, 0x00007f00);
4516         I915_WRITE(EG1, 0x0000000e);
4517         I915_WRITE(EG2, 0x000e0000);
4518         I915_WRITE(EG3, 0x68000300);
4519         I915_WRITE(EG4, 0x42000000);
4520         I915_WRITE(EG5, 0x00140031);
4521         I915_WRITE(EG6, 0);
4522         I915_WRITE(EG7, 0);
4523
4524         for (i = 0; i < 8; i++)
4525                 I915_WRITE(PXWL + (i * 4), 0);
4526
4527         /* Enable PMON + select events */
4528         I915_WRITE(ECR, 0x80000019);
4529
4530         lcfuse = I915_READ(LCFUSE02);
4531
4532         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4533 }
4534
4535 void intel_init_gt_powersave(struct drm_device *dev)
4536 {
4537         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4538
4539         if (IS_VALLEYVIEW(dev))
4540                 valleyview_init_gt_powersave(dev);
4541 }
4542
4543 void intel_cleanup_gt_powersave(struct drm_device *dev)
4544 {
4545         if (IS_VALLEYVIEW(dev))
4546                 valleyview_cleanup_gt_powersave(dev);
4547 }
4548
4549 void intel_disable_gt_powersave(struct drm_device *dev)
4550 {
4551         struct drm_i915_private *dev_priv = dev->dev_private;
4552
4553         /* Interrupts should be disabled already to avoid re-arming. */
4554         WARN_ON(dev->irq_enabled);
4555
4556         if (IS_IRONLAKE_M(dev)) {
4557                 ironlake_disable_drps(dev);
4558                 ironlake_disable_rc6(dev);
4559         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4560                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4561                 cancel_work_sync(&dev_priv->rps.work);
4562                 mutex_lock(&dev_priv->rps.hw_lock);
4563                 if (IS_VALLEYVIEW(dev))
4564                         valleyview_disable_rps(dev);
4565                 else
4566                         gen6_disable_rps(dev);
4567                 dev_priv->rps.enabled = false;
4568                 mutex_unlock(&dev_priv->rps.hw_lock);
4569         }
4570 }
4571
4572 static void intel_gen6_powersave_work(struct work_struct *work)
4573 {
4574         struct drm_i915_private *dev_priv =
4575                 container_of(work, struct drm_i915_private,
4576                              rps.delayed_resume_work.work);
4577         struct drm_device *dev = dev_priv->dev;
4578
4579         mutex_lock(&dev_priv->rps.hw_lock);
4580
4581         if (IS_VALLEYVIEW(dev)) {
4582                 valleyview_enable_rps(dev);
4583         } else if (IS_BROADWELL(dev)) {
4584                 gen8_enable_rps(dev);
4585                 __gen6_update_ring_freq(dev);
4586         } else {
4587                 gen6_enable_rps(dev);
4588                 __gen6_update_ring_freq(dev);
4589         }
4590         dev_priv->rps.enabled = true;
4591         mutex_unlock(&dev_priv->rps.hw_lock);
4592
4593         intel_runtime_pm_put(dev_priv);
4594 }
4595
4596 void intel_enable_gt_powersave(struct drm_device *dev)
4597 {
4598         struct drm_i915_private *dev_priv = dev->dev_private;
4599
4600         if (IS_IRONLAKE_M(dev)) {
4601                 mutex_lock(&dev->struct_mutex);
4602                 ironlake_enable_drps(dev);
4603                 ironlake_enable_rc6(dev);
4604                 intel_init_emon(dev);
4605                 mutex_unlock(&dev->struct_mutex);
4606         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4607                 /*
4608                  * PCU communication is slow and this doesn't need to be
4609                  * done at any specific time, so do this out of our fast path
4610                  * to make resume and init faster.
4611                  *
4612                  * We depend on the HW RC6 power context save/restore
4613                  * mechanism when entering D3 through runtime PM suspend. So
4614                  * disable RPM until RPS/RC6 is properly setup. We can only
4615                  * get here via the driver load/system resume/runtime resume
4616                  * paths, so the _noresume version is enough (and in case of
4617                  * runtime resume it's necessary).
4618                  */
4619                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4620                                            round_jiffies_up_relative(HZ)))
4621                         intel_runtime_pm_get_noresume(dev_priv);
4622         }
4623 }
4624
4625 void intel_reset_gt_powersave(struct drm_device *dev)
4626 {
4627         struct drm_i915_private *dev_priv = dev->dev_private;
4628
4629         dev_priv->rps.enabled = false;
4630         intel_enable_gt_powersave(dev);
4631 }
4632
4633 static void ibx_init_clock_gating(struct drm_device *dev)
4634 {
4635         struct drm_i915_private *dev_priv = dev->dev_private;
4636
4637         /*
4638          * On Ibex Peak and Cougar Point, we need to disable clock
4639          * gating for the panel power sequencer or it will fail to
4640          * start up when no ports are active.
4641          */
4642         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4643 }
4644
4645 static void g4x_disable_trickle_feed(struct drm_device *dev)
4646 {
4647         struct drm_i915_private *dev_priv = dev->dev_private;
4648         int pipe;
4649
4650         for_each_pipe(pipe) {
4651                 I915_WRITE(DSPCNTR(pipe),
4652                            I915_READ(DSPCNTR(pipe)) |
4653                            DISPPLANE_TRICKLE_FEED_DISABLE);
4654                 intel_flush_primary_plane(dev_priv, pipe);
4655         }
4656 }
4657
4658 static void ilk_init_lp_watermarks(struct drm_device *dev)
4659 {
4660         struct drm_i915_private *dev_priv = dev->dev_private;
4661
4662         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4663         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4664         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4665
4666         /*
4667          * Don't touch WM1S_LP_EN here.
4668          * Doing so could cause underruns.
4669          */
4670 }
4671
4672 static void ironlake_init_clock_gating(struct drm_device *dev)
4673 {
4674         struct drm_i915_private *dev_priv = dev->dev_private;
4675         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4676
4677         /*
4678          * Required for FBC
4679          * WaFbcDisableDpfcClockGating:ilk
4680          */
4681         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4682                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4683                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4684
4685         I915_WRITE(PCH_3DCGDIS0,
4686                    MARIUNIT_CLOCK_GATE_DISABLE |
4687                    SVSMUNIT_CLOCK_GATE_DISABLE);
4688         I915_WRITE(PCH_3DCGDIS1,
4689                    VFMUNIT_CLOCK_GATE_DISABLE);
4690
4691         /*
4692          * According to the spec the following bits should be set in
4693          * order to enable memory self-refresh
4694          * The bit 22/21 of 0x42004
4695          * The bit 5 of 0x42020
4696          * The bit 15 of 0x45000
4697          */
4698         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4699                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4700                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4701         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4702         I915_WRITE(DISP_ARB_CTL,
4703                    (I915_READ(DISP_ARB_CTL) |
4704                     DISP_FBC_WM_DIS));
4705
4706         ilk_init_lp_watermarks(dev);
4707
4708         /*
4709          * Based on the document from hardware guys the following bits
4710          * should be set unconditionally in order to enable FBC.
4711          * The bit 22 of 0x42000
4712          * The bit 22 of 0x42004
4713          * The bit 7,8,9 of 0x42020.
4714          */
4715         if (IS_IRONLAKE_M(dev)) {
4716                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4717                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4718                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4719                            ILK_FBCQ_DIS);
4720                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4721                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4722                            ILK_DPARB_GATE);
4723         }
4724
4725         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4726
4727         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4728                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4729                    ILK_ELPIN_409_SELECT);
4730         I915_WRITE(_3D_CHICKEN2,
4731                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4732                    _3D_CHICKEN2_WM_READ_PIPELINED);
4733
4734         /* WaDisableRenderCachePipelinedFlush:ilk */
4735         I915_WRITE(CACHE_MODE_0,
4736                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4737
4738         /* WaDisable_RenderCache_OperationalFlush:ilk */
4739         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4740
4741         g4x_disable_trickle_feed(dev);
4742
4743         ibx_init_clock_gating(dev);
4744 }
4745
4746 static void cpt_init_clock_gating(struct drm_device *dev)
4747 {
4748         struct drm_i915_private *dev_priv = dev->dev_private;
4749         int pipe;
4750         uint32_t val;
4751
4752         /*
4753          * On Ibex Peak and Cougar Point, we need to disable clock
4754          * gating for the panel power sequencer or it will fail to
4755          * start up when no ports are active.
4756          */
4757         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4758                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4759                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
4760         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4761                    DPLS_EDP_PPS_FIX_DIS);
4762         /* The below fixes the weird display corruption, a few pixels shifted
4763          * downward, on (only) LVDS of some HP laptops with IVY.
4764          */
4765         for_each_pipe(pipe) {
4766                 val = I915_READ(TRANS_CHICKEN2(pipe));
4767                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4768                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4769                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4770                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4771                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4772                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4773                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4774                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4775         }
4776         /* WADP0ClockGatingDisable */
4777         for_each_pipe(pipe) {
4778                 I915_WRITE(TRANS_CHICKEN1(pipe),
4779                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4780         }
4781 }
4782
4783 static void gen6_check_mch_setup(struct drm_device *dev)
4784 {
4785         struct drm_i915_private *dev_priv = dev->dev_private;
4786         uint32_t tmp;
4787
4788         tmp = I915_READ(MCH_SSKPD);
4789         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4790                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4791                 DRM_INFO("This can cause pipe underruns and display issues.\n");
4792                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4793         }
4794 }
4795
4796 static void gen6_init_clock_gating(struct drm_device *dev)
4797 {
4798         struct drm_i915_private *dev_priv = dev->dev_private;
4799         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4800
4801         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4802
4803         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4804                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4805                    ILK_ELPIN_409_SELECT);
4806
4807         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4808         I915_WRITE(_3D_CHICKEN,
4809                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4810
4811         /* WaSetupGtModeTdRowDispatch:snb */
4812         if (IS_SNB_GT1(dev))
4813                 I915_WRITE(GEN6_GT_MODE,
4814                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4815
4816         /* WaDisable_RenderCache_OperationalFlush:snb */
4817         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4818
4819         /*
4820          * BSpec recoomends 8x4 when MSAA is used,
4821          * however in practice 16x4 seems fastest.
4822          *
4823          * Note that PS/WM thread counts depend on the WIZ hashing
4824          * disable bit, which we don't touch here, but it's good
4825          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4826          */
4827         I915_WRITE(GEN6_GT_MODE,
4828                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4829
4830         ilk_init_lp_watermarks(dev);
4831
4832         I915_WRITE(CACHE_MODE_0,
4833                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4834
4835         I915_WRITE(GEN6_UCGCTL1,
4836                    I915_READ(GEN6_UCGCTL1) |
4837                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4838                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4839
4840         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4841          * gating disable must be set.  Failure to set it results in
4842          * flickering pixels due to Z write ordering failures after
4843          * some amount of runtime in the Mesa "fire" demo, and Unigine
4844          * Sanctuary and Tropics, and apparently anything else with
4845          * alpha test or pixel discard.
4846          *
4847          * According to the spec, bit 11 (RCCUNIT) must also be set,
4848          * but we didn't debug actual testcases to find it out.
4849          *
4850          * WaDisableRCCUnitClockGating:snb
4851          * WaDisableRCPBUnitClockGating:snb
4852          */
4853         I915_WRITE(GEN6_UCGCTL2,
4854                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4855                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4856
4857         /* WaStripsFansDisableFastClipPerformanceFix:snb */
4858         I915_WRITE(_3D_CHICKEN3,
4859                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
4860
4861         /*
4862          * Bspec says:
4863          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
4864          * 3DSTATE_SF number of SF output attributes is more than 16."
4865          */
4866         I915_WRITE(_3D_CHICKEN3,
4867                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
4868
4869         /*
4870          * According to the spec the following bits should be
4871          * set in order to enable memory self-refresh and fbc:
4872          * The bit21 and bit22 of 0x42000
4873          * The bit21 and bit22 of 0x42004
4874          * The bit5 and bit7 of 0x42020
4875          * The bit14 of 0x70180
4876          * The bit14 of 0x71180
4877          *
4878          * WaFbcAsynchFlipDisableFbcQueue:snb
4879          */
4880         I915_WRITE(ILK_DISPLAY_CHICKEN1,
4881                    I915_READ(ILK_DISPLAY_CHICKEN1) |
4882                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4883         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4884                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4885                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4886         I915_WRITE(ILK_DSPCLK_GATE_D,
4887                    I915_READ(ILK_DSPCLK_GATE_D) |
4888                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
4889                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4890
4891         g4x_disable_trickle_feed(dev);
4892
4893         cpt_init_clock_gating(dev);
4894
4895         gen6_check_mch_setup(dev);
4896 }
4897
4898 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4899 {
4900         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4901
4902         /*
4903          * WaVSThreadDispatchOverride:ivb,vlv
4904          *
4905          * This actually overrides the dispatch
4906          * mode for all thread types.
4907          */
4908         reg &= ~GEN7_FF_SCHED_MASK;
4909         reg |= GEN7_FF_TS_SCHED_HW;
4910         reg |= GEN7_FF_VS_SCHED_HW;
4911         reg |= GEN7_FF_DS_SCHED_HW;
4912
4913         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4914 }
4915
4916 static void lpt_init_clock_gating(struct drm_device *dev)
4917 {
4918         struct drm_i915_private *dev_priv = dev->dev_private;
4919
4920         /*
4921          * TODO: this bit should only be enabled when really needed, then
4922          * disabled when not needed anymore in order to save power.
4923          */
4924         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4925                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4926                            I915_READ(SOUTH_DSPCLK_GATE_D) |
4927                            PCH_LP_PARTITION_LEVEL_DISABLE);
4928
4929         /* WADPOClockGatingDisable:hsw */
4930         I915_WRITE(_TRANSA_CHICKEN1,
4931                    I915_READ(_TRANSA_CHICKEN1) |
4932                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4933 }
4934
4935 static void lpt_suspend_hw(struct drm_device *dev)
4936 {
4937         struct drm_i915_private *dev_priv = dev->dev_private;
4938
4939         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4940                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4941
4942                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4943                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4944         }
4945 }
4946
4947 static void gen8_init_clock_gating(struct drm_device *dev)
4948 {
4949         struct drm_i915_private *dev_priv = dev->dev_private;
4950         enum pipe pipe;
4951
4952         I915_WRITE(WM3_LP_ILK, 0);
4953         I915_WRITE(WM2_LP_ILK, 0);
4954         I915_WRITE(WM1_LP_ILK, 0);
4955
4956         /* FIXME(BDW): Check all the w/a, some might only apply to
4957          * pre-production hw. */
4958
4959         /* WaDisablePartialInstShootdown:bdw */
4960         I915_WRITE(GEN8_ROW_CHICKEN,
4961                    _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
4962
4963         /* WaDisableThreadStallDopClockGating:bdw */
4964         /* FIXME: Unclear whether we really need this on production bdw. */
4965         I915_WRITE(GEN8_ROW_CHICKEN,
4966                    _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
4967
4968         /*
4969          * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
4970          * pre-production hardware
4971          */
4972         I915_WRITE(HALF_SLICE_CHICKEN3,
4973                    _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
4974         I915_WRITE(HALF_SLICE_CHICKEN3,
4975                    _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4976         I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
4977
4978         I915_WRITE(_3D_CHICKEN3,
4979                    _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
4980
4981         I915_WRITE(COMMON_SLICE_CHICKEN2,
4982                    _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
4983
4984         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4985                    _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
4986
4987         /* WaSwitchSolVfFArbitrationPriority:bdw */
4988         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4989
4990         /* WaPsrDPAMaskVBlankInSRD:bdw */
4991         I915_WRITE(CHICKEN_PAR1_1,
4992                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
4993
4994         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
4995         for_each_pipe(pipe) {
4996                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
4997                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
4998                            BDW_DPRS_MASK_VBLANK_SRD);
4999         }
5000
5001         /* Use Force Non-Coherent whenever executing a 3D context. This is a
5002          * workaround for for a possible hang in the unlikely event a TLB
5003          * invalidation occurs during a PSD flush.
5004          */
5005         I915_WRITE(HDC_CHICKEN0,
5006                    I915_READ(HDC_CHICKEN0) |
5007                    _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5008
5009         /* WaVSRefCountFullforceMissDisable:bdw */
5010         /* WaDSRefCountFullforceMissDisable:bdw */
5011         I915_WRITE(GEN7_FF_THREAD_MODE,
5012                    I915_READ(GEN7_FF_THREAD_MODE) &
5013                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5014
5015         /*
5016          * BSpec recommends 8x4 when MSAA is used,
5017          * however in practice 16x4 seems fastest.
5018          *
5019          * Note that PS/WM thread counts depend on the WIZ hashing
5020          * disable bit, which we don't touch here, but it's good
5021          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5022          */
5023         I915_WRITE(GEN7_GT_MODE,
5024                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5025
5026         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5027                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5028
5029         /* WaDisableSDEUnitClockGating:bdw */
5030         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5031                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5032
5033         /* Wa4x4STCOptimizationDisable:bdw */
5034         I915_WRITE(CACHE_MODE_1,
5035                    _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
5036 }
5037
5038 static void haswell_init_clock_gating(struct drm_device *dev)
5039 {
5040         struct drm_i915_private *dev_priv = dev->dev_private;
5041
5042         ilk_init_lp_watermarks(dev);
5043
5044         /* L3 caching of data atomics doesn't work -- disable it. */
5045         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5046         I915_WRITE(HSW_ROW_CHICKEN3,
5047                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5048
5049         /* This is required by WaCatErrorRejectionIssue:hsw */
5050         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5051                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5052                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5053
5054         /* WaVSRefCountFullforceMissDisable:hsw */
5055         I915_WRITE(GEN7_FF_THREAD_MODE,
5056                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5057
5058         /* WaDisable_RenderCache_OperationalFlush:hsw */
5059         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5060
5061         /* enable HiZ Raw Stall Optimization */
5062         I915_WRITE(CACHE_MODE_0_GEN7,
5063                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5064
5065         /* WaDisable4x2SubspanOptimization:hsw */
5066         I915_WRITE(CACHE_MODE_1,
5067                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5068
5069         /*
5070          * BSpec recommends 8x4 when MSAA is used,
5071          * however in practice 16x4 seems fastest.
5072          *
5073          * Note that PS/WM thread counts depend on the WIZ hashing
5074          * disable bit, which we don't touch here, but it's good
5075          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5076          */
5077         I915_WRITE(GEN7_GT_MODE,
5078                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5079
5080         /* WaSwitchSolVfFArbitrationPriority:hsw */
5081         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5082
5083         /* WaRsPkgCStateDisplayPMReq:hsw */
5084         I915_WRITE(CHICKEN_PAR1_1,
5085                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5086
5087         lpt_init_clock_gating(dev);
5088 }
5089
5090 static void ivybridge_init_clock_gating(struct drm_device *dev)
5091 {
5092         struct drm_i915_private *dev_priv = dev->dev_private;
5093         uint32_t snpcr;
5094
5095         ilk_init_lp_watermarks(dev);
5096
5097         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5098
5099         /* WaDisableEarlyCull:ivb */
5100         I915_WRITE(_3D_CHICKEN3,
5101                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5102
5103         /* WaDisableBackToBackFlipFix:ivb */
5104         I915_WRITE(IVB_CHICKEN3,
5105                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5106                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5107
5108         /* WaDisablePSDDualDispatchEnable:ivb */
5109         if (IS_IVB_GT1(dev))
5110                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5111                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5112
5113         /* WaDisable_RenderCache_OperationalFlush:ivb */
5114         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5115
5116         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5117         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5118                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5119
5120         /* WaApplyL3ControlAndL3ChickenMode:ivb */
5121         I915_WRITE(GEN7_L3CNTLREG1,
5122                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5123         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5124                    GEN7_WA_L3_CHICKEN_MODE);
5125         if (IS_IVB_GT1(dev))
5126                 I915_WRITE(GEN7_ROW_CHICKEN2,
5127                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5128         else {
5129                 /* must write both registers */
5130                 I915_WRITE(GEN7_ROW_CHICKEN2,
5131                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5132                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5133                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5134         }
5135
5136         /* WaForceL3Serialization:ivb */
5137         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5138                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5139
5140         /*
5141          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5142          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5143          */
5144         I915_WRITE(GEN6_UCGCTL2,
5145                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5146
5147         /* This is required by WaCatErrorRejectionIssue:ivb */
5148         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5149                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5150                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5151
5152         g4x_disable_trickle_feed(dev);
5153
5154         gen7_setup_fixed_func_scheduler(dev_priv);
5155
5156         if (0) { /* causes HiZ corruption on ivb:gt1 */
5157                 /* enable HiZ Raw Stall Optimization */
5158                 I915_WRITE(CACHE_MODE_0_GEN7,
5159                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5160         }
5161
5162         /* WaDisable4x2SubspanOptimization:ivb */
5163         I915_WRITE(CACHE_MODE_1,
5164                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5165
5166         /*
5167          * BSpec recommends 8x4 when MSAA is used,
5168          * however in practice 16x4 seems fastest.
5169          *
5170          * Note that PS/WM thread counts depend on the WIZ hashing
5171          * disable bit, which we don't touch here, but it's good
5172          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5173          */
5174         I915_WRITE(GEN7_GT_MODE,
5175                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5176
5177         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5178         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5179         snpcr |= GEN6_MBC_SNPCR_MED;
5180         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5181
5182         if (!HAS_PCH_NOP(dev))
5183                 cpt_init_clock_gating(dev);
5184
5185         gen6_check_mch_setup(dev);
5186 }
5187
5188 static void valleyview_init_clock_gating(struct drm_device *dev)
5189 {
5190         struct drm_i915_private *dev_priv = dev->dev_private;
5191         u32 val;
5192
5193         mutex_lock(&dev_priv->rps.hw_lock);
5194         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5195         mutex_unlock(&dev_priv->rps.hw_lock);
5196         switch ((val >> 6) & 3) {
5197         case 0:
5198         case 1:
5199                 dev_priv->mem_freq = 800;
5200                 break;
5201         case 2:
5202                 dev_priv->mem_freq = 1066;
5203                 break;
5204         case 3:
5205                 dev_priv->mem_freq = 1333;
5206                 break;
5207         }
5208         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5209
5210         dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
5211         DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz",
5212                          dev_priv->vlv_cdclk_freq);
5213
5214         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5215
5216         /* WaDisableEarlyCull:vlv */
5217         I915_WRITE(_3D_CHICKEN3,
5218                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5219
5220         /* WaDisableBackToBackFlipFix:vlv */
5221         I915_WRITE(IVB_CHICKEN3,
5222                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5223                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5224
5225         /* WaPsdDispatchEnable:vlv */
5226         /* WaDisablePSDDualDispatchEnable:vlv */
5227         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5228                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5229                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5230
5231         /* WaDisable_RenderCache_OperationalFlush:vlv */
5232         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5233
5234         /* WaForceL3Serialization:vlv */
5235         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5236                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5237
5238         /* WaDisableDopClockGating:vlv */
5239         I915_WRITE(GEN7_ROW_CHICKEN2,
5240                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5241
5242         /* This is required by WaCatErrorRejectionIssue:vlv */
5243         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5244                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5245                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5246
5247         gen7_setup_fixed_func_scheduler(dev_priv);
5248
5249         /*
5250          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5251          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5252          */
5253         I915_WRITE(GEN6_UCGCTL2,
5254                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5255
5256         /* WaDisableL3Bank2xClockGate:vlv */
5257         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5258
5259         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5260
5261         /*
5262          * BSpec says this must be set, even though
5263          * WaDisable4x2SubspanOptimization isn't listed for VLV.
5264          */
5265         I915_WRITE(CACHE_MODE_1,
5266                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5267
5268         /*
5269          * WaIncreaseL3CreditsForVLVB0:vlv
5270          * This is the hardware default actually.
5271          */
5272         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5273
5274         /*
5275          * WaDisableVLVClockGating_VBIIssue:vlv
5276          * Disable clock gating on th GCFG unit to prevent a delay
5277          * in the reporting of vblank events.
5278          */
5279         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5280 }
5281
5282 static void g4x_init_clock_gating(struct drm_device *dev)
5283 {
5284         struct drm_i915_private *dev_priv = dev->dev_private;
5285         uint32_t dspclk_gate;
5286
5287         I915_WRITE(RENCLK_GATE_D1, 0);
5288         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5289                    GS_UNIT_CLOCK_GATE_DISABLE |
5290                    CL_UNIT_CLOCK_GATE_DISABLE);
5291         I915_WRITE(RAMCLK_GATE_D, 0);
5292         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5293                 OVRUNIT_CLOCK_GATE_DISABLE |
5294                 OVCUNIT_CLOCK_GATE_DISABLE;
5295         if (IS_GM45(dev))
5296                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5297         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5298
5299         /* WaDisableRenderCachePipelinedFlush */
5300         I915_WRITE(CACHE_MODE_0,
5301                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5302
5303         /* WaDisable_RenderCache_OperationalFlush:g4x */
5304         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5305
5306         g4x_disable_trickle_feed(dev);
5307 }
5308
5309 static void crestline_init_clock_gating(struct drm_device *dev)
5310 {
5311         struct drm_i915_private *dev_priv = dev->dev_private;
5312
5313         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5314         I915_WRITE(RENCLK_GATE_D2, 0);
5315         I915_WRITE(DSPCLK_GATE_D, 0);
5316         I915_WRITE(RAMCLK_GATE_D, 0);
5317         I915_WRITE16(DEUC, 0);
5318         I915_WRITE(MI_ARB_STATE,
5319                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5320
5321         /* WaDisable_RenderCache_OperationalFlush:gen4 */
5322         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5323 }
5324
5325 static void broadwater_init_clock_gating(struct drm_device *dev)
5326 {
5327         struct drm_i915_private *dev_priv = dev->dev_private;
5328
5329         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5330                    I965_RCC_CLOCK_GATE_DISABLE |
5331                    I965_RCPB_CLOCK_GATE_DISABLE |
5332                    I965_ISC_CLOCK_GATE_DISABLE |
5333                    I965_FBC_CLOCK_GATE_DISABLE);
5334         I915_WRITE(RENCLK_GATE_D2, 0);
5335         I915_WRITE(MI_ARB_STATE,
5336                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5337
5338         /* WaDisable_RenderCache_OperationalFlush:gen4 */
5339         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5340 }
5341
5342 static void gen3_init_clock_gating(struct drm_device *dev)
5343 {
5344         struct drm_i915_private *dev_priv = dev->dev_private;
5345         u32 dstate = I915_READ(D_STATE);
5346
5347         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5348                 DSTATE_DOT_CLOCK_GATING;
5349         I915_WRITE(D_STATE, dstate);
5350
5351         if (IS_PINEVIEW(dev))
5352                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5353
5354         /* IIR "flip pending" means done if this bit is set */
5355         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5356 }
5357
5358 static void i85x_init_clock_gating(struct drm_device *dev)
5359 {
5360         struct drm_i915_private *dev_priv = dev->dev_private;
5361
5362         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5363 }
5364
5365 static void i830_init_clock_gating(struct drm_device *dev)
5366 {
5367         struct drm_i915_private *dev_priv = dev->dev_private;
5368
5369         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5370 }
5371
5372 void intel_init_clock_gating(struct drm_device *dev)
5373 {
5374         struct drm_i915_private *dev_priv = dev->dev_private;
5375
5376         dev_priv->display.init_clock_gating(dev);
5377 }
5378
5379 void intel_suspend_hw(struct drm_device *dev)
5380 {
5381         if (HAS_PCH_LPT(dev))
5382                 lpt_suspend_hw(dev);
5383 }
5384
5385 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
5386         for (i = 0;                                                     \
5387              i < (power_domains)->power_well_count &&                   \
5388                  ((power_well) = &(power_domains)->power_wells[i]);     \
5389              i++)                                                       \
5390                 if ((power_well)->domains & (domain_mask))
5391
5392 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5393         for (i = (power_domains)->power_well_count - 1;                  \
5394              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5395              i--)                                                        \
5396                 if ((power_well)->domains & (domain_mask))
5397
5398 /**
5399  * We should only use the power well if we explicitly asked the hardware to
5400  * enable it, so check if it's enabled and also check if we've requested it to
5401  * be enabled.
5402  */
5403 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
5404                                    struct i915_power_well *power_well)
5405 {
5406         return I915_READ(HSW_PWR_WELL_DRIVER) ==
5407                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5408 }
5409
5410 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
5411                                     enum intel_display_power_domain domain)
5412 {
5413         struct i915_power_domains *power_domains;
5414
5415         power_domains = &dev_priv->power_domains;
5416
5417         return power_domains->domain_use_count[domain];
5418 }
5419
5420 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
5421                                  enum intel_display_power_domain domain)
5422 {
5423         struct i915_power_domains *power_domains;
5424         struct i915_power_well *power_well;
5425         bool is_enabled;
5426         int i;
5427
5428         if (dev_priv->pm.suspended)
5429                 return false;
5430
5431         power_domains = &dev_priv->power_domains;
5432
5433         is_enabled = true;
5434
5435         mutex_lock(&power_domains->lock);
5436         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5437                 if (power_well->always_on)
5438                         continue;
5439
5440                 if (!power_well->ops->is_enabled(dev_priv, power_well)) {
5441                         is_enabled = false;
5442                         break;
5443                 }
5444         }
5445         mutex_unlock(&power_domains->lock);
5446
5447         return is_enabled;
5448 }
5449
5450 /*
5451  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5452  * when not needed anymore. We have 4 registers that can request the power well
5453  * to be enabled, and it will only be disabled if none of the registers is
5454  * requesting it to be enabled.
5455  */
5456 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5457 {
5458         struct drm_device *dev = dev_priv->dev;
5459         unsigned long irqflags;
5460
5461         /*
5462          * After we re-enable the power well, if we touch VGA register 0x3d5
5463          * we'll get unclaimed register interrupts. This stops after we write
5464          * anything to the VGA MSR register. The vgacon module uses this
5465          * register all the time, so if we unbind our driver and, as a
5466          * consequence, bind vgacon, we'll get stuck in an infinite loop at
5467          * console_unlock(). So make here we touch the VGA MSR register, making
5468          * sure vgacon can keep working normally without triggering interrupts
5469          * and error messages.
5470          */
5471         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5472         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5473         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5474
5475         if (IS_BROADWELL(dev)) {
5476                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5477                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5478                            dev_priv->de_irq_mask[PIPE_B]);
5479                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5480                            ~dev_priv->de_irq_mask[PIPE_B] |
5481                            GEN8_PIPE_VBLANK);
5482                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5483                            dev_priv->de_irq_mask[PIPE_C]);
5484                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5485                            ~dev_priv->de_irq_mask[PIPE_C] |
5486                            GEN8_PIPE_VBLANK);
5487                 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5488                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5489         }
5490 }
5491
5492 static void reset_vblank_counter(struct drm_device *dev, enum pipe pipe)
5493 {
5494         assert_spin_locked(&dev->vbl_lock);
5495
5496         dev->vblank[pipe].last = 0;
5497 }
5498
5499 static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5500 {
5501         struct drm_device *dev = dev_priv->dev;
5502         enum pipe pipe;
5503         unsigned long irqflags;
5504
5505         /*
5506          * After this, the registers on the pipes that are part of the power
5507          * well will become zero, so we have to adjust our counters according to
5508          * that.
5509          *
5510          * FIXME: Should we do this in general in drm_vblank_post_modeset?
5511          */
5512         spin_lock_irqsave(&dev->vbl_lock, irqflags);
5513         for_each_pipe(pipe)
5514                 if (pipe != PIPE_A)
5515                         reset_vblank_counter(dev, pipe);
5516         spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5517 }
5518
5519 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
5520                                struct i915_power_well *power_well, bool enable)
5521 {
5522         bool is_enabled, enable_requested;
5523         uint32_t tmp;
5524
5525         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5526         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5527         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5528
5529         if (enable) {
5530                 if (!enable_requested)
5531                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5532                                    HSW_PWR_WELL_ENABLE_REQUEST);
5533
5534                 if (!is_enabled) {
5535                         DRM_DEBUG_KMS("Enabling power well\n");
5536                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5537                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5538                                 DRM_ERROR("Timeout enabling power well\n");
5539                 }
5540
5541                 hsw_power_well_post_enable(dev_priv);
5542         } else {
5543                 if (enable_requested) {
5544                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5545                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5546                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5547
5548                         hsw_power_well_post_disable(dev_priv);
5549                 }
5550         }
5551 }
5552
5553 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5554                                    struct i915_power_well *power_well)
5555 {
5556         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5557
5558         /*
5559          * We're taking over the BIOS, so clear any requests made by it since
5560          * the driver is in charge now.
5561          */
5562         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5563                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5564 }
5565
5566 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5567                                   struct i915_power_well *power_well)
5568 {
5569         hsw_set_power_well(dev_priv, power_well, true);
5570 }
5571
5572 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5573                                    struct i915_power_well *power_well)
5574 {
5575         hsw_set_power_well(dev_priv, power_well, false);
5576 }
5577
5578 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5579                                            struct i915_power_well *power_well)
5580 {
5581 }
5582
5583 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5584                                              struct i915_power_well *power_well)
5585 {
5586         return true;
5587 }
5588
5589 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5590                                struct i915_power_well *power_well, bool enable)
5591 {
5592         enum punit_power_well power_well_id = power_well->data;
5593         u32 mask;
5594         u32 state;
5595         u32 ctrl;
5596
5597         mask = PUNIT_PWRGT_MASK(power_well_id);
5598         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
5599                          PUNIT_PWRGT_PWR_GATE(power_well_id);
5600
5601         mutex_lock(&dev_priv->rps.hw_lock);
5602
5603 #define COND \
5604         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
5605
5606         if (COND)
5607                 goto out;
5608
5609         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
5610         ctrl &= ~mask;
5611         ctrl |= state;
5612         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
5613
5614         if (wait_for(COND, 100))
5615                 DRM_ERROR("timout setting power well state %08x (%08x)\n",
5616                           state,
5617                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
5618
5619 #undef COND
5620
5621 out:
5622         mutex_unlock(&dev_priv->rps.hw_lock);
5623 }
5624
5625 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
5626                                    struct i915_power_well *power_well)
5627 {
5628         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
5629 }
5630
5631 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
5632                                   struct i915_power_well *power_well)
5633 {
5634         vlv_set_power_well(dev_priv, power_well, true);
5635 }
5636
5637 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
5638                                    struct i915_power_well *power_well)
5639 {
5640         vlv_set_power_well(dev_priv, power_well, false);
5641 }
5642
5643 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
5644                                    struct i915_power_well *power_well)
5645 {
5646         int power_well_id = power_well->data;
5647         bool enabled = false;
5648         u32 mask;
5649         u32 state;
5650         u32 ctrl;
5651
5652         mask = PUNIT_PWRGT_MASK(power_well_id);
5653         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
5654
5655         mutex_lock(&dev_priv->rps.hw_lock);
5656
5657         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
5658         /*
5659          * We only ever set the power-on and power-gate states, anything
5660          * else is unexpected.
5661          */
5662         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
5663                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
5664         if (state == ctrl)
5665                 enabled = true;
5666
5667         /*
5668          * A transient state at this point would mean some unexpected party
5669          * is poking at the power controls too.
5670          */
5671         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
5672         WARN_ON(ctrl != state);
5673
5674         mutex_unlock(&dev_priv->rps.hw_lock);
5675
5676         return enabled;
5677 }
5678
5679 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
5680                                           struct i915_power_well *power_well)
5681 {
5682         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5683
5684         vlv_set_power_well(dev_priv, power_well, true);
5685
5686         spin_lock_irq(&dev_priv->irq_lock);
5687         valleyview_enable_display_irqs(dev_priv);
5688         spin_unlock_irq(&dev_priv->irq_lock);
5689
5690         /*
5691          * During driver initialization we need to defer enabling hotplug
5692          * processing until fbdev is set up.
5693          */
5694         if (dev_priv->enable_hotplug_processing)
5695                 intel_hpd_init(dev_priv->dev);
5696
5697         i915_redisable_vga_power_on(dev_priv->dev);
5698 }
5699
5700 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
5701                                            struct i915_power_well *power_well)
5702 {
5703         struct drm_device *dev = dev_priv->dev;
5704         enum pipe pipe;
5705
5706         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5707
5708         spin_lock_irq(&dev_priv->irq_lock);
5709         for_each_pipe(pipe)
5710                 __intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
5711
5712         valleyview_disable_display_irqs(dev_priv);
5713         spin_unlock_irq(&dev_priv->irq_lock);
5714
5715         spin_lock_irq(&dev->vbl_lock);
5716         for_each_pipe(pipe)
5717                 reset_vblank_counter(dev, pipe);
5718         spin_unlock_irq(&dev->vbl_lock);
5719
5720         vlv_set_power_well(dev_priv, power_well, false);
5721 }
5722
5723 static void check_power_well_state(struct drm_i915_private *dev_priv,
5724                                    struct i915_power_well *power_well)
5725 {
5726         bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
5727
5728         if (power_well->always_on || !i915.disable_power_well) {
5729                 if (!enabled)
5730                         goto mismatch;
5731
5732                 return;
5733         }
5734
5735         if (enabled != (power_well->count > 0))
5736                 goto mismatch;
5737
5738         return;
5739
5740 mismatch:
5741         WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
5742                   power_well->name, power_well->always_on, enabled,
5743                   power_well->count, i915.disable_power_well);
5744 }
5745
5746 void intel_display_power_get(struct drm_i915_private *dev_priv,
5747                              enum intel_display_power_domain domain)
5748 {
5749         struct i915_power_domains *power_domains;
5750         struct i915_power_well *power_well;
5751         int i;
5752
5753         intel_runtime_pm_get(dev_priv);
5754
5755         power_domains = &dev_priv->power_domains;
5756
5757         mutex_lock(&power_domains->lock);
5758
5759         for_each_power_well(i, power_well, BIT(domain), power_domains) {
5760                 if (!power_well->count++) {
5761                         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
5762                         power_well->ops->enable(dev_priv, power_well);
5763                 }
5764
5765                 check_power_well_state(dev_priv, power_well);
5766         }
5767
5768         power_domains->domain_use_count[domain]++;
5769
5770         mutex_unlock(&power_domains->lock);
5771 }
5772
5773 void intel_display_power_put(struct drm_i915_private *dev_priv,
5774                              enum intel_display_power_domain domain)
5775 {
5776         struct i915_power_domains *power_domains;
5777         struct i915_power_well *power_well;
5778         int i;
5779
5780         power_domains = &dev_priv->power_domains;
5781
5782         mutex_lock(&power_domains->lock);
5783
5784         WARN_ON(!power_domains->domain_use_count[domain]);
5785         power_domains->domain_use_count[domain]--;
5786
5787         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5788                 WARN_ON(!power_well->count);
5789
5790                 if (!--power_well->count && i915.disable_power_well) {
5791                         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
5792                         power_well->ops->disable(dev_priv, power_well);
5793                 }
5794
5795                 check_power_well_state(dev_priv, power_well);
5796         }
5797
5798         mutex_unlock(&power_domains->lock);
5799
5800         intel_runtime_pm_put(dev_priv);
5801 }
5802
5803 static struct i915_power_domains *hsw_pwr;
5804
5805 /* Display audio driver power well request */
5806 void i915_request_power_well(void)
5807 {
5808         struct drm_i915_private *dev_priv;
5809
5810         if (WARN_ON(!hsw_pwr))
5811                 return;
5812
5813         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5814                                 power_domains);
5815         intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
5816 }
5817 EXPORT_SYMBOL_GPL(i915_request_power_well);
5818
5819 /* Display audio driver power well release */
5820 void i915_release_power_well(void)
5821 {
5822         struct drm_i915_private *dev_priv;
5823
5824         if (WARN_ON(!hsw_pwr))
5825                 return;
5826
5827         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5828                                 power_domains);
5829         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
5830 }
5831 EXPORT_SYMBOL_GPL(i915_release_power_well);
5832
5833 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
5834
5835 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
5836         BIT(POWER_DOMAIN_PIPE_A) |                      \
5837         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
5838         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
5839         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
5840         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
5841         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
5842         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
5843         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
5844         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
5845         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
5846         BIT(POWER_DOMAIN_PORT_CRT) |                    \
5847         BIT(POWER_DOMAIN_INIT))
5848 #define HSW_DISPLAY_POWER_DOMAINS (                             \
5849         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
5850         BIT(POWER_DOMAIN_INIT))
5851
5852 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
5853         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
5854         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
5855 #define BDW_DISPLAY_POWER_DOMAINS (                             \
5856         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
5857         BIT(POWER_DOMAIN_INIT))
5858
5859 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
5860 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
5861
5862 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
5863         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
5864         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
5865         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
5866         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
5867         BIT(POWER_DOMAIN_PORT_CRT) |            \
5868         BIT(POWER_DOMAIN_INIT))
5869
5870 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
5871         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
5872         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
5873         BIT(POWER_DOMAIN_INIT))
5874
5875 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
5876         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
5877         BIT(POWER_DOMAIN_INIT))
5878
5879 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
5880         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
5881         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
5882         BIT(POWER_DOMAIN_INIT))
5883
5884 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
5885         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
5886         BIT(POWER_DOMAIN_INIT))
5887
5888 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
5889         .sync_hw = i9xx_always_on_power_well_noop,
5890         .enable = i9xx_always_on_power_well_noop,
5891         .disable = i9xx_always_on_power_well_noop,
5892         .is_enabled = i9xx_always_on_power_well_enabled,
5893 };
5894
5895 static struct i915_power_well i9xx_always_on_power_well[] = {
5896         {
5897                 .name = "always-on",
5898                 .always_on = 1,
5899                 .domains = POWER_DOMAIN_MASK,
5900                 .ops = &i9xx_always_on_power_well_ops,
5901         },
5902 };
5903
5904 static const struct i915_power_well_ops hsw_power_well_ops = {
5905         .sync_hw = hsw_power_well_sync_hw,
5906         .enable = hsw_power_well_enable,
5907         .disable = hsw_power_well_disable,
5908         .is_enabled = hsw_power_well_enabled,
5909 };
5910
5911 static struct i915_power_well hsw_power_wells[] = {
5912         {
5913                 .name = "always-on",
5914                 .always_on = 1,
5915                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5916                 .ops = &i9xx_always_on_power_well_ops,
5917         },
5918         {
5919                 .name = "display",
5920                 .domains = HSW_DISPLAY_POWER_DOMAINS,
5921                 .ops = &hsw_power_well_ops,
5922         },
5923 };
5924
5925 static struct i915_power_well bdw_power_wells[] = {
5926         {
5927                 .name = "always-on",
5928                 .always_on = 1,
5929                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5930                 .ops = &i9xx_always_on_power_well_ops,
5931         },
5932         {
5933                 .name = "display",
5934                 .domains = BDW_DISPLAY_POWER_DOMAINS,
5935                 .ops = &hsw_power_well_ops,
5936         },
5937 };
5938
5939 static const struct i915_power_well_ops vlv_display_power_well_ops = {
5940         .sync_hw = vlv_power_well_sync_hw,
5941         .enable = vlv_display_power_well_enable,
5942         .disable = vlv_display_power_well_disable,
5943         .is_enabled = vlv_power_well_enabled,
5944 };
5945
5946 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
5947         .sync_hw = vlv_power_well_sync_hw,
5948         .enable = vlv_power_well_enable,
5949         .disable = vlv_power_well_disable,
5950         .is_enabled = vlv_power_well_enabled,
5951 };
5952
5953 static struct i915_power_well vlv_power_wells[] = {
5954         {
5955                 .name = "always-on",
5956                 .always_on = 1,
5957                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
5958                 .ops = &i9xx_always_on_power_well_ops,
5959         },
5960         {
5961                 .name = "display",
5962                 .domains = VLV_DISPLAY_POWER_DOMAINS,
5963                 .data = PUNIT_POWER_WELL_DISP2D,
5964                 .ops = &vlv_display_power_well_ops,
5965         },
5966         {
5967                 .name = "dpio-common",
5968                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
5969                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
5970                 .ops = &vlv_dpio_power_well_ops,
5971         },
5972         {
5973                 .name = "dpio-tx-b-01",
5974                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5975                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5976                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5977                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5978                 .ops = &vlv_dpio_power_well_ops,
5979                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
5980         },
5981         {
5982                 .name = "dpio-tx-b-23",
5983                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5984                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5985                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5986                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5987                 .ops = &vlv_dpio_power_well_ops,
5988                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
5989         },
5990         {
5991                 .name = "dpio-tx-c-01",
5992                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5993                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5994                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5995                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5996                 .ops = &vlv_dpio_power_well_ops,
5997                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
5998         },
5999         {
6000                 .name = "dpio-tx-c-23",
6001                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6002                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6003                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6004                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6005                 .ops = &vlv_dpio_power_well_ops,
6006                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6007         },
6008 };
6009
6010 #define set_power_wells(power_domains, __power_wells) ({                \
6011         (power_domains)->power_wells = (__power_wells);                 \
6012         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
6013 })
6014
6015 int intel_power_domains_init(struct drm_i915_private *dev_priv)
6016 {
6017         struct i915_power_domains *power_domains = &dev_priv->power_domains;
6018
6019         mutex_init(&power_domains->lock);
6020
6021         /*
6022          * The enabling order will be from lower to higher indexed wells,
6023          * the disabling order is reversed.
6024          */
6025         if (IS_HASWELL(dev_priv->dev)) {
6026                 set_power_wells(power_domains, hsw_power_wells);
6027                 hsw_pwr = power_domains;
6028         } else if (IS_BROADWELL(dev_priv->dev)) {
6029                 set_power_wells(power_domains, bdw_power_wells);
6030                 hsw_pwr = power_domains;
6031         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6032                 set_power_wells(power_domains, vlv_power_wells);
6033         } else {
6034                 set_power_wells(power_domains, i9xx_always_on_power_well);
6035         }
6036
6037         return 0;
6038 }
6039
6040 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
6041 {
6042         hsw_pwr = NULL;
6043 }
6044
6045 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
6046 {
6047         struct i915_power_domains *power_domains = &dev_priv->power_domains;
6048         struct i915_power_well *power_well;
6049         int i;
6050
6051         mutex_lock(&power_domains->lock);
6052         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
6053                 power_well->ops->sync_hw(dev_priv, power_well);
6054         mutex_unlock(&power_domains->lock);
6055 }
6056
6057 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
6058 {
6059         /* For now, we need the power well to be always enabled. */
6060         intel_display_set_init_power(dev_priv, true);
6061         intel_power_domains_resume(dev_priv);
6062 }
6063
6064 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6065 {
6066         intel_runtime_pm_get(dev_priv);
6067 }
6068
6069 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6070 {
6071         intel_runtime_pm_put(dev_priv);
6072 }
6073
6074 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6075 {
6076         struct drm_device *dev = dev_priv->dev;
6077         struct device *device = &dev->pdev->dev;
6078
6079         if (!HAS_RUNTIME_PM(dev))
6080                 return;
6081
6082         pm_runtime_get_sync(device);
6083         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6084 }
6085
6086 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6087 {
6088         struct drm_device *dev = dev_priv->dev;
6089         struct device *device = &dev->pdev->dev;
6090
6091         if (!HAS_RUNTIME_PM(dev))
6092                 return;
6093
6094         WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6095         pm_runtime_get_noresume(device);
6096 }
6097
6098 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6099 {
6100         struct drm_device *dev = dev_priv->dev;
6101         struct device *device = &dev->pdev->dev;
6102
6103         if (!HAS_RUNTIME_PM(dev))
6104                 return;
6105
6106         pm_runtime_mark_last_busy(device);
6107         pm_runtime_put_autosuspend(device);
6108 }
6109
6110 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6111 {
6112         struct drm_device *dev = dev_priv->dev;
6113         struct device *device = &dev->pdev->dev;
6114
6115         if (!HAS_RUNTIME_PM(dev))
6116                 return;
6117
6118         pm_runtime_set_active(device);
6119
6120         /*
6121          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6122          * requirement.
6123          */
6124         if (!intel_enable_rc6(dev)) {
6125                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6126                 return;
6127         }
6128
6129         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6130         pm_runtime_mark_last_busy(device);
6131         pm_runtime_use_autosuspend(device);
6132
6133         pm_runtime_put_autosuspend(device);
6134 }
6135
6136 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6137 {
6138         struct drm_device *dev = dev_priv->dev;
6139         struct device *device = &dev->pdev->dev;
6140
6141         if (!HAS_RUNTIME_PM(dev))
6142                 return;
6143
6144         if (!intel_enable_rc6(dev))
6145                 return;
6146
6147         /* Make sure we're not suspended first. */
6148         pm_runtime_get_sync(device);
6149         pm_runtime_disable(device);
6150 }
6151
6152 /* Set up chip specific power management-related functions */
6153 void intel_init_pm(struct drm_device *dev)
6154 {
6155         struct drm_i915_private *dev_priv = dev->dev_private;
6156
6157         if (HAS_FBC(dev)) {
6158                 if (INTEL_INFO(dev)->gen >= 7) {
6159                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6160                         dev_priv->display.enable_fbc = gen7_enable_fbc;
6161                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6162                 } else if (INTEL_INFO(dev)->gen >= 5) {
6163                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6164                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
6165                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6166                 } else if (IS_GM45(dev)) {
6167                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6168                         dev_priv->display.enable_fbc = g4x_enable_fbc;
6169                         dev_priv->display.disable_fbc = g4x_disable_fbc;
6170                 } else {
6171                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6172                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
6173                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
6174
6175                         /* This value was pulled out of someone's hat */
6176                         I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6177                 }
6178         }
6179
6180         /* For cxsr */
6181         if (IS_PINEVIEW(dev))
6182                 i915_pineview_get_mem_freq(dev);
6183         else if (IS_GEN5(dev))
6184                 i915_ironlake_get_mem_freq(dev);
6185
6186         /* For FIFO watermark updates */
6187         if (HAS_PCH_SPLIT(dev)) {
6188                 ilk_setup_wm_latency(dev);
6189
6190                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6191                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6192                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6193                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6194                         dev_priv->display.update_wm = ilk_update_wm;
6195                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6196                 } else {
6197                         DRM_DEBUG_KMS("Failed to read display plane latency. "
6198                                       "Disable CxSR\n");
6199                 }
6200
6201                 if (IS_GEN5(dev))
6202                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6203                 else if (IS_GEN6(dev))
6204                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6205                 else if (IS_IVYBRIDGE(dev))
6206                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6207                 else if (IS_HASWELL(dev))
6208                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6209                 else if (INTEL_INFO(dev)->gen == 8)
6210                         dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6211         } else if (IS_VALLEYVIEW(dev)) {
6212                 dev_priv->display.update_wm = valleyview_update_wm;
6213                 dev_priv->display.init_clock_gating =
6214                         valleyview_init_clock_gating;
6215         } else if (IS_PINEVIEW(dev)) {
6216                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6217                                             dev_priv->is_ddr3,
6218                                             dev_priv->fsb_freq,
6219                                             dev_priv->mem_freq)) {
6220                         DRM_INFO("failed to find known CxSR latency "
6221                                  "(found ddr%s fsb freq %d, mem freq %d), "
6222                                  "disabling CxSR\n",
6223                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
6224                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6225                         /* Disable CxSR and never update its watermark again */
6226                         pineview_disable_cxsr(dev);
6227                         dev_priv->display.update_wm = NULL;
6228                 } else
6229                         dev_priv->display.update_wm = pineview_update_wm;
6230                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6231         } else if (IS_G4X(dev)) {
6232                 dev_priv->display.update_wm = g4x_update_wm;
6233                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6234         } else if (IS_GEN4(dev)) {
6235                 dev_priv->display.update_wm = i965_update_wm;
6236                 if (IS_CRESTLINE(dev))
6237                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6238                 else if (IS_BROADWATER(dev))
6239                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6240         } else if (IS_GEN3(dev)) {
6241                 dev_priv->display.update_wm = i9xx_update_wm;
6242                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6243                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6244         } else if (IS_GEN2(dev)) {
6245                 if (INTEL_INFO(dev)->num_pipes == 1) {
6246                         dev_priv->display.update_wm = i845_update_wm;
6247                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6248                 } else {
6249                         dev_priv->display.update_wm = i9xx_update_wm;
6250                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6251                 }
6252
6253                 if (IS_I85X(dev) || IS_I865G(dev))
6254                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6255                 else
6256                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
6257         } else {
6258                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6259         }
6260 }
6261
6262 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6263 {
6264         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6265
6266         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6267                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6268                 return -EAGAIN;
6269         }
6270
6271         I915_WRITE(GEN6_PCODE_DATA, *val);
6272         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6273
6274         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6275                      500)) {
6276                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6277                 return -ETIMEDOUT;
6278         }
6279
6280         *val = I915_READ(GEN6_PCODE_DATA);
6281         I915_WRITE(GEN6_PCODE_DATA, 0);
6282
6283         return 0;
6284 }
6285
6286 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6287 {
6288         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6289
6290         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6291                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6292                 return -EAGAIN;
6293         }
6294
6295         I915_WRITE(GEN6_PCODE_DATA, val);
6296         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6297
6298         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6299                      500)) {
6300                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6301                 return -ETIMEDOUT;
6302         }
6303
6304         I915_WRITE(GEN6_PCODE_DATA, 0);
6305
6306         return 0;
6307 }
6308
6309 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6310 {
6311         int div;
6312
6313         /* 4 x czclk */
6314         switch (dev_priv->mem_freq) {
6315         case 800:
6316                 div = 10;
6317                 break;
6318         case 1066:
6319                 div = 12;
6320                 break;
6321         case 1333:
6322                 div = 16;
6323                 break;
6324         default:
6325                 return -1;
6326         }
6327
6328         return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6329 }
6330
6331 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6332 {
6333         int mul;
6334
6335         /* 4 x czclk */
6336         switch (dev_priv->mem_freq) {
6337         case 800:
6338                 mul = 10;
6339                 break;
6340         case 1066:
6341                 mul = 12;
6342                 break;
6343         case 1333:
6344                 mul = 16;
6345                 break;
6346         default:
6347                 return -1;
6348         }
6349
6350         return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6351 }
6352
6353 void intel_pm_setup(struct drm_device *dev)
6354 {
6355         struct drm_i915_private *dev_priv = dev->dev_private;
6356
6357         mutex_init(&dev_priv->rps.hw_lock);
6358
6359         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6360                           intel_gen6_powersave_work);
6361
6362         dev_priv->pm.suspended = false;
6363         dev_priv->pm.irqs_disabled = false;
6364 }