drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/i915_powerwell.h>
  35 #include <linux/pm_runtime.h>
  36
  37 /**
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  59  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  60  * during in-memory transfers and, therefore, reduce the power packet.
  61  *
  62  * The benefits of FBC are mostly visible with solid backgrounds and
  63  * variation-less patterns.
  64  *
  65  * FBC-related functionality can be enabled by the means of the
  66  * i915.i915_enable_fbc parameter
  67  */
  68
  69 static void i8xx_disable_fbc(struct drm_device *dev)
  70 {
  71         struct drm_i915_private *dev_priv = dev->dev_private;
  72         u32 fbc_ctl;
  73
  74         /* Disable compression */
  75         fbc_ctl = I915_READ(FBC_CONTROL);
  76         if ((fbc_ctl & FBC_CTL_EN) == 0)
  77                 return;
  78
  79         fbc_ctl &= ~FBC_CTL_EN;
  80         I915_WRITE(FBC_CONTROL, fbc_ctl);
  81
  82         /* Wait for compressing bit to clear */
  83         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  84                 DRM_DEBUG_KMS("FBC idle timed out\n");
  85                 return;
  86         }
  87
  88         DRM_DEBUG_KMS("disabled FBC\n");
  89 }
  90
  91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
  92 {
  93         struct drm_device *dev = crtc->dev;
  94         struct drm_i915_private *dev_priv = dev->dev_private;
  95         struct drm_framebuffer *fb = crtc->primary->fb;
  96         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  97         struct drm_i915_gem_object *obj = intel_fb->obj;
  98         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  99         int cfb_pitch;
 100         int i;
 101         u32 fbc_ctl;
 102
 103         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
 104         if (fb->pitches[0] < cfb_pitch)
 105                 cfb_pitch = fb->pitches[0];
 106
 107         /* FBC_CTL wants 32B or 64B units */
 108         if (IS_GEN2(dev))
 109                 cfb_pitch = (cfb_pitch / 32) - 1;
 110         else
 111                 cfb_pitch = (cfb_pitch / 64) - 1;
 112
 113         /* Clear old tags */
 114         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 115                 I915_WRITE(FBC_TAG + (i * 4), 0);
 116
 117         if (IS_GEN4(dev)) {
 118                 u32 fbc_ctl2;
 119
 120                 /* Set it up... */
 121                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 122                 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
 123                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 124                 I915_WRITE(FBC_FENCE_OFF, crtc->y);
 125         }
 126
 127         /* enable it... */
 128         fbc_ctl = I915_READ(FBC_CONTROL);
 129         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 130         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 131         if (IS_I945GM(dev))
 132                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 133         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 134         fbc_ctl |= obj->fence_reg;
 135         I915_WRITE(FBC_CONTROL, fbc_ctl);
 136
 137         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
 138                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 139 }
 140
 141 static bool i8xx_fbc_enabled(struct drm_device *dev)
 142 {
 143         struct drm_i915_private *dev_priv = dev->dev_private;
 144
 145         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 146 }
 147
 148 static void g4x_enable_fbc(struct drm_crtc *crtc)
 149 {
 150         struct drm_device *dev = crtc->dev;
 151         struct drm_i915_private *dev_priv = dev->dev_private;
 152         struct drm_framebuffer *fb = crtc->primary->fb;
 153         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 154         struct drm_i915_gem_object *obj = intel_fb->obj;
 155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 156         u32 dpfc_ctl;
 157
 158         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
 159         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 160                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 161         else
 162                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 163         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 164
 165         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 166
 167         /* enable it... */
 168         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 169
 170         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 171 }
 172
 173 static void g4x_disable_fbc(struct drm_device *dev)
 174 {
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176         u32 dpfc_ctl;
 177
 178         /* Disable compression */
 179         dpfc_ctl = I915_READ(DPFC_CONTROL);
 180         if (dpfc_ctl & DPFC_CTL_EN) {
 181                 dpfc_ctl &= ~DPFC_CTL_EN;
 182                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 183
 184                 DRM_DEBUG_KMS("disabled FBC\n");
 185         }
 186 }
 187
 188 static bool g4x_fbc_enabled(struct drm_device *dev)
 189 {
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191
 192         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 193 }
 194
 195 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 196 {
 197         struct drm_i915_private *dev_priv = dev->dev_private;
 198         u32 blt_ecoskpd;
 199
 200         /* Make sure blitter notifies FBC of writes */
 201
 202         /* Blitter is part of Media powerwell on VLV. No impact of
 203          * his param in other platforms for now */
 204         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
 205
 206         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 207         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 208                 GEN6_BLITTER_LOCK_SHIFT;
 209         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 210         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 211         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 212         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 213                          GEN6_BLITTER_LOCK_SHIFT);
 214         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 215         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 216
 217         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
 218 }
 219
 220 static void ironlake_enable_fbc(struct drm_crtc *crtc)
 221 {
 222         struct drm_device *dev = crtc->dev;
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         struct drm_framebuffer *fb = crtc->primary->fb;
 225         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 226         struct drm_i915_gem_object *obj = intel_fb->obj;
 227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 228         u32 dpfc_ctl;
 229
 230         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
 231         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 232                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 233         else
 234                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 235         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 236         if (IS_GEN5(dev))
 237                 dpfc_ctl |= obj->fence_reg;
 238
 239         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 240         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 241         /* enable it... */
 242         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 243
 244         if (IS_GEN6(dev)) {
 245                 I915_WRITE(SNB_DPFC_CTL_SA,
 246                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 247                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 248                 sandybridge_blit_fbc_update(dev);
 249         }
 250
 251         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 252 }
 253
 254 static void ironlake_disable_fbc(struct drm_device *dev)
 255 {
 256         struct drm_i915_private *dev_priv = dev->dev_private;
 257         u32 dpfc_ctl;
 258
 259         /* Disable compression */
 260         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 261         if (dpfc_ctl & DPFC_CTL_EN) {
 262                 dpfc_ctl &= ~DPFC_CTL_EN;
 263                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 264
 265                 DRM_DEBUG_KMS("disabled FBC\n");
 266         }
 267 }
 268
 269 static bool ironlake_fbc_enabled(struct drm_device *dev)
 270 {
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272
 273         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 274 }
 275
 276 static void gen7_enable_fbc(struct drm_crtc *crtc)
 277 {
 278         struct drm_device *dev = crtc->dev;
 279         struct drm_i915_private *dev_priv = dev->dev_private;
 280         struct drm_framebuffer *fb = crtc->primary->fb;
 281         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 282         struct drm_i915_gem_object *obj = intel_fb->obj;
 283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 284         u32 dpfc_ctl;
 285
 286         dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
 287         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 288                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 289         else
 290                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 291         dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 292
 293         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 294
 295         if (IS_IVYBRIDGE(dev)) {
 296                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 297                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 298                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 299                            ILK_FBCQ_DIS);
 300         } else {
 301                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 302                 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
 303                            I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
 304                            HSW_FBCQ_DIS);
 305         }
 306
 307         I915_WRITE(SNB_DPFC_CTL_SA,
 308                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 309         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 310
 311         sandybridge_blit_fbc_update(dev);
 312
 313         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 314 }
 315
 316 bool intel_fbc_enabled(struct drm_device *dev)
 317 {
 318         struct drm_i915_private *dev_priv = dev->dev_private;
 319
 320         if (!dev_priv->display.fbc_enabled)
 321                 return false;
 322
 323         return dev_priv->display.fbc_enabled(dev);
 324 }
 325
 326 static void intel_fbc_work_fn(struct work_struct *__work)
 327 {
 328         struct intel_fbc_work *work =
 329                 container_of(to_delayed_work(__work),
 330                              struct intel_fbc_work, work);
 331         struct drm_device *dev = work->crtc->dev;
 332         struct drm_i915_private *dev_priv = dev->dev_private;
 333
 334         mutex_lock(&dev->struct_mutex);
 335         if (work == dev_priv->fbc.fbc_work) {
 336                 /* Double check that we haven't switched fb without cancelling
 337                  * the prior work.
 338                  */
 339                 if (work->crtc->primary->fb == work->fb) {
 340                         dev_priv->display.enable_fbc(work->crtc);
 341
 342                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 343                         dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
 344                         dev_priv->fbc.y = work->crtc->y;
 345                 }
 346
 347                 dev_priv->fbc.fbc_work = NULL;
 348         }
 349         mutex_unlock(&dev->struct_mutex);
 350
 351         kfree(work);
 352 }
 353
 354 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 355 {
 356         if (dev_priv->fbc.fbc_work == NULL)
 357                 return;
 358
 359         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 360
 361         /* Synchronisation is provided by struct_mutex and checking of
 362          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 363          * entirely asynchronously.
 364          */
 365         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 366                 /* tasklet was killed before being run, clean up */
 367                 kfree(dev_priv->fbc.fbc_work);
 368
 369         /* Mark the work as no longer wanted so that if it does
 370          * wake-up (because the work was already running and waiting
 371          * for our mutex), it will discover that is no longer
 372          * necessary to run.
 373          */
 374         dev_priv->fbc.fbc_work = NULL;
 375 }
 376
 377 static void intel_enable_fbc(struct drm_crtc *crtc)
 378 {
 379         struct intel_fbc_work *work;
 380         struct drm_device *dev = crtc->dev;
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382
 383         if (!dev_priv->display.enable_fbc)
 384                 return;
 385
 386         intel_cancel_fbc_work(dev_priv);
 387
 388         work = kzalloc(sizeof(*work), GFP_KERNEL);
 389         if (work == NULL) {
 390                 DRM_ERROR("Failed to allocate FBC work structure\n");
 391                 dev_priv->display.enable_fbc(crtc);
 392                 return;
 393         }
 394
 395         work->crtc = crtc;
 396         work->fb = crtc->primary->fb;
 397         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 398
 399         dev_priv->fbc.fbc_work = work;
 400
 401         /* Delay the actual enabling to let pageflipping cease and the
 402          * display to settle before starting the compression. Note that
 403          * this delay also serves a second purpose: it allows for a
 404          * vblank to pass after disabling the FBC before we attempt
 405          * to modify the control registers.
 406          *
 407          * A more complicated solution would involve tracking vblanks
 408          * following the termination of the page-flipping sequence
 409          * and indeed performing the enable as a co-routine and not
 410          * waiting synchronously upon the vblank.
 411          *
 412          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 413          */
 414         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 415 }
 416
 417 void intel_disable_fbc(struct drm_device *dev)
 418 {
 419         struct drm_i915_private *dev_priv = dev->dev_private;
 420
 421         intel_cancel_fbc_work(dev_priv);
 422
 423         if (!dev_priv->display.disable_fbc)
 424                 return;
 425
 426         dev_priv->display.disable_fbc(dev);
 427         dev_priv->fbc.plane = -1;
 428 }
 429
 430 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 431                               enum no_fbc_reason reason)
 432 {
 433         if (dev_priv->fbc.no_fbc_reason == reason)
 434                 return false;
 435
 436         dev_priv->fbc.no_fbc_reason = reason;
 437         return true;
 438 }
 439
 440 /**
 441  * intel_update_fbc - enable/disable FBC as needed
 442  * @dev: the drm_device
 443  *
 444  * Set up the framebuffer compression hardware at mode set time.  We
 445  * enable it if possible:
 446  *   - plane A only (on pre-965)
 447  *   - no pixel mulitply/line duplication
 448  *   - no alpha buffer discard
 449  *   - no dual wide
 450  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 451  *
 452  * We can't assume that any compression will take place (worst case),
 453  * so the compressed buffer has to be the same size as the uncompressed
 454  * one.  It also must reside (along with the line length buffer) in
 455  * stolen memory.
 456  *
 457  * We need to enable/disable FBC on a global basis.
 458  */
 459 void intel_update_fbc(struct drm_device *dev)
 460 {
 461         struct drm_i915_private *dev_priv = dev->dev_private;
 462         struct drm_crtc *crtc = NULL, *tmp_crtc;
 463         struct intel_crtc *intel_crtc;
 464         struct drm_framebuffer *fb;
 465         struct intel_framebuffer *intel_fb;
 466         struct drm_i915_gem_object *obj;
 467         const struct drm_display_mode *adjusted_mode;
 468         unsigned int max_width, max_height;
 469
 470         if (!HAS_FBC(dev)) {
 471                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 472                 return;
 473         }
 474
 475         if (!i915.powersave) {
 476                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 477                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 478                 return;
 479         }
 480
 481         /*
 482          * If FBC is already on, we just have to verify that we can
 483          * keep it that way...
 484          * Need to disable if:
 485          *   - more than one pipe is active
 486          *   - changing FBC params (stride, fence, mode)
 487          *   - new fb is too large to fit in compressed buffer
 488          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 489          */
 490         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 491                 if (intel_crtc_active(tmp_crtc) &&
 492                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 493                         if (crtc) {
 494                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 495                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 496                                 goto out_disable;
 497                         }
 498                         crtc = tmp_crtc;
 499                 }
 500         }
 501
 502         if (!crtc || crtc->primary->fb == NULL) {
 503                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 504                         DRM_DEBUG_KMS("no output, disabling\n");
 505                 goto out_disable;
 506         }
 507
 508         intel_crtc = to_intel_crtc(crtc);
 509         fb = crtc->primary->fb;
 510         intel_fb = to_intel_framebuffer(fb);
 511         obj = intel_fb->obj;
 512         adjusted_mode = &intel_crtc->config.adjusted_mode;
 513
 514         if (i915.enable_fbc < 0 &&
 515             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
 516                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 517                         DRM_DEBUG_KMS("disabled per chip default\n");
 518                 goto out_disable;
 519         }
 520         if (!i915.enable_fbc) {
 521                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 522                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 523                 goto out_disable;
 524         }
 525         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 526             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 527                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 528                         DRM_DEBUG_KMS("mode incompatible with compression, "
 529                                       "disabling\n");
 530                 goto out_disable;
 531         }
 532
 533         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 534                 max_width = 4096;
 535                 max_height = 2048;
 536         } else {
 537                 max_width = 2048;
 538                 max_height = 1536;
 539         }
 540         if (intel_crtc->config.pipe_src_w > max_width ||
 541             intel_crtc->config.pipe_src_h > max_height) {
 542                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 543                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 544                 goto out_disable;
 545         }
 546         if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
 547             intel_crtc->plane != PLANE_A) {
 548                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 549                         DRM_DEBUG_KMS("plane not A, disabling compression\n");
 550                 goto out_disable;
 551         }
 552
 553         /* The use of a CPU fence is mandatory in order to detect writes
 554          * by the CPU to the scanout and trigger updates to the FBC.
 555          */
 556         if (obj->tiling_mode != I915_TILING_X ||
 557             obj->fence_reg == I915_FENCE_REG_NONE) {
 558                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 559                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 560                 goto out_disable;
 561         }
 562
 563         /* If the kernel debugger is active, always disable compression */
 564         if (in_dbg_master())
 565                 goto out_disable;
 566
 567         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 568                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 569                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 570                 goto out_disable;
 571         }
 572
 573         /* If the scanout has not changed, don't modify the FBC settings.
 574          * Note that we make the fundamental assumption that the fb->obj
 575          * cannot be unpinned (and have its GTT offset and fence revoked)
 576          * without first being decoupled from the scanout and FBC disabled.
 577          */
 578         if (dev_priv->fbc.plane == intel_crtc->plane &&
 579             dev_priv->fbc.fb_id == fb->base.id &&
 580             dev_priv->fbc.y == crtc->y)
 581                 return;
 582
 583         if (intel_fbc_enabled(dev)) {
 584                 /* We update FBC along two paths, after changing fb/crtc
 585                  * configuration (modeswitching) and after page-flipping
 586                  * finishes. For the latter, we know that not only did
 587                  * we disable the FBC at the start of the page-flip
 588                  * sequence, but also more than one vblank has passed.
 589                  *
 590                  * For the former case of modeswitching, it is possible
 591                  * to switch between two FBC valid configurations
 592                  * instantaneously so we do need to disable the FBC
 593                  * before we can modify its control registers. We also
 594                  * have to wait for the next vblank for that to take
 595                  * effect. However, since we delay enabling FBC we can
 596                  * assume that a vblank has passed since disabling and
 597                  * that we can safely alter the registers in the deferred
 598                  * callback.
 599                  *
 600                  * In the scenario that we go from a valid to invalid
 601                  * and then back to valid FBC configuration we have
 602                  * no strict enforcement that a vblank occurred since
 603                  * disabling the FBC. However, along all current pipe
 604                  * disabling paths we do need to wait for a vblank at
 605                  * some point. And we wait before enabling FBC anyway.
 606                  */
 607                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 608                 intel_disable_fbc(dev);
 609         }
 610
 611         intel_enable_fbc(crtc);
 612         dev_priv->fbc.no_fbc_reason = FBC_OK;
 613         return;
 614
 615 out_disable:
 616         /* Multiple disables should be harmless */
 617         if (intel_fbc_enabled(dev)) {
 618                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 619                 intel_disable_fbc(dev);
 620         }
 621         i915_gem_stolen_cleanup_compression(dev);
 622 }
 623
 624 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 625 {
 626         struct drm_i915_private *dev_priv = dev->dev_private;
 627         u32 tmp;
 628
 629         tmp = I915_READ(CLKCFG);
 630
 631         switch (tmp & CLKCFG_FSB_MASK) {
 632         case CLKCFG_FSB_533:
 633                 dev_priv->fsb_freq = 533; /* 133*4 */
 634                 break;
 635         case CLKCFG_FSB_800:
 636                 dev_priv->fsb_freq = 800; /* 200*4 */
 637                 break;
 638         case CLKCFG_FSB_667:
 639                 dev_priv->fsb_freq =  667; /* 167*4 */
 640                 break;
 641         case CLKCFG_FSB_400:
 642                 dev_priv->fsb_freq = 400; /* 100*4 */
 643                 break;
 644         }
 645
 646         switch (tmp & CLKCFG_MEM_MASK) {
 647         case CLKCFG_MEM_533:
 648                 dev_priv->mem_freq = 533;
 649                 break;
 650         case CLKCFG_MEM_667:
 651                 dev_priv->mem_freq = 667;
 652                 break;
 653         case CLKCFG_MEM_800:
 654                 dev_priv->mem_freq = 800;
 655                 break;
 656         }
 657
 658         /* detect pineview DDR3 setting */
 659         tmp = I915_READ(CSHRDDR3CTL);
 660         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 661 }
 662
 663 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 664 {
 665         struct drm_i915_private *dev_priv = dev->dev_private;
 666         u16 ddrpll, csipll;
 667
 668         ddrpll = I915_READ16(DDRMPLL1);
 669         csipll = I915_READ16(CSIPLL0);
 670
 671         switch (ddrpll & 0xff) {
 672         case 0xc:
 673                 dev_priv->mem_freq = 800;
 674                 break;
 675         case 0x10:
 676                 dev_priv->mem_freq = 1066;
 677                 break;
 678         case 0x14:
 679                 dev_priv->mem_freq = 1333;
 680                 break;
 681         case 0x18:
 682                 dev_priv->mem_freq = 1600;
 683                 break;
 684         default:
 685                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 686                                  ddrpll & 0xff);
 687                 dev_priv->mem_freq = 0;
 688                 break;
 689         }
 690
 691         dev_priv->ips.r_t = dev_priv->mem_freq;
 692
 693         switch (csipll & 0x3ff) {
 694         case 0x00c:
 695                 dev_priv->fsb_freq = 3200;
 696                 break;
 697         case 0x00e:
 698                 dev_priv->fsb_freq = 3733;
 699                 break;
 700         case 0x010:
 701                 dev_priv->fsb_freq = 4266;
 702                 break;
 703         case 0x012:
 704                 dev_priv->fsb_freq = 4800;
 705                 break;
 706         case 0x014:
 707                 dev_priv->fsb_freq = 5333;
 708                 break;
 709         case 0x016:
 710                 dev_priv->fsb_freq = 5866;
 711                 break;
 712         case 0x018:
 713                 dev_priv->fsb_freq = 6400;
 714                 break;
 715         default:
 716                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 717                                  csipll & 0x3ff);
 718                 dev_priv->fsb_freq = 0;
 719                 break;
 720         }
 721
 722         if (dev_priv->fsb_freq == 3200) {
 723                 dev_priv->ips.c_m = 0;
 724         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 725                 dev_priv->ips.c_m = 1;
 726         } else {
 727                 dev_priv->ips.c_m = 2;
 728         }
 729 }
 730
 731 static const struct cxsr_latency cxsr_latency_table[] = {
 732         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 733         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 734         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 735         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 736         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 737
 738         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 739         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 740         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 741         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 742         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 743
 744         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 745         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 746         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 747         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 748         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 749
 750         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 751         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 752         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 753         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 754         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 755
 756         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 757         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 758         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 759         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 760         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 761
 762         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 763         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 764         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 765         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 766         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 767 };
 768
 769 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 770                                                          int is_ddr3,
 771                                                          int fsb,
 772                                                          int mem)
 773 {
 774         const struct cxsr_latency *latency;
 775         int i;
 776
 777         if (fsb == 0 || mem == 0)
 778                 return NULL;
 779
 780         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 781                 latency = &cxsr_latency_table[i];
 782                 if (is_desktop == latency->is_desktop &&
 783                     is_ddr3 == latency->is_ddr3 &&
 784                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 785                         return latency;
 786         }
 787
 788         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 789
 790         return NULL;
 791 }
 792
 793 static void pineview_disable_cxsr(struct drm_device *dev)
 794 {
 795         struct drm_i915_private *dev_priv = dev->dev_private;
 796
 797         /* deactivate cxsr */
 798         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 799 }
 800
 801 /*
 802  * Latency for FIFO fetches is dependent on several factors:
 803  *   - memory configuration (speed, channels)
 804  *   - chipset
 805  *   - current MCH state
 806  * It can be fairly high in some situations, so here we assume a fairly
 807  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 808  * set this value too high, the FIFO will fetch frequently to stay full)
 809  * and power consumption (set it too low to save power and we might see
 810  * FIFO underruns and display "flicker").
 811  *
 812  * A value of 5us seems to be a good balance; safe for very low end
 813  * platforms but not overly aggressive on lower latency configs.
 814  */
 815 static const int latency_ns = 5000;
 816
 817 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 818 {
 819         struct drm_i915_private *dev_priv = dev->dev_private;
 820         uint32_t dsparb = I915_READ(DSPARB);
 821         int size;
 822
 823         size = dsparb & 0x7f;
 824         if (plane)
 825                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 826
 827         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 828                       plane ? "B" : "A", size);
 829
 830         return size;
 831 }
 832
 833 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 834 {
 835         struct drm_i915_private *dev_priv = dev->dev_private;
 836         uint32_t dsparb = I915_READ(DSPARB);
 837         int size;
 838
 839         size = dsparb & 0x1ff;
 840         if (plane)
 841                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 842         size >>= 1; /* Convert to cachelines */
 843
 844         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 845                       plane ? "B" : "A", size);
 846
 847         return size;
 848 }
 849
 850 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 851 {
 852         struct drm_i915_private *dev_priv = dev->dev_private;
 853         uint32_t dsparb = I915_READ(DSPARB);
 854         int size;
 855
 856         size = dsparb & 0x7f;
 857         size >>= 2; /* Convert to cachelines */
 858
 859         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 860                       plane ? "B" : "A",
 861                       size);
 862
 863         return size;
 864 }
 865
 866 /* Pineview has different values for various configs */
 867 static const struct intel_watermark_params pineview_display_wm = {
 868         PINEVIEW_DISPLAY_FIFO,
 869         PINEVIEW_MAX_WM,
 870         PINEVIEW_DFT_WM,
 871         PINEVIEW_GUARD_WM,
 872         PINEVIEW_FIFO_LINE_SIZE
 873 };
 874 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 875         PINEVIEW_DISPLAY_FIFO,
 876         PINEVIEW_MAX_WM,
 877         PINEVIEW_DFT_HPLLOFF_WM,
 878         PINEVIEW_GUARD_WM,
 879         PINEVIEW_FIFO_LINE_SIZE
 880 };
 881 static const struct intel_watermark_params pineview_cursor_wm = {
 882         PINEVIEW_CURSOR_FIFO,
 883         PINEVIEW_CURSOR_MAX_WM,
 884         PINEVIEW_CURSOR_DFT_WM,
 885         PINEVIEW_CURSOR_GUARD_WM,
 886         PINEVIEW_FIFO_LINE_SIZE,
 887 };
 888 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 889         PINEVIEW_CURSOR_FIFO,
 890         PINEVIEW_CURSOR_MAX_WM,
 891         PINEVIEW_CURSOR_DFT_WM,
 892         PINEVIEW_CURSOR_GUARD_WM,
 893         PINEVIEW_FIFO_LINE_SIZE
 894 };
 895 static const struct intel_watermark_params g4x_wm_info = {
 896         G4X_FIFO_SIZE,
 897         G4X_MAX_WM,
 898         G4X_MAX_WM,
 899         2,
 900         G4X_FIFO_LINE_SIZE,
 901 };
 902 static const struct intel_watermark_params g4x_cursor_wm_info = {
 903         I965_CURSOR_FIFO,
 904         I965_CURSOR_MAX_WM,
 905         I965_CURSOR_DFT_WM,
 906         2,
 907         G4X_FIFO_LINE_SIZE,
 908 };
 909 static const struct intel_watermark_params valleyview_wm_info = {
 910         VALLEYVIEW_FIFO_SIZE,
 911         VALLEYVIEW_MAX_WM,
 912         VALLEYVIEW_MAX_WM,
 913         2,
 914         G4X_FIFO_LINE_SIZE,
 915 };
 916 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 917         I965_CURSOR_FIFO,
 918         VALLEYVIEW_CURSOR_MAX_WM,
 919         I965_CURSOR_DFT_WM,
 920         2,
 921         G4X_FIFO_LINE_SIZE,
 922 };
 923 static const struct intel_watermark_params i965_cursor_wm_info = {
 924         I965_CURSOR_FIFO,
 925         I965_CURSOR_MAX_WM,
 926         I965_CURSOR_DFT_WM,
 927         2,
 928         I915_FIFO_LINE_SIZE,
 929 };
 930 static const struct intel_watermark_params i945_wm_info = {
 931         I945_FIFO_SIZE,
 932         I915_MAX_WM,
 933         1,
 934         2,
 935         I915_FIFO_LINE_SIZE
 936 };
 937 static const struct intel_watermark_params i915_wm_info = {
 938         I915_FIFO_SIZE,
 939         I915_MAX_WM,
 940         1,
 941         2,
 942         I915_FIFO_LINE_SIZE
 943 };
 944 static const struct intel_watermark_params i830_wm_info = {
 945         I855GM_FIFO_SIZE,
 946         I915_MAX_WM,
 947         1,
 948         2,
 949         I830_FIFO_LINE_SIZE
 950 };
 951 static const struct intel_watermark_params i845_wm_info = {
 952         I830_FIFO_SIZE,
 953         I915_MAX_WM,
 954         1,
 955         2,
 956         I830_FIFO_LINE_SIZE
 957 };
 958
 959 /**
 960  * intel_calculate_wm - calculate watermark level
 961  * @clock_in_khz: pixel clock
 962  * @wm: chip FIFO params
 963  * @pixel_size: display pixel size
 964  * @latency_ns: memory latency for the platform
 965  *
 966  * Calculate the watermark level (the level at which the display plane will
 967  * start fetching from memory again).  Each chip has a different display
 968  * FIFO size and allocation, so the caller needs to figure that out and pass
 969  * in the correct intel_watermark_params structure.
 970  *
 971  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 972  * on the pixel size.  When it reaches the watermark level, it'll start
 973  * fetching FIFO line sized based chunks from memory until the FIFO fills
 974  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 975  * will occur, and a display engine hang could result.
 976  */
 977 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 978                                         const struct intel_watermark_params *wm,
 979                                         int fifo_size,
 980                                         int pixel_size,
 981                                         unsigned long latency_ns)
 982 {
 983         long entries_required, wm_size;
 984
 985         /*
 986          * Note: we need to make sure we don't overflow for various clock &
 987          * latency values.
 988          * clocks go from a few thousand to several hundred thousand.
 989          * latency is usually a few thousand
 990          */
 991         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 992                 1000;
 993         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 994
 995         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 996
 997         wm_size = fifo_size - (entries_required + wm->guard_size);
 998
 999         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1000
1001         /* Don't promote wm_size to unsigned... */
1002         if (wm_size > (long)wm->max_wm)
1003                 wm_size = wm->max_wm;
1004         if (wm_size <= 0)
1005                 wm_size = wm->default_wm;
1006         return wm_size;
1007 }
1008
1009 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1010 {
1011         struct drm_crtc *crtc, *enabled = NULL;
1012
1013         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1014                 if (intel_crtc_active(crtc)) {
1015                         if (enabled)
1016                                 return NULL;
1017                         enabled = crtc;
1018                 }
1019         }
1020
1021         return enabled;
1022 }
1023
1024 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1025 {
1026         struct drm_device *dev = unused_crtc->dev;
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028         struct drm_crtc *crtc;
1029         const struct cxsr_latency *latency;
1030         u32 reg;
1031         unsigned long wm;
1032
1033         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1034                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1035         if (!latency) {
1036                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1037                 pineview_disable_cxsr(dev);
1038                 return;
1039         }
1040
1041         crtc = single_enabled_crtc(dev);
1042         if (crtc) {
1043                 const struct drm_display_mode *adjusted_mode;
1044                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1045                 int clock;
1046
1047                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1048                 clock = adjusted_mode->crtc_clock;
1049
1050                 /* Display SR */
1051                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1052                                         pineview_display_wm.fifo_size,
1053                                         pixel_size, latency->display_sr);
1054                 reg = I915_READ(DSPFW1);
1055                 reg &= ~DSPFW_SR_MASK;
1056                 reg |= wm << DSPFW_SR_SHIFT;
1057                 I915_WRITE(DSPFW1, reg);
1058                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1059
1060                 /* cursor SR */
1061                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1062                                         pineview_display_wm.fifo_size,
1063                                         pixel_size, latency->cursor_sr);
1064                 reg = I915_READ(DSPFW3);
1065                 reg &= ~DSPFW_CURSOR_SR_MASK;
1066                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1067                 I915_WRITE(DSPFW3, reg);
1068
1069                 /* Display HPLL off SR */
1070                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1071                                         pineview_display_hplloff_wm.fifo_size,
1072                                         pixel_size, latency->display_hpll_disable);
1073                 reg = I915_READ(DSPFW3);
1074                 reg &= ~DSPFW_HPLL_SR_MASK;
1075                 reg |= wm & DSPFW_HPLL_SR_MASK;
1076                 I915_WRITE(DSPFW3, reg);
1077
1078                 /* cursor HPLL off SR */
1079                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1080                                         pineview_display_hplloff_wm.fifo_size,
1081                                         pixel_size, latency->cursor_hpll_disable);
1082                 reg = I915_READ(DSPFW3);
1083                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1084                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1085                 I915_WRITE(DSPFW3, reg);
1086                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1087
1088                 /* activate cxsr */
1089                 I915_WRITE(DSPFW3,
1090                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1091                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1092         } else {
1093                 pineview_disable_cxsr(dev);
1094                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1095         }
1096 }
1097
1098 static bool g4x_compute_wm0(struct drm_device *dev,
1099                             int plane,
1100                             const struct intel_watermark_params *display,
1101                             int display_latency_ns,
1102                             const struct intel_watermark_params *cursor,
1103                             int cursor_latency_ns,
1104                             int *plane_wm,
1105                             int *cursor_wm)
1106 {
1107         struct drm_crtc *crtc;
1108         const struct drm_display_mode *adjusted_mode;
1109         int htotal, hdisplay, clock, pixel_size;
1110         int line_time_us, line_count;
1111         int entries, tlb_miss;
1112
1113         crtc = intel_get_crtc_for_plane(dev, plane);
1114         if (!intel_crtc_active(crtc)) {
1115                 *cursor_wm = cursor->guard_size;
1116                 *plane_wm = display->guard_size;
1117                 return false;
1118         }
1119
1120         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1121         clock = adjusted_mode->crtc_clock;
1122         htotal = adjusted_mode->crtc_htotal;
1123         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1124         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1125
1126         /* Use the small buffer method to calculate plane watermark */
1127         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1128         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1129         if (tlb_miss > 0)
1130                 entries += tlb_miss;
1131         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1132         *plane_wm = entries + display->guard_size;
1133         if (*plane_wm > (int)display->max_wm)
1134                 *plane_wm = display->max_wm;
1135
1136         /* Use the large buffer method to calculate cursor watermark */
1137         line_time_us = max(htotal * 1000 / clock, 1);
1138         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1139         entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1140         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1141         if (tlb_miss > 0)
1142                 entries += tlb_miss;
1143         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1144         *cursor_wm = entries + cursor->guard_size;
1145         if (*cursor_wm > (int)cursor->max_wm)
1146                 *cursor_wm = (int)cursor->max_wm;
1147
1148         return true;
1149 }
1150
1151 /*
1152  * Check the wm result.
1153  *
1154  * If any calculated watermark values is larger than the maximum value that
1155  * can be programmed into the associated watermark register, that watermark
1156  * must be disabled.
1157  */
1158 static bool g4x_check_srwm(struct drm_device *dev,
1159                            int display_wm, int cursor_wm,
1160                            const struct intel_watermark_params *display,
1161                            const struct intel_watermark_params *cursor)
1162 {
1163         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1164                       display_wm, cursor_wm);
1165
1166         if (display_wm > display->max_wm) {
1167                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1168                               display_wm, display->max_wm);
1169                 return false;
1170         }
1171
1172         if (cursor_wm > cursor->max_wm) {
1173                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1174                               cursor_wm, cursor->max_wm);
1175                 return false;
1176         }
1177
1178         if (!(display_wm || cursor_wm)) {
1179                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1180                 return false;
1181         }
1182
1183         return true;
1184 }
1185
1186 static bool g4x_compute_srwm(struct drm_device *dev,
1187                              int plane,
1188                              int latency_ns,
1189                              const struct intel_watermark_params *display,
1190                              const struct intel_watermark_params *cursor,
1191                              int *display_wm, int *cursor_wm)
1192 {
1193         struct drm_crtc *crtc;
1194         const struct drm_display_mode *adjusted_mode;
1195         int hdisplay, htotal, pixel_size, clock;
1196         unsigned long line_time_us;
1197         int line_count, line_size;
1198         int small, large;
1199         int entries;
1200
1201         if (!latency_ns) {
1202                 *display_wm = *cursor_wm = 0;
1203                 return false;
1204         }
1205
1206         crtc = intel_get_crtc_for_plane(dev, plane);
1207         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1208         clock = adjusted_mode->crtc_clock;
1209         htotal = adjusted_mode->crtc_htotal;
1210         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1211         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1212
1213         line_time_us = max(htotal * 1000 / clock, 1);
1214         line_count = (latency_ns / line_time_us + 1000) / 1000;
1215         line_size = hdisplay * pixel_size;
1216
1217         /* Use the minimum of the small and large buffer method for primary */
1218         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1219         large = line_count * line_size;
1220
1221         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1222         *display_wm = entries + display->guard_size;
1223
1224         /* calculate the self-refresh watermark for display cursor */
1225         entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1226         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1227         *cursor_wm = entries + cursor->guard_size;
1228
1229         return g4x_check_srwm(dev,
1230                               *display_wm, *cursor_wm,
1231                               display, cursor);
1232 }
1233
1234 static bool vlv_compute_drain_latency(struct drm_device *dev,
1235                                      int plane,
1236                                      int *plane_prec_mult,
1237                                      int *plane_dl,
1238                                      int *cursor_prec_mult,
1239                                      int *cursor_dl)
1240 {
1241         struct drm_crtc *crtc;
1242         int clock, pixel_size;
1243         int entries;
1244
1245         crtc = intel_get_crtc_for_plane(dev, plane);
1246         if (!intel_crtc_active(crtc))
1247                 return false;
1248
1249         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1250         pixel_size = crtc->primary->fb->bits_per_pixel / 8;     /* BPP */
1251
1252         entries = (clock / 1000) * pixel_size;
1253         *plane_prec_mult = (entries > 256) ?
1254                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1255         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1256                                                      pixel_size);
1257
1258         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1259         *cursor_prec_mult = (entries > 256) ?
1260                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1261         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1262
1263         return true;
1264 }
1265
1266 /*
1267  * Update drain latency registers of memory arbiter
1268  *
1269  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1270  * to be programmed. Each plane has a drain latency multiplier and a drain
1271  * latency value.
1272  */
1273
1274 static void vlv_update_drain_latency(struct drm_device *dev)
1275 {
1276         struct drm_i915_private *dev_priv = dev->dev_private;
1277         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1278         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1279         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1280                                                         either 16 or 32 */
1281
1282         /* For plane A, Cursor A */
1283         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1284                                       &cursor_prec_mult, &cursora_dl)) {
1285                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1286                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1287                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1288                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1289
1290                 I915_WRITE(VLV_DDL1, cursora_prec |
1291                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1292                                 planea_prec | planea_dl);
1293         }
1294
1295         /* For plane B, Cursor B */
1296         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1297                                       &cursor_prec_mult, &cursorb_dl)) {
1298                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1299                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1300                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1301                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1302
1303                 I915_WRITE(VLV_DDL2, cursorb_prec |
1304                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1305                                 planeb_prec | planeb_dl);
1306         }
1307 }
1308
1309 #define single_plane_enabled(mask) is_power_of_2(mask)
1310
1311 static void valleyview_update_wm(struct drm_crtc *crtc)
1312 {
1313         struct drm_device *dev = crtc->dev;
1314         static const int sr_latency_ns = 12000;
1315         struct drm_i915_private *dev_priv = dev->dev_private;
1316         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1317         int plane_sr, cursor_sr;
1318         int ignore_plane_sr, ignore_cursor_sr;
1319         unsigned int enabled = 0;
1320
1321         vlv_update_drain_latency(dev);
1322
1323         if (g4x_compute_wm0(dev, PIPE_A,
1324                             &valleyview_wm_info, latency_ns,
1325                             &valleyview_cursor_wm_info, latency_ns,
1326                             &planea_wm, &cursora_wm))
1327                 enabled |= 1 << PIPE_A;
1328
1329         if (g4x_compute_wm0(dev, PIPE_B,
1330                             &valleyview_wm_info, latency_ns,
1331                             &valleyview_cursor_wm_info, latency_ns,
1332                             &planeb_wm, &cursorb_wm))
1333                 enabled |= 1 << PIPE_B;
1334
1335         if (single_plane_enabled(enabled) &&
1336             g4x_compute_srwm(dev, ffs(enabled) - 1,
1337                              sr_latency_ns,
1338                              &valleyview_wm_info,
1339                              &valleyview_cursor_wm_info,
1340                              &plane_sr, &ignore_cursor_sr) &&
1341             g4x_compute_srwm(dev, ffs(enabled) - 1,
1342                              2*sr_latency_ns,
1343                              &valleyview_wm_info,
1344                              &valleyview_cursor_wm_info,
1345                              &ignore_plane_sr, &cursor_sr)) {
1346                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1347         } else {
1348                 I915_WRITE(FW_BLC_SELF_VLV,
1349                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1350                 plane_sr = cursor_sr = 0;
1351         }
1352
1353         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1354                       planea_wm, cursora_wm,
1355                       planeb_wm, cursorb_wm,
1356                       plane_sr, cursor_sr);
1357
1358         I915_WRITE(DSPFW1,
1359                    (plane_sr << DSPFW_SR_SHIFT) |
1360                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1361                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1362                    planea_wm);
1363         I915_WRITE(DSPFW2,
1364                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1365                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1366         I915_WRITE(DSPFW3,
1367                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1368                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1369 }
1370
1371 static void g4x_update_wm(struct drm_crtc *crtc)
1372 {
1373         struct drm_device *dev = crtc->dev;
1374         static const int sr_latency_ns = 12000;
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377         int plane_sr, cursor_sr;
1378         unsigned int enabled = 0;
1379
1380         if (g4x_compute_wm0(dev, PIPE_A,
1381                             &g4x_wm_info, latency_ns,
1382                             &g4x_cursor_wm_info, latency_ns,
1383                             &planea_wm, &cursora_wm))
1384                 enabled |= 1 << PIPE_A;
1385
1386         if (g4x_compute_wm0(dev, PIPE_B,
1387                             &g4x_wm_info, latency_ns,
1388                             &g4x_cursor_wm_info, latency_ns,
1389                             &planeb_wm, &cursorb_wm))
1390                 enabled |= 1 << PIPE_B;
1391
1392         if (single_plane_enabled(enabled) &&
1393             g4x_compute_srwm(dev, ffs(enabled) - 1,
1394                              sr_latency_ns,
1395                              &g4x_wm_info,
1396                              &g4x_cursor_wm_info,
1397                              &plane_sr, &cursor_sr)) {
1398                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1399         } else {
1400                 I915_WRITE(FW_BLC_SELF,
1401                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1402                 plane_sr = cursor_sr = 0;
1403         }
1404
1405         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1406                       planea_wm, cursora_wm,
1407                       planeb_wm, cursorb_wm,
1408                       plane_sr, cursor_sr);
1409
1410         I915_WRITE(DSPFW1,
1411                    (plane_sr << DSPFW_SR_SHIFT) |
1412                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1413                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1414                    planea_wm);
1415         I915_WRITE(DSPFW2,
1416                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1417                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1418         /* HPLL off in SR has some issues on G4x... disable it */
1419         I915_WRITE(DSPFW3,
1420                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1421                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1422 }
1423
1424 static void i965_update_wm(struct drm_crtc *unused_crtc)
1425 {
1426         struct drm_device *dev = unused_crtc->dev;
1427         struct drm_i915_private *dev_priv = dev->dev_private;
1428         struct drm_crtc *crtc;
1429         int srwm = 1;
1430         int cursor_sr = 16;
1431
1432         /* Calc sr entries for one plane configs */
1433         crtc = single_enabled_crtc(dev);
1434         if (crtc) {
1435                 /* self-refresh has much higher latency */
1436                 static const int sr_latency_ns = 12000;
1437                 const struct drm_display_mode *adjusted_mode =
1438                         &to_intel_crtc(crtc)->config.adjusted_mode;
1439                 int clock = adjusted_mode->crtc_clock;
1440                 int htotal = adjusted_mode->crtc_htotal;
1441                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1442                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1443                 unsigned long line_time_us;
1444                 int entries;
1445
1446                 line_time_us = max(htotal * 1000 / clock, 1);
1447
1448                 /* Use ns/us then divide to preserve precision */
1449                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450                         pixel_size * hdisplay;
1451                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1452                 srwm = I965_FIFO_SIZE - entries;
1453                 if (srwm < 0)
1454                         srwm = 1;
1455                 srwm &= 0x1ff;
1456                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1457                               entries, srwm);
1458
1459                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1460                         pixel_size * to_intel_crtc(crtc)->cursor_width;
1461                 entries = DIV_ROUND_UP(entries,
1462                                           i965_cursor_wm_info.cacheline_size);
1463                 cursor_sr = i965_cursor_wm_info.fifo_size -
1464                         (entries + i965_cursor_wm_info.guard_size);
1465
1466                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1467                         cursor_sr = i965_cursor_wm_info.max_wm;
1468
1469                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470                               "cursor %d\n", srwm, cursor_sr);
1471
1472                 if (IS_CRESTLINE(dev))
1473                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1474         } else {
1475                 /* Turn off self refresh if both pipes are enabled */
1476                 if (IS_CRESTLINE(dev))
1477                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1478                                    & ~FW_BLC_SELF_EN);
1479         }
1480
1481         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1482                       srwm);
1483
1484         /* 965 has limitations... */
1485         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1486                    (8 << 16) | (8 << 8) | (8 << 0));
1487         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1488         /* update cursor SR watermark */
1489         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490 }
1491
1492 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1493 {
1494         struct drm_device *dev = unused_crtc->dev;
1495         struct drm_i915_private *dev_priv = dev->dev_private;
1496         const struct intel_watermark_params *wm_info;
1497         uint32_t fwater_lo;
1498         uint32_t fwater_hi;
1499         int cwm, srwm = 1;
1500         int fifo_size;
1501         int planea_wm, planeb_wm;
1502         struct drm_crtc *crtc, *enabled = NULL;
1503
1504         if (IS_I945GM(dev))
1505                 wm_info = &i945_wm_info;
1506         else if (!IS_GEN2(dev))
1507                 wm_info = &i915_wm_info;
1508         else
1509                 wm_info = &i830_wm_info;
1510
1511         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1512         crtc = intel_get_crtc_for_plane(dev, 0);
1513         if (intel_crtc_active(crtc)) {
1514                 const struct drm_display_mode *adjusted_mode;
1515                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1516                 if (IS_GEN2(dev))
1517                         cpp = 4;
1518
1519                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1520                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1521                                                wm_info, fifo_size, cpp,
1522                                                latency_ns);
1523                 enabled = crtc;
1524         } else
1525                 planea_wm = fifo_size - wm_info->guard_size;
1526
1527         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1528         crtc = intel_get_crtc_for_plane(dev, 1);
1529         if (intel_crtc_active(crtc)) {
1530                 const struct drm_display_mode *adjusted_mode;
1531                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1532                 if (IS_GEN2(dev))
1533                         cpp = 4;
1534
1535                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1536                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1537                                                wm_info, fifo_size, cpp,
1538                                                latency_ns);
1539                 if (enabled == NULL)
1540                         enabled = crtc;
1541                 else
1542                         enabled = NULL;
1543         } else
1544                 planeb_wm = fifo_size - wm_info->guard_size;
1545
1546         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
1548         if (IS_I915GM(dev) && enabled) {
1549                 struct intel_framebuffer *fb;
1550
1551                 fb = to_intel_framebuffer(enabled->primary->fb);
1552
1553                 /* self-refresh seems busted with untiled */
1554                 if (fb->obj->tiling_mode == I915_TILING_NONE)
1555                         enabled = NULL;
1556         }
1557
1558         /*
1559          * Overlay gets an aggressive default since video jitter is bad.
1560          */
1561         cwm = 2;
1562
1563         /* Play safe and disable self-refresh before adjusting watermarks. */
1564         if (IS_I945G(dev) || IS_I945GM(dev))
1565                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1566         else if (IS_I915GM(dev))
1567                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
1568
1569         /* Calc sr entries for one plane configs */
1570         if (HAS_FW_BLC(dev) && enabled) {
1571                 /* self-refresh has much higher latency */
1572                 static const int sr_latency_ns = 6000;
1573                 const struct drm_display_mode *adjusted_mode =
1574                         &to_intel_crtc(enabled)->config.adjusted_mode;
1575                 int clock = adjusted_mode->crtc_clock;
1576                 int htotal = adjusted_mode->crtc_htotal;
1577                 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1578                 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1579                 unsigned long line_time_us;
1580                 int entries;
1581
1582                 line_time_us = max(htotal * 1000 / clock, 1);
1583
1584                 /* Use ns/us then divide to preserve precision */
1585                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1586                         pixel_size * hdisplay;
1587                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1588                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1589                 srwm = wm_info->fifo_size - entries;
1590                 if (srwm < 0)
1591                         srwm = 1;
1592
1593                 if (IS_I945G(dev) || IS_I945GM(dev))
1594                         I915_WRITE(FW_BLC_SELF,
1595                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1596                 else if (IS_I915GM(dev))
1597                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1598         }
1599
1600         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1601                       planea_wm, planeb_wm, cwm, srwm);
1602
1603         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1604         fwater_hi = (cwm & 0x1f);
1605
1606         /* Set request length to 8 cachelines per fetch */
1607         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1608         fwater_hi = fwater_hi | (1 << 8);
1609
1610         I915_WRITE(FW_BLC, fwater_lo);
1611         I915_WRITE(FW_BLC2, fwater_hi);
1612
1613         if (HAS_FW_BLC(dev)) {
1614                 if (enabled) {
1615                         if (IS_I945G(dev) || IS_I945GM(dev))
1616                                 I915_WRITE(FW_BLC_SELF,
1617                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1618                         else if (IS_I915GM(dev))
1619                                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
1620                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1621                 } else
1622                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1623         }
1624 }
1625
1626 static void i845_update_wm(struct drm_crtc *unused_crtc)
1627 {
1628         struct drm_device *dev = unused_crtc->dev;
1629         struct drm_i915_private *dev_priv = dev->dev_private;
1630         struct drm_crtc *crtc;
1631         const struct drm_display_mode *adjusted_mode;
1632         uint32_t fwater_lo;
1633         int planea_wm;
1634
1635         crtc = single_enabled_crtc(dev);
1636         if (crtc == NULL)
1637                 return;
1638
1639         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1640         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1641                                        &i845_wm_info,
1642                                        dev_priv->display.get_fifo_size(dev, 0),
1643                                        4, latency_ns);
1644         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1645         fwater_lo |= (3<<8) | planea_wm;
1646
1647         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1648
1649         I915_WRITE(FW_BLC, fwater_lo);
1650 }
1651
1652 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1653                                     struct drm_crtc *crtc)
1654 {
1655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1656         uint32_t pixel_rate;
1657
1658         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1659
1660         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1661          * adjust the pixel_rate here. */
1662
1663         if (intel_crtc->config.pch_pfit.enabled) {
1664                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1665                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1666
1667                 pipe_w = intel_crtc->config.pipe_src_w;
1668                 pipe_h = intel_crtc->config.pipe_src_h;
1669                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670                 pfit_h = pfit_size & 0xFFFF;
1671                 if (pipe_w < pfit_w)
1672                         pipe_w = pfit_w;
1673                 if (pipe_h < pfit_h)
1674                         pipe_h = pfit_h;
1675
1676                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1677                                      pfit_w * pfit_h);
1678         }
1679
1680         return pixel_rate;
1681 }
1682
1683 /* latency must be in 0.1us units. */
1684 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1685                                uint32_t latency)
1686 {
1687         uint64_t ret;
1688
1689         if (WARN(latency == 0, "Latency value missing\n"))
1690                 return UINT_MAX;
1691
1692         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1693         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1694
1695         return ret;
1696 }
1697
1698 /* latency must be in 0.1us units. */
1699 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1700                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1701                                uint32_t latency)
1702 {
1703         uint32_t ret;
1704
1705         if (WARN(latency == 0, "Latency value missing\n"))
1706                 return UINT_MAX;
1707
1708         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1709         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1710         ret = DIV_ROUND_UP(ret, 64) + 2;
1711         return ret;
1712 }
1713
1714 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1715                            uint8_t bytes_per_pixel)
1716 {
1717         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1718 }
1719
1720 struct ilk_pipe_wm_parameters {
1721         bool active;
1722         uint32_t pipe_htotal;
1723         uint32_t pixel_rate;
1724         struct intel_plane_wm_parameters pri;
1725         struct intel_plane_wm_parameters spr;
1726         struct intel_plane_wm_parameters cur;
1727 };
1728
1729 struct ilk_wm_maximums {
1730         uint16_t pri;
1731         uint16_t spr;
1732         uint16_t cur;
1733         uint16_t fbc;
1734 };
1735
1736 /* used in computing the new watermarks state */
1737 struct intel_wm_config {
1738         unsigned int num_pipes_active;
1739         bool sprites_enabled;
1740         bool sprites_scaled;
1741 };
1742
1743 /*
1744  * For both WM_PIPE and WM_LP.
1745  * mem_value must be in 0.1us units.
1746  */
1747 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1748                                    uint32_t mem_value,
1749                                    bool is_lp)
1750 {
1751         uint32_t method1, method2;
1752
1753         if (!params->active || !params->pri.enabled)
1754                 return 0;
1755
1756         method1 = ilk_wm_method1(params->pixel_rate,
1757                                  params->pri.bytes_per_pixel,
1758                                  mem_value);
1759
1760         if (!is_lp)
1761                 return method1;
1762
1763         method2 = ilk_wm_method2(params->pixel_rate,
1764                                  params->pipe_htotal,
1765                                  params->pri.horiz_pixels,
1766                                  params->pri.bytes_per_pixel,
1767                                  mem_value);
1768
1769         return min(method1, method2);
1770 }
1771
1772 /*
1773  * For both WM_PIPE and WM_LP.
1774  * mem_value must be in 0.1us units.
1775  */
1776 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1777                                    uint32_t mem_value)
1778 {
1779         uint32_t method1, method2;
1780
1781         if (!params->active || !params->spr.enabled)
1782                 return 0;
1783
1784         method1 = ilk_wm_method1(params->pixel_rate,
1785                                  params->spr.bytes_per_pixel,
1786                                  mem_value);
1787         method2 = ilk_wm_method2(params->pixel_rate,
1788                                  params->pipe_htotal,
1789                                  params->spr.horiz_pixels,
1790                                  params->spr.bytes_per_pixel,
1791                                  mem_value);
1792         return min(method1, method2);
1793 }
1794
1795 /*
1796  * For both WM_PIPE and WM_LP.
1797  * mem_value must be in 0.1us units.
1798  */
1799 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1800                                    uint32_t mem_value)
1801 {
1802         if (!params->active || !params->cur.enabled)
1803                 return 0;
1804
1805         return ilk_wm_method2(params->pixel_rate,
1806                               params->pipe_htotal,
1807                               params->cur.horiz_pixels,
1808                               params->cur.bytes_per_pixel,
1809                               mem_value);
1810 }
1811
1812 /* Only for WM_LP. */
1813 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1814                                    uint32_t pri_val)
1815 {
1816         if (!params->active || !params->pri.enabled)
1817                 return 0;
1818
1819         return ilk_wm_fbc(pri_val,
1820                           params->pri.horiz_pixels,
1821                           params->pri.bytes_per_pixel);
1822 }
1823
1824 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1825 {
1826         if (INTEL_INFO(dev)->gen >= 8)
1827                 return 3072;
1828         else if (INTEL_INFO(dev)->gen >= 7)
1829                 return 768;
1830         else
1831                 return 512;
1832 }
1833
1834 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1835                                          int level, bool is_sprite)
1836 {
1837         if (INTEL_INFO(dev)->gen >= 8)
1838                 /* BDW primary/sprite plane watermarks */
1839                 return level == 0 ? 255 : 2047;
1840         else if (INTEL_INFO(dev)->gen >= 7)
1841                 /* IVB/HSW primary/sprite plane watermarks */
1842                 return level == 0 ? 127 : 1023;
1843         else if (!is_sprite)
1844                 /* ILK/SNB primary plane watermarks */
1845                 return level == 0 ? 127 : 511;
1846         else
1847                 /* ILK/SNB sprite plane watermarks */
1848                 return level == 0 ? 63 : 255;
1849 }
1850
1851 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1852                                           int level)
1853 {
1854         if (INTEL_INFO(dev)->gen >= 7)
1855                 return level == 0 ? 63 : 255;
1856         else
1857                 return level == 0 ? 31 : 63;
1858 }
1859
1860 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1861 {
1862         if (INTEL_INFO(dev)->gen >= 8)
1863                 return 31;
1864         else
1865                 return 15;
1866 }
1867
1868 /* Calculate the maximum primary/sprite plane watermark */
1869 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1870                                      int level,
1871                                      const struct intel_wm_config *config,
1872                                      enum intel_ddb_partitioning ddb_partitioning,
1873                                      bool is_sprite)
1874 {
1875         unsigned int fifo_size = ilk_display_fifo_size(dev);
1876
1877         /* if sprites aren't enabled, sprites get nothing */
1878         if (is_sprite && !config->sprites_enabled)
1879                 return 0;
1880
1881         /* HSW allows LP1+ watermarks even with multiple pipes */
1882         if (level == 0 || config->num_pipes_active > 1) {
1883                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1884
1885                 /*
1886                  * For some reason the non self refresh
1887                  * FIFO size is only half of the self
1888                  * refresh FIFO size on ILK/SNB.
1889                  */
1890                 if (INTEL_INFO(dev)->gen <= 6)
1891                         fifo_size /= 2;
1892         }
1893
1894         if (config->sprites_enabled) {
1895                 /* level 0 is always calculated with 1:1 split */
1896                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1897                         if (is_sprite)
1898                                 fifo_size *= 5;
1899                         fifo_size /= 6;
1900                 } else {
1901                         fifo_size /= 2;
1902                 }
1903         }
1904
1905         /* clamp to max that the registers can hold */
1906         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1907 }
1908
1909 /* Calculate the maximum cursor plane watermark */
1910 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1911                                       int level,
1912                                       const struct intel_wm_config *config)
1913 {
1914         /* HSW LP1+ watermarks w/ multiple pipes */
1915         if (level > 0 && config->num_pipes_active > 1)
1916                 return 64;
1917
1918         /* otherwise just report max that registers can hold */
1919         return ilk_cursor_wm_reg_max(dev, level);
1920 }
1921
1922 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1923                                     int level,
1924                                     const struct intel_wm_config *config,
1925                                     enum intel_ddb_partitioning ddb_partitioning,
1926                                     struct ilk_wm_maximums *max)
1927 {
1928         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1929         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1930         max->cur = ilk_cursor_wm_max(dev, level, config);
1931         max->fbc = ilk_fbc_wm_reg_max(dev);
1932 }
1933
1934 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1935                                         int level,
1936                                         struct ilk_wm_maximums *max)
1937 {
1938         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1939         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1940         max->cur = ilk_cursor_wm_reg_max(dev, level);
1941         max->fbc = ilk_fbc_wm_reg_max(dev);
1942 }
1943
1944 static bool ilk_validate_wm_level(int level,
1945                                   const struct ilk_wm_maximums *max,
1946                                   struct intel_wm_level *result)
1947 {
1948         bool ret;
1949
1950         /* already determined to be invalid? */
1951         if (!result->enable)
1952                 return false;
1953
1954         result->enable = result->pri_val <= max->pri &&
1955                          result->spr_val <= max->spr &&
1956                          result->cur_val <= max->cur;
1957
1958         ret = result->enable;
1959
1960         /*
1961          * HACK until we can pre-compute everything,
1962          * and thus fail gracefully if LP0 watermarks
1963          * are exceeded...
1964          */
1965         if (level == 0 && !result->enable) {
1966                 if (result->pri_val > max->pri)
1967                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1968                                       level, result->pri_val, max->pri);
1969                 if (result->spr_val > max->spr)
1970                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1971                                       level, result->spr_val, max->spr);
1972                 if (result->cur_val > max->cur)
1973                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1974                                       level, result->cur_val, max->cur);
1975
1976                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1977                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1978                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1979                 result->enable = true;
1980         }
1981
1982         return ret;
1983 }
1984
1985 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1986                                  int level,
1987                                  const struct ilk_pipe_wm_parameters *p,
1988                                  struct intel_wm_level *result)
1989 {
1990         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1991         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1992         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1993
1994         /* WM1+ latency values stored in 0.5us units */
1995         if (level > 0) {
1996                 pri_latency *= 5;
1997                 spr_latency *= 5;
1998                 cur_latency *= 5;
1999         }
2000
2001         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2002         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2003         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2004         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2005         result->enable = true;
2006 }
2007
2008 static uint32_t
2009 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2010 {
2011         struct drm_i915_private *dev_priv = dev->dev_private;
2012         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2013         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2014         u32 linetime, ips_linetime;
2015
2016         if (!intel_crtc_active(crtc))
2017                 return 0;
2018
2019         /* The WM are computed with base on how long it takes to fill a single
2020          * row at the given clock rate, multiplied by 8.
2021          * */
2022         linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2023                                      mode->crtc_clock);
2024         ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2025                                          intel_ddi_get_cdclk_freq(dev_priv));
2026
2027         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2028                PIPE_WM_LINETIME_TIME(linetime);
2029 }
2030
2031 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2032 {
2033         struct drm_i915_private *dev_priv = dev->dev_private;
2034
2035         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2036                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2037
2038                 wm[0] = (sskpd >> 56) & 0xFF;
2039                 if (wm[0] == 0)
2040                         wm[0] = sskpd & 0xF;
2041                 wm[1] = (sskpd >> 4) & 0xFF;
2042                 wm[2] = (sskpd >> 12) & 0xFF;
2043                 wm[3] = (sskpd >> 20) & 0x1FF;
2044                 wm[4] = (sskpd >> 32) & 0x1FF;
2045         } else if (INTEL_INFO(dev)->gen >= 6) {
2046                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2047
2048                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2049                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2050                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2051                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2052         } else if (INTEL_INFO(dev)->gen >= 5) {
2053                 uint32_t mltr = I915_READ(MLTR_ILK);
2054
2055                 /* ILK primary LP0 latency is 700 ns */
2056                 wm[0] = 7;
2057                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2058                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2059         }
2060 }
2061
2062 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2063 {
2064         /* ILK sprite LP0 latency is 1300 ns */
2065         if (INTEL_INFO(dev)->gen == 5)
2066                 wm[0] = 13;
2067 }
2068
2069 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2070 {
2071         /* ILK cursor LP0 latency is 1300 ns */
2072         if (INTEL_INFO(dev)->gen == 5)
2073                 wm[0] = 13;
2074
2075         /* WaDoubleCursorLP3Latency:ivb */
2076         if (IS_IVYBRIDGE(dev))
2077                 wm[3] *= 2;
2078 }
2079
2080 static int ilk_wm_max_level(const struct drm_device *dev)
2081 {
2082         /* how many WM levels are we expecting */
2083         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2084                 return 4;
2085         else if (INTEL_INFO(dev)->gen >= 6)
2086                 return 3;
2087         else
2088                 return 2;
2089 }
2090
2091 static void intel_print_wm_latency(struct drm_device *dev,
2092                                    const char *name,
2093                                    const uint16_t wm[5])
2094 {
2095         int level, max_level = ilk_wm_max_level(dev);
2096
2097         for (level = 0; level <= max_level; level++) {
2098                 unsigned int latency = wm[level];
2099
2100                 if (latency == 0) {
2101                         DRM_ERROR("%s WM%d latency not provided\n",
2102                                   name, level);
2103                         continue;
2104                 }
2105
2106                 /* WM1+ latency values in 0.5us units */
2107                 if (level > 0)
2108                         latency *= 5;
2109
2110                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2111                               name, level, wm[level],
2112                               latency / 10, latency % 10);
2113         }
2114 }
2115
2116 static void ilk_setup_wm_latency(struct drm_device *dev)
2117 {
2118         struct drm_i915_private *dev_priv = dev->dev_private;
2119
2120         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2121
2122         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2123                sizeof(dev_priv->wm.pri_latency));
2124         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2125                sizeof(dev_priv->wm.pri_latency));
2126
2127         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2128         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2129
2130         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2131         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2132         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2133 }
2134
2135 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2136                                       struct ilk_pipe_wm_parameters *p)
2137 {
2138         struct drm_device *dev = crtc->dev;
2139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2140         enum pipe pipe = intel_crtc->pipe;
2141         struct drm_plane *plane;
2142
2143         if (!intel_crtc_active(crtc))
2144                 return;
2145
2146         p->active = true;
2147         p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2148         p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2149         p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2150         p->cur.bytes_per_pixel = 4;
2151         p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2152         p->cur.horiz_pixels = intel_crtc->cursor_width;
2153         /* TODO: for now, assume primary and cursor planes are always enabled. */
2154         p->pri.enabled = true;
2155         p->cur.enabled = true;
2156
2157         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2158                 struct intel_plane *intel_plane = to_intel_plane(plane);
2159
2160                 if (intel_plane->pipe == pipe) {
2161                         p->spr = intel_plane->wm;
2162                         break;
2163                 }
2164         }
2165 }
2166
2167 static void ilk_compute_wm_config(struct drm_device *dev,
2168                                   struct intel_wm_config *config)
2169 {
2170         struct intel_crtc *intel_crtc;
2171
2172         /* Compute the currently _active_ config */
2173         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2174                 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2175
2176                 if (!wm->pipe_enabled)
2177                         continue;
2178
2179                 config->sprites_enabled |= wm->sprites_enabled;
2180                 config->sprites_scaled |= wm->sprites_scaled;
2181                 config->num_pipes_active++;
2182         }
2183 }
2184
2185 /* Compute new watermarks for the pipe */
2186 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2187                                   const struct ilk_pipe_wm_parameters *params,
2188                                   struct intel_pipe_wm *pipe_wm)
2189 {
2190         struct drm_device *dev = crtc->dev;
2191         const struct drm_i915_private *dev_priv = dev->dev_private;
2192         int level, max_level = ilk_wm_max_level(dev);
2193         /* LP0 watermark maximums depend on this pipe alone */
2194         struct intel_wm_config config = {
2195                 .num_pipes_active = 1,
2196                 .sprites_enabled = params->spr.enabled,
2197                 .sprites_scaled = params->spr.scaled,
2198         };
2199         struct ilk_wm_maximums max;
2200
2201         pipe_wm->pipe_enabled = params->active;
2202         pipe_wm->sprites_enabled = params->spr.enabled;
2203         pipe_wm->sprites_scaled = params->spr.scaled;
2204
2205         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2206         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2207                 max_level = 1;
2208
2209         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2210         if (params->spr.scaled)
2211                 max_level = 0;
2212
2213         ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2214
2215         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2216                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2217
2218         /* LP0 watermarks always use 1/2 DDB partitioning */
2219         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2220
2221         /* At least LP0 must be valid */
2222         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2223                 return false;
2224
2225         ilk_compute_wm_reg_maximums(dev, 1, &max);
2226
2227         for (level = 1; level <= max_level; level++) {
2228                 struct intel_wm_level wm = {};
2229
2230                 ilk_compute_wm_level(dev_priv, level, params, &wm);
2231
2232                 /*
2233                  * Disable any watermark level that exceeds the
2234                  * register maximums since such watermarks are
2235                  * always invalid.
2236                  */
2237                 if (!ilk_validate_wm_level(level, &max, &wm))
2238                         break;
2239
2240                 pipe_wm->wm[level] = wm;
2241         }
2242
2243         return true;
2244 }
2245
2246 /*
2247  * Merge the watermarks from all active pipes for a specific level.
2248  */
2249 static void ilk_merge_wm_level(struct drm_device *dev,
2250                                int level,
2251                                struct intel_wm_level *ret_wm)
2252 {
2253         const struct intel_crtc *intel_crtc;
2254
2255         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2256                 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2257                 const struct intel_wm_level *wm = &active->wm[level];
2258
2259                 if (!active->pipe_enabled)
2260                         continue;
2261
2262                 if (!wm->enable)
2263                         return;
2264
2265                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2266                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2267                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2268                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2269         }
2270
2271         ret_wm->enable = true;
2272 }
2273
2274 /*
2275  * Merge all low power watermarks for all active pipes.
2276  */
2277 static void ilk_wm_merge(struct drm_device *dev,
2278                          const struct intel_wm_config *config,
2279                          const struct ilk_wm_maximums *max,
2280                          struct intel_pipe_wm *merged)
2281 {
2282         int level, max_level = ilk_wm_max_level(dev);
2283
2284         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2285         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2286             config->num_pipes_active > 1)
2287                 return;
2288
2289         /* ILK: FBC WM must be disabled always */
2290         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2291
2292         /* merge each WM1+ level */
2293         for (level = 1; level <= max_level; level++) {
2294                 struct intel_wm_level *wm = &merged->wm[level];
2295
2296                 ilk_merge_wm_level(dev, level, wm);
2297
2298                 if (!ilk_validate_wm_level(level, max, wm))
2299                         break;
2300
2301                 /*
2302                  * The spec says it is preferred to disable
2303                  * FBC WMs instead of disabling a WM level.
2304                  */
2305                 if (wm->fbc_val > max->fbc) {
2306                         merged->fbc_wm_enabled = false;
2307                         wm->fbc_val = 0;
2308                 }
2309         }
2310
2311         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2312         /*
2313          * FIXME this is racy. FBC might get enabled later.
2314          * What we should check here is whether FBC can be
2315          * enabled sometime later.
2316          */
2317         if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2318                 for (level = 2; level <= max_level; level++) {
2319                         struct intel_wm_level *wm = &merged->wm[level];
2320
2321                         wm->enable = false;
2322                 }
2323         }
2324 }
2325
2326 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2327 {
2328         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2329         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2330 }
2331
2332 /* The value we need to program into the WM_LPx latency field */
2333 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2334 {
2335         struct drm_i915_private *dev_priv = dev->dev_private;
2336
2337         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2338                 return 2 * level;
2339         else
2340                 return dev_priv->wm.pri_latency[level];
2341 }
2342
2343 static void ilk_compute_wm_results(struct drm_device *dev,
2344                                    const struct intel_pipe_wm *merged,
2345                                    enum intel_ddb_partitioning partitioning,
2346                                    struct ilk_wm_values *results)
2347 {
2348         struct intel_crtc *intel_crtc;
2349         int level, wm_lp;
2350
2351         results->enable_fbc_wm = merged->fbc_wm_enabled;
2352         results->partitioning = partitioning;
2353
2354         /* LP1+ register values */
2355         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2356                 const struct intel_wm_level *r;
2357
2358                 level = ilk_wm_lp_to_level(wm_lp, merged);
2359
2360                 r = &merged->wm[level];
2361                 if (!r->enable)
2362                         break;
2363
2364                 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2365                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2366                         (r->pri_val << WM1_LP_SR_SHIFT) |
2367                         r->cur_val;
2368
2369                 if (INTEL_INFO(dev)->gen >= 8)
2370                         results->wm_lp[wm_lp - 1] |=
2371                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2372                 else
2373                         results->wm_lp[wm_lp - 1] |=
2374                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2375
2376                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2377                         WARN_ON(wm_lp != 1);
2378                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2379                 } else
2380                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2381         }
2382
2383         /* LP0 register values */
2384         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2385                 enum pipe pipe = intel_crtc->pipe;
2386                 const struct intel_wm_level *r =
2387                         &intel_crtc->wm.active.wm[0];
2388
2389                 if (WARN_ON(!r->enable))
2390                         continue;
2391
2392                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2393
2394                 results->wm_pipe[pipe] =
2395                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2396                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2397                         r->cur_val;
2398         }
2399 }
2400
2401 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2402  * case both are at the same level. Prefer r1 in case they're the same. */
2403 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2404                                                   struct intel_pipe_wm *r1,
2405                                                   struct intel_pipe_wm *r2)
2406 {
2407         int level, max_level = ilk_wm_max_level(dev);
2408         int level1 = 0, level2 = 0;
2409
2410         for (level = 1; level <= max_level; level++) {
2411                 if (r1->wm[level].enable)
2412                         level1 = level;
2413                 if (r2->wm[level].enable)
2414                         level2 = level;
2415         }
2416
2417         if (level1 == level2) {
2418                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2419                         return r2;
2420                 else
2421                         return r1;
2422         } else if (level1 > level2) {
2423                 return r1;
2424         } else {
2425                 return r2;
2426         }
2427 }
2428
2429 /* dirty bits used to track which watermarks need changes */
2430 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2431 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2432 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2433 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2434 #define WM_DIRTY_FBC (1 << 24)
2435 #define WM_DIRTY_DDB (1 << 25)
2436
2437 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2438                                          const struct ilk_wm_values *old,
2439                                          const struct ilk_wm_values *new)
2440 {
2441         unsigned int dirty = 0;
2442         enum pipe pipe;
2443         int wm_lp;
2444
2445         for_each_pipe(pipe) {
2446                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2447                         dirty |= WM_DIRTY_LINETIME(pipe);
2448                         /* Must disable LP1+ watermarks too */
2449                         dirty |= WM_DIRTY_LP_ALL;
2450                 }
2451
2452                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2453                         dirty |= WM_DIRTY_PIPE(pipe);
2454                         /* Must disable LP1+ watermarks too */
2455                         dirty |= WM_DIRTY_LP_ALL;
2456                 }
2457         }
2458
2459         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2460                 dirty |= WM_DIRTY_FBC;
2461                 /* Must disable LP1+ watermarks too */
2462                 dirty |= WM_DIRTY_LP_ALL;
2463         }
2464
2465         if (old->partitioning != new->partitioning) {
2466                 dirty |= WM_DIRTY_DDB;
2467                 /* Must disable LP1+ watermarks too */
2468                 dirty |= WM_DIRTY_LP_ALL;
2469         }
2470
2471         /* LP1+ watermarks already deemed dirty, no need to continue */
2472         if (dirty & WM_DIRTY_LP_ALL)
2473                 return dirty;
2474
2475         /* Find the lowest numbered LP1+ watermark in need of an update... */
2476         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2477                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2478                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2479                         break;
2480         }
2481
2482         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2483         for (; wm_lp <= 3; wm_lp++)
2484                 dirty |= WM_DIRTY_LP(wm_lp);
2485
2486         return dirty;
2487 }
2488
2489 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2490                                unsigned int dirty)
2491 {
2492         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2493         bool changed = false;
2494
2495         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2496                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2497                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2498                 changed = true;
2499         }
2500         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2501                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2502                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2503                 changed = true;
2504         }
2505         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2506                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2507                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2508                 changed = true;
2509         }
2510
2511         /*
2512          * Don't touch WM1S_LP_EN here.
2513          * Doing so could cause underruns.
2514          */
2515
2516         return changed;
2517 }
2518
2519 /*
2520  * The spec says we shouldn't write when we don't need, because every write
2521  * causes WMs to be re-evaluated, expending some power.
2522  */
2523 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2524                                 struct ilk_wm_values *results)
2525 {
2526         struct drm_device *dev = dev_priv->dev;
2527         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2528         unsigned int dirty;
2529         uint32_t val;
2530
2531         dirty = ilk_compute_wm_dirty(dev, previous, results);
2532         if (!dirty)
2533                 return;
2534
2535         _ilk_disable_lp_wm(dev_priv, dirty);
2536
2537         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2538                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2539         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2540                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2541         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2542                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2543
2544         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2545                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2546         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2547                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2548         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2549                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2550
2551         if (dirty & WM_DIRTY_DDB) {
2552                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2553                         val = I915_READ(WM_MISC);
2554                         if (results->partitioning == INTEL_DDB_PART_1_2)
2555                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2556                         else
2557                                 val |= WM_MISC_DATA_PARTITION_5_6;
2558                         I915_WRITE(WM_MISC, val);
2559                 } else {
2560                         val = I915_READ(DISP_ARB_CTL2);
2561                         if (results->partitioning == INTEL_DDB_PART_1_2)
2562                                 val &= ~DISP_DATA_PARTITION_5_6;
2563                         else
2564                                 val |= DISP_DATA_PARTITION_5_6;
2565                         I915_WRITE(DISP_ARB_CTL2, val);
2566                 }
2567         }
2568
2569         if (dirty & WM_DIRTY_FBC) {
2570                 val = I915_READ(DISP_ARB_CTL);
2571                 if (results->enable_fbc_wm)
2572                         val &= ~DISP_FBC_WM_DIS;
2573                 else
2574                         val |= DISP_FBC_WM_DIS;
2575                 I915_WRITE(DISP_ARB_CTL, val);
2576         }
2577
2578         if (dirty & WM_DIRTY_LP(1) &&
2579             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2580                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2581
2582         if (INTEL_INFO(dev)->gen >= 7) {
2583                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2584                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2585                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2586                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2587         }
2588
2589         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2590                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2591         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2592                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2593         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2594                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2595
2596         dev_priv->wm.hw = *results;
2597 }
2598
2599 static bool ilk_disable_lp_wm(struct drm_device *dev)
2600 {
2601         struct drm_i915_private *dev_priv = dev->dev_private;
2602
2603         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2604 }
2605
2606 static void ilk_update_wm(struct drm_crtc *crtc)
2607 {
2608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2609         struct drm_device *dev = crtc->dev;
2610         struct drm_i915_private *dev_priv = dev->dev_private;
2611         struct ilk_wm_maximums max;
2612         struct ilk_pipe_wm_parameters params = {};
2613         struct ilk_wm_values results = {};
2614         enum intel_ddb_partitioning partitioning;
2615         struct intel_pipe_wm pipe_wm = {};
2616         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2617         struct intel_wm_config config = {};
2618
2619         ilk_compute_wm_parameters(crtc, &params);
2620
2621         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2622
2623         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2624                 return;
2625
2626         intel_crtc->wm.active = pipe_wm;
2627
2628         ilk_compute_wm_config(dev, &config);
2629
2630         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2631         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2632
2633         /* 5/6 split only in single pipe config on IVB+ */
2634         if (INTEL_INFO(dev)->gen >= 7 &&
2635             config.num_pipes_active == 1 && config.sprites_enabled) {
2636                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2637                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2638
2639                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2640         } else {
2641                 best_lp_wm = &lp_wm_1_2;
2642         }
2643
2644         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2645                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2646
2647         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2648
2649         ilk_write_wm_values(dev_priv, &results);
2650 }
2651
2652 static void ilk_update_sprite_wm(struct drm_plane *plane,
2653                                      struct drm_crtc *crtc,
2654                                      uint32_t sprite_width, int pixel_size,
2655                                      bool enabled, bool scaled)
2656 {
2657         struct drm_device *dev = plane->dev;
2658         struct intel_plane *intel_plane = to_intel_plane(plane);
2659
2660         intel_plane->wm.enabled = enabled;
2661         intel_plane->wm.scaled = scaled;
2662         intel_plane->wm.horiz_pixels = sprite_width;
2663         intel_plane->wm.bytes_per_pixel = pixel_size;
2664
2665         /*
2666          * IVB workaround: must disable low power watermarks for at least
2667          * one frame before enabling scaling.  LP watermarks can be re-enabled
2668          * when scaling is disabled.
2669          *
2670          * WaCxSRDisabledForSpriteScaling:ivb
2671          */
2672         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2673                 intel_wait_for_vblank(dev, intel_plane->pipe);
2674
2675         ilk_update_wm(crtc);
2676 }
2677
2678 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2679 {
2680         struct drm_device *dev = crtc->dev;
2681         struct drm_i915_private *dev_priv = dev->dev_private;
2682         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2683         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2684         struct intel_pipe_wm *active = &intel_crtc->wm.active;
2685         enum pipe pipe = intel_crtc->pipe;
2686         static const unsigned int wm0_pipe_reg[] = {
2687                 [PIPE_A] = WM0_PIPEA_ILK,
2688                 [PIPE_B] = WM0_PIPEB_ILK,
2689                 [PIPE_C] = WM0_PIPEC_IVB,
2690         };
2691
2692         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2693         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2694                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2695
2696         active->pipe_enabled = intel_crtc_active(crtc);
2697
2698         if (active->pipe_enabled) {
2699                 u32 tmp = hw->wm_pipe[pipe];
2700
2701                 /*
2702                  * For active pipes LP0 watermark is marked as
2703                  * enabled, and LP1+ watermaks as disabled since
2704                  * we can't really reverse compute them in case
2705                  * multiple pipes are active.
2706                  */
2707                 active->wm[0].enable = true;
2708                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2709                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2710                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2711                 active->linetime = hw->wm_linetime[pipe];
2712         } else {
2713                 int level, max_level = ilk_wm_max_level(dev);
2714
2715                 /*
2716                  * For inactive pipes, all watermark levels
2717                  * should be marked as enabled but zeroed,
2718                  * which is what we'd compute them to.
2719                  */
2720                 for (level = 0; level <= max_level; level++)
2721                         active->wm[level].enable = true;
2722         }
2723 }
2724
2725 void ilk_wm_get_hw_state(struct drm_device *dev)
2726 {
2727         struct drm_i915_private *dev_priv = dev->dev_private;
2728         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2729         struct drm_crtc *crtc;
2730
2731         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2732                 ilk_pipe_wm_get_hw_state(crtc);
2733
2734         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2735         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2736         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2737
2738         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2739         if (INTEL_INFO(dev)->gen >= 7) {
2740                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2741                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2742         }
2743
2744         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2745                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2746                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2747         else if (IS_IVYBRIDGE(dev))
2748                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2749                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2750
2751         hw->enable_fbc_wm =
2752                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2753 }
2754
2755 /**
2756  * intel_update_watermarks - update FIFO watermark values based on current modes
2757  *
2758  * Calculate watermark values for the various WM regs based on current mode
2759  * and plane configuration.
2760  *
2761  * There are several cases to deal with here:
2762  *   - normal (i.e. non-self-refresh)
2763  *   - self-refresh (SR) mode
2764  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2765  *   - lines are small relative to FIFO size (buffer can hold more than 2
2766  *     lines), so need to account for TLB latency
2767  *
2768  *   The normal calculation is:
2769  *     watermark = dotclock * bytes per pixel * latency
2770  *   where latency is platform & configuration dependent (we assume pessimal
2771  *   values here).
2772  *
2773  *   The SR calculation is:
2774  *     watermark = (trunc(latency/line time)+1) * surface width *
2775  *       bytes per pixel
2776  *   where
2777  *     line time = htotal / dotclock
2778  *     surface width = hdisplay for normal plane and 64 for cursor
2779  *   and latency is assumed to be high, as above.
2780  *
2781  * The final value programmed to the register should always be rounded up,
2782  * and include an extra 2 entries to account for clock crossings.
2783  *
2784  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2785  * to set the non-SR watermarks to 8.
2786  */
2787 void intel_update_watermarks(struct drm_crtc *crtc)
2788 {
2789         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2790
2791         if (dev_priv->display.update_wm)
2792                 dev_priv->display.update_wm(crtc);
2793 }
2794
2795 void intel_update_sprite_watermarks(struct drm_plane *plane,
2796                                     struct drm_crtc *crtc,
2797                                     uint32_t sprite_width, int pixel_size,
2798                                     bool enabled, bool scaled)
2799 {
2800         struct drm_i915_private *dev_priv = plane->dev->dev_private;
2801
2802         if (dev_priv->display.update_sprite_wm)
2803                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
2804                                                    pixel_size, enabled, scaled);
2805 }
2806
2807 static struct drm_i915_gem_object *
2808 intel_alloc_context_page(struct drm_device *dev)
2809 {
2810         struct drm_i915_gem_object *ctx;
2811         int ret;
2812
2813         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2814
2815         ctx = i915_gem_alloc_object(dev, 4096);
2816         if (!ctx) {
2817                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2818                 return NULL;
2819         }
2820
2821         ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2822         if (ret) {
2823                 DRM_ERROR("failed to pin power context: %d\n", ret);
2824                 goto err_unref;
2825         }
2826
2827         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2828         if (ret) {
2829                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2830                 goto err_unpin;
2831         }
2832
2833         return ctx;
2834
2835 err_unpin:
2836         i915_gem_object_ggtt_unpin(ctx);
2837 err_unref:
2838         drm_gem_object_unreference(&ctx->base);
2839         return NULL;
2840 }
2841
2842 /**
2843  * Lock protecting IPS related data structures
2844  */
2845 DEFINE_SPINLOCK(mchdev_lock);
2846
2847 /* Global for IPS driver to get at the current i915 device. Protected by
2848  * mchdev_lock. */
2849 static struct drm_i915_private *i915_mch_dev;
2850
2851 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2852 {
2853         struct drm_i915_private *dev_priv = dev->dev_private;
2854         u16 rgvswctl;
2855
2856         assert_spin_locked(&mchdev_lock);
2857
2858         rgvswctl = I915_READ16(MEMSWCTL);
2859         if (rgvswctl & MEMCTL_CMD_STS) {
2860                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2861                 return false; /* still busy with another command */
2862         }
2863
2864         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2865                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2866         I915_WRITE16(MEMSWCTL, rgvswctl);
2867         POSTING_READ16(MEMSWCTL);
2868
2869         rgvswctl |= MEMCTL_CMD_STS;
2870         I915_WRITE16(MEMSWCTL, rgvswctl);
2871
2872         return true;
2873 }
2874
2875 static void ironlake_enable_drps(struct drm_device *dev)
2876 {
2877         struct drm_i915_private *dev_priv = dev->dev_private;
2878         u32 rgvmodectl = I915_READ(MEMMODECTL);
2879         u8 fmax, fmin, fstart, vstart;
2880
2881         spin_lock_irq(&mchdev_lock);
2882
2883         /* Enable temp reporting */
2884         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2885         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2886
2887         /* 100ms RC evaluation intervals */
2888         I915_WRITE(RCUPEI, 100000);
2889         I915_WRITE(RCDNEI, 100000);
2890
2891         /* Set max/min thresholds to 90ms and 80ms respectively */
2892         I915_WRITE(RCBMAXAVG, 90000);
2893         I915_WRITE(RCBMINAVG, 80000);
2894
2895         I915_WRITE(MEMIHYST, 1);
2896
2897         /* Set up min, max, and cur for interrupt handling */
2898         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2899         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2900         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2901                 MEMMODE_FSTART_SHIFT;
2902
2903         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2904                 PXVFREQ_PX_SHIFT;
2905
2906         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2907         dev_priv->ips.fstart = fstart;
2908
2909         dev_priv->ips.max_delay = fstart;
2910         dev_priv->ips.min_delay = fmin;
2911         dev_priv->ips.cur_delay = fstart;
2912
2913         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2914                          fmax, fmin, fstart);
2915
2916         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2917
2918         /*
2919          * Interrupts will be enabled in ironlake_irq_postinstall
2920          */
2921
2922         I915_WRITE(VIDSTART, vstart);
2923         POSTING_READ(VIDSTART);
2924
2925         rgvmodectl |= MEMMODE_SWMODE_EN;
2926         I915_WRITE(MEMMODECTL, rgvmodectl);
2927
2928         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2929                 DRM_ERROR("stuck trying to change perf mode\n");
2930         mdelay(1);
2931
2932         ironlake_set_drps(dev, fstart);
2933
2934         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2935                 I915_READ(0x112e0);
2936         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2937         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2938         getrawmonotonic(&dev_priv->ips.last_time2);
2939
2940         spin_unlock_irq(&mchdev_lock);
2941 }
2942
2943 static void ironlake_disable_drps(struct drm_device *dev)
2944 {
2945         struct drm_i915_private *dev_priv = dev->dev_private;
2946         u16 rgvswctl;
2947
2948         spin_lock_irq(&mchdev_lock);
2949
2950         rgvswctl = I915_READ16(MEMSWCTL);
2951
2952         /* Ack interrupts, disable EFC interrupt */
2953         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2954         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2955         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2956         I915_WRITE(DEIIR, DE_PCU_EVENT);
2957         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2958
2959         /* Go back to the starting frequency */
2960         ironlake_set_drps(dev, dev_priv->ips.fstart);
2961         mdelay(1);
2962         rgvswctl |= MEMCTL_CMD_STS;
2963         I915_WRITE(MEMSWCTL, rgvswctl);
2964         mdelay(1);
2965
2966         spin_unlock_irq(&mchdev_lock);
2967 }
2968
2969 /* There's a funny hw issue where the hw returns all 0 when reading from
2970  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2971  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2972  * all limits and the gpu stuck at whatever frequency it is at atm).
2973  */
2974 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2975 {
2976         u32 limits;
2977
2978         /* Only set the down limit when we've reached the lowest level to avoid
2979          * getting more interrupts, otherwise leave this clear. This prevents a
2980          * race in the hw when coming out of rc6: There's a tiny window where
2981          * the hw runs at the minimal clock before selecting the desired
2982          * frequency, if the down threshold expires in that window we will not
2983          * receive a down interrupt. */
2984         limits = dev_priv->rps.max_freq_softlimit << 24;
2985         if (val <= dev_priv->rps.min_freq_softlimit)
2986                 limits |= dev_priv->rps.min_freq_softlimit << 16;
2987
2988         return limits;
2989 }
2990
2991 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
2992 {
2993         int new_power;
2994
2995         new_power = dev_priv->rps.power;
2996         switch (dev_priv->rps.power) {
2997         case LOW_POWER:
2998                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
2999                         new_power = BETWEEN;
3000                 break;
3001
3002         case BETWEEN:
3003                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3004                         new_power = LOW_POWER;
3005                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3006                         new_power = HIGH_POWER;
3007                 break;
3008
3009         case HIGH_POWER:
3010                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3011                         new_power = BETWEEN;
3012                 break;
3013         }
3014         /* Max/min bins are special */
3015         if (val == dev_priv->rps.min_freq_softlimit)
3016                 new_power = LOW_POWER;
3017         if (val == dev_priv->rps.max_freq_softlimit)
3018                 new_power = HIGH_POWER;
3019         if (new_power == dev_priv->rps.power)
3020                 return;
3021
3022         /* Note the units here are not exactly 1us, but 1280ns. */
3023         switch (new_power) {
3024         case LOW_POWER:
3025                 /* Upclock if more than 95% busy over 16ms */
3026                 I915_WRITE(GEN6_RP_UP_EI, 12500);
3027                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3028
3029                 /* Downclock if less than 85% busy over 32ms */
3030                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3031                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3032
3033                 I915_WRITE(GEN6_RP_CONTROL,
3034                            GEN6_RP_MEDIA_TURBO |
3035                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3036                            GEN6_RP_MEDIA_IS_GFX |
3037                            GEN6_RP_ENABLE |
3038                            GEN6_RP_UP_BUSY_AVG |
3039                            GEN6_RP_DOWN_IDLE_AVG);
3040                 break;
3041
3042         case BETWEEN:
3043                 /* Upclock if more than 90% busy over 13ms */
3044                 I915_WRITE(GEN6_RP_UP_EI, 10250);
3045                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3046
3047                 /* Downclock if less than 75% busy over 32ms */
3048                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3049                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3050
3051                 I915_WRITE(GEN6_RP_CONTROL,
3052                            GEN6_RP_MEDIA_TURBO |
3053                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3054                            GEN6_RP_MEDIA_IS_GFX |
3055                            GEN6_RP_ENABLE |
3056                            GEN6_RP_UP_BUSY_AVG |
3057                            GEN6_RP_DOWN_IDLE_AVG);
3058                 break;
3059
3060         case HIGH_POWER:
3061                 /* Upclock if more than 85% busy over 10ms */
3062                 I915_WRITE(GEN6_RP_UP_EI, 8000);
3063                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3064
3065                 /* Downclock if less than 60% busy over 32ms */
3066                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3067                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3068
3069                 I915_WRITE(GEN6_RP_CONTROL,
3070                            GEN6_RP_MEDIA_TURBO |
3071                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3072                            GEN6_RP_MEDIA_IS_GFX |
3073                            GEN6_RP_ENABLE |
3074                            GEN6_RP_UP_BUSY_AVG |
3075                            GEN6_RP_DOWN_IDLE_AVG);
3076                 break;
3077         }
3078
3079         dev_priv->rps.power = new_power;
3080         dev_priv->rps.last_adj = 0;
3081 }
3082
3083 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3084 {
3085         u32 mask = 0;
3086
3087         if (val > dev_priv->rps.min_freq_softlimit)
3088                 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3089         if (val < dev_priv->rps.max_freq_softlimit)
3090                 mask |= GEN6_PM_RP_UP_THRESHOLD;
3091
3092         /* IVB and SNB hard hangs on looping batchbuffer
3093          * if GEN6_PM_UP_EI_EXPIRED is masked.
3094          */
3095         if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3096                 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3097
3098         return ~mask;
3099 }
3100
3101 /* gen6_set_rps is called to update the frequency request, but should also be
3102  * called when the range (min_delay and max_delay) is modified so that we can
3103  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3104 void gen6_set_rps(struct drm_device *dev, u8 val)
3105 {
3106         struct drm_i915_private *dev_priv = dev->dev_private;
3107
3108         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3109         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3110         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3111
3112         /* min/max delay may still have been modified so be sure to
3113          * write the limits value.
3114          */
3115         if (val != dev_priv->rps.cur_freq) {
3116                 gen6_set_rps_thresholds(dev_priv, val);
3117
3118                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3119                         I915_WRITE(GEN6_RPNSWREQ,
3120                                    HSW_FREQUENCY(val));
3121                 else
3122                         I915_WRITE(GEN6_RPNSWREQ,
3123                                    GEN6_FREQUENCY(val) |
3124                                    GEN6_OFFSET(0) |
3125                                    GEN6_AGGRESSIVE_TURBO);
3126         }
3127
3128         /* Make sure we continue to get interrupts
3129          * until we hit the minimum or maximum frequencies.
3130          */
3131         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3132         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3133
3134         POSTING_READ(GEN6_RPNSWREQ);
3135
3136         dev_priv->rps.cur_freq = val;
3137         trace_intel_gpu_freq_change(val * 50);
3138 }
3139
3140 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3141  *
3142  * * If Gfx is Idle, then
3143  * 1. Mask Turbo interrupts
3144  * 2. Bring up Gfx clock
3145  * 3. Change the freq to Rpn and wait till P-Unit updates freq
3146  * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3147  * 5. Unmask Turbo interrupts
3148 */
3149 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3150 {
3151         /*
3152          * When we are idle.  Drop to min voltage state.
3153          */
3154
3155         if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3156                 return;
3157
3158         /* Mask turbo interrupt so that they will not come in between */
3159         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3160
3161         vlv_force_gfx_clock(dev_priv, true);
3162
3163         dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3164
3165         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3166                                         dev_priv->rps.min_freq_softlimit);
3167
3168         if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3169                                 & GENFREQSTATUS) == 0, 5))
3170                 DRM_ERROR("timed out waiting for Punit\n");
3171
3172         vlv_force_gfx_clock(dev_priv, false);
3173
3174         I915_WRITE(GEN6_PMINTRMSK,
3175                    gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3176 }
3177
3178 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3179 {
3180         struct drm_device *dev = dev_priv->dev;
3181
3182         mutex_lock(&dev_priv->rps.hw_lock);
3183         if (dev_priv->rps.enabled) {
3184                 if (IS_VALLEYVIEW(dev))
3185                         vlv_set_rps_idle(dev_priv);
3186                 else
3187                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3188                 dev_priv->rps.last_adj = 0;
3189         }
3190         mutex_unlock(&dev_priv->rps.hw_lock);
3191 }
3192
3193 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3194 {
3195         struct drm_device *dev = dev_priv->dev;
3196
3197         mutex_lock(&dev_priv->rps.hw_lock);
3198         if (dev_priv->rps.enabled) {
3199                 if (IS_VALLEYVIEW(dev))
3200                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3201                 else
3202                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3203                 dev_priv->rps.last_adj = 0;
3204         }
3205         mutex_unlock(&dev_priv->rps.hw_lock);
3206 }
3207
3208 void valleyview_set_rps(struct drm_device *dev, u8 val)
3209 {
3210         struct drm_i915_private *dev_priv = dev->dev_private;
3211
3212         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3213         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3214         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3215
3216         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3217                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3218                          dev_priv->rps.cur_freq,
3219                          vlv_gpu_freq(dev_priv, val), val);
3220
3221         if (val != dev_priv->rps.cur_freq)
3222                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3223
3224         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3225
3226         dev_priv->rps.cur_freq = val;
3227         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3228 }
3229
3230 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3231 {
3232         struct drm_i915_private *dev_priv = dev->dev_private;
3233
3234         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3235         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3236                                 ~dev_priv->pm_rps_events);
3237         /* Complete PM interrupt masking here doesn't race with the rps work
3238          * item again unmasking PM interrupts because that is using a different
3239          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3240          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3241
3242         spin_lock_irq(&dev_priv->irq_lock);
3243         dev_priv->rps.pm_iir = 0;
3244         spin_unlock_irq(&dev_priv->irq_lock);
3245
3246         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3247 }
3248
3249 static void gen6_disable_rps(struct drm_device *dev)
3250 {
3251         struct drm_i915_private *dev_priv = dev->dev_private;
3252
3253         I915_WRITE(GEN6_RC_CONTROL, 0);
3254         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3255
3256         gen6_disable_rps_interrupts(dev);
3257 }
3258
3259 static void valleyview_disable_rps(struct drm_device *dev)
3260 {
3261         struct drm_i915_private *dev_priv = dev->dev_private;
3262
3263         I915_WRITE(GEN6_RC_CONTROL, 0);
3264
3265         gen6_disable_rps_interrupts(dev);
3266 }
3267
3268 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3269 {
3270         if (IS_VALLEYVIEW(dev)) {
3271                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3272                         mode = GEN6_RC_CTL_RC6_ENABLE;
3273                 else
3274                         mode = 0;
3275         }
3276         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3277                  (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3278                  (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3279                  (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3280 }
3281
3282 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3283 {
3284         /* No RC6 before Ironlake */
3285         if (INTEL_INFO(dev)->gen < 5)
3286                 return 0;
3287
3288         /* RC6 is only on Ironlake mobile not on desktop */
3289         if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3290                 return 0;
3291
3292         /* Disable RC6 on Broadwell for now */
3293         if (IS_BROADWELL(dev))
3294                 return 0;
3295
3296         /* Respect the kernel parameter if it is set */
3297         if (enable_rc6 >= 0) {
3298                 int mask;
3299
3300                 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3301                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3302                                INTEL_RC6pp_ENABLE;
3303                 else
3304                         mask = INTEL_RC6_ENABLE;
3305
3306                 if ((enable_rc6 & mask) != enable_rc6)
3307                         DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3308                                  enable_rc6, enable_rc6 & mask, mask);
3309
3310                 return enable_rc6 & mask;
3311         }
3312
3313         /* Disable RC6 on Ironlake */
3314         if (INTEL_INFO(dev)->gen == 5)
3315                 return 0;
3316
3317         if (IS_IVYBRIDGE(dev))
3318                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3319
3320         return INTEL_RC6_ENABLE;
3321 }
3322
3323 int intel_enable_rc6(const struct drm_device *dev)
3324 {
3325         return i915.enable_rc6;
3326 }
3327
3328 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3329 {
3330         struct drm_i915_private *dev_priv = dev->dev_private;
3331
3332         spin_lock_irq(&dev_priv->irq_lock);
3333         WARN_ON(dev_priv->rps.pm_iir);
3334         snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3335         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3336         spin_unlock_irq(&dev_priv->irq_lock);
3337 }
3338
3339 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3340 {
3341         /* All of these values are in units of 50MHz */
3342         dev_priv->rps.cur_freq          = 0;
3343         /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3344         dev_priv->rps.rp1_freq          = (rp_state_cap >>  8) & 0xff;
3345         dev_priv->rps.rp0_freq          = (rp_state_cap >>  0) & 0xff;
3346         dev_priv->rps.min_freq          = (rp_state_cap >> 16) & 0xff;
3347         /* XXX: only BYT has a special efficient freq */
3348         dev_priv->rps.efficient_freq    = dev_priv->rps.rp1_freq;
3349         /* hw_max = RP0 until we check for overclocking */
3350         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
3351
3352         /* Preserve min/max settings in case of re-init */
3353         if (dev_priv->rps.max_freq_softlimit == 0)
3354                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3355
3356         if (dev_priv->rps.min_freq_softlimit == 0)
3357                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3358 }
3359
3360 static void gen8_enable_rps(struct drm_device *dev)
3361 {
3362         struct drm_i915_private *dev_priv = dev->dev_private;
3363         struct intel_ring_buffer *ring;
3364         uint32_t rc6_mask = 0, rp_state_cap;
3365         int unused;
3366
3367         /* 1a: Software RC state - RC0 */
3368         I915_WRITE(GEN6_RC_STATE, 0);
3369
3370         /* 1c & 1d: Get forcewake during program sequence. Although the driver
3371          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3372         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3373
3374         /* 2a: Disable RC states. */
3375         I915_WRITE(GEN6_RC_CONTROL, 0);
3376
3377         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3378         parse_rp_state_cap(dev_priv, rp_state_cap);
3379
3380         /* 2b: Program RC6 thresholds.*/
3381         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3382         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3383         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3384         for_each_ring(ring, dev_priv, unused)
3385                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3386         I915_WRITE(GEN6_RC_SLEEP, 0);
3387         I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3388
3389         /* 3: Enable RC6 */
3390         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3391                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3392         intel_print_rc6_info(dev, rc6_mask);
3393         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3394                                     GEN6_RC_CTL_EI_MODE(1) |
3395                                     rc6_mask);
3396
3397         /* 4 Program defaults and thresholds for RPS*/
3398         I915_WRITE(GEN6_RPNSWREQ,
3399                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3400         I915_WRITE(GEN6_RC_VIDEO_FREQ,
3401                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3402         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3403         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3404
3405         /* Docs recommend 900MHz, and 300 MHz respectively */
3406         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3407                    dev_priv->rps.max_freq_softlimit << 24 |
3408                    dev_priv->rps.min_freq_softlimit << 16);
3409
3410         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3411         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3412         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3413         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3414
3415         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3416
3417         /* 5: Enable RPS */
3418         I915_WRITE(GEN6_RP_CONTROL,
3419                    GEN6_RP_MEDIA_TURBO |
3420                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3421                    GEN6_RP_MEDIA_IS_GFX |
3422                    GEN6_RP_ENABLE |
3423                    GEN6_RP_UP_BUSY_AVG |
3424                    GEN6_RP_DOWN_IDLE_AVG);
3425
3426         /* 6: Ring frequency + overclocking (our driver does this later */
3427
3428         gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3429
3430         gen6_enable_rps_interrupts(dev);
3431
3432         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3433 }
3434
3435 static void gen6_enable_rps(struct drm_device *dev)
3436 {
3437         struct drm_i915_private *dev_priv = dev->dev_private;
3438         struct intel_ring_buffer *ring;
3439         u32 rp_state_cap;
3440         u32 gt_perf_status;
3441         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3442         u32 gtfifodbg;
3443         int rc6_mode;
3444         int i, ret;
3445
3446         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3447
3448         /* Here begins a magic sequence of register writes to enable
3449          * auto-downclocking.
3450          *
3451          * Perhaps there might be some value in exposing these to
3452          * userspace...
3453          */
3454         I915_WRITE(GEN6_RC_STATE, 0);
3455
3456         /* Clear the DBG now so we don't confuse earlier errors */
3457         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3458                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3459                 I915_WRITE(GTFIFODBG, gtfifodbg);
3460         }
3461
3462         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3463
3464         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3465         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3466
3467         parse_rp_state_cap(dev_priv, rp_state_cap);
3468
3469         /* disable the counters and set deterministic thresholds */
3470         I915_WRITE(GEN6_RC_CONTROL, 0);
3471
3472         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3473         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3474         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3475         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3476         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3477
3478         for_each_ring(ring, dev_priv, i)
3479                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3480
3481         I915_WRITE(GEN6_RC_SLEEP, 0);
3482         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3483         if (IS_IVYBRIDGE(dev))
3484                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3485         else
3486                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3487         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3488         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3489
3490         /* Check if we are enabling RC6 */
3491         rc6_mode = intel_enable_rc6(dev_priv->dev);
3492         if (rc6_mode & INTEL_RC6_ENABLE)
3493                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3494
3495         /* We don't use those on Haswell */
3496         if (!IS_HASWELL(dev)) {
3497                 if (rc6_mode & INTEL_RC6p_ENABLE)
3498                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3499
3500                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3501                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3502         }
3503
3504         intel_print_rc6_info(dev, rc6_mask);
3505
3506         I915_WRITE(GEN6_RC_CONTROL,
3507                    rc6_mask |
3508                    GEN6_RC_CTL_EI_MODE(1) |
3509                    GEN6_RC_CTL_HW_ENABLE);
3510
3511         /* Power down if completely idle for over 50ms */
3512         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3513         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3514
3515         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3516         if (ret)
3517                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3518
3519         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3520         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3521                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3522                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3523                                  (pcu_mbox & 0xff) * 50);
3524                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3525         }
3526
3527         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3528         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3529
3530         gen6_enable_rps_interrupts(dev);
3531
3532         rc6vids = 0;
3533         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3534         if (IS_GEN6(dev) && ret) {
3535                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3536         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3537                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3538                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3539                 rc6vids &= 0xffff00;
3540                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3541                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3542                 if (ret)
3543                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3544         }
3545
3546         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3547 }
3548
3549 static void __gen6_update_ring_freq(struct drm_device *dev)
3550 {
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552         int min_freq = 15;
3553         unsigned int gpu_freq;
3554         unsigned int max_ia_freq, min_ring_freq;
3555         int scaling_factor = 180;
3556         struct cpufreq_policy *policy;
3557
3558         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3559
3560         policy = cpufreq_cpu_get(0);
3561         if (policy) {
3562                 max_ia_freq = policy->cpuinfo.max_freq;
3563                 cpufreq_cpu_put(policy);
3564         } else {
3565                 /*
3566                  * Default to measured freq if none found, PCU will ensure we
3567                  * don't go over
3568                  */
3569                 max_ia_freq = tsc_khz;
3570         }
3571
3572         /* Convert from kHz to MHz */
3573         max_ia_freq /= 1000;
3574
3575         min_ring_freq = I915_READ(DCLK) & 0xf;
3576         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3577         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3578
3579         /*
3580          * For each potential GPU frequency, load a ring frequency we'd like
3581          * to use for memory access.  We do this by specifying the IA frequency
3582          * the PCU should use as a reference to determine the ring frequency.
3583          */
3584         for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3585              gpu_freq--) {
3586                 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3587                 unsigned int ia_freq = 0, ring_freq = 0;
3588
3589                 if (INTEL_INFO(dev)->gen >= 8) {
3590                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
3591                         ring_freq = max(min_ring_freq, gpu_freq);
3592                 } else if (IS_HASWELL(dev)) {
3593                         ring_freq = mult_frac(gpu_freq, 5, 4);
3594                         ring_freq = max(min_ring_freq, ring_freq);
3595                         /* leave ia_freq as the default, chosen by cpufreq */
3596                 } else {
3597                         /* On older processors, there is no separate ring
3598                          * clock domain, so in order to boost the bandwidth
3599                          * of the ring, we need to upclock the CPU (ia_freq).
3600                          *
3601                          * For GPU frequencies less than 750MHz,
3602                          * just use the lowest ring freq.
3603                          */
3604                         if (gpu_freq < min_freq)
3605                                 ia_freq = 800;
3606                         else
3607                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3608                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3609                 }
3610
3611                 sandybridge_pcode_write(dev_priv,
3612                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3613                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3614                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3615                                         gpu_freq);
3616         }
3617 }
3618
3619 void gen6_update_ring_freq(struct drm_device *dev)
3620 {
3621         struct drm_i915_private *dev_priv = dev->dev_private;
3622
3623         if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3624                 return;
3625
3626         mutex_lock(&dev_priv->rps.hw_lock);
3627         __gen6_update_ring_freq(dev);
3628         mutex_unlock(&dev_priv->rps.hw_lock);
3629 }
3630
3631 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3632 {
3633         u32 val, rp0;
3634
3635         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3636
3637         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3638         /* Clamp to max */
3639         rp0 = min_t(u32, rp0, 0xea);
3640
3641         return rp0;
3642 }
3643
3644 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3645 {
3646         u32 val, rpe;
3647
3648         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3649         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3650         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3651         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3652
3653         return rpe;
3654 }
3655
3656 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3657 {
3658         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3659 }
3660
3661 /* Check that the pctx buffer wasn't move under us. */
3662 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3663 {
3664         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3665
3666         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3667                              dev_priv->vlv_pctx->stolen->start);
3668 }
3669
3670 static void valleyview_setup_pctx(struct drm_device *dev)
3671 {
3672         struct drm_i915_private *dev_priv = dev->dev_private;
3673         struct drm_i915_gem_object *pctx;
3674         unsigned long pctx_paddr;
3675         u32 pcbr;
3676         int pctx_size = 24*1024;
3677
3678         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3679
3680         pcbr = I915_READ(VLV_PCBR);
3681         if (pcbr) {
3682                 /* BIOS set it up already, grab the pre-alloc'd space */
3683                 int pcbr_offset;
3684
3685                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3686                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3687                                                                       pcbr_offset,
3688                                                                       I915_GTT_OFFSET_NONE,
3689                                                                       pctx_size);
3690                 goto out;
3691         }
3692
3693         /*
3694          * From the Gunit register HAS:
3695          * The Gfx driver is expected to program this register and ensure
3696          * proper allocation within Gfx stolen memory.  For example, this
3697          * register should be programmed such than the PCBR range does not
3698          * overlap with other ranges, such as the frame buffer, protected
3699          * memory, or any other relevant ranges.
3700          */
3701         pctx = i915_gem_object_create_stolen(dev, pctx_size);
3702         if (!pctx) {
3703                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3704                 return;
3705         }
3706
3707         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3708         I915_WRITE(VLV_PCBR, pctx_paddr);
3709
3710 out:
3711         dev_priv->vlv_pctx = pctx;
3712 }
3713
3714 static void valleyview_cleanup_pctx(struct drm_device *dev)
3715 {
3716         struct drm_i915_private *dev_priv = dev->dev_private;
3717
3718         if (WARN_ON(!dev_priv->vlv_pctx))
3719                 return;
3720
3721         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3722         dev_priv->vlv_pctx = NULL;
3723 }
3724
3725 static void valleyview_init_gt_powersave(struct drm_device *dev)
3726 {
3727         struct drm_i915_private *dev_priv = dev->dev_private;
3728
3729         valleyview_setup_pctx(dev);
3730
3731         mutex_lock(&dev_priv->rps.hw_lock);
3732
3733         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3734         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3735         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3736                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3737                          dev_priv->rps.max_freq);
3738
3739         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3740         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3741                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3742                          dev_priv->rps.efficient_freq);
3743
3744         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3745         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3746                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3747                          dev_priv->rps.min_freq);
3748
3749         /* Preserve min/max settings in case of re-init */
3750         if (dev_priv->rps.max_freq_softlimit == 0)
3751                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3752
3753         if (dev_priv->rps.min_freq_softlimit == 0)
3754                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3755
3756         mutex_unlock(&dev_priv->rps.hw_lock);
3757 }
3758
3759 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
3760 {
3761         valleyview_cleanup_pctx(dev);
3762 }
3763
3764 static void valleyview_enable_rps(struct drm_device *dev)
3765 {
3766         struct drm_i915_private *dev_priv = dev->dev_private;
3767         struct intel_ring_buffer *ring;
3768         u32 gtfifodbg, val, rc6_mode = 0;
3769         int i;
3770
3771         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3772
3773         valleyview_check_pctx(dev_priv);
3774
3775         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3776                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3777                                  gtfifodbg);
3778                 I915_WRITE(GTFIFODBG, gtfifodbg);
3779         }
3780
3781         /* If VLV, Forcewake all wells, else re-direct to regular path */
3782         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3783
3784         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3785         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3786         I915_WRITE(GEN6_RP_UP_EI, 66000);
3787         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3788
3789         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3790
3791         I915_WRITE(GEN6_RP_CONTROL,
3792                    GEN6_RP_MEDIA_TURBO |
3793                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3794                    GEN6_RP_MEDIA_IS_GFX |
3795                    GEN6_RP_ENABLE |
3796                    GEN6_RP_UP_BUSY_AVG |
3797                    GEN6_RP_DOWN_IDLE_CONT);
3798
3799         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3800         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3801         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3802
3803         for_each_ring(ring, dev_priv, i)
3804                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3805
3806         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
3807
3808         /* allows RC6 residency counter to work */
3809         I915_WRITE(VLV_COUNTER_CONTROL,
3810                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3811                                       VLV_MEDIA_RC6_COUNT_EN |
3812                                       VLV_RENDER_RC6_COUNT_EN));
3813         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3814                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
3815
3816         intel_print_rc6_info(dev, rc6_mode);
3817
3818         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3819
3820         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3821
3822         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3823         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3824
3825         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
3826         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3827                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3828                          dev_priv->rps.cur_freq);
3829
3830         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3831                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3832                          dev_priv->rps.efficient_freq);
3833
3834         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
3835
3836         gen6_enable_rps_interrupts(dev);
3837
3838         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3839 }
3840
3841 void ironlake_teardown_rc6(struct drm_device *dev)
3842 {
3843         struct drm_i915_private *dev_priv = dev->dev_private;
3844
3845         if (dev_priv->ips.renderctx) {
3846                 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3847                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3848                 dev_priv->ips.renderctx = NULL;
3849         }
3850
3851         if (dev_priv->ips.pwrctx) {
3852                 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3853                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3854                 dev_priv->ips.pwrctx = NULL;
3855         }
3856 }
3857
3858 static void ironlake_disable_rc6(struct drm_device *dev)
3859 {
3860         struct drm_i915_private *dev_priv = dev->dev_private;
3861
3862         if (I915_READ(PWRCTXA)) {
3863                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3864                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3865                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3866                          50);
3867
3868                 I915_WRITE(PWRCTXA, 0);
3869                 POSTING_READ(PWRCTXA);
3870
3871                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3872                 POSTING_READ(RSTDBYCTL);
3873         }
3874 }
3875
3876 static int ironlake_setup_rc6(struct drm_device *dev)
3877 {
3878         struct drm_i915_private *dev_priv = dev->dev_private;
3879
3880         if (dev_priv->ips.renderctx == NULL)
3881                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3882         if (!dev_priv->ips.renderctx)
3883                 return -ENOMEM;
3884
3885         if (dev_priv->ips.pwrctx == NULL)
3886                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3887         if (!dev_priv->ips.pwrctx) {
3888                 ironlake_teardown_rc6(dev);
3889                 return -ENOMEM;
3890         }
3891
3892         return 0;
3893 }
3894
3895 static void ironlake_enable_rc6(struct drm_device *dev)
3896 {
3897         struct drm_i915_private *dev_priv = dev->dev_private;
3898         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3899         bool was_interruptible;
3900         int ret;
3901
3902         /* rc6 disabled by default due to repeated reports of hanging during
3903          * boot and resume.
3904          */
3905         if (!intel_enable_rc6(dev))
3906                 return;
3907
3908         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3909
3910         ret = ironlake_setup_rc6(dev);
3911         if (ret)
3912                 return;
3913
3914         was_interruptible = dev_priv->mm.interruptible;
3915         dev_priv->mm.interruptible = false;
3916
3917         /*
3918          * GPU can automatically power down the render unit if given a page
3919          * to save state.
3920          */
3921         ret = intel_ring_begin(ring, 6);
3922         if (ret) {
3923                 ironlake_teardown_rc6(dev);
3924                 dev_priv->mm.interruptible = was_interruptible;
3925                 return;
3926         }
3927
3928         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3929         intel_ring_emit(ring, MI_SET_CONTEXT);
3930         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
3931                         MI_MM_SPACE_GTT |
3932                         MI_SAVE_EXT_STATE_EN |
3933                         MI_RESTORE_EXT_STATE_EN |
3934                         MI_RESTORE_INHIBIT);
3935         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3936         intel_ring_emit(ring, MI_NOOP);
3937         intel_ring_emit(ring, MI_FLUSH);
3938         intel_ring_advance(ring);
3939
3940         /*
3941          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3942          * does an implicit flush, combined with MI_FLUSH above, it should be
3943          * safe to assume that renderctx is valid
3944          */
3945         ret = intel_ring_idle(ring);
3946         dev_priv->mm.interruptible = was_interruptible;
3947         if (ret) {
3948                 DRM_ERROR("failed to enable ironlake power savings\n");
3949                 ironlake_teardown_rc6(dev);
3950                 return;
3951         }
3952
3953         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
3954         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3955
3956         intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
3957 }
3958
3959 static unsigned long intel_pxfreq(u32 vidfreq)
3960 {
3961         unsigned long freq;
3962         int div = (vidfreq & 0x3f0000) >> 16;
3963         int post = (vidfreq & 0x3000) >> 12;
3964         int pre = (vidfreq & 0x7);
3965
3966         if (!pre)
3967                 return 0;
3968
3969         freq = ((div * 133333) / ((1<<post) * pre));
3970
3971         return freq;
3972 }
3973
3974 static const struct cparams {
3975         u16 i;
3976         u16 t;
3977         u16 m;
3978         u16 c;
3979 } cparams[] = {
3980         { 1, 1333, 301, 28664 },
3981         { 1, 1066, 294, 24460 },
3982         { 1, 800, 294, 25192 },
3983         { 0, 1333, 276, 27605 },
3984         { 0, 1066, 276, 27605 },
3985         { 0, 800, 231, 23784 },
3986 };
3987
3988 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3989 {
3990         u64 total_count, diff, ret;
3991         u32 count1, count2, count3, m = 0, c = 0;
3992         unsigned long now = jiffies_to_msecs(jiffies), diff1;
3993         int i;
3994
3995         assert_spin_locked(&mchdev_lock);
3996
3997         diff1 = now - dev_priv->ips.last_time1;
3998
3999         /* Prevent division-by-zero if we are asking too fast.
4000          * Also, we don't get interesting results if we are polling
4001          * faster than once in 10ms, so just return the saved value
4002          * in such cases.
4003          */
4004         if (diff1 <= 10)
4005                 return dev_priv->ips.chipset_power;
4006
4007         count1 = I915_READ(DMIEC);
4008         count2 = I915_READ(DDREC);
4009         count3 = I915_READ(CSIEC);
4010
4011         total_count = count1 + count2 + count3;
4012
4013         /* FIXME: handle per-counter overflow */
4014         if (total_count < dev_priv->ips.last_count1) {
4015                 diff = ~0UL - dev_priv->ips.last_count1;
4016                 diff += total_count;
4017         } else {
4018                 diff = total_count - dev_priv->ips.last_count1;
4019         }
4020
4021         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4022                 if (cparams[i].i == dev_priv->ips.c_m &&
4023                     cparams[i].t == dev_priv->ips.r_t) {
4024                         m = cparams[i].m;
4025                         c = cparams[i].c;
4026                         break;
4027                 }
4028         }
4029
4030         diff = div_u64(diff, diff1);
4031         ret = ((m * diff) + c);
4032         ret = div_u64(ret, 10);
4033
4034         dev_priv->ips.last_count1 = total_count;
4035         dev_priv->ips.last_time1 = now;
4036
4037         dev_priv->ips.chipset_power = ret;
4038
4039         return ret;
4040 }
4041
4042 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4043 {
4044         struct drm_device *dev = dev_priv->dev;
4045         unsigned long val;
4046
4047         if (INTEL_INFO(dev)->gen != 5)
4048                 return 0;
4049
4050         spin_lock_irq(&mchdev_lock);
4051
4052         val = __i915_chipset_val(dev_priv);
4053
4054         spin_unlock_irq(&mchdev_lock);
4055
4056         return val;
4057 }
4058
4059 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4060 {
4061         unsigned long m, x, b;
4062         u32 tsfs;
4063
4064         tsfs = I915_READ(TSFS);
4065
4066         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4067         x = I915_READ8(TR1);
4068
4069         b = tsfs & TSFS_INTR_MASK;
4070
4071         return ((m * x) / 127) - b;
4072 }
4073
4074 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4075 {
4076         struct drm_device *dev = dev_priv->dev;
4077         static const struct v_table {
4078                 u16 vd; /* in .1 mil */
4079                 u16 vm; /* in .1 mil */
4080         } v_table[] = {
4081                 { 0, 0, },
4082                 { 375, 0, },
4083                 { 500, 0, },
4084                 { 625, 0, },
4085                 { 750, 0, },
4086                 { 875, 0, },
4087                 { 1000, 0, },
4088                 { 1125, 0, },
4089                 { 4125, 3000, },
4090                 { 4125, 3000, },
4091                 { 4125, 3000, },
4092                 { 4125, 3000, },
4093                 { 4125, 3000, },
4094                 { 4125, 3000, },
4095                 { 4125, 3000, },
4096                 { 4125, 3000, },
4097                 { 4125, 3000, },
4098                 { 4125, 3000, },
4099                 { 4125, 3000, },
4100                 { 4125, 3000, },
4101                 { 4125, 3000, },
4102                 { 4125, 3000, },
4103                 { 4125, 3000, },
4104                 { 4125, 3000, },
4105                 { 4125, 3000, },
4106                 { 4125, 3000, },
4107                 { 4125, 3000, },
4108                 { 4125, 3000, },
4109                 { 4125, 3000, },
4110                 { 4125, 3000, },
4111                 { 4125, 3000, },
4112                 { 4125, 3000, },
4113                 { 4250, 3125, },
4114                 { 4375, 3250, },
4115                 { 4500, 3375, },
4116                 { 4625, 3500, },
4117                 { 4750, 3625, },
4118                 { 4875, 3750, },
4119                 { 5000, 3875, },
4120                 { 5125, 4000, },
4121                 { 5250, 4125, },
4122                 { 5375, 4250, },
4123                 { 5500, 4375, },
4124                 { 5625, 4500, },
4125                 { 5750, 4625, },
4126                 { 5875, 4750, },
4127                 { 6000, 4875, },
4128                 { 6125, 5000, },
4129                 { 6250, 5125, },
4130                 { 6375, 5250, },
4131                 { 6500, 5375, },
4132                 { 6625, 5500, },
4133                 { 6750, 5625, },
4134                 { 6875, 5750, },
4135                 { 7000, 5875, },
4136                 { 7125, 6000, },
4137                 { 7250, 6125, },
4138                 { 7375, 6250, },
4139                 { 7500, 6375, },
4140                 { 7625, 6500, },
4141                 { 7750, 6625, },
4142                 { 7875, 6750, },
4143                 { 8000, 6875, },
4144                 { 8125, 7000, },
4145                 { 8250, 7125, },
4146                 { 8375, 7250, },
4147                 { 8500, 7375, },
4148                 { 8625, 7500, },
4149                 { 8750, 7625, },
4150                 { 8875, 7750, },
4151                 { 9000, 7875, },
4152                 { 9125, 8000, },
4153                 { 9250, 8125, },
4154                 { 9375, 8250, },
4155                 { 9500, 8375, },
4156                 { 9625, 8500, },
4157                 { 9750, 8625, },
4158                 { 9875, 8750, },
4159                 { 10000, 8875, },
4160                 { 10125, 9000, },
4161                 { 10250, 9125, },
4162                 { 10375, 9250, },
4163                 { 10500, 9375, },
4164                 { 10625, 9500, },
4165                 { 10750, 9625, },
4166                 { 10875, 9750, },
4167                 { 11000, 9875, },
4168                 { 11125, 10000, },
4169                 { 11250, 10125, },
4170                 { 11375, 10250, },
4171                 { 11500, 10375, },
4172                 { 11625, 10500, },
4173                 { 11750, 10625, },
4174                 { 11875, 10750, },
4175                 { 12000, 10875, },
4176                 { 12125, 11000, },
4177                 { 12250, 11125, },
4178                 { 12375, 11250, },
4179                 { 12500, 11375, },
4180                 { 12625, 11500, },
4181                 { 12750, 11625, },
4182                 { 12875, 11750, },
4183                 { 13000, 11875, },
4184                 { 13125, 12000, },
4185                 { 13250, 12125, },
4186                 { 13375, 12250, },
4187                 { 13500, 12375, },
4188                 { 13625, 12500, },
4189                 { 13750, 12625, },
4190                 { 13875, 12750, },
4191                 { 14000, 12875, },
4192                 { 14125, 13000, },
4193                 { 14250, 13125, },
4194                 { 14375, 13250, },
4195                 { 14500, 13375, },
4196                 { 14625, 13500, },
4197                 { 14750, 13625, },
4198                 { 14875, 13750, },
4199                 { 15000, 13875, },
4200                 { 15125, 14000, },
4201                 { 15250, 14125, },
4202                 { 15375, 14250, },
4203                 { 15500, 14375, },
4204                 { 15625, 14500, },
4205                 { 15750, 14625, },
4206                 { 15875, 14750, },
4207                 { 16000, 14875, },
4208                 { 16125, 15000, },
4209         };
4210         if (INTEL_INFO(dev)->is_mobile)
4211                 return v_table[pxvid].vm;
4212         else
4213                 return v_table[pxvid].vd;
4214 }
4215
4216 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4217 {
4218         struct timespec now, diff1;
4219         u64 diff;
4220         unsigned long diffms;
4221         u32 count;
4222
4223         assert_spin_locked(&mchdev_lock);
4224
4225         getrawmonotonic(&now);
4226         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4227
4228         /* Don't divide by 0 */
4229         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4230         if (!diffms)
4231                 return;
4232
4233         count = I915_READ(GFXEC);
4234
4235         if (count < dev_priv->ips.last_count2) {
4236                 diff = ~0UL - dev_priv->ips.last_count2;
4237                 diff += count;
4238         } else {
4239                 diff = count - dev_priv->ips.last_count2;
4240         }
4241
4242         dev_priv->ips.last_count2 = count;
4243         dev_priv->ips.last_time2 = now;
4244
4245         /* More magic constants... */
4246         diff = diff * 1181;
4247         diff = div_u64(diff, diffms * 10);
4248         dev_priv->ips.gfx_power = diff;
4249 }
4250
4251 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4252 {
4253         struct drm_device *dev = dev_priv->dev;
4254
4255         if (INTEL_INFO(dev)->gen != 5)
4256                 return;
4257
4258         spin_lock_irq(&mchdev_lock);
4259
4260         __i915_update_gfx_val(dev_priv);
4261
4262         spin_unlock_irq(&mchdev_lock);
4263 }
4264
4265 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4266 {
4267         unsigned long t, corr, state1, corr2, state2;
4268         u32 pxvid, ext_v;
4269
4270         assert_spin_locked(&mchdev_lock);
4271
4272         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4273         pxvid = (pxvid >> 24) & 0x7f;
4274         ext_v = pvid_to_extvid(dev_priv, pxvid);
4275
4276         state1 = ext_v;
4277
4278         t = i915_mch_val(dev_priv);
4279
4280         /* Revel in the empirically derived constants */
4281
4282         /* Correction factor in 1/100000 units */
4283         if (t > 80)
4284                 corr = ((t * 2349) + 135940);
4285         else if (t >= 50)
4286                 corr = ((t * 964) + 29317);
4287         else /* < 50 */
4288                 corr = ((t * 301) + 1004);
4289
4290         corr = corr * ((150142 * state1) / 10000 - 78642);
4291         corr /= 100000;
4292         corr2 = (corr * dev_priv->ips.corr);
4293
4294         state2 = (corr2 * state1) / 10000;
4295         state2 /= 100; /* convert to mW */
4296
4297         __i915_update_gfx_val(dev_priv);
4298
4299         return dev_priv->ips.gfx_power + state2;
4300 }
4301
4302 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4303 {
4304         struct drm_device *dev = dev_priv->dev;
4305         unsigned long val;
4306
4307         if (INTEL_INFO(dev)->gen != 5)
4308                 return 0;
4309
4310         spin_lock_irq(&mchdev_lock);
4311
4312         val = __i915_gfx_val(dev_priv);
4313
4314         spin_unlock_irq(&mchdev_lock);
4315
4316         return val;
4317 }
4318
4319 /**
4320  * i915_read_mch_val - return value for IPS use
4321  *
4322  * Calculate and return a value for the IPS driver to use when deciding whether
4323  * we have thermal and power headroom to increase CPU or GPU power budget.
4324  */
4325 unsigned long i915_read_mch_val(void)
4326 {
4327         struct drm_i915_private *dev_priv;
4328         unsigned long chipset_val, graphics_val, ret = 0;
4329
4330         spin_lock_irq(&mchdev_lock);
4331         if (!i915_mch_dev)
4332                 goto out_unlock;
4333         dev_priv = i915_mch_dev;
4334
4335         chipset_val = __i915_chipset_val(dev_priv);
4336         graphics_val = __i915_gfx_val(dev_priv);
4337
4338         ret = chipset_val + graphics_val;
4339
4340 out_unlock:
4341         spin_unlock_irq(&mchdev_lock);
4342
4343         return ret;
4344 }
4345 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4346
4347 /**
4348  * i915_gpu_raise - raise GPU frequency limit
4349  *
4350  * Raise the limit; IPS indicates we have thermal headroom.
4351  */
4352 bool i915_gpu_raise(void)
4353 {
4354         struct drm_i915_private *dev_priv;
4355         bool ret = true;
4356
4357         spin_lock_irq(&mchdev_lock);
4358         if (!i915_mch_dev) {
4359                 ret = false;
4360                 goto out_unlock;
4361         }
4362         dev_priv = i915_mch_dev;
4363
4364         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4365                 dev_priv->ips.max_delay--;
4366
4367 out_unlock:
4368         spin_unlock_irq(&mchdev_lock);
4369
4370         return ret;
4371 }
4372 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4373
4374 /**
4375  * i915_gpu_lower - lower GPU frequency limit
4376  *
4377  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4378  * frequency maximum.
4379  */
4380 bool i915_gpu_lower(void)
4381 {
4382         struct drm_i915_private *dev_priv;
4383         bool ret = true;
4384
4385         spin_lock_irq(&mchdev_lock);
4386         if (!i915_mch_dev) {
4387                 ret = false;
4388                 goto out_unlock;
4389         }
4390         dev_priv = i915_mch_dev;
4391
4392         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4393                 dev_priv->ips.max_delay++;
4394
4395 out_unlock:
4396         spin_unlock_irq(&mchdev_lock);
4397
4398         return ret;
4399 }
4400 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4401
4402 /**
4403  * i915_gpu_busy - indicate GPU business to IPS
4404  *
4405  * Tell the IPS driver whether or not the GPU is busy.
4406  */
4407 bool i915_gpu_busy(void)
4408 {
4409         struct drm_i915_private *dev_priv;
4410         struct intel_ring_buffer *ring;
4411         bool ret = false;
4412         int i;
4413
4414         spin_lock_irq(&mchdev_lock);
4415         if (!i915_mch_dev)
4416                 goto out_unlock;
4417         dev_priv = i915_mch_dev;
4418
4419         for_each_ring(ring, dev_priv, i)
4420                 ret |= !list_empty(&ring->request_list);
4421
4422 out_unlock:
4423         spin_unlock_irq(&mchdev_lock);
4424
4425         return ret;
4426 }
4427 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4428
4429 /**
4430  * i915_gpu_turbo_disable - disable graphics turbo
4431  *
4432  * Disable graphics turbo by resetting the max frequency and setting the
4433  * current frequency to the default.
4434  */
4435 bool i915_gpu_turbo_disable(void)
4436 {
4437         struct drm_i915_private *dev_priv;
4438         bool ret = true;
4439
4440         spin_lock_irq(&mchdev_lock);
4441         if (!i915_mch_dev) {
4442                 ret = false;
4443                 goto out_unlock;
4444         }
4445         dev_priv = i915_mch_dev;
4446
4447         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4448
4449         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4450                 ret = false;
4451
4452 out_unlock:
4453         spin_unlock_irq(&mchdev_lock);
4454
4455         return ret;
4456 }
4457 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4458
4459 /**
4460  * Tells the intel_ips driver that the i915 driver is now loaded, if
4461  * IPS got loaded first.
4462  *
4463  * This awkward dance is so that neither module has to depend on the
4464  * other in order for IPS to do the appropriate communication of
4465  * GPU turbo limits to i915.
4466  */
4467 static void
4468 ips_ping_for_i915_load(void)
4469 {
4470         void (*link)(void);
4471
4472         link = symbol_get(ips_link_to_i915_driver);
4473         if (link) {
4474                 link();
4475                 symbol_put(ips_link_to_i915_driver);
4476         }
4477 }
4478
4479 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4480 {
4481         /* We only register the i915 ips part with intel-ips once everything is
4482          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4483         spin_lock_irq(&mchdev_lock);
4484         i915_mch_dev = dev_priv;
4485         spin_unlock_irq(&mchdev_lock);
4486
4487         ips_ping_for_i915_load();
4488 }
4489
4490 void intel_gpu_ips_teardown(void)
4491 {
4492         spin_lock_irq(&mchdev_lock);
4493         i915_mch_dev = NULL;
4494         spin_unlock_irq(&mchdev_lock);
4495 }
4496
4497 static void intel_init_emon(struct drm_device *dev)
4498 {
4499         struct drm_i915_private *dev_priv = dev->dev_private;
4500         u32 lcfuse;
4501         u8 pxw[16];
4502         int i;
4503
4504         /* Disable to program */
4505         I915_WRITE(ECR, 0);
4506         POSTING_READ(ECR);
4507
4508         /* Program energy weights for various events */
4509         I915_WRITE(SDEW, 0x15040d00);
4510         I915_WRITE(CSIEW0, 0x007f0000);
4511         I915_WRITE(CSIEW1, 0x1e220004);
4512         I915_WRITE(CSIEW2, 0x04000004);
4513
4514         for (i = 0; i < 5; i++)
4515                 I915_WRITE(PEW + (i * 4), 0);
4516         for (i = 0; i < 3; i++)
4517                 I915_WRITE(DEW + (i * 4), 0);
4518
4519         /* Program P-state weights to account for frequency power adjustment */
4520         for (i = 0; i < 16; i++) {
4521                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4522                 unsigned long freq = intel_pxfreq(pxvidfreq);
4523                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4524                         PXVFREQ_PX_SHIFT;
4525                 unsigned long val;
4526
4527                 val = vid * vid;
4528                 val *= (freq / 1000);
4529                 val *= 255;
4530                 val /= (127*127*900);
4531                 if (val > 0xff)
4532                         DRM_ERROR("bad pxval: %ld\n", val);
4533                 pxw[i] = val;
4534         }
4535         /* Render standby states get 0 weight */
4536         pxw[14] = 0;
4537         pxw[15] = 0;
4538
4539         for (i = 0; i < 4; i++) {
4540                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4541                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4542                 I915_WRITE(PXW + (i * 4), val);
4543         }
4544
4545         /* Adjust magic regs to magic values (more experimental results) */
4546         I915_WRITE(OGW0, 0);
4547         I915_WRITE(OGW1, 0);
4548         I915_WRITE(EG0, 0x00007f00);
4549         I915_WRITE(EG1, 0x0000000e);
4550         I915_WRITE(EG2, 0x000e0000);
4551         I915_WRITE(EG3, 0x68000300);
4552         I915_WRITE(EG4, 0x42000000);
4553         I915_WRITE(EG5, 0x00140031);
4554         I915_WRITE(EG6, 0);
4555         I915_WRITE(EG7, 0);
4556
4557         for (i = 0; i < 8; i++)
4558                 I915_WRITE(PXWL + (i * 4), 0);
4559
4560         /* Enable PMON + select events */
4561         I915_WRITE(ECR, 0x80000019);
4562
4563         lcfuse = I915_READ(LCFUSE02);
4564
4565         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4566 }
4567
4568 void intel_init_gt_powersave(struct drm_device *dev)
4569 {
4570         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4571
4572         if (IS_VALLEYVIEW(dev))
4573                 valleyview_init_gt_powersave(dev);
4574 }
4575
4576 void intel_cleanup_gt_powersave(struct drm_device *dev)
4577 {
4578         if (IS_VALLEYVIEW(dev))
4579                 valleyview_cleanup_gt_powersave(dev);
4580 }
4581
4582 void intel_disable_gt_powersave(struct drm_device *dev)
4583 {
4584         struct drm_i915_private *dev_priv = dev->dev_private;
4585
4586         /* Interrupts should be disabled already to avoid re-arming. */
4587         WARN_ON(dev->irq_enabled);
4588
4589         if (IS_IRONLAKE_M(dev)) {
4590                 ironlake_disable_drps(dev);
4591                 ironlake_disable_rc6(dev);
4592         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4593                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4594                 cancel_work_sync(&dev_priv->rps.work);
4595                 mutex_lock(&dev_priv->rps.hw_lock);
4596                 if (IS_VALLEYVIEW(dev))
4597                         valleyview_disable_rps(dev);
4598                 else
4599                         gen6_disable_rps(dev);
4600                 dev_priv->rps.enabled = false;
4601                 mutex_unlock(&dev_priv->rps.hw_lock);
4602         }
4603 }
4604
4605 static void intel_gen6_powersave_work(struct work_struct *work)
4606 {
4607         struct drm_i915_private *dev_priv =
4608                 container_of(work, struct drm_i915_private,
4609                              rps.delayed_resume_work.work);
4610         struct drm_device *dev = dev_priv->dev;
4611
4612         mutex_lock(&dev_priv->rps.hw_lock);
4613
4614         if (IS_VALLEYVIEW(dev)) {
4615                 valleyview_enable_rps(dev);
4616         } else if (IS_BROADWELL(dev)) {
4617                 gen8_enable_rps(dev);
4618                 __gen6_update_ring_freq(dev);
4619         } else {
4620                 gen6_enable_rps(dev);
4621                 __gen6_update_ring_freq(dev);
4622         }
4623         dev_priv->rps.enabled = true;
4624         mutex_unlock(&dev_priv->rps.hw_lock);
4625
4626         intel_runtime_pm_put(dev_priv);
4627 }
4628
4629 void intel_enable_gt_powersave(struct drm_device *dev)
4630 {
4631         struct drm_i915_private *dev_priv = dev->dev_private;
4632
4633         if (IS_IRONLAKE_M(dev)) {
4634                 mutex_lock(&dev->struct_mutex);
4635                 ironlake_enable_drps(dev);
4636                 ironlake_enable_rc6(dev);
4637                 intel_init_emon(dev);
4638                 mutex_unlock(&dev->struct_mutex);
4639         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4640                 /*
4641                  * PCU communication is slow and this doesn't need to be
4642                  * done at any specific time, so do this out of our fast path
4643                  * to make resume and init faster.
4644                  *
4645                  * We depend on the HW RC6 power context save/restore
4646                  * mechanism when entering D3 through runtime PM suspend. So
4647                  * disable RPM until RPS/RC6 is properly setup. We can only
4648                  * get here via the driver load/system resume/runtime resume
4649                  * paths, so the _noresume version is enough (and in case of
4650                  * runtime resume it's necessary).
4651                  */
4652                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4653                                            round_jiffies_up_relative(HZ)))
4654                         intel_runtime_pm_get_noresume(dev_priv);
4655         }
4656 }
4657
4658 void intel_reset_gt_powersave(struct drm_device *dev)
4659 {
4660         struct drm_i915_private *dev_priv = dev->dev_private;
4661
4662         dev_priv->rps.enabled = false;
4663         intel_enable_gt_powersave(dev);
4664 }
4665
4666 static void ibx_init_clock_gating(struct drm_device *dev)
4667 {
4668         struct drm_i915_private *dev_priv = dev->dev_private;
4669
4670         /*
4671          * On Ibex Peak and Cougar Point, we need to disable clock
4672          * gating for the panel power sequencer or it will fail to
4673          * start up when no ports are active.
4674          */
4675         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4676 }
4677
4678 static void g4x_disable_trickle_feed(struct drm_device *dev)
4679 {
4680         struct drm_i915_private *dev_priv = dev->dev_private;
4681         int pipe;
4682
4683         for_each_pipe(pipe) {
4684                 I915_WRITE(DSPCNTR(pipe),
4685                            I915_READ(DSPCNTR(pipe)) |
4686                            DISPPLANE_TRICKLE_FEED_DISABLE);
4687                 intel_flush_primary_plane(dev_priv, pipe);
4688         }
4689 }
4690
4691 static void ilk_init_lp_watermarks(struct drm_device *dev)
4692 {
4693         struct drm_i915_private *dev_priv = dev->dev_private;
4694
4695         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4696         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4697         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4698
4699         /*
4700          * Don't touch WM1S_LP_EN here.
4701          * Doing so could cause underruns.
4702          */
4703 }
4704
4705 static void ironlake_init_clock_gating(struct drm_device *dev)
4706 {
4707         struct drm_i915_private *dev_priv = dev->dev_private;
4708         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4709
4710         /*
4711          * Required for FBC
4712          * WaFbcDisableDpfcClockGating:ilk
4713          */
4714         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4715                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4716                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4717
4718         I915_WRITE(PCH_3DCGDIS0,
4719                    MARIUNIT_CLOCK_GATE_DISABLE |
4720                    SVSMUNIT_CLOCK_GATE_DISABLE);
4721         I915_WRITE(PCH_3DCGDIS1,
4722                    VFMUNIT_CLOCK_GATE_DISABLE);
4723
4724         /*
4725          * According to the spec the following bits should be set in
4726          * order to enable memory self-refresh
4727          * The bit 22/21 of 0x42004
4728          * The bit 5 of 0x42020
4729          * The bit 15 of 0x45000
4730          */
4731         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4732                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4733                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4734         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4735         I915_WRITE(DISP_ARB_CTL,
4736                    (I915_READ(DISP_ARB_CTL) |
4737                     DISP_FBC_WM_DIS));
4738
4739         ilk_init_lp_watermarks(dev);
4740
4741         /*
4742          * Based on the document from hardware guys the following bits
4743          * should be set unconditionally in order to enable FBC.
4744          * The bit 22 of 0x42000
4745          * The bit 22 of 0x42004
4746          * The bit 7,8,9 of 0x42020.
4747          */
4748         if (IS_IRONLAKE_M(dev)) {
4749                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4750                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4751                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4752                            ILK_FBCQ_DIS);
4753                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4754                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4755                            ILK_DPARB_GATE);
4756         }
4757
4758         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4759
4760         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4761                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4762                    ILK_ELPIN_409_SELECT);
4763         I915_WRITE(_3D_CHICKEN2,
4764                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4765                    _3D_CHICKEN2_WM_READ_PIPELINED);
4766
4767         /* WaDisableRenderCachePipelinedFlush:ilk */
4768         I915_WRITE(CACHE_MODE_0,
4769                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4770
4771         /* WaDisable_RenderCache_OperationalFlush:ilk */
4772         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4773
4774         g4x_disable_trickle_feed(dev);
4775
4776         ibx_init_clock_gating(dev);
4777 }
4778
4779 static void cpt_init_clock_gating(struct drm_device *dev)
4780 {
4781         struct drm_i915_private *dev_priv = dev->dev_private;
4782         int pipe;
4783         uint32_t val;
4784
4785         /*
4786          * On Ibex Peak and Cougar Point, we need to disable clock
4787          * gating for the panel power sequencer or it will fail to
4788          * start up when no ports are active.
4789          */
4790         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4791                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4792                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
4793         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4794                    DPLS_EDP_PPS_FIX_DIS);
4795         /* The below fixes the weird display corruption, a few pixels shifted
4796          * downward, on (only) LVDS of some HP laptops with IVY.
4797          */
4798         for_each_pipe(pipe) {
4799                 val = I915_READ(TRANS_CHICKEN2(pipe));
4800                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4801                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4802                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4803                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4804                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4805                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4806                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4807                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4808         }
4809         /* WADP0ClockGatingDisable */
4810         for_each_pipe(pipe) {
4811                 I915_WRITE(TRANS_CHICKEN1(pipe),
4812                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4813         }
4814 }
4815
4816 static void gen6_check_mch_setup(struct drm_device *dev)
4817 {
4818         struct drm_i915_private *dev_priv = dev->dev_private;
4819         uint32_t tmp;
4820
4821         tmp = I915_READ(MCH_SSKPD);
4822         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4823                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4824                 DRM_INFO("This can cause pipe underruns and display issues.\n");
4825                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4826         }
4827 }
4828
4829 static void gen6_init_clock_gating(struct drm_device *dev)
4830 {
4831         struct drm_i915_private *dev_priv = dev->dev_private;
4832         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4833
4834         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4835
4836         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4837                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4838                    ILK_ELPIN_409_SELECT);
4839
4840         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4841         I915_WRITE(_3D_CHICKEN,
4842                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4843
4844         /* WaSetupGtModeTdRowDispatch:snb */
4845         if (IS_SNB_GT1(dev))
4846                 I915_WRITE(GEN6_GT_MODE,
4847                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4848
4849         /* WaDisable_RenderCache_OperationalFlush:snb */
4850         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4851
4852         /*
4853          * BSpec recoomends 8x4 when MSAA is used,
4854          * however in practice 16x4 seems fastest.
4855          *
4856          * Note that PS/WM thread counts depend on the WIZ hashing
4857          * disable bit, which we don't touch here, but it's good
4858          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4859          */
4860         I915_WRITE(GEN6_GT_MODE,
4861                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4862
4863         ilk_init_lp_watermarks(dev);
4864
4865         I915_WRITE(CACHE_MODE_0,
4866                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4867
4868         I915_WRITE(GEN6_UCGCTL1,
4869                    I915_READ(GEN6_UCGCTL1) |
4870                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4871                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4872
4873         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4874          * gating disable must be set.  Failure to set it results in
4875          * flickering pixels due to Z write ordering failures after
4876          * some amount of runtime in the Mesa "fire" demo, and Unigine
4877          * Sanctuary and Tropics, and apparently anything else with
4878          * alpha test or pixel discard.
4879          *
4880          * According to the spec, bit 11 (RCCUNIT) must also be set,
4881          * but we didn't debug actual testcases to find it out.
4882          *
4883          * WaDisableRCCUnitClockGating:snb
4884          * WaDisableRCPBUnitClockGating:snb
4885          */
4886         I915_WRITE(GEN6_UCGCTL2,
4887                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4888                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4889
4890         /* WaStripsFansDisableFastClipPerformanceFix:snb */
4891         I915_WRITE(_3D_CHICKEN3,
4892                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
4893
4894         /*
4895          * Bspec says:
4896          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
4897          * 3DSTATE_SF number of SF output attributes is more than 16."
4898          */
4899         I915_WRITE(_3D_CHICKEN3,
4900                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
4901
4902         /*
4903          * According to the spec the following bits should be
4904          * set in order to enable memory self-refresh and fbc:
4905          * The bit21 and bit22 of 0x42000
4906          * The bit21 and bit22 of 0x42004
4907          * The bit5 and bit7 of 0x42020
4908          * The bit14 of 0x70180
4909          * The bit14 of 0x71180
4910          *
4911          * WaFbcAsynchFlipDisableFbcQueue:snb
4912          */
4913         I915_WRITE(ILK_DISPLAY_CHICKEN1,
4914                    I915_READ(ILK_DISPLAY_CHICKEN1) |
4915                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4916         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4917                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4918                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4919         I915_WRITE(ILK_DSPCLK_GATE_D,
4920                    I915_READ(ILK_DSPCLK_GATE_D) |
4921                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
4922                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4923
4924         g4x_disable_trickle_feed(dev);
4925
4926         cpt_init_clock_gating(dev);
4927
4928         gen6_check_mch_setup(dev);
4929 }
4930
4931 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4932 {
4933         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4934
4935         /*
4936          * WaVSThreadDispatchOverride:ivb,vlv
4937          *
4938          * This actually overrides the dispatch
4939          * mode for all thread types.
4940          */
4941         reg &= ~GEN7_FF_SCHED_MASK;
4942         reg |= GEN7_FF_TS_SCHED_HW;
4943         reg |= GEN7_FF_VS_SCHED_HW;
4944         reg |= GEN7_FF_DS_SCHED_HW;
4945
4946         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4947 }
4948
4949 static void lpt_init_clock_gating(struct drm_device *dev)
4950 {
4951         struct drm_i915_private *dev_priv = dev->dev_private;
4952
4953         /*
4954          * TODO: this bit should only be enabled when really needed, then
4955          * disabled when not needed anymore in order to save power.
4956          */
4957         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4958                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4959                            I915_READ(SOUTH_DSPCLK_GATE_D) |
4960                            PCH_LP_PARTITION_LEVEL_DISABLE);
4961
4962         /* WADPOClockGatingDisable:hsw */
4963         I915_WRITE(_TRANSA_CHICKEN1,
4964                    I915_READ(_TRANSA_CHICKEN1) |
4965                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4966 }
4967
4968 static void lpt_suspend_hw(struct drm_device *dev)
4969 {
4970         struct drm_i915_private *dev_priv = dev->dev_private;
4971
4972         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4973                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4974
4975                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4976                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4977         }
4978 }
4979
4980 static void gen8_init_clock_gating(struct drm_device *dev)
4981 {
4982         struct drm_i915_private *dev_priv = dev->dev_private;
4983         enum pipe pipe;
4984
4985         I915_WRITE(WM3_LP_ILK, 0);
4986         I915_WRITE(WM2_LP_ILK, 0);
4987         I915_WRITE(WM1_LP_ILK, 0);
4988
4989         /* FIXME(BDW): Check all the w/a, some might only apply to
4990          * pre-production hw. */
4991
4992         /* WaDisablePartialInstShootdown:bdw */
4993         I915_WRITE(GEN8_ROW_CHICKEN,
4994                    _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
4995
4996         /* WaDisableThreadStallDopClockGating:bdw */
4997         /* FIXME: Unclear whether we really need this on production bdw. */
4998         I915_WRITE(GEN8_ROW_CHICKEN,
4999                    _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5000
5001         /*
5002          * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5003          * pre-production hardware
5004          */
5005         I915_WRITE(HALF_SLICE_CHICKEN3,
5006                    _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5007         I915_WRITE(HALF_SLICE_CHICKEN3,
5008                    _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5009         I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5010
5011         I915_WRITE(_3D_CHICKEN3,
5012                    _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5013
5014         I915_WRITE(COMMON_SLICE_CHICKEN2,
5015                    _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5016
5017         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5018                    _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5019
5020         /* WaDisableDopClockGating:bdw May not be needed for production */
5021         I915_WRITE(GEN7_ROW_CHICKEN2,
5022                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5023
5024         /* WaSwitchSolVfFArbitrationPriority:bdw */
5025         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5026
5027         /* WaPsrDPAMaskVBlankInSRD:bdw */
5028         I915_WRITE(CHICKEN_PAR1_1,
5029                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5030
5031         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5032         for_each_pipe(pipe) {
5033                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5034                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
5035                            BDW_DPRS_MASK_VBLANK_SRD);
5036         }
5037
5038         /* Use Force Non-Coherent whenever executing a 3D context. This is a
5039          * workaround for for a possible hang in the unlikely event a TLB
5040          * invalidation occurs during a PSD flush.
5041          */
5042         I915_WRITE(HDC_CHICKEN0,
5043                    I915_READ(HDC_CHICKEN0) |
5044                    _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5045
5046         /* WaVSRefCountFullforceMissDisable:bdw */
5047         /* WaDSRefCountFullforceMissDisable:bdw */
5048         I915_WRITE(GEN7_FF_THREAD_MODE,
5049                    I915_READ(GEN7_FF_THREAD_MODE) &
5050                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5051
5052         /*
5053          * BSpec recommends 8x4 when MSAA is used,
5054          * however in practice 16x4 seems fastest.
5055          *
5056          * Note that PS/WM thread counts depend on the WIZ hashing
5057          * disable bit, which we don't touch here, but it's good
5058          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5059          */
5060         I915_WRITE(GEN7_GT_MODE,
5061                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5062
5063         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5064                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5065
5066         /* WaDisableSDEUnitClockGating:bdw */
5067         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5068                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5069
5070         /* Wa4x4STCOptimizationDisable:bdw */
5071         I915_WRITE(CACHE_MODE_1,
5072                    _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
5073 }
5074
5075 static void haswell_init_clock_gating(struct drm_device *dev)
5076 {
5077         struct drm_i915_private *dev_priv = dev->dev_private;
5078
5079         ilk_init_lp_watermarks(dev);
5080
5081         /* L3 caching of data atomics doesn't work -- disable it. */
5082         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5083         I915_WRITE(HSW_ROW_CHICKEN3,
5084                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5085
5086         /* This is required by WaCatErrorRejectionIssue:hsw */
5087         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5088                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5089                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5090
5091         /* WaVSRefCountFullforceMissDisable:hsw */
5092         I915_WRITE(GEN7_FF_THREAD_MODE,
5093                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5094
5095         /* WaDisable_RenderCache_OperationalFlush:hsw */
5096         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5097
5098         /* enable HiZ Raw Stall Optimization */
5099         I915_WRITE(CACHE_MODE_0_GEN7,
5100                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5101
5102         /* WaDisable4x2SubspanOptimization:hsw */
5103         I915_WRITE(CACHE_MODE_1,
5104                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5105
5106         /*
5107          * BSpec recommends 8x4 when MSAA is used,
5108          * however in practice 16x4 seems fastest.
5109          *
5110          * Note that PS/WM thread counts depend on the WIZ hashing
5111          * disable bit, which we don't touch here, but it's good
5112          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5113          */
5114         I915_WRITE(GEN7_GT_MODE,
5115                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5116
5117         /* WaSwitchSolVfFArbitrationPriority:hsw */
5118         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5119
5120         /* WaRsPkgCStateDisplayPMReq:hsw */
5121         I915_WRITE(CHICKEN_PAR1_1,
5122                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5123
5124         lpt_init_clock_gating(dev);
5125 }
5126
5127 static void ivybridge_init_clock_gating(struct drm_device *dev)
5128 {
5129         struct drm_i915_private *dev_priv = dev->dev_private;
5130         uint32_t snpcr;
5131
5132         ilk_init_lp_watermarks(dev);
5133
5134         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5135
5136         /* WaDisableEarlyCull:ivb */
5137         I915_WRITE(_3D_CHICKEN3,
5138                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5139
5140         /* WaDisableBackToBackFlipFix:ivb */
5141         I915_WRITE(IVB_CHICKEN3,
5142                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5143                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5144
5145         /* WaDisablePSDDualDispatchEnable:ivb */
5146         if (IS_IVB_GT1(dev))
5147                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5148                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5149
5150         /* WaDisable_RenderCache_OperationalFlush:ivb */
5151         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5152
5153         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5154         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5155                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5156
5157         /* WaApplyL3ControlAndL3ChickenMode:ivb */
5158         I915_WRITE(GEN7_L3CNTLREG1,
5159                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5160         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5161                    GEN7_WA_L3_CHICKEN_MODE);
5162         if (IS_IVB_GT1(dev))
5163                 I915_WRITE(GEN7_ROW_CHICKEN2,
5164                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5165         else {
5166                 /* must write both registers */
5167                 I915_WRITE(GEN7_ROW_CHICKEN2,
5168                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5169                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5170                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5171         }
5172
5173         /* WaForceL3Serialization:ivb */
5174         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5175                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5176
5177         /*
5178          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5179          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5180          */
5181         I915_WRITE(GEN6_UCGCTL2,
5182                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5183
5184         /* This is required by WaCatErrorRejectionIssue:ivb */
5185         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5186                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5187                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5188
5189         g4x_disable_trickle_feed(dev);
5190
5191         gen7_setup_fixed_func_scheduler(dev_priv);
5192
5193         if (0) { /* causes HiZ corruption on ivb:gt1 */
5194                 /* enable HiZ Raw Stall Optimization */
5195                 I915_WRITE(CACHE_MODE_0_GEN7,
5196                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5197         }
5198
5199         /* WaDisable4x2SubspanOptimization:ivb */
5200         I915_WRITE(CACHE_MODE_1,
5201                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5202
5203         /*
5204          * BSpec recommends 8x4 when MSAA is used,
5205          * however in practice 16x4 seems fastest.
5206          *
5207          * Note that PS/WM thread counts depend on the WIZ hashing
5208          * disable bit, which we don't touch here, but it's good
5209          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5210          */
5211         I915_WRITE(GEN7_GT_MODE,
5212                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5213
5214         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5215         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5216         snpcr |= GEN6_MBC_SNPCR_MED;
5217         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5218
5219         if (!HAS_PCH_NOP(dev))
5220                 cpt_init_clock_gating(dev);
5221
5222         gen6_check_mch_setup(dev);
5223 }
5224
5225 static void valleyview_init_clock_gating(struct drm_device *dev)
5226 {
5227         struct drm_i915_private *dev_priv = dev->dev_private;
5228         u32 val;
5229
5230         mutex_lock(&dev_priv->rps.hw_lock);
5231         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5232         mutex_unlock(&dev_priv->rps.hw_lock);
5233         switch ((val >> 6) & 3) {
5234         case 0:
5235         case 1:
5236                 dev_priv->mem_freq = 800;
5237                 break;
5238         case 2:
5239                 dev_priv->mem_freq = 1066;
5240                 break;
5241         case 3:
5242                 dev_priv->mem_freq = 1333;
5243                 break;
5244         }
5245         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5246
5247         dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
5248         DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz",
5249                          dev_priv->vlv_cdclk_freq);
5250
5251         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5252
5253         /* WaDisableEarlyCull:vlv */
5254         I915_WRITE(_3D_CHICKEN3,
5255                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5256
5257         /* WaDisableBackToBackFlipFix:vlv */
5258         I915_WRITE(IVB_CHICKEN3,
5259                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5260                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5261
5262         /* WaPsdDispatchEnable:vlv */
5263         /* WaDisablePSDDualDispatchEnable:vlv */
5264         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5265                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5266                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5267
5268         /* WaDisable_RenderCache_OperationalFlush:vlv */
5269         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5270
5271         /* WaForceL3Serialization:vlv */
5272         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5273                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5274
5275         /* WaDisableDopClockGating:vlv */
5276         I915_WRITE(GEN7_ROW_CHICKEN2,
5277                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5278
5279         /* This is required by WaCatErrorRejectionIssue:vlv */
5280         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5281                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5282                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5283
5284         gen7_setup_fixed_func_scheduler(dev_priv);
5285
5286         /*
5287          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5288          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5289          */
5290         I915_WRITE(GEN6_UCGCTL2,
5291                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5292
5293         /* WaDisableL3Bank2xClockGate:vlv */
5294         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5295
5296         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5297
5298         /*
5299          * BSpec says this must be set, even though
5300          * WaDisable4x2SubspanOptimization isn't listed for VLV.
5301          */
5302         I915_WRITE(CACHE_MODE_1,
5303                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5304
5305         /*
5306          * WaIncreaseL3CreditsForVLVB0:vlv
5307          * This is the hardware default actually.
5308          */
5309         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5310
5311         /*
5312          * WaDisableVLVClockGating_VBIIssue:vlv
5313          * Disable clock gating on th GCFG unit to prevent a delay
5314          * in the reporting of vblank events.
5315          */
5316         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5317 }
5318
5319 static void g4x_init_clock_gating(struct drm_device *dev)
5320 {
5321         struct drm_i915_private *dev_priv = dev->dev_private;
5322         uint32_t dspclk_gate;
5323
5324         I915_WRITE(RENCLK_GATE_D1, 0);
5325         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5326                    GS_UNIT_CLOCK_GATE_DISABLE |
5327                    CL_UNIT_CLOCK_GATE_DISABLE);
5328         I915_WRITE(RAMCLK_GATE_D, 0);
5329         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5330                 OVRUNIT_CLOCK_GATE_DISABLE |
5331                 OVCUNIT_CLOCK_GATE_DISABLE;
5332         if (IS_GM45(dev))
5333                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5334         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5335
5336         /* WaDisableRenderCachePipelinedFlush */
5337         I915_WRITE(CACHE_MODE_0,
5338                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5339
5340         /* WaDisable_RenderCache_OperationalFlush:g4x */
5341         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5342
5343         g4x_disable_trickle_feed(dev);
5344 }
5345
5346 static void crestline_init_clock_gating(struct drm_device *dev)
5347 {
5348         struct drm_i915_private *dev_priv = dev->dev_private;
5349
5350         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5351         I915_WRITE(RENCLK_GATE_D2, 0);
5352         I915_WRITE(DSPCLK_GATE_D, 0);
5353         I915_WRITE(RAMCLK_GATE_D, 0);
5354         I915_WRITE16(DEUC, 0);
5355         I915_WRITE(MI_ARB_STATE,
5356                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5357
5358         /* WaDisable_RenderCache_OperationalFlush:gen4 */
5359         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5360 }
5361
5362 static void broadwater_init_clock_gating(struct drm_device *dev)
5363 {
5364         struct drm_i915_private *dev_priv = dev->dev_private;
5365
5366         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5367                    I965_RCC_CLOCK_GATE_DISABLE |
5368                    I965_RCPB_CLOCK_GATE_DISABLE |
5369                    I965_ISC_CLOCK_GATE_DISABLE |
5370                    I965_FBC_CLOCK_GATE_DISABLE);
5371         I915_WRITE(RENCLK_GATE_D2, 0);
5372         I915_WRITE(MI_ARB_STATE,
5373                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5374
5375         /* WaDisable_RenderCache_OperationalFlush:gen4 */
5376         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5377 }
5378
5379 static void gen3_init_clock_gating(struct drm_device *dev)
5380 {
5381         struct drm_i915_private *dev_priv = dev->dev_private;
5382         u32 dstate = I915_READ(D_STATE);
5383
5384         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5385                 DSTATE_DOT_CLOCK_GATING;
5386         I915_WRITE(D_STATE, dstate);
5387
5388         if (IS_PINEVIEW(dev))
5389                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5390
5391         /* IIR "flip pending" means done if this bit is set */
5392         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5393 }
5394
5395 static void i85x_init_clock_gating(struct drm_device *dev)
5396 {
5397         struct drm_i915_private *dev_priv = dev->dev_private;
5398
5399         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5400 }
5401
5402 static void i830_init_clock_gating(struct drm_device *dev)
5403 {
5404         struct drm_i915_private *dev_priv = dev->dev_private;
5405
5406         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5407 }
5408
5409 void intel_init_clock_gating(struct drm_device *dev)
5410 {
5411         struct drm_i915_private *dev_priv = dev->dev_private;
5412
5413         dev_priv->display.init_clock_gating(dev);
5414 }
5415
5416 void intel_suspend_hw(struct drm_device *dev)
5417 {
5418         if (HAS_PCH_LPT(dev))
5419                 lpt_suspend_hw(dev);
5420 }
5421
5422 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
5423         for (i = 0;                                                     \
5424              i < (power_domains)->power_well_count &&                   \
5425                  ((power_well) = &(power_domains)->power_wells[i]);     \
5426              i++)                                                       \
5427                 if ((power_well)->domains & (domain_mask))
5428
5429 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5430         for (i = (power_domains)->power_well_count - 1;                  \
5431              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5432              i--)                                                        \
5433                 if ((power_well)->domains & (domain_mask))
5434
5435 /**
5436  * We should only use the power well if we explicitly asked the hardware to
5437  * enable it, so check if it's enabled and also check if we've requested it to
5438  * be enabled.
5439  */
5440 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
5441                                    struct i915_power_well *power_well)
5442 {
5443         return I915_READ(HSW_PWR_WELL_DRIVER) ==
5444                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5445 }
5446
5447 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
5448                                     enum intel_display_power_domain domain)
5449 {
5450         struct i915_power_domains *power_domains;
5451
5452         power_domains = &dev_priv->power_domains;
5453
5454         return power_domains->domain_use_count[domain];
5455 }
5456
5457 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
5458                                  enum intel_display_power_domain domain)
5459 {
5460         struct i915_power_domains *power_domains;
5461         struct i915_power_well *power_well;
5462         bool is_enabled;
5463         int i;
5464
5465         if (dev_priv->pm.suspended)
5466                 return false;
5467
5468         power_domains = &dev_priv->power_domains;
5469
5470         is_enabled = true;
5471
5472         mutex_lock(&power_domains->lock);
5473         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5474                 if (power_well->always_on)
5475                         continue;
5476
5477                 if (!power_well->ops->is_enabled(dev_priv, power_well)) {
5478                         is_enabled = false;
5479                         break;
5480                 }
5481         }
5482         mutex_unlock(&power_domains->lock);
5483
5484         return is_enabled;
5485 }
5486
5487 /*
5488  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5489  * when not needed anymore. We have 4 registers that can request the power well
5490  * to be enabled, and it will only be disabled if none of the registers is
5491  * requesting it to be enabled.
5492  */
5493 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5494 {
5495         struct drm_device *dev = dev_priv->dev;
5496         unsigned long irqflags;
5497
5498         /*
5499          * After we re-enable the power well, if we touch VGA register 0x3d5
5500          * we'll get unclaimed register interrupts. This stops after we write
5501          * anything to the VGA MSR register. The vgacon module uses this
5502          * register all the time, so if we unbind our driver and, as a
5503          * consequence, bind vgacon, we'll get stuck in an infinite loop at
5504          * console_unlock(). So make here we touch the VGA MSR register, making
5505          * sure vgacon can keep working normally without triggering interrupts
5506          * and error messages.
5507          */
5508         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5509         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5510         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5511
5512         if (IS_BROADWELL(dev)) {
5513                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5514                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5515                            dev_priv->de_irq_mask[PIPE_B]);
5516                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5517                            ~dev_priv->de_irq_mask[PIPE_B] |
5518                            GEN8_PIPE_VBLANK);
5519                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5520                            dev_priv->de_irq_mask[PIPE_C]);
5521                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5522                            ~dev_priv->de_irq_mask[PIPE_C] |
5523                            GEN8_PIPE_VBLANK);
5524                 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5525                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5526         }
5527 }
5528
5529 static void reset_vblank_counter(struct drm_device *dev, enum pipe pipe)
5530 {
5531         assert_spin_locked(&dev->vbl_lock);
5532
5533         dev->vblank[pipe].last = 0;
5534 }
5535
5536 static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5537 {
5538         struct drm_device *dev = dev_priv->dev;
5539         enum pipe pipe;
5540         unsigned long irqflags;
5541
5542         /*
5543          * After this, the registers on the pipes that are part of the power
5544          * well will become zero, so we have to adjust our counters according to
5545          * that.
5546          *
5547          * FIXME: Should we do this in general in drm_vblank_post_modeset?
5548          */
5549         spin_lock_irqsave(&dev->vbl_lock, irqflags);
5550         for_each_pipe(pipe)
5551                 if (pipe != PIPE_A)
5552                         reset_vblank_counter(dev, pipe);
5553         spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5554 }
5555
5556 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
5557                                struct i915_power_well *power_well, bool enable)
5558 {
5559         bool is_enabled, enable_requested;
5560         uint32_t tmp;
5561
5562         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5563         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5564         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5565
5566         if (enable) {
5567                 if (!enable_requested)
5568                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5569                                    HSW_PWR_WELL_ENABLE_REQUEST);
5570
5571                 if (!is_enabled) {
5572                         DRM_DEBUG_KMS("Enabling power well\n");
5573                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5574                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5575                                 DRM_ERROR("Timeout enabling power well\n");
5576                 }
5577
5578                 hsw_power_well_post_enable(dev_priv);
5579         } else {
5580                 if (enable_requested) {
5581                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5582                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5583                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5584
5585                         hsw_power_well_post_disable(dev_priv);
5586                 }
5587         }
5588 }
5589
5590 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5591                                    struct i915_power_well *power_well)
5592 {
5593         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5594
5595         /*
5596          * We're taking over the BIOS, so clear any requests made by it since
5597          * the driver is in charge now.
5598          */
5599         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5600                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5601 }
5602
5603 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5604                                   struct i915_power_well *power_well)
5605 {
5606         hsw_set_power_well(dev_priv, power_well, true);
5607 }
5608
5609 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5610                                    struct i915_power_well *power_well)
5611 {
5612         hsw_set_power_well(dev_priv, power_well, false);
5613 }
5614
5615 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5616                                            struct i915_power_well *power_well)
5617 {
5618 }
5619
5620 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5621                                              struct i915_power_well *power_well)
5622 {
5623         return true;
5624 }
5625
5626 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5627                                struct i915_power_well *power_well, bool enable)
5628 {
5629         enum punit_power_well power_well_id = power_well->data;
5630         u32 mask;
5631         u32 state;
5632         u32 ctrl;
5633
5634         mask = PUNIT_PWRGT_MASK(power_well_id);
5635         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
5636                          PUNIT_PWRGT_PWR_GATE(power_well_id);
5637
5638         mutex_lock(&dev_priv->rps.hw_lock);
5639
5640 #define COND \
5641         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
5642
5643         if (COND)
5644                 goto out;
5645
5646         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
5647         ctrl &= ~mask;
5648         ctrl |= state;
5649         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
5650
5651         if (wait_for(COND, 100))
5652                 DRM_ERROR("timout setting power well state %08x (%08x)\n",
5653                           state,
5654                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
5655
5656 #undef COND
5657
5658 out:
5659         mutex_unlock(&dev_priv->rps.hw_lock);
5660 }
5661
5662 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
5663                                    struct i915_power_well *power_well)
5664 {
5665         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
5666 }
5667
5668 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
5669                                   struct i915_power_well *power_well)
5670 {
5671         vlv_set_power_well(dev_priv, power_well, true);
5672 }
5673
5674 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
5675                                    struct i915_power_well *power_well)
5676 {
5677         vlv_set_power_well(dev_priv, power_well, false);
5678 }
5679
5680 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
5681                                    struct i915_power_well *power_well)
5682 {
5683         int power_well_id = power_well->data;
5684         bool enabled = false;
5685         u32 mask;
5686         u32 state;
5687         u32 ctrl;
5688
5689         mask = PUNIT_PWRGT_MASK(power_well_id);
5690         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
5691
5692         mutex_lock(&dev_priv->rps.hw_lock);
5693
5694         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
5695         /*
5696          * We only ever set the power-on and power-gate states, anything
5697          * else is unexpected.
5698          */
5699         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
5700                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
5701         if (state == ctrl)
5702                 enabled = true;
5703
5704         /*
5705          * A transient state at this point would mean some unexpected party
5706          * is poking at the power controls too.
5707          */
5708         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
5709         WARN_ON(ctrl != state);
5710
5711         mutex_unlock(&dev_priv->rps.hw_lock);
5712
5713         return enabled;
5714 }
5715
5716 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
5717                                           struct i915_power_well *power_well)
5718 {
5719         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5720
5721         vlv_set_power_well(dev_priv, power_well, true);
5722
5723         spin_lock_irq(&dev_priv->irq_lock);
5724         valleyview_enable_display_irqs(dev_priv);
5725         spin_unlock_irq(&dev_priv->irq_lock);
5726
5727         /*
5728          * During driver initialization/resume we can avoid restoring the
5729          * part of the HW/SW state that will be inited anyway explicitly.
5730          */
5731         if (dev_priv->power_domains.initializing)
5732                 return;
5733
5734         intel_hpd_init(dev_priv->dev);
5735
5736         i915_redisable_vga_power_on(dev_priv->dev);
5737 }
5738
5739 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
5740                                            struct i915_power_well *power_well)
5741 {
5742         struct drm_device *dev = dev_priv->dev;
5743         enum pipe pipe;
5744
5745         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5746
5747         spin_lock_irq(&dev_priv->irq_lock);
5748         for_each_pipe(pipe)
5749                 __intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
5750
5751         valleyview_disable_display_irqs(dev_priv);
5752         spin_unlock_irq(&dev_priv->irq_lock);
5753
5754         spin_lock_irq(&dev->vbl_lock);
5755         for_each_pipe(pipe)
5756                 reset_vblank_counter(dev, pipe);
5757         spin_unlock_irq(&dev->vbl_lock);
5758
5759         vlv_set_power_well(dev_priv, power_well, false);
5760 }
5761
5762 static void check_power_well_state(struct drm_i915_private *dev_priv,
5763                                    struct i915_power_well *power_well)
5764 {
5765         bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
5766
5767         if (power_well->always_on || !i915.disable_power_well) {
5768                 if (!enabled)
5769                         goto mismatch;
5770
5771                 return;
5772         }
5773
5774         if (enabled != (power_well->count > 0))
5775                 goto mismatch;
5776
5777         return;
5778
5779 mismatch:
5780         WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
5781                   power_well->name, power_well->always_on, enabled,
5782                   power_well->count, i915.disable_power_well);
5783 }
5784
5785 void intel_display_power_get(struct drm_i915_private *dev_priv,
5786                              enum intel_display_power_domain domain)
5787 {
5788         struct i915_power_domains *power_domains;
5789         struct i915_power_well *power_well;
5790         int i;
5791
5792         intel_runtime_pm_get(dev_priv);
5793
5794         power_domains = &dev_priv->power_domains;
5795
5796         mutex_lock(&power_domains->lock);
5797
5798         for_each_power_well(i, power_well, BIT(domain), power_domains) {
5799                 if (!power_well->count++) {
5800                         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
5801                         power_well->ops->enable(dev_priv, power_well);
5802                 }
5803
5804                 check_power_well_state(dev_priv, power_well);
5805         }
5806
5807         power_domains->domain_use_count[domain]++;
5808
5809         mutex_unlock(&power_domains->lock);
5810 }
5811
5812 void intel_display_power_put(struct drm_i915_private *dev_priv,
5813                              enum intel_display_power_domain domain)
5814 {
5815         struct i915_power_domains *power_domains;
5816         struct i915_power_well *power_well;
5817         int i;
5818
5819         power_domains = &dev_priv->power_domains;
5820
5821         mutex_lock(&power_domains->lock);
5822
5823         WARN_ON(!power_domains->domain_use_count[domain]);
5824         power_domains->domain_use_count[domain]--;
5825
5826         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5827                 WARN_ON(!power_well->count);
5828
5829                 if (!--power_well->count && i915.disable_power_well) {
5830                         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
5831                         power_well->ops->disable(dev_priv, power_well);
5832                 }
5833
5834                 check_power_well_state(dev_priv, power_well);
5835         }
5836
5837         mutex_unlock(&power_domains->lock);
5838
5839         intel_runtime_pm_put(dev_priv);
5840 }
5841
5842 static struct i915_power_domains *hsw_pwr;
5843
5844 /* Display audio driver power well request */
5845 void i915_request_power_well(void)
5846 {
5847         struct drm_i915_private *dev_priv;
5848
5849         if (WARN_ON(!hsw_pwr))
5850                 return;
5851
5852         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5853                                 power_domains);
5854         intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
5855 }
5856 EXPORT_SYMBOL_GPL(i915_request_power_well);
5857
5858 /* Display audio driver power well release */
5859 void i915_release_power_well(void)
5860 {
5861         struct drm_i915_private *dev_priv;
5862
5863         if (WARN_ON(!hsw_pwr))
5864                 return;
5865
5866         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5867                                 power_domains);
5868         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
5869 }
5870 EXPORT_SYMBOL_GPL(i915_release_power_well);
5871
5872 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
5873
5874 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
5875         BIT(POWER_DOMAIN_PIPE_A) |                      \
5876         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
5877         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
5878         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
5879         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
5880         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
5881         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
5882         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
5883         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
5884         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
5885         BIT(POWER_DOMAIN_PORT_CRT) |                    \
5886         BIT(POWER_DOMAIN_INIT))
5887 #define HSW_DISPLAY_POWER_DOMAINS (                             \
5888         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
5889         BIT(POWER_DOMAIN_INIT))
5890
5891 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
5892         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
5893         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
5894 #define BDW_DISPLAY_POWER_DOMAINS (                             \
5895         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
5896         BIT(POWER_DOMAIN_INIT))
5897
5898 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
5899 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
5900
5901 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
5902         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
5903         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
5904         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
5905         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
5906         BIT(POWER_DOMAIN_PORT_CRT) |            \
5907         BIT(POWER_DOMAIN_INIT))
5908
5909 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
5910         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
5911         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
5912         BIT(POWER_DOMAIN_INIT))
5913
5914 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
5915         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
5916         BIT(POWER_DOMAIN_INIT))
5917
5918 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
5919         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
5920         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
5921         BIT(POWER_DOMAIN_INIT))
5922
5923 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
5924         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
5925         BIT(POWER_DOMAIN_INIT))
5926
5927 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
5928         .sync_hw = i9xx_always_on_power_well_noop,
5929         .enable = i9xx_always_on_power_well_noop,
5930         .disable = i9xx_always_on_power_well_noop,
5931         .is_enabled = i9xx_always_on_power_well_enabled,
5932 };
5933
5934 static struct i915_power_well i9xx_always_on_power_well[] = {
5935         {
5936                 .name = "always-on",
5937                 .always_on = 1,
5938                 .domains = POWER_DOMAIN_MASK,
5939                 .ops = &i9xx_always_on_power_well_ops,
5940         },
5941 };
5942
5943 static const struct i915_power_well_ops hsw_power_well_ops = {
5944         .sync_hw = hsw_power_well_sync_hw,
5945         .enable = hsw_power_well_enable,
5946         .disable = hsw_power_well_disable,
5947         .is_enabled = hsw_power_well_enabled,
5948 };
5949
5950 static struct i915_power_well hsw_power_wells[] = {
5951         {
5952                 .name = "always-on",
5953                 .always_on = 1,
5954                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5955                 .ops = &i9xx_always_on_power_well_ops,
5956         },
5957         {
5958                 .name = "display",
5959                 .domains = HSW_DISPLAY_POWER_DOMAINS,
5960                 .ops = &hsw_power_well_ops,
5961         },
5962 };
5963
5964 static struct i915_power_well bdw_power_wells[] = {
5965         {
5966                 .name = "always-on",
5967                 .always_on = 1,
5968                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5969                 .ops = &i9xx_always_on_power_well_ops,
5970         },
5971         {
5972                 .name = "display",
5973                 .domains = BDW_DISPLAY_POWER_DOMAINS,
5974                 .ops = &hsw_power_well_ops,
5975         },
5976 };
5977
5978 static const struct i915_power_well_ops vlv_display_power_well_ops = {
5979         .sync_hw = vlv_power_well_sync_hw,
5980         .enable = vlv_display_power_well_enable,
5981         .disable = vlv_display_power_well_disable,
5982         .is_enabled = vlv_power_well_enabled,
5983 };
5984
5985 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
5986         .sync_hw = vlv_power_well_sync_hw,
5987         .enable = vlv_power_well_enable,
5988         .disable = vlv_power_well_disable,
5989         .is_enabled = vlv_power_well_enabled,
5990 };
5991
5992 static struct i915_power_well vlv_power_wells[] = {
5993         {
5994                 .name = "always-on",
5995                 .always_on = 1,
5996                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
5997                 .ops = &i9xx_always_on_power_well_ops,
5998         },
5999         {
6000                 .name = "display",
6001                 .domains = VLV_DISPLAY_POWER_DOMAINS,
6002                 .data = PUNIT_POWER_WELL_DISP2D,
6003                 .ops = &vlv_display_power_well_ops,
6004         },
6005         {
6006                 .name = "dpio-common",
6007                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6008                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6009                 .ops = &vlv_dpio_power_well_ops,
6010         },
6011         {
6012                 .name = "dpio-tx-b-01",
6013                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6014                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6015                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6016                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6017                 .ops = &vlv_dpio_power_well_ops,
6018                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6019         },
6020         {
6021                 .name = "dpio-tx-b-23",
6022                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6023                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6024                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6025                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6026                 .ops = &vlv_dpio_power_well_ops,
6027                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6028         },
6029         {
6030                 .name = "dpio-tx-c-01",
6031                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6032                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6033                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6034                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6035                 .ops = &vlv_dpio_power_well_ops,
6036                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6037         },
6038         {
6039                 .name = "dpio-tx-c-23",
6040                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6041                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6042                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6043                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6044                 .ops = &vlv_dpio_power_well_ops,
6045                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6046         },
6047 };
6048
6049 #define set_power_wells(power_domains, __power_wells) ({                \
6050         (power_domains)->power_wells = (__power_wells);                 \
6051         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
6052 })
6053
6054 int intel_power_domains_init(struct drm_i915_private *dev_priv)
6055 {
6056         struct i915_power_domains *power_domains = &dev_priv->power_domains;
6057
6058         mutex_init(&power_domains->lock);
6059
6060         /*
6061          * The enabling order will be from lower to higher indexed wells,
6062          * the disabling order is reversed.
6063          */
6064         if (IS_HASWELL(dev_priv->dev)) {
6065                 set_power_wells(power_domains, hsw_power_wells);
6066                 hsw_pwr = power_domains;
6067         } else if (IS_BROADWELL(dev_priv->dev)) {
6068                 set_power_wells(power_domains, bdw_power_wells);
6069                 hsw_pwr = power_domains;
6070         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6071                 set_power_wells(power_domains, vlv_power_wells);
6072         } else {
6073                 set_power_wells(power_domains, i9xx_always_on_power_well);
6074         }
6075
6076         return 0;
6077 }
6078
6079 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
6080 {
6081         hsw_pwr = NULL;
6082 }
6083
6084 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
6085 {
6086         struct i915_power_domains *power_domains = &dev_priv->power_domains;
6087         struct i915_power_well *power_well;
6088         int i;
6089
6090         mutex_lock(&power_domains->lock);
6091         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
6092                 power_well->ops->sync_hw(dev_priv, power_well);
6093         mutex_unlock(&power_domains->lock);
6094 }
6095
6096 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
6097 {
6098         struct i915_power_domains *power_domains = &dev_priv->power_domains;
6099
6100         power_domains->initializing = true;
6101         /* For now, we need the power well to be always enabled. */
6102         intel_display_set_init_power(dev_priv, true);
6103         intel_power_domains_resume(dev_priv);
6104         power_domains->initializing = false;
6105 }
6106
6107 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6108 {
6109         intel_runtime_pm_get(dev_priv);
6110 }
6111
6112 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6113 {
6114         intel_runtime_pm_put(dev_priv);
6115 }
6116
6117 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6118 {
6119         struct drm_device *dev = dev_priv->dev;
6120         struct device *device = &dev->pdev->dev;
6121
6122         if (!HAS_RUNTIME_PM(dev))
6123                 return;
6124
6125         pm_runtime_get_sync(device);
6126         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6127 }
6128
6129 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6130 {
6131         struct drm_device *dev = dev_priv->dev;
6132         struct device *device = &dev->pdev->dev;
6133
6134         if (!HAS_RUNTIME_PM(dev))
6135                 return;
6136
6137         WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6138         pm_runtime_get_noresume(device);
6139 }
6140
6141 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6142 {
6143         struct drm_device *dev = dev_priv->dev;
6144         struct device *device = &dev->pdev->dev;
6145
6146         if (!HAS_RUNTIME_PM(dev))
6147                 return;
6148
6149         pm_runtime_mark_last_busy(device);
6150         pm_runtime_put_autosuspend(device);
6151 }
6152
6153 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6154 {
6155         struct drm_device *dev = dev_priv->dev;
6156         struct device *device = &dev->pdev->dev;
6157
6158         if (!HAS_RUNTIME_PM(dev))
6159                 return;
6160
6161         pm_runtime_set_active(device);
6162
6163         /*
6164          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6165          * requirement.
6166          */
6167         if (!intel_enable_rc6(dev)) {
6168                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6169                 return;
6170         }
6171
6172         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6173         pm_runtime_mark_last_busy(device);
6174         pm_runtime_use_autosuspend(device);
6175
6176         pm_runtime_put_autosuspend(device);
6177 }
6178
6179 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6180 {
6181         struct drm_device *dev = dev_priv->dev;
6182         struct device *device = &dev->pdev->dev;
6183
6184         if (!HAS_RUNTIME_PM(dev))
6185                 return;
6186
6187         if (!intel_enable_rc6(dev))
6188                 return;
6189
6190         /* Make sure we're not suspended first. */
6191         pm_runtime_get_sync(device);
6192         pm_runtime_disable(device);
6193 }
6194
6195 /* Set up chip specific power management-related functions */
6196 void intel_init_pm(struct drm_device *dev)
6197 {
6198         struct drm_i915_private *dev_priv = dev->dev_private;
6199
6200         if (HAS_FBC(dev)) {
6201                 if (INTEL_INFO(dev)->gen >= 7) {
6202                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6203                         dev_priv->display.enable_fbc = gen7_enable_fbc;
6204                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6205                 } else if (INTEL_INFO(dev)->gen >= 5) {
6206                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6207                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
6208                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6209                 } else if (IS_GM45(dev)) {
6210                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6211                         dev_priv->display.enable_fbc = g4x_enable_fbc;
6212                         dev_priv->display.disable_fbc = g4x_disable_fbc;
6213                 } else {
6214                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6215                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
6216                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
6217
6218                         /* This value was pulled out of someone's hat */
6219                         I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6220                 }
6221         }
6222
6223         /* For cxsr */
6224         if (IS_PINEVIEW(dev))
6225                 i915_pineview_get_mem_freq(dev);
6226         else if (IS_GEN5(dev))
6227                 i915_ironlake_get_mem_freq(dev);
6228
6229         /* For FIFO watermark updates */
6230         if (HAS_PCH_SPLIT(dev)) {
6231                 ilk_setup_wm_latency(dev);
6232
6233                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6234                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6235                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6236                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6237                         dev_priv->display.update_wm = ilk_update_wm;
6238                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6239                 } else {
6240                         DRM_DEBUG_KMS("Failed to read display plane latency. "
6241                                       "Disable CxSR\n");
6242                 }
6243
6244                 if (IS_GEN5(dev))
6245                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6246                 else if (IS_GEN6(dev))
6247                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6248                 else if (IS_IVYBRIDGE(dev))
6249                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6250                 else if (IS_HASWELL(dev))
6251                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6252                 else if (INTEL_INFO(dev)->gen == 8)
6253                         dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6254         } else if (IS_VALLEYVIEW(dev)) {
6255                 dev_priv->display.update_wm = valleyview_update_wm;
6256                 dev_priv->display.init_clock_gating =
6257                         valleyview_init_clock_gating;
6258         } else if (IS_PINEVIEW(dev)) {
6259                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6260                                             dev_priv->is_ddr3,
6261                                             dev_priv->fsb_freq,
6262                                             dev_priv->mem_freq)) {
6263                         DRM_INFO("failed to find known CxSR latency "
6264                                  "(found ddr%s fsb freq %d, mem freq %d), "
6265                                  "disabling CxSR\n",
6266                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
6267                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6268                         /* Disable CxSR and never update its watermark again */
6269                         pineview_disable_cxsr(dev);
6270                         dev_priv->display.update_wm = NULL;
6271                 } else
6272                         dev_priv->display.update_wm = pineview_update_wm;
6273                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6274         } else if (IS_G4X(dev)) {
6275                 dev_priv->display.update_wm = g4x_update_wm;
6276                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6277         } else if (IS_GEN4(dev)) {
6278                 dev_priv->display.update_wm = i965_update_wm;
6279                 if (IS_CRESTLINE(dev))
6280                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6281                 else if (IS_BROADWATER(dev))
6282                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6283         } else if (IS_GEN3(dev)) {
6284                 dev_priv->display.update_wm = i9xx_update_wm;
6285                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6286                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6287         } else if (IS_GEN2(dev)) {
6288                 if (INTEL_INFO(dev)->num_pipes == 1) {
6289                         dev_priv->display.update_wm = i845_update_wm;
6290                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6291                 } else {
6292                         dev_priv->display.update_wm = i9xx_update_wm;
6293                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6294                 }
6295
6296                 if (IS_I85X(dev) || IS_I865G(dev))
6297                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6298                 else
6299                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
6300         } else {
6301                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6302         }
6303 }
6304
6305 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6306 {
6307         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6308
6309         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6310                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6311                 return -EAGAIN;
6312         }
6313
6314         I915_WRITE(GEN6_PCODE_DATA, *val);
6315         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6316
6317         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6318                      500)) {
6319                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6320                 return -ETIMEDOUT;
6321         }
6322
6323         *val = I915_READ(GEN6_PCODE_DATA);
6324         I915_WRITE(GEN6_PCODE_DATA, 0);
6325
6326         return 0;
6327 }
6328
6329 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6330 {
6331         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6332
6333         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6334                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6335                 return -EAGAIN;
6336         }
6337
6338         I915_WRITE(GEN6_PCODE_DATA, val);
6339         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6340
6341         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6342                      500)) {
6343                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6344                 return -ETIMEDOUT;
6345         }
6346
6347         I915_WRITE(GEN6_PCODE_DATA, 0);
6348
6349         return 0;
6350 }
6351
6352 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6353 {
6354         int div;
6355
6356         /* 4 x czclk */
6357         switch (dev_priv->mem_freq) {
6358         case 800:
6359                 div = 10;
6360                 break;
6361         case 1066:
6362                 div = 12;
6363                 break;
6364         case 1333:
6365                 div = 16;
6366                 break;
6367         default:
6368                 return -1;
6369         }
6370
6371         return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6372 }
6373
6374 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6375 {
6376         int mul;
6377
6378         /* 4 x czclk */
6379         switch (dev_priv->mem_freq) {
6380         case 800:
6381                 mul = 10;
6382                 break;
6383         case 1066:
6384                 mul = 12;
6385                 break;
6386         case 1333:
6387                 mul = 16;
6388                 break;
6389         default:
6390                 return -1;
6391         }
6392
6393         return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6394 }
6395
6396 void intel_pm_setup(struct drm_device *dev)
6397 {
6398         struct drm_i915_private *dev_priv = dev->dev_private;
6399
6400         mutex_init(&dev_priv->rps.hw_lock);
6401
6402         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6403                           intel_gen6_powersave_work);
6404
6405         dev_priv->pm.suspended = false;
6406         dev_priv->pm.irqs_disabled = false;
6407 }