2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
51 #define INTEL_RC6_ENABLE (1<<0)
52 #define INTEL_RC6p_ENABLE (1<<1)
53 #define INTEL_RC6pp_ENABLE (1<<2)
55 static void gen9_init_clock_gating(struct drm_device *dev)
57 struct drm_i915_private *dev_priv = dev->dev_private;
59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
63 /* WaDisableKillLogic:bxt,skl */
64 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
68 static void skl_init_clock_gating(struct drm_device *dev)
70 struct drm_i915_private *dev_priv = dev->dev_private;
72 gen9_init_clock_gating(dev);
74 if (INTEL_REVID(dev) <= SKL_REVID_B0) {
76 * WaDisableSDEUnitClockGating:skl
77 * WaSetGAPSunitClckGateDisable:skl
79 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
80 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
81 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
83 /* WaDisableVFUnitClockGating:skl */
84 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
85 GEN6_VFUNIT_CLOCK_GATE_DISABLE);
88 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
89 /* WaDisableHDCInvalidation:skl */
90 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
91 BDW_DISABLE_HDC_INVALIDATION);
93 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
94 I915_WRITE(FF_SLICE_CS_CHICKEN2,
95 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
98 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
99 * involving this register should also be added to WA batch as required.
101 if (INTEL_REVID(dev) <= SKL_REVID_E0)
102 /* WaDisableLSQCROPERFforOCL:skl */
103 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
104 GEN8_LQSC_RO_PERF_DIS);
106 /* WaEnableGapsTsvCreditFix:skl */
107 if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
108 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
109 GEN9_GAPS_TSV_CREDIT_DISABLE));
113 static void bxt_init_clock_gating(struct drm_device *dev)
115 struct drm_i915_private *dev_priv = dev->dev_private;
117 gen9_init_clock_gating(dev);
119 /* WaDisableSDEUnitClockGating:bxt */
120 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
121 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
125 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
127 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
128 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
130 if (INTEL_REVID(dev) == BXT_REVID_A0) {
132 * Hardware specification requires this bit to be
135 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
139 static void i915_pineview_get_mem_freq(struct drm_device *dev)
141 struct drm_i915_private *dev_priv = dev->dev_private;
144 tmp = I915_READ(CLKCFG);
146 switch (tmp & CLKCFG_FSB_MASK) {
148 dev_priv->fsb_freq = 533; /* 133*4 */
151 dev_priv->fsb_freq = 800; /* 200*4 */
154 dev_priv->fsb_freq = 667; /* 167*4 */
157 dev_priv->fsb_freq = 400; /* 100*4 */
161 switch (tmp & CLKCFG_MEM_MASK) {
163 dev_priv->mem_freq = 533;
166 dev_priv->mem_freq = 667;
169 dev_priv->mem_freq = 800;
173 /* detect pineview DDR3 setting */
174 tmp = I915_READ(CSHRDDR3CTL);
175 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
178 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
180 struct drm_i915_private *dev_priv = dev->dev_private;
183 ddrpll = I915_READ16(DDRMPLL1);
184 csipll = I915_READ16(CSIPLL0);
186 switch (ddrpll & 0xff) {
188 dev_priv->mem_freq = 800;
191 dev_priv->mem_freq = 1066;
194 dev_priv->mem_freq = 1333;
197 dev_priv->mem_freq = 1600;
200 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
202 dev_priv->mem_freq = 0;
206 dev_priv->ips.r_t = dev_priv->mem_freq;
208 switch (csipll & 0x3ff) {
210 dev_priv->fsb_freq = 3200;
213 dev_priv->fsb_freq = 3733;
216 dev_priv->fsb_freq = 4266;
219 dev_priv->fsb_freq = 4800;
222 dev_priv->fsb_freq = 5333;
225 dev_priv->fsb_freq = 5866;
228 dev_priv->fsb_freq = 6400;
231 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
233 dev_priv->fsb_freq = 0;
237 if (dev_priv->fsb_freq == 3200) {
238 dev_priv->ips.c_m = 0;
239 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
240 dev_priv->ips.c_m = 1;
242 dev_priv->ips.c_m = 2;
246 static const struct cxsr_latency cxsr_latency_table[] = {
247 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
248 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
249 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
250 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
251 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
253 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
254 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
255 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
256 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
257 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
259 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
260 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
261 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
262 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
263 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
265 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
266 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
267 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
268 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
269 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
271 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
272 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
273 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
274 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
275 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
277 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
278 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
279 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
280 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
281 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
284 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
289 const struct cxsr_latency *latency;
292 if (fsb == 0 || mem == 0)
295 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
296 latency = &cxsr_latency_table[i];
297 if (is_desktop == latency->is_desktop &&
298 is_ddr3 == latency->is_ddr3 &&
299 fsb == latency->fsb_freq && mem == latency->mem_freq)
303 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
308 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
312 mutex_lock(&dev_priv->rps.hw_lock);
314 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
316 val &= ~FORCE_DDR_HIGH_FREQ;
318 val |= FORCE_DDR_HIGH_FREQ;
319 val &= ~FORCE_DDR_LOW_FREQ;
320 val |= FORCE_DDR_FREQ_REQ_ACK;
321 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
323 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
324 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
325 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
327 mutex_unlock(&dev_priv->rps.hw_lock);
330 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
334 mutex_lock(&dev_priv->rps.hw_lock);
336 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
338 val |= DSP_MAXFIFO_PM5_ENABLE;
340 val &= ~DSP_MAXFIFO_PM5_ENABLE;
341 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
343 mutex_unlock(&dev_priv->rps.hw_lock);
346 #define FW_WM(value, plane) \
347 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
349 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
351 struct drm_device *dev = dev_priv->dev;
354 if (IS_VALLEYVIEW(dev)) {
355 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
356 POSTING_READ(FW_BLC_SELF_VLV);
357 dev_priv->wm.vlv.cxsr = enable;
358 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
359 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
360 POSTING_READ(FW_BLC_SELF);
361 } else if (IS_PINEVIEW(dev)) {
362 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
363 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
364 I915_WRITE(DSPFW3, val);
365 POSTING_READ(DSPFW3);
366 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
367 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
368 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
369 I915_WRITE(FW_BLC_SELF, val);
370 POSTING_READ(FW_BLC_SELF);
371 } else if (IS_I915GM(dev)) {
372 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
373 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
374 I915_WRITE(INSTPM, val);
375 POSTING_READ(INSTPM);
380 DRM_DEBUG_KMS("memory self-refresh is %s\n",
381 enable ? "enabled" : "disabled");
386 * Latency for FIFO fetches is dependent on several factors:
387 * - memory configuration (speed, channels)
389 * - current MCH state
390 * It can be fairly high in some situations, so here we assume a fairly
391 * pessimal value. It's a tradeoff between extra memory fetches (if we
392 * set this value too high, the FIFO will fetch frequently to stay full)
393 * and power consumption (set it too low to save power and we might see
394 * FIFO underruns and display "flicker").
396 * A value of 5us seems to be a good balance; safe for very low end
397 * platforms but not overly aggressive on lower latency configs.
399 static const int pessimal_latency_ns = 5000;
401 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
402 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
404 static int vlv_get_fifo_size(struct drm_device *dev,
405 enum pipe pipe, int plane)
407 struct drm_i915_private *dev_priv = dev->dev_private;
408 int sprite0_start, sprite1_start, size;
411 uint32_t dsparb, dsparb2, dsparb3;
413 dsparb = I915_READ(DSPARB);
414 dsparb2 = I915_READ(DSPARB2);
415 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
416 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
419 dsparb = I915_READ(DSPARB);
420 dsparb2 = I915_READ(DSPARB2);
421 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
422 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
425 dsparb2 = I915_READ(DSPARB2);
426 dsparb3 = I915_READ(DSPARB3);
427 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
428 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
436 size = sprite0_start;
439 size = sprite1_start - sprite0_start;
442 size = 512 - 1 - sprite1_start;
448 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
449 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
450 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
456 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
458 struct drm_i915_private *dev_priv = dev->dev_private;
459 uint32_t dsparb = I915_READ(DSPARB);
462 size = dsparb & 0x7f;
464 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
466 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
467 plane ? "B" : "A", size);
472 static int i830_get_fifo_size(struct drm_device *dev, int plane)
474 struct drm_i915_private *dev_priv = dev->dev_private;
475 uint32_t dsparb = I915_READ(DSPARB);
478 size = dsparb & 0x1ff;
480 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
481 size >>= 1; /* Convert to cachelines */
483 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
484 plane ? "B" : "A", size);
489 static int i845_get_fifo_size(struct drm_device *dev, int plane)
491 struct drm_i915_private *dev_priv = dev->dev_private;
492 uint32_t dsparb = I915_READ(DSPARB);
495 size = dsparb & 0x7f;
496 size >>= 2; /* Convert to cachelines */
498 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
505 /* Pineview has different values for various configs */
506 static const struct intel_watermark_params pineview_display_wm = {
507 .fifo_size = PINEVIEW_DISPLAY_FIFO,
508 .max_wm = PINEVIEW_MAX_WM,
509 .default_wm = PINEVIEW_DFT_WM,
510 .guard_size = PINEVIEW_GUARD_WM,
511 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
513 static const struct intel_watermark_params pineview_display_hplloff_wm = {
514 .fifo_size = PINEVIEW_DISPLAY_FIFO,
515 .max_wm = PINEVIEW_MAX_WM,
516 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
517 .guard_size = PINEVIEW_GUARD_WM,
518 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
520 static const struct intel_watermark_params pineview_cursor_wm = {
521 .fifo_size = PINEVIEW_CURSOR_FIFO,
522 .max_wm = PINEVIEW_CURSOR_MAX_WM,
523 .default_wm = PINEVIEW_CURSOR_DFT_WM,
524 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
525 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
527 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
528 .fifo_size = PINEVIEW_CURSOR_FIFO,
529 .max_wm = PINEVIEW_CURSOR_MAX_WM,
530 .default_wm = PINEVIEW_CURSOR_DFT_WM,
531 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
532 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
534 static const struct intel_watermark_params g4x_wm_info = {
535 .fifo_size = G4X_FIFO_SIZE,
536 .max_wm = G4X_MAX_WM,
537 .default_wm = G4X_MAX_WM,
539 .cacheline_size = G4X_FIFO_LINE_SIZE,
541 static const struct intel_watermark_params g4x_cursor_wm_info = {
542 .fifo_size = I965_CURSOR_FIFO,
543 .max_wm = I965_CURSOR_MAX_WM,
544 .default_wm = I965_CURSOR_DFT_WM,
546 .cacheline_size = G4X_FIFO_LINE_SIZE,
548 static const struct intel_watermark_params valleyview_wm_info = {
549 .fifo_size = VALLEYVIEW_FIFO_SIZE,
550 .max_wm = VALLEYVIEW_MAX_WM,
551 .default_wm = VALLEYVIEW_MAX_WM,
553 .cacheline_size = G4X_FIFO_LINE_SIZE,
555 static const struct intel_watermark_params valleyview_cursor_wm_info = {
556 .fifo_size = I965_CURSOR_FIFO,
557 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
558 .default_wm = I965_CURSOR_DFT_WM,
560 .cacheline_size = G4X_FIFO_LINE_SIZE,
562 static const struct intel_watermark_params i965_cursor_wm_info = {
563 .fifo_size = I965_CURSOR_FIFO,
564 .max_wm = I965_CURSOR_MAX_WM,
565 .default_wm = I965_CURSOR_DFT_WM,
567 .cacheline_size = I915_FIFO_LINE_SIZE,
569 static const struct intel_watermark_params i945_wm_info = {
570 .fifo_size = I945_FIFO_SIZE,
571 .max_wm = I915_MAX_WM,
574 .cacheline_size = I915_FIFO_LINE_SIZE,
576 static const struct intel_watermark_params i915_wm_info = {
577 .fifo_size = I915_FIFO_SIZE,
578 .max_wm = I915_MAX_WM,
581 .cacheline_size = I915_FIFO_LINE_SIZE,
583 static const struct intel_watermark_params i830_a_wm_info = {
584 .fifo_size = I855GM_FIFO_SIZE,
585 .max_wm = I915_MAX_WM,
588 .cacheline_size = I830_FIFO_LINE_SIZE,
590 static const struct intel_watermark_params i830_bc_wm_info = {
591 .fifo_size = I855GM_FIFO_SIZE,
592 .max_wm = I915_MAX_WM/2,
595 .cacheline_size = I830_FIFO_LINE_SIZE,
597 static const struct intel_watermark_params i845_wm_info = {
598 .fifo_size = I830_FIFO_SIZE,
599 .max_wm = I915_MAX_WM,
602 .cacheline_size = I830_FIFO_LINE_SIZE,
606 * intel_calculate_wm - calculate watermark level
607 * @clock_in_khz: pixel clock
608 * @wm: chip FIFO params
609 * @pixel_size: display pixel size
610 * @latency_ns: memory latency for the platform
612 * Calculate the watermark level (the level at which the display plane will
613 * start fetching from memory again). Each chip has a different display
614 * FIFO size and allocation, so the caller needs to figure that out and pass
615 * in the correct intel_watermark_params structure.
617 * As the pixel clock runs, the FIFO will be drained at a rate that depends
618 * on the pixel size. When it reaches the watermark level, it'll start
619 * fetching FIFO line sized based chunks from memory until the FIFO fills
620 * past the watermark point. If the FIFO drains completely, a FIFO underrun
621 * will occur, and a display engine hang could result.
623 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
624 const struct intel_watermark_params *wm,
627 unsigned long latency_ns)
629 long entries_required, wm_size;
632 * Note: we need to make sure we don't overflow for various clock &
634 * clocks go from a few thousand to several hundred thousand.
635 * latency is usually a few thousand
637 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
639 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
641 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
643 wm_size = fifo_size - (entries_required + wm->guard_size);
645 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
647 /* Don't promote wm_size to unsigned... */
648 if (wm_size > (long)wm->max_wm)
649 wm_size = wm->max_wm;
651 wm_size = wm->default_wm;
654 * Bspec seems to indicate that the value shouldn't be lower than
655 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
656 * Lets go for 8 which is the burst size since certain platforms
657 * already use a hardcoded 8 (which is what the spec says should be
666 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
668 struct drm_crtc *crtc, *enabled = NULL;
670 for_each_crtc(dev, crtc) {
671 if (intel_crtc_active(crtc)) {
681 static void pineview_update_wm(struct drm_crtc *unused_crtc)
683 struct drm_device *dev = unused_crtc->dev;
684 struct drm_i915_private *dev_priv = dev->dev_private;
685 struct drm_crtc *crtc;
686 const struct cxsr_latency *latency;
690 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
691 dev_priv->fsb_freq, dev_priv->mem_freq);
693 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
694 intel_set_memory_cxsr(dev_priv, false);
698 crtc = single_enabled_crtc(dev);
700 const struct drm_display_mode *adjusted_mode;
701 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
704 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
705 clock = adjusted_mode->crtc_clock;
708 wm = intel_calculate_wm(clock, &pineview_display_wm,
709 pineview_display_wm.fifo_size,
710 pixel_size, latency->display_sr);
711 reg = I915_READ(DSPFW1);
712 reg &= ~DSPFW_SR_MASK;
713 reg |= FW_WM(wm, SR);
714 I915_WRITE(DSPFW1, reg);
715 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
718 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
719 pineview_display_wm.fifo_size,
720 pixel_size, latency->cursor_sr);
721 reg = I915_READ(DSPFW3);
722 reg &= ~DSPFW_CURSOR_SR_MASK;
723 reg |= FW_WM(wm, CURSOR_SR);
724 I915_WRITE(DSPFW3, reg);
726 /* Display HPLL off SR */
727 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
728 pineview_display_hplloff_wm.fifo_size,
729 pixel_size, latency->display_hpll_disable);
730 reg = I915_READ(DSPFW3);
731 reg &= ~DSPFW_HPLL_SR_MASK;
732 reg |= FW_WM(wm, HPLL_SR);
733 I915_WRITE(DSPFW3, reg);
735 /* cursor HPLL off SR */
736 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
737 pineview_display_hplloff_wm.fifo_size,
738 pixel_size, latency->cursor_hpll_disable);
739 reg = I915_READ(DSPFW3);
740 reg &= ~DSPFW_HPLL_CURSOR_MASK;
741 reg |= FW_WM(wm, HPLL_CURSOR);
742 I915_WRITE(DSPFW3, reg);
743 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
745 intel_set_memory_cxsr(dev_priv, true);
747 intel_set_memory_cxsr(dev_priv, false);
751 static bool g4x_compute_wm0(struct drm_device *dev,
753 const struct intel_watermark_params *display,
754 int display_latency_ns,
755 const struct intel_watermark_params *cursor,
756 int cursor_latency_ns,
760 struct drm_crtc *crtc;
761 const struct drm_display_mode *adjusted_mode;
762 int htotal, hdisplay, clock, pixel_size;
763 int line_time_us, line_count;
764 int entries, tlb_miss;
766 crtc = intel_get_crtc_for_plane(dev, plane);
767 if (!intel_crtc_active(crtc)) {
768 *cursor_wm = cursor->guard_size;
769 *plane_wm = display->guard_size;
773 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
774 clock = adjusted_mode->crtc_clock;
775 htotal = adjusted_mode->crtc_htotal;
776 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
777 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
779 /* Use the small buffer method to calculate plane watermark */
780 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
781 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
784 entries = DIV_ROUND_UP(entries, display->cacheline_size);
785 *plane_wm = entries + display->guard_size;
786 if (*plane_wm > (int)display->max_wm)
787 *plane_wm = display->max_wm;
789 /* Use the large buffer method to calculate cursor watermark */
790 line_time_us = max(htotal * 1000 / clock, 1);
791 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
792 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
793 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
796 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
797 *cursor_wm = entries + cursor->guard_size;
798 if (*cursor_wm > (int)cursor->max_wm)
799 *cursor_wm = (int)cursor->max_wm;
805 * Check the wm result.
807 * If any calculated watermark values is larger than the maximum value that
808 * can be programmed into the associated watermark register, that watermark
811 static bool g4x_check_srwm(struct drm_device *dev,
812 int display_wm, int cursor_wm,
813 const struct intel_watermark_params *display,
814 const struct intel_watermark_params *cursor)
816 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
817 display_wm, cursor_wm);
819 if (display_wm > display->max_wm) {
820 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
821 display_wm, display->max_wm);
825 if (cursor_wm > cursor->max_wm) {
826 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
827 cursor_wm, cursor->max_wm);
831 if (!(display_wm || cursor_wm)) {
832 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
839 static bool g4x_compute_srwm(struct drm_device *dev,
842 const struct intel_watermark_params *display,
843 const struct intel_watermark_params *cursor,
844 int *display_wm, int *cursor_wm)
846 struct drm_crtc *crtc;
847 const struct drm_display_mode *adjusted_mode;
848 int hdisplay, htotal, pixel_size, clock;
849 unsigned long line_time_us;
850 int line_count, line_size;
855 *display_wm = *cursor_wm = 0;
859 crtc = intel_get_crtc_for_plane(dev, plane);
860 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
861 clock = adjusted_mode->crtc_clock;
862 htotal = adjusted_mode->crtc_htotal;
863 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
864 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
866 line_time_us = max(htotal * 1000 / clock, 1);
867 line_count = (latency_ns / line_time_us + 1000) / 1000;
868 line_size = hdisplay * pixel_size;
870 /* Use the minimum of the small and large buffer method for primary */
871 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
872 large = line_count * line_size;
874 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
875 *display_wm = entries + display->guard_size;
877 /* calculate the self-refresh watermark for display cursor */
878 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
879 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
880 *cursor_wm = entries + cursor->guard_size;
882 return g4x_check_srwm(dev,
883 *display_wm, *cursor_wm,
887 #define FW_WM_VLV(value, plane) \
888 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
890 static void vlv_write_wm_values(struct intel_crtc *crtc,
891 const struct vlv_wm_values *wm)
893 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
894 enum pipe pipe = crtc->pipe;
896 I915_WRITE(VLV_DDL(pipe),
897 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
898 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
899 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
900 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
903 FW_WM(wm->sr.plane, SR) |
904 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
905 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
906 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
908 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
909 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
910 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
912 FW_WM(wm->sr.cursor, CURSOR_SR));
914 if (IS_CHERRYVIEW(dev_priv)) {
915 I915_WRITE(DSPFW7_CHV,
916 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
917 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
918 I915_WRITE(DSPFW8_CHV,
919 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
920 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
921 I915_WRITE(DSPFW9_CHV,
922 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
923 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
925 FW_WM(wm->sr.plane >> 9, SR_HI) |
926 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
927 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
928 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
929 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
930 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
931 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
932 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
933 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
934 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
937 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
938 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
940 FW_WM(wm->sr.plane >> 9, SR_HI) |
941 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
942 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
943 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
944 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
945 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
946 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
949 /* zero (unused) WM1 watermarks */
950 I915_WRITE(DSPFW4, 0);
951 I915_WRITE(DSPFW5, 0);
952 I915_WRITE(DSPFW6, 0);
953 I915_WRITE(DSPHOWM1, 0);
955 POSTING_READ(DSPFW1);
963 VLV_WM_LEVEL_DDR_DVFS,
966 /* latency must be in 0.1us units. */
967 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
968 unsigned int pipe_htotal,
969 unsigned int horiz_pixels,
970 unsigned int bytes_per_pixel,
971 unsigned int latency)
975 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
976 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
977 ret = DIV_ROUND_UP(ret, 64);
982 static void vlv_setup_wm_latency(struct drm_device *dev)
984 struct drm_i915_private *dev_priv = dev->dev_private;
986 /* all latencies in usec */
987 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
989 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
991 if (IS_CHERRYVIEW(dev_priv)) {
992 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
993 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
995 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
999 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
1000 struct intel_crtc *crtc,
1001 const struct intel_plane_state *state,
1004 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1005 int clock, htotal, pixel_size, width, wm;
1007 if (dev_priv->wm.pri_latency[level] == 0)
1010 if (!state->visible)
1013 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1014 clock = crtc->config->base.adjusted_mode.crtc_clock;
1015 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
1016 width = crtc->config->pipe_src_w;
1017 if (WARN_ON(htotal == 0))
1020 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1022 * FIXME the formula gives values that are
1023 * too big for the cursor FIFO, and hence we
1024 * would never be able to use cursors. For
1025 * now just hardcode the watermark.
1029 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1030 dev_priv->wm.pri_latency[level] * 10);
1033 return min_t(int, wm, USHRT_MAX);
1036 static void vlv_compute_fifo(struct intel_crtc *crtc)
1038 struct drm_device *dev = crtc->base.dev;
1039 struct vlv_wm_state *wm_state = &crtc->wm_state;
1040 struct intel_plane *plane;
1041 unsigned int total_rate = 0;
1042 const int fifo_size = 512 - 1;
1043 int fifo_extra, fifo_left = fifo_size;
1045 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1046 struct intel_plane_state *state =
1047 to_intel_plane_state(plane->base.state);
1049 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1052 if (state->visible) {
1053 wm_state->num_active_planes++;
1054 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1058 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1059 struct intel_plane_state *state =
1060 to_intel_plane_state(plane->base.state);
1063 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1064 plane->wm.fifo_size = 63;
1068 if (!state->visible) {
1069 plane->wm.fifo_size = 0;
1073 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1074 plane->wm.fifo_size = fifo_size * rate / total_rate;
1075 fifo_left -= plane->wm.fifo_size;
1078 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1080 /* spread the remainder evenly */
1081 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1087 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1090 /* give it all to the first plane if none are active */
1091 if (plane->wm.fifo_size == 0 &&
1092 wm_state->num_active_planes)
1095 plane_extra = min(fifo_extra, fifo_left);
1096 plane->wm.fifo_size += plane_extra;
1097 fifo_left -= plane_extra;
1100 WARN_ON(fifo_left != 0);
1103 static void vlv_invert_wms(struct intel_crtc *crtc)
1105 struct vlv_wm_state *wm_state = &crtc->wm_state;
1108 for (level = 0; level < wm_state->num_levels; level++) {
1109 struct drm_device *dev = crtc->base.dev;
1110 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1111 struct intel_plane *plane;
1113 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1114 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1116 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1117 switch (plane->base.type) {
1119 case DRM_PLANE_TYPE_CURSOR:
1120 wm_state->wm[level].cursor = plane->wm.fifo_size -
1121 wm_state->wm[level].cursor;
1123 case DRM_PLANE_TYPE_PRIMARY:
1124 wm_state->wm[level].primary = plane->wm.fifo_size -
1125 wm_state->wm[level].primary;
1127 case DRM_PLANE_TYPE_OVERLAY:
1128 sprite = plane->plane;
1129 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1130 wm_state->wm[level].sprite[sprite];
1137 static void vlv_compute_wm(struct intel_crtc *crtc)
1139 struct drm_device *dev = crtc->base.dev;
1140 struct vlv_wm_state *wm_state = &crtc->wm_state;
1141 struct intel_plane *plane;
1142 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1145 memset(wm_state, 0, sizeof(*wm_state));
1147 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1148 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1150 wm_state->num_active_planes = 0;
1152 vlv_compute_fifo(crtc);
1154 if (wm_state->num_active_planes != 1)
1155 wm_state->cxsr = false;
1157 if (wm_state->cxsr) {
1158 for (level = 0; level < wm_state->num_levels; level++) {
1159 wm_state->sr[level].plane = sr_fifo_size;
1160 wm_state->sr[level].cursor = 63;
1164 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1165 struct intel_plane_state *state =
1166 to_intel_plane_state(plane->base.state);
1168 if (!state->visible)
1171 /* normal watermarks */
1172 for (level = 0; level < wm_state->num_levels; level++) {
1173 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1174 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1177 if (WARN_ON(level == 0 && wm > max_wm))
1180 if (wm > plane->wm.fifo_size)
1183 switch (plane->base.type) {
1185 case DRM_PLANE_TYPE_CURSOR:
1186 wm_state->wm[level].cursor = wm;
1188 case DRM_PLANE_TYPE_PRIMARY:
1189 wm_state->wm[level].primary = wm;
1191 case DRM_PLANE_TYPE_OVERLAY:
1192 sprite = plane->plane;
1193 wm_state->wm[level].sprite[sprite] = wm;
1198 wm_state->num_levels = level;
1200 if (!wm_state->cxsr)
1203 /* maxfifo watermarks */
1204 switch (plane->base.type) {
1206 case DRM_PLANE_TYPE_CURSOR:
1207 for (level = 0; level < wm_state->num_levels; level++)
1208 wm_state->sr[level].cursor =
1209 wm_state->sr[level].cursor;
1211 case DRM_PLANE_TYPE_PRIMARY:
1212 for (level = 0; level < wm_state->num_levels; level++)
1213 wm_state->sr[level].plane =
1214 min(wm_state->sr[level].plane,
1215 wm_state->wm[level].primary);
1217 case DRM_PLANE_TYPE_OVERLAY:
1218 sprite = plane->plane;
1219 for (level = 0; level < wm_state->num_levels; level++)
1220 wm_state->sr[level].plane =
1221 min(wm_state->sr[level].plane,
1222 wm_state->wm[level].sprite[sprite]);
1227 /* clear any (partially) filled invalid levels */
1228 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1229 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1230 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1233 vlv_invert_wms(crtc);
1236 #define VLV_FIFO(plane, value) \
1237 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1239 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1241 struct drm_device *dev = crtc->base.dev;
1242 struct drm_i915_private *dev_priv = to_i915(dev);
1243 struct intel_plane *plane;
1244 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1246 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1247 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1248 WARN_ON(plane->wm.fifo_size != 63);
1252 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1253 sprite0_start = plane->wm.fifo_size;
1254 else if (plane->plane == 0)
1255 sprite1_start = sprite0_start + plane->wm.fifo_size;
1257 fifo_size = sprite1_start + plane->wm.fifo_size;
1260 WARN_ON(fifo_size != 512 - 1);
1262 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1263 pipe_name(crtc->pipe), sprite0_start,
1264 sprite1_start, fifo_size);
1266 switch (crtc->pipe) {
1267 uint32_t dsparb, dsparb2, dsparb3;
1269 dsparb = I915_READ(DSPARB);
1270 dsparb2 = I915_READ(DSPARB2);
1272 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1273 VLV_FIFO(SPRITEB, 0xff));
1274 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1275 VLV_FIFO(SPRITEB, sprite1_start));
1277 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1278 VLV_FIFO(SPRITEB_HI, 0x1));
1279 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1280 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1282 I915_WRITE(DSPARB, dsparb);
1283 I915_WRITE(DSPARB2, dsparb2);
1286 dsparb = I915_READ(DSPARB);
1287 dsparb2 = I915_READ(DSPARB2);
1289 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1290 VLV_FIFO(SPRITED, 0xff));
1291 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1292 VLV_FIFO(SPRITED, sprite1_start));
1294 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1295 VLV_FIFO(SPRITED_HI, 0xff));
1296 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1297 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1299 I915_WRITE(DSPARB, dsparb);
1300 I915_WRITE(DSPARB2, dsparb2);
1303 dsparb3 = I915_READ(DSPARB3);
1304 dsparb2 = I915_READ(DSPARB2);
1306 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1307 VLV_FIFO(SPRITEF, 0xff));
1308 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1309 VLV_FIFO(SPRITEF, sprite1_start));
1311 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1312 VLV_FIFO(SPRITEF_HI, 0xff));
1313 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1314 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1316 I915_WRITE(DSPARB3, dsparb3);
1317 I915_WRITE(DSPARB2, dsparb2);
1326 static void vlv_merge_wm(struct drm_device *dev,
1327 struct vlv_wm_values *wm)
1329 struct intel_crtc *crtc;
1330 int num_active_crtcs = 0;
1332 wm->level = to_i915(dev)->wm.max_level;
1335 for_each_intel_crtc(dev, crtc) {
1336 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1341 if (!wm_state->cxsr)
1345 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1348 if (num_active_crtcs != 1)
1351 if (num_active_crtcs > 1)
1352 wm->level = VLV_WM_LEVEL_PM2;
1354 for_each_intel_crtc(dev, crtc) {
1355 struct vlv_wm_state *wm_state = &crtc->wm_state;
1356 enum pipe pipe = crtc->pipe;
1361 wm->pipe[pipe] = wm_state->wm[wm->level];
1363 wm->sr = wm_state->sr[wm->level];
1365 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1366 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1367 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1368 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1372 static void vlv_update_wm(struct drm_crtc *crtc)
1374 struct drm_device *dev = crtc->dev;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1377 enum pipe pipe = intel_crtc->pipe;
1378 struct vlv_wm_values wm = {};
1380 vlv_compute_wm(intel_crtc);
1381 vlv_merge_wm(dev, &wm);
1383 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1384 /* FIXME should be part of crtc atomic commit */
1385 vlv_pipe_set_fifo_size(intel_crtc);
1389 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1390 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1391 chv_set_memory_dvfs(dev_priv, false);
1393 if (wm.level < VLV_WM_LEVEL_PM5 &&
1394 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1395 chv_set_memory_pm5(dev_priv, false);
1397 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1398 intel_set_memory_cxsr(dev_priv, false);
1400 /* FIXME should be part of crtc atomic commit */
1401 vlv_pipe_set_fifo_size(intel_crtc);
1403 vlv_write_wm_values(intel_crtc, &wm);
1405 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1406 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1407 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1408 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1409 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1411 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1412 intel_set_memory_cxsr(dev_priv, true);
1414 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1415 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1416 chv_set_memory_pm5(dev_priv, true);
1418 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1419 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1420 chv_set_memory_dvfs(dev_priv, true);
1422 dev_priv->wm.vlv = wm;
1425 #define single_plane_enabled(mask) is_power_of_2(mask)
1427 static void g4x_update_wm(struct drm_crtc *crtc)
1429 struct drm_device *dev = crtc->dev;
1430 static const int sr_latency_ns = 12000;
1431 struct drm_i915_private *dev_priv = dev->dev_private;
1432 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1433 int plane_sr, cursor_sr;
1434 unsigned int enabled = 0;
1437 if (g4x_compute_wm0(dev, PIPE_A,
1438 &g4x_wm_info, pessimal_latency_ns,
1439 &g4x_cursor_wm_info, pessimal_latency_ns,
1440 &planea_wm, &cursora_wm))
1441 enabled |= 1 << PIPE_A;
1443 if (g4x_compute_wm0(dev, PIPE_B,
1444 &g4x_wm_info, pessimal_latency_ns,
1445 &g4x_cursor_wm_info, pessimal_latency_ns,
1446 &planeb_wm, &cursorb_wm))
1447 enabled |= 1 << PIPE_B;
1449 if (single_plane_enabled(enabled) &&
1450 g4x_compute_srwm(dev, ffs(enabled) - 1,
1453 &g4x_cursor_wm_info,
1454 &plane_sr, &cursor_sr)) {
1455 cxsr_enabled = true;
1457 cxsr_enabled = false;
1458 intel_set_memory_cxsr(dev_priv, false);
1459 plane_sr = cursor_sr = 0;
1462 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1463 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1464 planea_wm, cursora_wm,
1465 planeb_wm, cursorb_wm,
1466 plane_sr, cursor_sr);
1469 FW_WM(plane_sr, SR) |
1470 FW_WM(cursorb_wm, CURSORB) |
1471 FW_WM(planeb_wm, PLANEB) |
1472 FW_WM(planea_wm, PLANEA));
1474 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1475 FW_WM(cursora_wm, CURSORA));
1476 /* HPLL off in SR has some issues on G4x... disable it */
1478 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1479 FW_WM(cursor_sr, CURSOR_SR));
1482 intel_set_memory_cxsr(dev_priv, true);
1485 static void i965_update_wm(struct drm_crtc *unused_crtc)
1487 struct drm_device *dev = unused_crtc->dev;
1488 struct drm_i915_private *dev_priv = dev->dev_private;
1489 struct drm_crtc *crtc;
1494 /* Calc sr entries for one plane configs */
1495 crtc = single_enabled_crtc(dev);
1497 /* self-refresh has much higher latency */
1498 static const int sr_latency_ns = 12000;
1499 const struct drm_display_mode *adjusted_mode =
1500 &to_intel_crtc(crtc)->config->base.adjusted_mode;
1501 int clock = adjusted_mode->crtc_clock;
1502 int htotal = adjusted_mode->crtc_htotal;
1503 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1504 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1505 unsigned long line_time_us;
1508 line_time_us = max(htotal * 1000 / clock, 1);
1510 /* Use ns/us then divide to preserve precision */
1511 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1512 pixel_size * hdisplay;
1513 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1514 srwm = I965_FIFO_SIZE - entries;
1518 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1521 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1522 pixel_size * crtc->cursor->state->crtc_w;
1523 entries = DIV_ROUND_UP(entries,
1524 i965_cursor_wm_info.cacheline_size);
1525 cursor_sr = i965_cursor_wm_info.fifo_size -
1526 (entries + i965_cursor_wm_info.guard_size);
1528 if (cursor_sr > i965_cursor_wm_info.max_wm)
1529 cursor_sr = i965_cursor_wm_info.max_wm;
1531 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1532 "cursor %d\n", srwm, cursor_sr);
1534 cxsr_enabled = true;
1536 cxsr_enabled = false;
1537 /* Turn off self refresh if both pipes are enabled */
1538 intel_set_memory_cxsr(dev_priv, false);
1541 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1544 /* 965 has limitations... */
1545 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1549 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1550 FW_WM(8, PLANEC_OLD));
1551 /* update cursor SR watermark */
1552 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1555 intel_set_memory_cxsr(dev_priv, true);
1560 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1562 struct drm_device *dev = unused_crtc->dev;
1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 const struct intel_watermark_params *wm_info;
1569 int planea_wm, planeb_wm;
1570 struct drm_crtc *crtc, *enabled = NULL;
1573 wm_info = &i945_wm_info;
1574 else if (!IS_GEN2(dev))
1575 wm_info = &i915_wm_info;
1577 wm_info = &i830_a_wm_info;
1579 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1580 crtc = intel_get_crtc_for_plane(dev, 0);
1581 if (intel_crtc_active(crtc)) {
1582 const struct drm_display_mode *adjusted_mode;
1583 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1587 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1588 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1589 wm_info, fifo_size, cpp,
1590 pessimal_latency_ns);
1593 planea_wm = fifo_size - wm_info->guard_size;
1594 if (planea_wm > (long)wm_info->max_wm)
1595 planea_wm = wm_info->max_wm;
1599 wm_info = &i830_bc_wm_info;
1601 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1602 crtc = intel_get_crtc_for_plane(dev, 1);
1603 if (intel_crtc_active(crtc)) {
1604 const struct drm_display_mode *adjusted_mode;
1605 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1609 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1610 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1611 wm_info, fifo_size, cpp,
1612 pessimal_latency_ns);
1613 if (enabled == NULL)
1618 planeb_wm = fifo_size - wm_info->guard_size;
1619 if (planeb_wm > (long)wm_info->max_wm)
1620 planeb_wm = wm_info->max_wm;
1623 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1625 if (IS_I915GM(dev) && enabled) {
1626 struct drm_i915_gem_object *obj;
1628 obj = intel_fb_obj(enabled->primary->state->fb);
1630 /* self-refresh seems busted with untiled */
1631 if (obj->tiling_mode == I915_TILING_NONE)
1636 * Overlay gets an aggressive default since video jitter is bad.
1640 /* Play safe and disable self-refresh before adjusting watermarks. */
1641 intel_set_memory_cxsr(dev_priv, false);
1643 /* Calc sr entries for one plane configs */
1644 if (HAS_FW_BLC(dev) && enabled) {
1645 /* self-refresh has much higher latency */
1646 static const int sr_latency_ns = 6000;
1647 const struct drm_display_mode *adjusted_mode =
1648 &to_intel_crtc(enabled)->config->base.adjusted_mode;
1649 int clock = adjusted_mode->crtc_clock;
1650 int htotal = adjusted_mode->crtc_htotal;
1651 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1652 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1653 unsigned long line_time_us;
1656 line_time_us = max(htotal * 1000 / clock, 1);
1658 /* Use ns/us then divide to preserve precision */
1659 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1660 pixel_size * hdisplay;
1661 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1662 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1663 srwm = wm_info->fifo_size - entries;
1667 if (IS_I945G(dev) || IS_I945GM(dev))
1668 I915_WRITE(FW_BLC_SELF,
1669 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1670 else if (IS_I915GM(dev))
1671 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1674 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1675 planea_wm, planeb_wm, cwm, srwm);
1677 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1678 fwater_hi = (cwm & 0x1f);
1680 /* Set request length to 8 cachelines per fetch */
1681 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1682 fwater_hi = fwater_hi | (1 << 8);
1684 I915_WRITE(FW_BLC, fwater_lo);
1685 I915_WRITE(FW_BLC2, fwater_hi);
1688 intel_set_memory_cxsr(dev_priv, true);
1691 static void i845_update_wm(struct drm_crtc *unused_crtc)
1693 struct drm_device *dev = unused_crtc->dev;
1694 struct drm_i915_private *dev_priv = dev->dev_private;
1695 struct drm_crtc *crtc;
1696 const struct drm_display_mode *adjusted_mode;
1700 crtc = single_enabled_crtc(dev);
1704 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1705 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1707 dev_priv->display.get_fifo_size(dev, 0),
1708 4, pessimal_latency_ns);
1709 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1710 fwater_lo |= (3<<8) | planea_wm;
1712 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1714 I915_WRITE(FW_BLC, fwater_lo);
1717 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1719 uint32_t pixel_rate;
1721 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1723 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1724 * adjust the pixel_rate here. */
1726 if (pipe_config->pch_pfit.enabled) {
1727 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1728 uint32_t pfit_size = pipe_config->pch_pfit.size;
1730 pipe_w = pipe_config->pipe_src_w;
1731 pipe_h = pipe_config->pipe_src_h;
1733 pfit_w = (pfit_size >> 16) & 0xFFFF;
1734 pfit_h = pfit_size & 0xFFFF;
1735 if (pipe_w < pfit_w)
1737 if (pipe_h < pfit_h)
1740 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1747 /* latency must be in 0.1us units. */
1748 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1753 if (WARN(latency == 0, "Latency value missing\n"))
1756 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1757 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1762 /* latency must be in 0.1us units. */
1763 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1764 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1769 if (WARN(latency == 0, "Latency value missing\n"))
1772 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1773 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1774 ret = DIV_ROUND_UP(ret, 64) + 2;
1778 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1779 uint8_t bytes_per_pixel)
1781 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1784 struct skl_pipe_wm_parameters {
1786 uint32_t pipe_htotal;
1787 uint32_t pixel_rate; /* in KHz */
1788 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1789 struct intel_plane_wm_parameters cursor;
1792 struct ilk_pipe_wm_parameters {
1794 uint32_t pipe_htotal;
1795 uint32_t pixel_rate;
1796 struct intel_plane_wm_parameters pri;
1797 struct intel_plane_wm_parameters spr;
1798 struct intel_plane_wm_parameters cur;
1801 struct ilk_wm_maximums {
1808 /* used in computing the new watermarks state */
1809 struct intel_wm_config {
1810 unsigned int num_pipes_active;
1811 bool sprites_enabled;
1812 bool sprites_scaled;
1816 * For both WM_PIPE and WM_LP.
1817 * mem_value must be in 0.1us units.
1819 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1823 uint32_t method1, method2;
1825 if (!params->active || !params->pri.enabled)
1828 method1 = ilk_wm_method1(params->pixel_rate,
1829 params->pri.bytes_per_pixel,
1835 method2 = ilk_wm_method2(params->pixel_rate,
1836 params->pipe_htotal,
1837 params->pri.horiz_pixels,
1838 params->pri.bytes_per_pixel,
1841 return min(method1, method2);
1845 * For both WM_PIPE and WM_LP.
1846 * mem_value must be in 0.1us units.
1848 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1851 uint32_t method1, method2;
1853 if (!params->active || !params->spr.enabled)
1856 method1 = ilk_wm_method1(params->pixel_rate,
1857 params->spr.bytes_per_pixel,
1859 method2 = ilk_wm_method2(params->pixel_rate,
1860 params->pipe_htotal,
1861 params->spr.horiz_pixels,
1862 params->spr.bytes_per_pixel,
1864 return min(method1, method2);
1868 * For both WM_PIPE and WM_LP.
1869 * mem_value must be in 0.1us units.
1871 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1874 if (!params->active || !params->cur.enabled)
1877 return ilk_wm_method2(params->pixel_rate,
1878 params->pipe_htotal,
1879 params->cur.horiz_pixels,
1880 params->cur.bytes_per_pixel,
1884 /* Only for WM_LP. */
1885 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1888 if (!params->active || !params->pri.enabled)
1891 return ilk_wm_fbc(pri_val,
1892 params->pri.horiz_pixels,
1893 params->pri.bytes_per_pixel);
1896 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1898 if (INTEL_INFO(dev)->gen >= 8)
1900 else if (INTEL_INFO(dev)->gen >= 7)
1906 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1907 int level, bool is_sprite)
1909 if (INTEL_INFO(dev)->gen >= 8)
1910 /* BDW primary/sprite plane watermarks */
1911 return level == 0 ? 255 : 2047;
1912 else if (INTEL_INFO(dev)->gen >= 7)
1913 /* IVB/HSW primary/sprite plane watermarks */
1914 return level == 0 ? 127 : 1023;
1915 else if (!is_sprite)
1916 /* ILK/SNB primary plane watermarks */
1917 return level == 0 ? 127 : 511;
1919 /* ILK/SNB sprite plane watermarks */
1920 return level == 0 ? 63 : 255;
1923 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1926 if (INTEL_INFO(dev)->gen >= 7)
1927 return level == 0 ? 63 : 255;
1929 return level == 0 ? 31 : 63;
1932 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1934 if (INTEL_INFO(dev)->gen >= 8)
1940 /* Calculate the maximum primary/sprite plane watermark */
1941 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1943 const struct intel_wm_config *config,
1944 enum intel_ddb_partitioning ddb_partitioning,
1947 unsigned int fifo_size = ilk_display_fifo_size(dev);
1949 /* if sprites aren't enabled, sprites get nothing */
1950 if (is_sprite && !config->sprites_enabled)
1953 /* HSW allows LP1+ watermarks even with multiple pipes */
1954 if (level == 0 || config->num_pipes_active > 1) {
1955 fifo_size /= INTEL_INFO(dev)->num_pipes;
1958 * For some reason the non self refresh
1959 * FIFO size is only half of the self
1960 * refresh FIFO size on ILK/SNB.
1962 if (INTEL_INFO(dev)->gen <= 6)
1966 if (config->sprites_enabled) {
1967 /* level 0 is always calculated with 1:1 split */
1968 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1977 /* clamp to max that the registers can hold */
1978 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1981 /* Calculate the maximum cursor plane watermark */
1982 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1984 const struct intel_wm_config *config)
1986 /* HSW LP1+ watermarks w/ multiple pipes */
1987 if (level > 0 && config->num_pipes_active > 1)
1990 /* otherwise just report max that registers can hold */
1991 return ilk_cursor_wm_reg_max(dev, level);
1994 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1996 const struct intel_wm_config *config,
1997 enum intel_ddb_partitioning ddb_partitioning,
1998 struct ilk_wm_maximums *max)
2000 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2001 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2002 max->cur = ilk_cursor_wm_max(dev, level, config);
2003 max->fbc = ilk_fbc_wm_reg_max(dev);
2006 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2008 struct ilk_wm_maximums *max)
2010 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2011 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2012 max->cur = ilk_cursor_wm_reg_max(dev, level);
2013 max->fbc = ilk_fbc_wm_reg_max(dev);
2016 static bool ilk_validate_wm_level(int level,
2017 const struct ilk_wm_maximums *max,
2018 struct intel_wm_level *result)
2022 /* already determined to be invalid? */
2023 if (!result->enable)
2026 result->enable = result->pri_val <= max->pri &&
2027 result->spr_val <= max->spr &&
2028 result->cur_val <= max->cur;
2030 ret = result->enable;
2033 * HACK until we can pre-compute everything,
2034 * and thus fail gracefully if LP0 watermarks
2037 if (level == 0 && !result->enable) {
2038 if (result->pri_val > max->pri)
2039 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2040 level, result->pri_val, max->pri);
2041 if (result->spr_val > max->spr)
2042 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2043 level, result->spr_val, max->spr);
2044 if (result->cur_val > max->cur)
2045 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2046 level, result->cur_val, max->cur);
2048 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2049 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2050 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2051 result->enable = true;
2057 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2059 const struct ilk_pipe_wm_parameters *p,
2060 struct intel_wm_level *result)
2062 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2063 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2064 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2066 /* WM1+ latency values stored in 0.5us units */
2073 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2074 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2075 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2076 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2077 result->enable = true;
2081 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
2086 u32 linetime, ips_linetime;
2088 if (!intel_crtc->active)
2091 /* The WM are computed with base on how long it takes to fill a single
2092 * row at the given clock rate, multiplied by 8.
2094 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2096 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2097 dev_priv->cdclk_freq);
2099 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2100 PIPE_WM_LINETIME_TIME(linetime);
2103 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2105 struct drm_i915_private *dev_priv = dev->dev_private;
2110 int level, max_level = ilk_wm_max_level(dev);
2112 /* read the first set of memory latencies[0:3] */
2113 val = 0; /* data0 to be programmed to 0 for first set */
2114 mutex_lock(&dev_priv->rps.hw_lock);
2115 ret = sandybridge_pcode_read(dev_priv,
2116 GEN9_PCODE_READ_MEM_LATENCY,
2118 mutex_unlock(&dev_priv->rps.hw_lock);
2121 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2125 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2129 GEN9_MEM_LATENCY_LEVEL_MASK;
2130 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2131 GEN9_MEM_LATENCY_LEVEL_MASK;
2133 /* read the second set of memory latencies[4:7] */
2134 val = 1; /* data0 to be programmed to 1 for second set */
2135 mutex_lock(&dev_priv->rps.hw_lock);
2136 ret = sandybridge_pcode_read(dev_priv,
2137 GEN9_PCODE_READ_MEM_LATENCY,
2139 mutex_unlock(&dev_priv->rps.hw_lock);
2141 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2145 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2146 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2147 GEN9_MEM_LATENCY_LEVEL_MASK;
2148 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2149 GEN9_MEM_LATENCY_LEVEL_MASK;
2150 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2151 GEN9_MEM_LATENCY_LEVEL_MASK;
2154 * WaWmMemoryReadLatency:skl
2156 * punit doesn't take into account the read latency so we need
2157 * to add 2us to the various latency levels we retrieve from
2159 * - W0 is a bit special in that it's the only level that
2160 * can't be disabled if we want to have display working, so
2161 * we always add 2us there.
2162 * - For levels >=1, punit returns 0us latency when they are
2163 * disabled, so we respect that and don't add 2us then
2165 * Additionally, if a level n (n > 1) has a 0us latency, all
2166 * levels m (m >= n) need to be disabled. We make sure to
2167 * sanitize the values out of the punit to satisfy this
2171 for (level = 1; level <= max_level; level++)
2175 for (i = level + 1; i <= max_level; i++)
2180 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2181 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2183 wm[0] = (sskpd >> 56) & 0xFF;
2185 wm[0] = sskpd & 0xF;
2186 wm[1] = (sskpd >> 4) & 0xFF;
2187 wm[2] = (sskpd >> 12) & 0xFF;
2188 wm[3] = (sskpd >> 20) & 0x1FF;
2189 wm[4] = (sskpd >> 32) & 0x1FF;
2190 } else if (INTEL_INFO(dev)->gen >= 6) {
2191 uint32_t sskpd = I915_READ(MCH_SSKPD);
2193 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2194 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2195 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2196 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2197 } else if (INTEL_INFO(dev)->gen >= 5) {
2198 uint32_t mltr = I915_READ(MLTR_ILK);
2200 /* ILK primary LP0 latency is 700 ns */
2202 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2203 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2207 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2209 /* ILK sprite LP0 latency is 1300 ns */
2210 if (INTEL_INFO(dev)->gen == 5)
2214 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2216 /* ILK cursor LP0 latency is 1300 ns */
2217 if (INTEL_INFO(dev)->gen == 5)
2220 /* WaDoubleCursorLP3Latency:ivb */
2221 if (IS_IVYBRIDGE(dev))
2225 int ilk_wm_max_level(const struct drm_device *dev)
2227 /* how many WM levels are we expecting */
2228 if (INTEL_INFO(dev)->gen >= 9)
2230 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2232 else if (INTEL_INFO(dev)->gen >= 6)
2238 static void intel_print_wm_latency(struct drm_device *dev,
2240 const uint16_t wm[8])
2242 int level, max_level = ilk_wm_max_level(dev);
2244 for (level = 0; level <= max_level; level++) {
2245 unsigned int latency = wm[level];
2248 DRM_ERROR("%s WM%d latency not provided\n",
2254 * - latencies are in us on gen9.
2255 * - before then, WM1+ latency values are in 0.5us units
2262 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2263 name, level, wm[level],
2264 latency / 10, latency % 10);
2268 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2269 uint16_t wm[5], uint16_t min)
2271 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2276 wm[0] = max(wm[0], min);
2277 for (level = 1; level <= max_level; level++)
2278 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2283 static void snb_wm_latency_quirk(struct drm_device *dev)
2285 struct drm_i915_private *dev_priv = dev->dev_private;
2289 * The BIOS provided WM memory latency values are often
2290 * inadequate for high resolution displays. Adjust them.
2292 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2293 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2294 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2299 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2300 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2301 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2302 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2305 static void ilk_setup_wm_latency(struct drm_device *dev)
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2309 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2311 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2312 sizeof(dev_priv->wm.pri_latency));
2313 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2314 sizeof(dev_priv->wm.pri_latency));
2316 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2317 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2319 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2320 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2321 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2324 snb_wm_latency_quirk(dev);
2327 static void skl_setup_wm_latency(struct drm_device *dev)
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2331 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2332 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2335 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2336 struct ilk_pipe_wm_parameters *p)
2338 struct drm_device *dev = crtc->dev;
2339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2340 enum pipe pipe = intel_crtc->pipe;
2341 struct drm_plane *plane;
2343 if (!intel_crtc->active)
2347 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2348 p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
2350 if (crtc->primary->state->fb)
2351 p->pri.bytes_per_pixel =
2352 crtc->primary->state->fb->bits_per_pixel / 8;
2354 p->pri.bytes_per_pixel = 4;
2356 p->cur.bytes_per_pixel = 4;
2358 * TODO: for now, assume primary and cursor planes are always enabled.
2359 * Setting them to false makes the screen flicker.
2361 p->pri.enabled = true;
2362 p->cur.enabled = true;
2364 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
2365 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
2367 drm_for_each_legacy_plane(plane, dev) {
2368 struct intel_plane *intel_plane = to_intel_plane(plane);
2370 if (intel_plane->pipe == pipe) {
2371 p->spr = intel_plane->wm;
2377 static void ilk_compute_wm_config(struct drm_device *dev,
2378 struct intel_wm_config *config)
2380 struct intel_crtc *intel_crtc;
2382 /* Compute the currently _active_ config */
2383 for_each_intel_crtc(dev, intel_crtc) {
2384 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2386 if (!wm->pipe_enabled)
2389 config->sprites_enabled |= wm->sprites_enabled;
2390 config->sprites_scaled |= wm->sprites_scaled;
2391 config->num_pipes_active++;
2395 /* Compute new watermarks for the pipe */
2396 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2397 const struct ilk_pipe_wm_parameters *params,
2398 struct intel_pipe_wm *pipe_wm)
2400 struct drm_device *dev = crtc->dev;
2401 const struct drm_i915_private *dev_priv = dev->dev_private;
2402 int level, max_level = ilk_wm_max_level(dev);
2403 /* LP0 watermark maximums depend on this pipe alone */
2404 struct intel_wm_config config = {
2405 .num_pipes_active = 1,
2406 .sprites_enabled = params->spr.enabled,
2407 .sprites_scaled = params->spr.scaled,
2409 struct ilk_wm_maximums max;
2411 pipe_wm->pipe_enabled = params->active;
2412 pipe_wm->sprites_enabled = params->spr.enabled;
2413 pipe_wm->sprites_scaled = params->spr.scaled;
2415 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2416 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2419 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2420 if (params->spr.scaled)
2423 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2425 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2426 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2428 /* LP0 watermarks always use 1/2 DDB partitioning */
2429 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2431 /* At least LP0 must be valid */
2432 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2435 ilk_compute_wm_reg_maximums(dev, 1, &max);
2437 for (level = 1; level <= max_level; level++) {
2438 struct intel_wm_level wm = {};
2440 ilk_compute_wm_level(dev_priv, level, params, &wm);
2443 * Disable any watermark level that exceeds the
2444 * register maximums since such watermarks are
2447 if (!ilk_validate_wm_level(level, &max, &wm))
2450 pipe_wm->wm[level] = wm;
2457 * Merge the watermarks from all active pipes for a specific level.
2459 static void ilk_merge_wm_level(struct drm_device *dev,
2461 struct intel_wm_level *ret_wm)
2463 const struct intel_crtc *intel_crtc;
2465 ret_wm->enable = true;
2467 for_each_intel_crtc(dev, intel_crtc) {
2468 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2469 const struct intel_wm_level *wm = &active->wm[level];
2471 if (!active->pipe_enabled)
2475 * The watermark values may have been used in the past,
2476 * so we must maintain them in the registers for some
2477 * time even if the level is now disabled.
2480 ret_wm->enable = false;
2482 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2483 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2484 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2485 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2490 * Merge all low power watermarks for all active pipes.
2492 static void ilk_wm_merge(struct drm_device *dev,
2493 const struct intel_wm_config *config,
2494 const struct ilk_wm_maximums *max,
2495 struct intel_pipe_wm *merged)
2497 struct drm_i915_private *dev_priv = dev->dev_private;
2498 int level, max_level = ilk_wm_max_level(dev);
2499 int last_enabled_level = max_level;
2501 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2502 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2503 config->num_pipes_active > 1)
2506 /* ILK: FBC WM must be disabled always */
2507 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2509 /* merge each WM1+ level */
2510 for (level = 1; level <= max_level; level++) {
2511 struct intel_wm_level *wm = &merged->wm[level];
2513 ilk_merge_wm_level(dev, level, wm);
2515 if (level > last_enabled_level)
2517 else if (!ilk_validate_wm_level(level, max, wm))
2518 /* make sure all following levels get disabled */
2519 last_enabled_level = level - 1;
2522 * The spec says it is preferred to disable
2523 * FBC WMs instead of disabling a WM level.
2525 if (wm->fbc_val > max->fbc) {
2527 merged->fbc_wm_enabled = false;
2532 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2534 * FIXME this is racy. FBC might get enabled later.
2535 * What we should check here is whether FBC can be
2536 * enabled sometime later.
2538 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2539 intel_fbc_enabled(dev_priv)) {
2540 for (level = 2; level <= max_level; level++) {
2541 struct intel_wm_level *wm = &merged->wm[level];
2548 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2550 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2551 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2554 /* The value we need to program into the WM_LPx latency field */
2555 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2557 struct drm_i915_private *dev_priv = dev->dev_private;
2559 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2562 return dev_priv->wm.pri_latency[level];
2565 static void ilk_compute_wm_results(struct drm_device *dev,
2566 const struct intel_pipe_wm *merged,
2567 enum intel_ddb_partitioning partitioning,
2568 struct ilk_wm_values *results)
2570 struct intel_crtc *intel_crtc;
2573 results->enable_fbc_wm = merged->fbc_wm_enabled;
2574 results->partitioning = partitioning;
2576 /* LP1+ register values */
2577 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2578 const struct intel_wm_level *r;
2580 level = ilk_wm_lp_to_level(wm_lp, merged);
2582 r = &merged->wm[level];
2585 * Maintain the watermark values even if the level is
2586 * disabled. Doing otherwise could cause underruns.
2588 results->wm_lp[wm_lp - 1] =
2589 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2590 (r->pri_val << WM1_LP_SR_SHIFT) |
2594 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2596 if (INTEL_INFO(dev)->gen >= 8)
2597 results->wm_lp[wm_lp - 1] |=
2598 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2600 results->wm_lp[wm_lp - 1] |=
2601 r->fbc_val << WM1_LP_FBC_SHIFT;
2604 * Always set WM1S_LP_EN when spr_val != 0, even if the
2605 * level is disabled. Doing otherwise could cause underruns.
2607 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2608 WARN_ON(wm_lp != 1);
2609 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2611 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2614 /* LP0 register values */
2615 for_each_intel_crtc(dev, intel_crtc) {
2616 enum pipe pipe = intel_crtc->pipe;
2617 const struct intel_wm_level *r =
2618 &intel_crtc->wm.active.wm[0];
2620 if (WARN_ON(!r->enable))
2623 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2625 results->wm_pipe[pipe] =
2626 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2627 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2632 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2633 * case both are at the same level. Prefer r1 in case they're the same. */
2634 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2635 struct intel_pipe_wm *r1,
2636 struct intel_pipe_wm *r2)
2638 int level, max_level = ilk_wm_max_level(dev);
2639 int level1 = 0, level2 = 0;
2641 for (level = 1; level <= max_level; level++) {
2642 if (r1->wm[level].enable)
2644 if (r2->wm[level].enable)
2648 if (level1 == level2) {
2649 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2653 } else if (level1 > level2) {
2660 /* dirty bits used to track which watermarks need changes */
2661 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2662 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2663 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2664 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2665 #define WM_DIRTY_FBC (1 << 24)
2666 #define WM_DIRTY_DDB (1 << 25)
2668 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2669 const struct ilk_wm_values *old,
2670 const struct ilk_wm_values *new)
2672 unsigned int dirty = 0;
2676 for_each_pipe(dev_priv, pipe) {
2677 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2678 dirty |= WM_DIRTY_LINETIME(pipe);
2679 /* Must disable LP1+ watermarks too */
2680 dirty |= WM_DIRTY_LP_ALL;
2683 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2684 dirty |= WM_DIRTY_PIPE(pipe);
2685 /* Must disable LP1+ watermarks too */
2686 dirty |= WM_DIRTY_LP_ALL;
2690 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2691 dirty |= WM_DIRTY_FBC;
2692 /* Must disable LP1+ watermarks too */
2693 dirty |= WM_DIRTY_LP_ALL;
2696 if (old->partitioning != new->partitioning) {
2697 dirty |= WM_DIRTY_DDB;
2698 /* Must disable LP1+ watermarks too */
2699 dirty |= WM_DIRTY_LP_ALL;
2702 /* LP1+ watermarks already deemed dirty, no need to continue */
2703 if (dirty & WM_DIRTY_LP_ALL)
2706 /* Find the lowest numbered LP1+ watermark in need of an update... */
2707 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2708 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2709 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2713 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2714 for (; wm_lp <= 3; wm_lp++)
2715 dirty |= WM_DIRTY_LP(wm_lp);
2720 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2723 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2724 bool changed = false;
2726 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2727 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2728 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2731 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2732 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2733 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2736 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2737 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2738 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2743 * Don't touch WM1S_LP_EN here.
2744 * Doing so could cause underruns.
2751 * The spec says we shouldn't write when we don't need, because every write
2752 * causes WMs to be re-evaluated, expending some power.
2754 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2755 struct ilk_wm_values *results)
2757 struct drm_device *dev = dev_priv->dev;
2758 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2762 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2766 _ilk_disable_lp_wm(dev_priv, dirty);
2768 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2769 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2770 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2771 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2772 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2773 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2775 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2776 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2777 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2778 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2779 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2780 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2782 if (dirty & WM_DIRTY_DDB) {
2783 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2784 val = I915_READ(WM_MISC);
2785 if (results->partitioning == INTEL_DDB_PART_1_2)
2786 val &= ~WM_MISC_DATA_PARTITION_5_6;
2788 val |= WM_MISC_DATA_PARTITION_5_6;
2789 I915_WRITE(WM_MISC, val);
2791 val = I915_READ(DISP_ARB_CTL2);
2792 if (results->partitioning == INTEL_DDB_PART_1_2)
2793 val &= ~DISP_DATA_PARTITION_5_6;
2795 val |= DISP_DATA_PARTITION_5_6;
2796 I915_WRITE(DISP_ARB_CTL2, val);
2800 if (dirty & WM_DIRTY_FBC) {
2801 val = I915_READ(DISP_ARB_CTL);
2802 if (results->enable_fbc_wm)
2803 val &= ~DISP_FBC_WM_DIS;
2805 val |= DISP_FBC_WM_DIS;
2806 I915_WRITE(DISP_ARB_CTL, val);
2809 if (dirty & WM_DIRTY_LP(1) &&
2810 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2811 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2813 if (INTEL_INFO(dev)->gen >= 7) {
2814 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2815 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2816 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2817 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2820 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2821 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2822 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2823 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2824 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2825 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2827 dev_priv->wm.hw = *results;
2830 static bool ilk_disable_lp_wm(struct drm_device *dev)
2832 struct drm_i915_private *dev_priv = dev->dev_private;
2834 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2838 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2839 * different active planes.
2842 #define SKL_DDB_SIZE 896 /* in blocks */
2843 #define BXT_DDB_SIZE 512
2846 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2847 struct drm_crtc *for_crtc,
2848 const struct intel_wm_config *config,
2849 const struct skl_pipe_wm_parameters *params,
2850 struct skl_ddb_entry *alloc /* out */)
2852 struct drm_crtc *crtc;
2853 unsigned int pipe_size, ddb_size;
2854 int nth_active_pipe;
2856 if (!params->active) {
2862 if (IS_BROXTON(dev))
2863 ddb_size = BXT_DDB_SIZE;
2865 ddb_size = SKL_DDB_SIZE;
2867 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2869 nth_active_pipe = 0;
2870 for_each_crtc(dev, crtc) {
2871 if (!to_intel_crtc(crtc)->active)
2874 if (crtc == for_crtc)
2880 pipe_size = ddb_size / config->num_pipes_active;
2881 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2882 alloc->end = alloc->start + pipe_size;
2885 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2887 if (config->num_pipes_active == 1)
2893 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2895 entry->start = reg & 0x3ff;
2896 entry->end = (reg >> 16) & 0x3ff;
2901 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2902 struct skl_ddb_allocation *ddb /* out */)
2908 for_each_pipe(dev_priv, pipe) {
2909 for_each_plane(dev_priv, pipe, plane) {
2910 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2911 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2915 val = I915_READ(CUR_BUF_CFG(pipe));
2916 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2921 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
2924 /* for planar format */
2925 if (p->y_bytes_per_pixel) {
2926 if (y) /* y-plane data rate */
2927 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2928 else /* uv-plane data rate */
2929 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2932 /* for packed formats */
2933 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2937 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2938 * a 8192x4096@32bpp framebuffer:
2939 * 3 * 4096 * 8192 * 4 < 2^32
2942 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2943 const struct skl_pipe_wm_parameters *params)
2945 unsigned int total_data_rate = 0;
2948 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2949 const struct intel_plane_wm_parameters *p;
2951 p = ¶ms->plane[plane];
2955 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2956 if (p->y_bytes_per_pixel) {
2957 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2961 return total_data_rate;
2965 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2966 const struct intel_wm_config *config,
2967 const struct skl_pipe_wm_parameters *params,
2968 struct skl_ddb_allocation *ddb /* out */)
2970 struct drm_device *dev = crtc->dev;
2971 struct drm_i915_private *dev_priv = dev->dev_private;
2972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2973 enum pipe pipe = intel_crtc->pipe;
2974 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2975 uint16_t alloc_size, start, cursor_blocks;
2976 uint16_t minimum[I915_MAX_PLANES];
2977 uint16_t y_minimum[I915_MAX_PLANES];
2978 unsigned int total_data_rate;
2981 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2982 alloc_size = skl_ddb_entry_size(alloc);
2983 if (alloc_size == 0) {
2984 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2985 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2989 cursor_blocks = skl_cursor_allocation(config);
2990 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2991 ddb->cursor[pipe].end = alloc->end;
2993 alloc_size -= cursor_blocks;
2994 alloc->end -= cursor_blocks;
2996 /* 1. Allocate the mininum required blocks for each active plane */
2997 for_each_plane(dev_priv, pipe, plane) {
2998 const struct intel_plane_wm_parameters *p;
3000 p = ¶ms->plane[plane];
3005 alloc_size -= minimum[plane];
3006 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
3007 alloc_size -= y_minimum[plane];
3011 * 2. Distribute the remaining space in proportion to the amount of
3012 * data each plane needs to fetch from memory.
3014 * FIXME: we may not allocate every single block here.
3016 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
3018 start = alloc->start;
3019 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3020 const struct intel_plane_wm_parameters *p;
3021 unsigned int data_rate, y_data_rate;
3022 uint16_t plane_blocks, y_plane_blocks = 0;
3024 p = ¶ms->plane[plane];
3028 data_rate = skl_plane_relative_data_rate(p, 0);
3031 * allocation for (packed formats) or (uv-plane part of planar format):
3032 * promote the expression to 64 bits to avoid overflowing, the
3033 * result is < available as data_rate / total_data_rate < 1
3035 plane_blocks = minimum[plane];
3036 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3039 ddb->plane[pipe][plane].start = start;
3040 ddb->plane[pipe][plane].end = start + plane_blocks;
3042 start += plane_blocks;
3045 * allocation for y_plane part of planar format:
3047 if (p->y_bytes_per_pixel) {
3048 y_data_rate = skl_plane_relative_data_rate(p, 1);
3049 y_plane_blocks = y_minimum[plane];
3050 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3053 ddb->y_plane[pipe][plane].start = start;
3054 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
3056 start += y_plane_blocks;
3063 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3065 /* TODO: Take into account the scalers once we support them */
3066 return config->base.adjusted_mode.crtc_clock;
3070 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3071 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3072 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3073 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3075 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3078 uint32_t wm_intermediate_val, ret;
3083 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3084 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3089 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3090 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3091 uint64_t tiling, uint32_t latency)
3094 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3095 uint32_t wm_intermediate_val;
3100 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3102 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3103 tiling == I915_FORMAT_MOD_Yf_TILED) {
3104 plane_bytes_per_line *= 4;
3105 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3106 plane_blocks_per_line /= 4;
3108 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3111 wm_intermediate_val = latency * pixel_rate;
3112 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3113 plane_blocks_per_line;
3118 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3119 const struct intel_crtc *intel_crtc)
3121 struct drm_device *dev = intel_crtc->base.dev;
3122 struct drm_i915_private *dev_priv = dev->dev_private;
3123 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3124 enum pipe pipe = intel_crtc->pipe;
3126 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3127 sizeof(new_ddb->plane[pipe])))
3130 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
3131 sizeof(new_ddb->cursor[pipe])))
3137 static void skl_compute_wm_global_parameters(struct drm_device *dev,
3138 struct intel_wm_config *config)
3140 struct drm_crtc *crtc;
3141 struct drm_plane *plane;
3143 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3144 config->num_pipes_active += to_intel_crtc(crtc)->active;
3146 /* FIXME: I don't think we need those two global parameters on SKL */
3147 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3148 struct intel_plane *intel_plane = to_intel_plane(plane);
3150 config->sprites_enabled |= intel_plane->wm.enabled;
3151 config->sprites_scaled |= intel_plane->wm.scaled;
3155 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3156 struct skl_pipe_wm_parameters *p)
3158 struct drm_device *dev = crtc->dev;
3159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3160 enum pipe pipe = intel_crtc->pipe;
3161 struct drm_plane *plane;
3162 struct drm_framebuffer *fb;
3163 int i = 1; /* Index for sprite planes start */
3165 p->active = intel_crtc->active;
3167 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3168 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
3170 fb = crtc->primary->state->fb;
3171 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
3173 p->plane[0].enabled = true;
3174 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3175 drm_format_plane_cpp(fb->pixel_format, 1) :
3176 drm_format_plane_cpp(fb->pixel_format, 0);
3177 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3178 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
3179 p->plane[0].tiling = fb->modifier[0];
3181 p->plane[0].enabled = false;
3182 p->plane[0].bytes_per_pixel = 0;
3183 p->plane[0].y_bytes_per_pixel = 0;
3184 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3186 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3187 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
3188 p->plane[0].rotation = crtc->primary->state->rotation;
3190 fb = crtc->cursor->state->fb;
3191 p->cursor.y_bytes_per_pixel = 0;
3193 p->cursor.enabled = true;
3194 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
3195 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
3196 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
3198 p->cursor.enabled = false;
3199 p->cursor.bytes_per_pixel = 0;
3200 p->cursor.horiz_pixels = 64;
3201 p->cursor.vert_pixels = 64;
3205 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3206 struct intel_plane *intel_plane = to_intel_plane(plane);
3208 if (intel_plane->pipe == pipe &&
3209 plane->type == DRM_PLANE_TYPE_OVERLAY)
3210 p->plane[i++] = intel_plane->wm;
3214 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3215 struct skl_pipe_wm_parameters *p,
3216 struct intel_plane_wm_parameters *p_params,
3217 uint16_t ddb_allocation,
3219 uint16_t *out_blocks, /* out */
3220 uint8_t *out_lines /* out */)
3222 uint32_t latency = dev_priv->wm.skl_latency[level];
3223 uint32_t method1, method2;
3224 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3225 uint32_t res_blocks, res_lines;
3226 uint32_t selected_result;
3227 uint8_t bytes_per_pixel;
3229 if (latency == 0 || !p->active || !p_params->enabled)
3232 bytes_per_pixel = p_params->y_bytes_per_pixel ?
3233 p_params->y_bytes_per_pixel :
3234 p_params->bytes_per_pixel;
3235 method1 = skl_wm_method1(p->pixel_rate,
3238 method2 = skl_wm_method2(p->pixel_rate,
3240 p_params->horiz_pixels,
3245 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
3246 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3248 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3249 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
3250 uint32_t min_scanlines = 4;
3251 uint32_t y_tile_minimum;
3252 if (intel_rotation_90_or_270(p_params->rotation)) {
3253 switch (p_params->bytes_per_pixel) {
3261 WARN(1, "Unsupported pixel depth for rotation");
3264 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3265 selected_result = max(method2, y_tile_minimum);
3267 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3268 selected_result = min(method1, method2);
3270 selected_result = method1;
3273 res_blocks = selected_result + 1;
3274 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3276 if (level >= 1 && level <= 7) {
3277 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3278 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3284 if (res_blocks >= ddb_allocation || res_lines > 31)
3287 *out_blocks = res_blocks;
3288 *out_lines = res_lines;
3293 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3294 struct skl_ddb_allocation *ddb,
3295 struct skl_pipe_wm_parameters *p,
3299 struct skl_wm_level *result)
3301 uint16_t ddb_blocks;
3304 for (i = 0; i < num_planes; i++) {
3305 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3307 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3311 &result->plane_res_b[i],
3312 &result->plane_res_l[i]);
3315 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
3316 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3318 &result->cursor_res_b,
3319 &result->cursor_res_l);
3323 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3325 if (!to_intel_crtc(crtc)->active)
3328 if (WARN_ON(p->pixel_rate == 0))
3331 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3334 static void skl_compute_transition_wm(struct drm_crtc *crtc,
3335 struct skl_pipe_wm_parameters *params,
3336 struct skl_wm_level *trans_wm /* out */)
3338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3341 if (!params->active)
3344 /* Until we know more, just disable transition WMs */
3345 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3346 trans_wm->plane_en[i] = false;
3347 trans_wm->cursor_en = false;
3350 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3351 struct skl_ddb_allocation *ddb,
3352 struct skl_pipe_wm_parameters *params,
3353 struct skl_pipe_wm *pipe_wm)
3355 struct drm_device *dev = crtc->dev;
3356 const struct drm_i915_private *dev_priv = dev->dev_private;
3357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3358 int level, max_level = ilk_wm_max_level(dev);
3360 for (level = 0; level <= max_level; level++) {
3361 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3362 level, intel_num_planes(intel_crtc),
3363 &pipe_wm->wm[level]);
3365 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3367 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3370 static void skl_compute_wm_results(struct drm_device *dev,
3371 struct skl_pipe_wm_parameters *p,
3372 struct skl_pipe_wm *p_wm,
3373 struct skl_wm_values *r,
3374 struct intel_crtc *intel_crtc)
3376 int level, max_level = ilk_wm_max_level(dev);
3377 enum pipe pipe = intel_crtc->pipe;
3381 for (level = 0; level <= max_level; level++) {
3382 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3385 temp |= p_wm->wm[level].plane_res_l[i] <<
3386 PLANE_WM_LINES_SHIFT;
3387 temp |= p_wm->wm[level].plane_res_b[i];
3388 if (p_wm->wm[level].plane_en[i])
3389 temp |= PLANE_WM_EN;
3391 r->plane[pipe][i][level] = temp;
3396 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3397 temp |= p_wm->wm[level].cursor_res_b;
3399 if (p_wm->wm[level].cursor_en)
3400 temp |= PLANE_WM_EN;
3402 r->cursor[pipe][level] = temp;
3406 /* transition WMs */
3407 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3409 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3410 temp |= p_wm->trans_wm.plane_res_b[i];
3411 if (p_wm->trans_wm.plane_en[i])
3412 temp |= PLANE_WM_EN;
3414 r->plane_trans[pipe][i] = temp;
3418 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3419 temp |= p_wm->trans_wm.cursor_res_b;
3420 if (p_wm->trans_wm.cursor_en)
3421 temp |= PLANE_WM_EN;
3423 r->cursor_trans[pipe] = temp;
3425 r->wm_linetime[pipe] = p_wm->linetime;
3428 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3429 const struct skl_ddb_entry *entry)
3432 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3437 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3438 const struct skl_wm_values *new)
3440 struct drm_device *dev = dev_priv->dev;
3441 struct intel_crtc *crtc;
3443 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3444 int i, level, max_level = ilk_wm_max_level(dev);
3445 enum pipe pipe = crtc->pipe;
3447 if (!new->dirty[pipe])
3450 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3452 for (level = 0; level <= max_level; level++) {
3453 for (i = 0; i < intel_num_planes(crtc); i++)
3454 I915_WRITE(PLANE_WM(pipe, i, level),
3455 new->plane[pipe][i][level]);
3456 I915_WRITE(CUR_WM(pipe, level),
3457 new->cursor[pipe][level]);
3459 for (i = 0; i < intel_num_planes(crtc); i++)
3460 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3461 new->plane_trans[pipe][i]);
3462 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3464 for (i = 0; i < intel_num_planes(crtc); i++) {
3465 skl_ddb_entry_write(dev_priv,
3466 PLANE_BUF_CFG(pipe, i),
3467 &new->ddb.plane[pipe][i]);
3468 skl_ddb_entry_write(dev_priv,
3469 PLANE_NV12_BUF_CFG(pipe, i),
3470 &new->ddb.y_plane[pipe][i]);
3473 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3474 &new->ddb.cursor[pipe]);
3479 * When setting up a new DDB allocation arrangement, we need to correctly
3480 * sequence the times at which the new allocations for the pipes are taken into
3481 * account or we'll have pipes fetching from space previously allocated to
3484 * Roughly the sequence looks like:
3485 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3486 * overlapping with a previous light-up pipe (another way to put it is:
3487 * pipes with their new allocation strickly included into their old ones).
3488 * 2. re-allocate the other pipes that get their allocation reduced
3489 * 3. allocate the pipes having their allocation increased
3491 * Steps 1. and 2. are here to take care of the following case:
3492 * - Initially DDB looks like this:
3495 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3499 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3503 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3507 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3509 for_each_plane(dev_priv, pipe, plane) {
3510 I915_WRITE(PLANE_SURF(pipe, plane),
3511 I915_READ(PLANE_SURF(pipe, plane)));
3513 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3517 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3518 const struct skl_ddb_allocation *new,
3521 uint16_t old_size, new_size;
3523 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3524 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3526 return old_size != new_size &&
3527 new->pipe[pipe].start >= old->pipe[pipe].start &&
3528 new->pipe[pipe].end <= old->pipe[pipe].end;
3531 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3532 struct skl_wm_values *new_values)
3534 struct drm_device *dev = dev_priv->dev;
3535 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3536 bool reallocated[I915_MAX_PIPES] = {};
3537 struct intel_crtc *crtc;
3540 new_ddb = &new_values->ddb;
3541 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3544 * First pass: flush the pipes with the new allocation contained into
3547 * We'll wait for the vblank on those pipes to ensure we can safely
3548 * re-allocate the freed space without this pipe fetching from it.
3550 for_each_intel_crtc(dev, crtc) {
3556 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3559 skl_wm_flush_pipe(dev_priv, pipe, 1);
3560 intel_wait_for_vblank(dev, pipe);
3562 reallocated[pipe] = true;
3567 * Second pass: flush the pipes that are having their allocation
3568 * reduced, but overlapping with a previous allocation.
3570 * Here as well we need to wait for the vblank to make sure the freed
3571 * space is not used anymore.
3573 for_each_intel_crtc(dev, crtc) {
3579 if (reallocated[pipe])
3582 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3583 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3584 skl_wm_flush_pipe(dev_priv, pipe, 2);
3585 intel_wait_for_vblank(dev, pipe);
3586 reallocated[pipe] = true;
3591 * Third pass: flush the pipes that got more space allocated.
3593 * We don't need to actively wait for the update here, next vblank
3594 * will just get more DDB space with the correct WM values.
3596 for_each_intel_crtc(dev, crtc) {
3603 * At this point, only the pipes more space than before are
3604 * left to re-allocate.
3606 if (reallocated[pipe])
3609 skl_wm_flush_pipe(dev_priv, pipe, 3);
3613 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3614 struct skl_pipe_wm_parameters *params,
3615 struct intel_wm_config *config,
3616 struct skl_ddb_allocation *ddb, /* out */
3617 struct skl_pipe_wm *pipe_wm /* out */)
3619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3621 skl_compute_wm_pipe_parameters(crtc, params);
3622 skl_allocate_pipe_ddb(crtc, config, params, ddb);
3623 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3625 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3628 intel_crtc->wm.skl_active = *pipe_wm;
3633 static void skl_update_other_pipe_wm(struct drm_device *dev,
3634 struct drm_crtc *crtc,
3635 struct intel_wm_config *config,
3636 struct skl_wm_values *r)
3638 struct intel_crtc *intel_crtc;
3639 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3642 * If the WM update hasn't changed the allocation for this_crtc (the
3643 * crtc we are currently computing the new WM values for), other
3644 * enabled crtcs will keep the same allocation and we don't need to
3645 * recompute anything for them.
3647 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3651 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3652 * other active pipes need new DDB allocation and WM values.
3654 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3656 struct skl_pipe_wm_parameters params = {};
3657 struct skl_pipe_wm pipe_wm = {};
3660 if (this_crtc->pipe == intel_crtc->pipe)
3663 if (!intel_crtc->active)
3666 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3671 * If we end up re-computing the other pipe WM values, it's
3672 * because it was really needed, so we expect the WM values to
3675 WARN_ON(!wm_changed);
3677 skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc);
3678 r->dirty[intel_crtc->pipe] = true;
3682 static void skl_update_wm(struct drm_crtc *crtc)
3684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3685 struct drm_device *dev = crtc->dev;
3686 struct drm_i915_private *dev_priv = dev->dev_private;
3687 struct skl_pipe_wm_parameters params = {};
3688 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3689 struct skl_pipe_wm pipe_wm = {};
3690 struct intel_wm_config config = {};
3692 memset(results, 0, sizeof(*results));
3694 skl_compute_wm_global_parameters(dev, &config);
3696 if (!skl_update_pipe_wm(crtc, ¶ms, &config,
3697 &results->ddb, &pipe_wm))
3700 skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc);
3701 results->dirty[intel_crtc->pipe] = true;
3703 skl_update_other_pipe_wm(dev, crtc, &config, results);
3704 skl_write_wm_values(dev_priv, results);
3705 skl_flush_wm_values(dev_priv, results);
3707 /* store the new configuration */
3708 dev_priv->wm.skl_hw = *results;
3712 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3713 uint32_t sprite_width, uint32_t sprite_height,
3714 int pixel_size, bool enabled, bool scaled)
3716 struct intel_plane *intel_plane = to_intel_plane(plane);
3717 struct drm_framebuffer *fb = plane->state->fb;
3719 intel_plane->wm.enabled = enabled;
3720 intel_plane->wm.scaled = scaled;
3721 intel_plane->wm.horiz_pixels = sprite_width;
3722 intel_plane->wm.vert_pixels = sprite_height;
3723 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3725 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3726 intel_plane->wm.bytes_per_pixel =
3727 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3728 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3729 intel_plane->wm.y_bytes_per_pixel =
3730 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3731 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3734 * Framebuffer can be NULL on plane disable, but it does not
3735 * matter for watermarks if we assume no tiling in that case.
3738 intel_plane->wm.tiling = fb->modifier[0];
3739 intel_plane->wm.rotation = plane->state->rotation;
3741 skl_update_wm(crtc);
3744 static void ilk_update_wm(struct drm_crtc *crtc)
3746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3747 struct drm_device *dev = crtc->dev;
3748 struct drm_i915_private *dev_priv = dev->dev_private;
3749 struct ilk_wm_maximums max;
3750 struct ilk_pipe_wm_parameters params = {};
3751 struct ilk_wm_values results = {};
3752 enum intel_ddb_partitioning partitioning;
3753 struct intel_pipe_wm pipe_wm = {};
3754 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3755 struct intel_wm_config config = {};
3757 ilk_compute_wm_parameters(crtc, ¶ms);
3759 intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm);
3761 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3764 intel_crtc->wm.active = pipe_wm;
3766 ilk_compute_wm_config(dev, &config);
3768 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3769 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3771 /* 5/6 split only in single pipe config on IVB+ */
3772 if (INTEL_INFO(dev)->gen >= 7 &&
3773 config.num_pipes_active == 1 && config.sprites_enabled) {
3774 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3775 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3777 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3779 best_lp_wm = &lp_wm_1_2;
3782 partitioning = (best_lp_wm == &lp_wm_1_2) ?
3783 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3785 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3787 ilk_write_wm_values(dev_priv, &results);
3791 ilk_update_sprite_wm(struct drm_plane *plane,
3792 struct drm_crtc *crtc,
3793 uint32_t sprite_width, uint32_t sprite_height,
3794 int pixel_size, bool enabled, bool scaled)
3796 struct drm_device *dev = plane->dev;
3797 struct intel_plane *intel_plane = to_intel_plane(plane);
3799 intel_plane->wm.enabled = enabled;
3800 intel_plane->wm.scaled = scaled;
3801 intel_plane->wm.horiz_pixels = sprite_width;
3802 intel_plane->wm.vert_pixels = sprite_width;
3803 intel_plane->wm.bytes_per_pixel = pixel_size;
3806 * IVB workaround: must disable low power watermarks for at least
3807 * one frame before enabling scaling. LP watermarks can be re-enabled
3808 * when scaling is disabled.
3810 * WaCxSRDisabledForSpriteScaling:ivb
3812 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3813 intel_wait_for_vblank(dev, intel_plane->pipe);
3815 ilk_update_wm(crtc);
3818 static void skl_pipe_wm_active_state(uint32_t val,
3819 struct skl_pipe_wm *active,
3825 bool is_enabled = (val & PLANE_WM_EN) != 0;
3829 active->wm[level].plane_en[i] = is_enabled;
3830 active->wm[level].plane_res_b[i] =
3831 val & PLANE_WM_BLOCKS_MASK;
3832 active->wm[level].plane_res_l[i] =
3833 (val >> PLANE_WM_LINES_SHIFT) &
3834 PLANE_WM_LINES_MASK;
3836 active->wm[level].cursor_en = is_enabled;
3837 active->wm[level].cursor_res_b =
3838 val & PLANE_WM_BLOCKS_MASK;
3839 active->wm[level].cursor_res_l =
3840 (val >> PLANE_WM_LINES_SHIFT) &
3841 PLANE_WM_LINES_MASK;
3845 active->trans_wm.plane_en[i] = is_enabled;
3846 active->trans_wm.plane_res_b[i] =
3847 val & PLANE_WM_BLOCKS_MASK;
3848 active->trans_wm.plane_res_l[i] =
3849 (val >> PLANE_WM_LINES_SHIFT) &
3850 PLANE_WM_LINES_MASK;
3852 active->trans_wm.cursor_en = is_enabled;
3853 active->trans_wm.cursor_res_b =
3854 val & PLANE_WM_BLOCKS_MASK;
3855 active->trans_wm.cursor_res_l =
3856 (val >> PLANE_WM_LINES_SHIFT) &
3857 PLANE_WM_LINES_MASK;
3862 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3864 struct drm_device *dev = crtc->dev;
3865 struct drm_i915_private *dev_priv = dev->dev_private;
3866 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3868 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3869 enum pipe pipe = intel_crtc->pipe;
3870 int level, i, max_level;
3873 max_level = ilk_wm_max_level(dev);
3875 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3877 for (level = 0; level <= max_level; level++) {
3878 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3879 hw->plane[pipe][i][level] =
3880 I915_READ(PLANE_WM(pipe, i, level));
3881 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3884 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3885 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3886 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3888 if (!intel_crtc->active)
3891 hw->dirty[pipe] = true;
3893 active->linetime = hw->wm_linetime[pipe];
3895 for (level = 0; level <= max_level; level++) {
3896 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3897 temp = hw->plane[pipe][i][level];
3898 skl_pipe_wm_active_state(temp, active, false,
3901 temp = hw->cursor[pipe][level];
3902 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3905 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3906 temp = hw->plane_trans[pipe][i];
3907 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3910 temp = hw->cursor_trans[pipe];
3911 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3914 void skl_wm_get_hw_state(struct drm_device *dev)
3916 struct drm_i915_private *dev_priv = dev->dev_private;
3917 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3918 struct drm_crtc *crtc;
3920 skl_ddb_get_hw_state(dev_priv, ddb);
3921 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3922 skl_pipe_wm_get_hw_state(crtc);
3925 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3927 struct drm_device *dev = crtc->dev;
3928 struct drm_i915_private *dev_priv = dev->dev_private;
3929 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3931 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3932 enum pipe pipe = intel_crtc->pipe;
3933 static const unsigned int wm0_pipe_reg[] = {
3934 [PIPE_A] = WM0_PIPEA_ILK,
3935 [PIPE_B] = WM0_PIPEB_ILK,
3936 [PIPE_C] = WM0_PIPEC_IVB,
3939 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3940 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3941 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3943 active->pipe_enabled = intel_crtc->active;
3945 if (active->pipe_enabled) {
3946 u32 tmp = hw->wm_pipe[pipe];
3949 * For active pipes LP0 watermark is marked as
3950 * enabled, and LP1+ watermaks as disabled since
3951 * we can't really reverse compute them in case
3952 * multiple pipes are active.
3954 active->wm[0].enable = true;
3955 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3956 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3957 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3958 active->linetime = hw->wm_linetime[pipe];
3960 int level, max_level = ilk_wm_max_level(dev);
3963 * For inactive pipes, all watermark levels
3964 * should be marked as enabled but zeroed,
3965 * which is what we'd compute them to.
3967 for (level = 0; level <= max_level; level++)
3968 active->wm[level].enable = true;
3972 #define _FW_WM(value, plane) \
3973 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3974 #define _FW_WM_VLV(value, plane) \
3975 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3977 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3978 struct vlv_wm_values *wm)
3983 for_each_pipe(dev_priv, pipe) {
3984 tmp = I915_READ(VLV_DDL(pipe));
3986 wm->ddl[pipe].primary =
3987 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3988 wm->ddl[pipe].cursor =
3989 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3990 wm->ddl[pipe].sprite[0] =
3991 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3992 wm->ddl[pipe].sprite[1] =
3993 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3996 tmp = I915_READ(DSPFW1);
3997 wm->sr.plane = _FW_WM(tmp, SR);
3998 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3999 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4000 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4002 tmp = I915_READ(DSPFW2);
4003 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4004 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4005 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4007 tmp = I915_READ(DSPFW3);
4008 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4010 if (IS_CHERRYVIEW(dev_priv)) {
4011 tmp = I915_READ(DSPFW7_CHV);
4012 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4013 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4015 tmp = I915_READ(DSPFW8_CHV);
4016 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4017 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4019 tmp = I915_READ(DSPFW9_CHV);
4020 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4021 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4023 tmp = I915_READ(DSPHOWM);
4024 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4025 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4026 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4027 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4028 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4029 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4030 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4031 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4032 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4033 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4035 tmp = I915_READ(DSPFW7);
4036 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4037 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4039 tmp = I915_READ(DSPHOWM);
4040 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4041 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4042 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4043 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4044 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4045 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4046 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4053 void vlv_wm_get_hw_state(struct drm_device *dev)
4055 struct drm_i915_private *dev_priv = to_i915(dev);
4056 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4057 struct intel_plane *plane;
4061 vlv_read_wm_values(dev_priv, wm);
4063 for_each_intel_plane(dev, plane) {
4064 switch (plane->base.type) {
4066 case DRM_PLANE_TYPE_CURSOR:
4067 plane->wm.fifo_size = 63;
4069 case DRM_PLANE_TYPE_PRIMARY:
4070 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4072 case DRM_PLANE_TYPE_OVERLAY:
4073 sprite = plane->plane;
4074 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4079 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4080 wm->level = VLV_WM_LEVEL_PM2;
4082 if (IS_CHERRYVIEW(dev_priv)) {
4083 mutex_lock(&dev_priv->rps.hw_lock);
4085 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4086 if (val & DSP_MAXFIFO_PM5_ENABLE)
4087 wm->level = VLV_WM_LEVEL_PM5;
4090 * If DDR DVFS is disabled in the BIOS, Punit
4091 * will never ack the request. So if that happens
4092 * assume we don't have to enable/disable DDR DVFS
4093 * dynamically. To test that just set the REQ_ACK
4094 * bit to poke the Punit, but don't change the
4095 * HIGH/LOW bits so that we don't actually change
4096 * the current state.
4098 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4099 val |= FORCE_DDR_FREQ_REQ_ACK;
4100 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4102 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4103 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4104 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4105 "assuming DDR DVFS is disabled\n");
4106 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4108 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4109 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4110 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4113 mutex_unlock(&dev_priv->rps.hw_lock);
4116 for_each_pipe(dev_priv, pipe)
4117 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4118 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4119 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4121 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4122 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4125 void ilk_wm_get_hw_state(struct drm_device *dev)
4127 struct drm_i915_private *dev_priv = dev->dev_private;
4128 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4129 struct drm_crtc *crtc;
4131 for_each_crtc(dev, crtc)
4132 ilk_pipe_wm_get_hw_state(crtc);
4134 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4135 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4136 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4138 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4139 if (INTEL_INFO(dev)->gen >= 7) {
4140 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4141 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4144 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4145 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4146 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4147 else if (IS_IVYBRIDGE(dev))
4148 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4149 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4152 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4156 * intel_update_watermarks - update FIFO watermark values based on current modes
4158 * Calculate watermark values for the various WM regs based on current mode
4159 * and plane configuration.
4161 * There are several cases to deal with here:
4162 * - normal (i.e. non-self-refresh)
4163 * - self-refresh (SR) mode
4164 * - lines are large relative to FIFO size (buffer can hold up to 2)
4165 * - lines are small relative to FIFO size (buffer can hold more than 2
4166 * lines), so need to account for TLB latency
4168 * The normal calculation is:
4169 * watermark = dotclock * bytes per pixel * latency
4170 * where latency is platform & configuration dependent (we assume pessimal
4173 * The SR calculation is:
4174 * watermark = (trunc(latency/line time)+1) * surface width *
4177 * line time = htotal / dotclock
4178 * surface width = hdisplay for normal plane and 64 for cursor
4179 * and latency is assumed to be high, as above.
4181 * The final value programmed to the register should always be rounded up,
4182 * and include an extra 2 entries to account for clock crossings.
4184 * We don't use the sprite, so we can ignore that. And on Crestline we have
4185 * to set the non-SR watermarks to 8.
4187 void intel_update_watermarks(struct drm_crtc *crtc)
4189 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4191 if (dev_priv->display.update_wm)
4192 dev_priv->display.update_wm(crtc);
4195 void intel_update_sprite_watermarks(struct drm_plane *plane,
4196 struct drm_crtc *crtc,
4197 uint32_t sprite_width,
4198 uint32_t sprite_height,
4200 bool enabled, bool scaled)
4202 struct drm_i915_private *dev_priv = plane->dev->dev_private;
4204 if (dev_priv->display.update_sprite_wm)
4205 dev_priv->display.update_sprite_wm(plane, crtc,
4206 sprite_width, sprite_height,
4207 pixel_size, enabled, scaled);
4211 * Lock protecting IPS related data structures
4213 DEFINE_SPINLOCK(mchdev_lock);
4215 /* Global for IPS driver to get at the current i915 device. Protected by
4217 static struct drm_i915_private *i915_mch_dev;
4219 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4221 struct drm_i915_private *dev_priv = dev->dev_private;
4224 assert_spin_locked(&mchdev_lock);
4226 rgvswctl = I915_READ16(MEMSWCTL);
4227 if (rgvswctl & MEMCTL_CMD_STS) {
4228 DRM_DEBUG("gpu busy, RCS change rejected\n");
4229 return false; /* still busy with another command */
4232 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4233 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4234 I915_WRITE16(MEMSWCTL, rgvswctl);
4235 POSTING_READ16(MEMSWCTL);
4237 rgvswctl |= MEMCTL_CMD_STS;
4238 I915_WRITE16(MEMSWCTL, rgvswctl);
4243 static void ironlake_enable_drps(struct drm_device *dev)
4245 struct drm_i915_private *dev_priv = dev->dev_private;
4246 u32 rgvmodectl = I915_READ(MEMMODECTL);
4247 u8 fmax, fmin, fstart, vstart;
4249 spin_lock_irq(&mchdev_lock);
4251 /* Enable temp reporting */
4252 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4253 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4255 /* 100ms RC evaluation intervals */
4256 I915_WRITE(RCUPEI, 100000);
4257 I915_WRITE(RCDNEI, 100000);
4259 /* Set max/min thresholds to 90ms and 80ms respectively */
4260 I915_WRITE(RCBMAXAVG, 90000);
4261 I915_WRITE(RCBMINAVG, 80000);
4263 I915_WRITE(MEMIHYST, 1);
4265 /* Set up min, max, and cur for interrupt handling */
4266 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4267 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4268 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4269 MEMMODE_FSTART_SHIFT;
4271 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4274 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4275 dev_priv->ips.fstart = fstart;
4277 dev_priv->ips.max_delay = fstart;
4278 dev_priv->ips.min_delay = fmin;
4279 dev_priv->ips.cur_delay = fstart;
4281 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4282 fmax, fmin, fstart);
4284 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4287 * Interrupts will be enabled in ironlake_irq_postinstall
4290 I915_WRITE(VIDSTART, vstart);
4291 POSTING_READ(VIDSTART);
4293 rgvmodectl |= MEMMODE_SWMODE_EN;
4294 I915_WRITE(MEMMODECTL, rgvmodectl);
4296 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4297 DRM_ERROR("stuck trying to change perf mode\n");
4300 ironlake_set_drps(dev, fstart);
4302 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
4304 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4305 dev_priv->ips.last_count2 = I915_READ(0x112f4);
4306 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4308 spin_unlock_irq(&mchdev_lock);
4311 static void ironlake_disable_drps(struct drm_device *dev)
4313 struct drm_i915_private *dev_priv = dev->dev_private;
4316 spin_lock_irq(&mchdev_lock);
4318 rgvswctl = I915_READ16(MEMSWCTL);
4320 /* Ack interrupts, disable EFC interrupt */
4321 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4322 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4323 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4324 I915_WRITE(DEIIR, DE_PCU_EVENT);
4325 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4327 /* Go back to the starting frequency */
4328 ironlake_set_drps(dev, dev_priv->ips.fstart);
4330 rgvswctl |= MEMCTL_CMD_STS;
4331 I915_WRITE(MEMSWCTL, rgvswctl);
4334 spin_unlock_irq(&mchdev_lock);
4337 /* There's a funny hw issue where the hw returns all 0 when reading from
4338 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4339 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4340 * all limits and the gpu stuck at whatever frequency it is at atm).
4342 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4346 /* Only set the down limit when we've reached the lowest level to avoid
4347 * getting more interrupts, otherwise leave this clear. This prevents a
4348 * race in the hw when coming out of rc6: There's a tiny window where
4349 * the hw runs at the minimal clock before selecting the desired
4350 * frequency, if the down threshold expires in that window we will not
4351 * receive a down interrupt. */
4352 if (IS_GEN9(dev_priv->dev)) {
4353 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4354 if (val <= dev_priv->rps.min_freq_softlimit)
4355 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4357 limits = dev_priv->rps.max_freq_softlimit << 24;
4358 if (val <= dev_priv->rps.min_freq_softlimit)
4359 limits |= dev_priv->rps.min_freq_softlimit << 16;
4365 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4368 u32 threshold_up = 0, threshold_down = 0; /* in % */
4369 u32 ei_up = 0, ei_down = 0;
4371 new_power = dev_priv->rps.power;
4372 switch (dev_priv->rps.power) {
4374 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4375 new_power = BETWEEN;
4379 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4380 new_power = LOW_POWER;
4381 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4382 new_power = HIGH_POWER;
4386 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4387 new_power = BETWEEN;
4390 /* Max/min bins are special */
4391 if (val <= dev_priv->rps.min_freq_softlimit)
4392 new_power = LOW_POWER;
4393 if (val >= dev_priv->rps.max_freq_softlimit)
4394 new_power = HIGH_POWER;
4395 if (new_power == dev_priv->rps.power)
4398 /* Note the units here are not exactly 1us, but 1280ns. */
4399 switch (new_power) {
4401 /* Upclock if more than 95% busy over 16ms */
4405 /* Downclock if less than 85% busy over 32ms */
4407 threshold_down = 85;
4411 /* Upclock if more than 90% busy over 13ms */
4415 /* Downclock if less than 75% busy over 32ms */
4417 threshold_down = 75;
4421 /* Upclock if more than 85% busy over 10ms */
4425 /* Downclock if less than 60% busy over 32ms */
4427 threshold_down = 60;
4431 I915_WRITE(GEN6_RP_UP_EI,
4432 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4433 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4434 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4436 I915_WRITE(GEN6_RP_DOWN_EI,
4437 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4438 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4439 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4441 I915_WRITE(GEN6_RP_CONTROL,
4442 GEN6_RP_MEDIA_TURBO |
4443 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4444 GEN6_RP_MEDIA_IS_GFX |
4446 GEN6_RP_UP_BUSY_AVG |
4447 GEN6_RP_DOWN_IDLE_AVG);
4449 dev_priv->rps.power = new_power;
4450 dev_priv->rps.up_threshold = threshold_up;
4451 dev_priv->rps.down_threshold = threshold_down;
4452 dev_priv->rps.last_adj = 0;
4455 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4459 if (val > dev_priv->rps.min_freq_softlimit)
4460 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4461 if (val < dev_priv->rps.max_freq_softlimit)
4462 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4464 mask &= dev_priv->pm_rps_events;
4466 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4469 /* gen6_set_rps is called to update the frequency request, but should also be
4470 * called when the range (min_delay and max_delay) is modified so that we can
4471 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4472 static void gen6_set_rps(struct drm_device *dev, u8 val)
4474 struct drm_i915_private *dev_priv = dev->dev_private;
4476 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4477 WARN_ON(val > dev_priv->rps.max_freq);
4478 WARN_ON(val < dev_priv->rps.min_freq);
4480 /* min/max delay may still have been modified so be sure to
4481 * write the limits value.
4483 if (val != dev_priv->rps.cur_freq) {
4484 gen6_set_rps_thresholds(dev_priv, val);
4487 I915_WRITE(GEN6_RPNSWREQ,
4488 GEN9_FREQUENCY(val));
4489 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4490 I915_WRITE(GEN6_RPNSWREQ,
4491 HSW_FREQUENCY(val));
4493 I915_WRITE(GEN6_RPNSWREQ,
4494 GEN6_FREQUENCY(val) |
4496 GEN6_AGGRESSIVE_TURBO);
4499 /* Make sure we continue to get interrupts
4500 * until we hit the minimum or maximum frequencies.
4502 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4503 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4505 POSTING_READ(GEN6_RPNSWREQ);
4507 dev_priv->rps.cur_freq = val;
4508 trace_intel_gpu_freq_change(val * 50);
4511 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4513 struct drm_i915_private *dev_priv = dev->dev_private;
4515 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4516 WARN_ON(val > dev_priv->rps.max_freq);
4517 WARN_ON(val < dev_priv->rps.min_freq);
4519 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4520 "Odd GPU freq value\n"))
4523 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4525 if (val != dev_priv->rps.cur_freq) {
4526 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4527 if (!IS_CHERRYVIEW(dev_priv))
4528 gen6_set_rps_thresholds(dev_priv, val);
4531 dev_priv->rps.cur_freq = val;
4532 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4535 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4537 * * If Gfx is Idle, then
4538 * 1. Forcewake Media well.
4539 * 2. Request idle freq.
4540 * 3. Release Forcewake of Media well.
4542 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4544 u32 val = dev_priv->rps.idle_freq;
4546 if (dev_priv->rps.cur_freq <= val)
4549 /* Wake up the media well, as that takes a lot less
4550 * power than the Render well. */
4551 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4552 valleyview_set_rps(dev_priv->dev, val);
4553 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4556 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4558 mutex_lock(&dev_priv->rps.hw_lock);
4559 if (dev_priv->rps.enabled) {
4560 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4561 gen6_rps_reset_ei(dev_priv);
4562 I915_WRITE(GEN6_PMINTRMSK,
4563 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4565 mutex_unlock(&dev_priv->rps.hw_lock);
4568 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4570 struct drm_device *dev = dev_priv->dev;
4572 mutex_lock(&dev_priv->rps.hw_lock);
4573 if (dev_priv->rps.enabled) {
4574 if (IS_VALLEYVIEW(dev))
4575 vlv_set_rps_idle(dev_priv);
4577 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4578 dev_priv->rps.last_adj = 0;
4579 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4581 mutex_unlock(&dev_priv->rps.hw_lock);
4583 spin_lock(&dev_priv->rps.client_lock);
4584 while (!list_empty(&dev_priv->rps.clients))
4585 list_del_init(dev_priv->rps.clients.next);
4586 spin_unlock(&dev_priv->rps.client_lock);
4589 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4590 struct intel_rps_client *rps,
4591 unsigned long submitted)
4593 /* This is intentionally racy! We peek at the state here, then
4594 * validate inside the RPS worker.
4596 if (!(dev_priv->mm.busy &&
4597 dev_priv->rps.enabled &&
4598 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4601 /* Force a RPS boost (and don't count it against the client) if
4602 * the GPU is severely congested.
4604 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4607 spin_lock(&dev_priv->rps.client_lock);
4608 if (rps == NULL || list_empty(&rps->link)) {
4609 spin_lock_irq(&dev_priv->irq_lock);
4610 if (dev_priv->rps.interrupts_enabled) {
4611 dev_priv->rps.client_boost = true;
4612 queue_work(dev_priv->wq, &dev_priv->rps.work);
4614 spin_unlock_irq(&dev_priv->irq_lock);
4617 list_add(&rps->link, &dev_priv->rps.clients);
4620 dev_priv->rps.boosts++;
4622 spin_unlock(&dev_priv->rps.client_lock);
4625 void intel_set_rps(struct drm_device *dev, u8 val)
4627 if (IS_VALLEYVIEW(dev))
4628 valleyview_set_rps(dev, val);
4630 gen6_set_rps(dev, val);
4633 static void gen9_disable_rps(struct drm_device *dev)
4635 struct drm_i915_private *dev_priv = dev->dev_private;
4637 I915_WRITE(GEN6_RC_CONTROL, 0);
4638 I915_WRITE(GEN9_PG_ENABLE, 0);
4641 static void gen6_disable_rps(struct drm_device *dev)
4643 struct drm_i915_private *dev_priv = dev->dev_private;
4645 I915_WRITE(GEN6_RC_CONTROL, 0);
4646 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4649 static void cherryview_disable_rps(struct drm_device *dev)
4651 struct drm_i915_private *dev_priv = dev->dev_private;
4653 I915_WRITE(GEN6_RC_CONTROL, 0);
4656 static void valleyview_disable_rps(struct drm_device *dev)
4658 struct drm_i915_private *dev_priv = dev->dev_private;
4660 /* we're doing forcewake before Disabling RC6,
4661 * This what the BIOS expects when going into suspend */
4662 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4664 I915_WRITE(GEN6_RC_CONTROL, 0);
4666 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4669 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4671 if (IS_VALLEYVIEW(dev)) {
4672 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4673 mode = GEN6_RC_CTL_RC6_ENABLE;
4678 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4679 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4680 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4681 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4684 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4685 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4688 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4690 /* No RC6 before Ironlake and code is gone for ilk. */
4691 if (INTEL_INFO(dev)->gen < 6)
4694 /* Respect the kernel parameter if it is set */
4695 if (enable_rc6 >= 0) {
4699 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4702 mask = INTEL_RC6_ENABLE;
4704 if ((enable_rc6 & mask) != enable_rc6)
4705 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4706 enable_rc6 & mask, enable_rc6, mask);
4708 return enable_rc6 & mask;
4711 if (IS_IVYBRIDGE(dev))
4712 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4714 return INTEL_RC6_ENABLE;
4717 int intel_enable_rc6(const struct drm_device *dev)
4719 return i915.enable_rc6;
4722 static void gen6_init_rps_frequencies(struct drm_device *dev)
4724 struct drm_i915_private *dev_priv = dev->dev_private;
4725 uint32_t rp_state_cap;
4726 u32 ddcc_status = 0;
4729 /* All of these values are in units of 50MHz */
4730 dev_priv->rps.cur_freq = 0;
4731 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4732 if (IS_BROXTON(dev)) {
4733 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4734 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4735 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4736 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4738 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4739 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4740 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4741 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4744 /* hw_max = RP0 until we check for overclocking */
4745 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4747 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4748 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
4749 ret = sandybridge_pcode_read(dev_priv,
4750 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4753 dev_priv->rps.efficient_freq =
4755 ((ddcc_status >> 8) & 0xff),
4756 dev_priv->rps.min_freq,
4757 dev_priv->rps.max_freq);
4760 if (IS_SKYLAKE(dev)) {
4761 /* Store the frequency values in 16.66 MHZ units, which is
4762 the natural hardware unit for SKL */
4763 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4764 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4765 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4766 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4767 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4770 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4772 /* Preserve min/max settings in case of re-init */
4773 if (dev_priv->rps.max_freq_softlimit == 0)
4774 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4776 if (dev_priv->rps.min_freq_softlimit == 0) {
4777 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4778 dev_priv->rps.min_freq_softlimit =
4779 max_t(int, dev_priv->rps.efficient_freq,
4780 intel_freq_opcode(dev_priv, 450));
4782 dev_priv->rps.min_freq_softlimit =
4783 dev_priv->rps.min_freq;
4787 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4788 static void gen9_enable_rps(struct drm_device *dev)
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4792 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4794 gen6_init_rps_frequencies(dev);
4796 /* Program defaults and thresholds for RPS*/
4797 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4798 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4800 /* 1 second timeout*/
4801 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4802 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4804 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4806 /* Leaning on the below call to gen6_set_rps to program/setup the
4807 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4808 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4809 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4810 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4812 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4815 static void gen9_enable_rc6(struct drm_device *dev)
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4818 struct intel_engine_cs *ring;
4819 uint32_t rc6_mask = 0;
4822 /* 1a: Software RC state - RC0 */
4823 I915_WRITE(GEN6_RC_STATE, 0);
4825 /* 1b: Get forcewake during program sequence. Although the driver
4826 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4827 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4829 /* 2a: Disable RC states. */
4830 I915_WRITE(GEN6_RC_CONTROL, 0);
4832 /* 2b: Program RC6 thresholds.*/
4833 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4834 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4835 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4836 for_each_ring(ring, dev_priv, unused)
4837 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4838 I915_WRITE(GEN6_RC_SLEEP, 0);
4839 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4841 /* 2c: Program Coarse Power Gating Policies. */
4842 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4843 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4845 /* 3a: Enable RC6 */
4846 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4847 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4848 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4850 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4851 GEN6_RC_CTL_EI_MODE(1) |
4855 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4856 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
4858 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4859 GEN9_MEDIA_PG_ENABLE : 0);
4862 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4866 static void gen8_enable_rps(struct drm_device *dev)
4868 struct drm_i915_private *dev_priv = dev->dev_private;
4869 struct intel_engine_cs *ring;
4870 uint32_t rc6_mask = 0;
4873 /* 1a: Software RC state - RC0 */
4874 I915_WRITE(GEN6_RC_STATE, 0);
4876 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4877 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4878 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4880 /* 2a: Disable RC states. */
4881 I915_WRITE(GEN6_RC_CONTROL, 0);
4883 /* Initialize rps frequencies */
4884 gen6_init_rps_frequencies(dev);
4886 /* 2b: Program RC6 thresholds.*/
4887 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4888 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4889 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4890 for_each_ring(ring, dev_priv, unused)
4891 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4892 I915_WRITE(GEN6_RC_SLEEP, 0);
4893 if (IS_BROADWELL(dev))
4894 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4896 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4899 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4900 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4901 intel_print_rc6_info(dev, rc6_mask);
4902 if (IS_BROADWELL(dev))
4903 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4904 GEN7_RC_CTL_TO_MODE |
4907 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4908 GEN6_RC_CTL_EI_MODE(1) |
4911 /* 4 Program defaults and thresholds for RPS*/
4912 I915_WRITE(GEN6_RPNSWREQ,
4913 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4914 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4915 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4916 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4917 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4919 /* Docs recommend 900MHz, and 300 MHz respectively */
4920 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4921 dev_priv->rps.max_freq_softlimit << 24 |
4922 dev_priv->rps.min_freq_softlimit << 16);
4924 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4925 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4926 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4927 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4929 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4932 I915_WRITE(GEN6_RP_CONTROL,
4933 GEN6_RP_MEDIA_TURBO |
4934 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4935 GEN6_RP_MEDIA_IS_GFX |
4937 GEN6_RP_UP_BUSY_AVG |
4938 GEN6_RP_DOWN_IDLE_AVG);
4940 /* 6: Ring frequency + overclocking (our driver does this later */
4942 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4943 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4945 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4948 static void gen6_enable_rps(struct drm_device *dev)
4950 struct drm_i915_private *dev_priv = dev->dev_private;
4951 struct intel_engine_cs *ring;
4952 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4957 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4959 /* Here begins a magic sequence of register writes to enable
4960 * auto-downclocking.
4962 * Perhaps there might be some value in exposing these to
4965 I915_WRITE(GEN6_RC_STATE, 0);
4967 /* Clear the DBG now so we don't confuse earlier errors */
4968 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4969 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4970 I915_WRITE(GTFIFODBG, gtfifodbg);
4973 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4975 /* Initialize rps frequencies */
4976 gen6_init_rps_frequencies(dev);
4978 /* disable the counters and set deterministic thresholds */
4979 I915_WRITE(GEN6_RC_CONTROL, 0);
4981 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4982 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4983 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4984 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4985 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4987 for_each_ring(ring, dev_priv, i)
4988 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4990 I915_WRITE(GEN6_RC_SLEEP, 0);
4991 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4992 if (IS_IVYBRIDGE(dev))
4993 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4995 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4996 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4997 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4999 /* Check if we are enabling RC6 */
5000 rc6_mode = intel_enable_rc6(dev_priv->dev);
5001 if (rc6_mode & INTEL_RC6_ENABLE)
5002 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5004 /* We don't use those on Haswell */
5005 if (!IS_HASWELL(dev)) {
5006 if (rc6_mode & INTEL_RC6p_ENABLE)
5007 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5009 if (rc6_mode & INTEL_RC6pp_ENABLE)
5010 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5013 intel_print_rc6_info(dev, rc6_mask);
5015 I915_WRITE(GEN6_RC_CONTROL,
5017 GEN6_RC_CTL_EI_MODE(1) |
5018 GEN6_RC_CTL_HW_ENABLE);
5020 /* Power down if completely idle for over 50ms */
5021 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5022 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5024 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5026 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5028 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5029 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5030 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5031 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5032 (pcu_mbox & 0xff) * 50);
5033 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5036 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5037 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5040 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5041 if (IS_GEN6(dev) && ret) {
5042 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5043 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5044 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5045 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5046 rc6vids &= 0xffff00;
5047 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5048 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5050 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5053 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5056 static void __gen6_update_ring_freq(struct drm_device *dev)
5058 struct drm_i915_private *dev_priv = dev->dev_private;
5060 unsigned int gpu_freq;
5061 unsigned int max_ia_freq, min_ring_freq;
5062 unsigned int max_gpu_freq, min_gpu_freq;
5063 int scaling_factor = 180;
5064 struct cpufreq_policy *policy;
5066 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5068 policy = cpufreq_cpu_get(0);
5070 max_ia_freq = policy->cpuinfo.max_freq;
5071 cpufreq_cpu_put(policy);
5074 * Default to measured freq if none found, PCU will ensure we
5077 max_ia_freq = tsc_khz;
5080 /* Convert from kHz to MHz */
5081 max_ia_freq /= 1000;
5083 min_ring_freq = I915_READ(DCLK) & 0xf;
5084 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5085 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5087 if (IS_SKYLAKE(dev)) {
5088 /* Convert GT frequency to 50 HZ units */
5089 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5090 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5092 min_gpu_freq = dev_priv->rps.min_freq;
5093 max_gpu_freq = dev_priv->rps.max_freq;
5097 * For each potential GPU frequency, load a ring frequency we'd like
5098 * to use for memory access. We do this by specifying the IA frequency
5099 * the PCU should use as a reference to determine the ring frequency.
5101 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5102 int diff = max_gpu_freq - gpu_freq;
5103 unsigned int ia_freq = 0, ring_freq = 0;
5105 if (IS_SKYLAKE(dev)) {
5107 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5108 * No floor required for ring frequency on SKL.
5110 ring_freq = gpu_freq;
5111 } else if (INTEL_INFO(dev)->gen >= 8) {
5112 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5113 ring_freq = max(min_ring_freq, gpu_freq);
5114 } else if (IS_HASWELL(dev)) {
5115 ring_freq = mult_frac(gpu_freq, 5, 4);
5116 ring_freq = max(min_ring_freq, ring_freq);
5117 /* leave ia_freq as the default, chosen by cpufreq */
5119 /* On older processors, there is no separate ring
5120 * clock domain, so in order to boost the bandwidth
5121 * of the ring, we need to upclock the CPU (ia_freq).
5123 * For GPU frequencies less than 750MHz,
5124 * just use the lowest ring freq.
5126 if (gpu_freq < min_freq)
5129 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5130 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5133 sandybridge_pcode_write(dev_priv,
5134 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5135 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5136 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5141 void gen6_update_ring_freq(struct drm_device *dev)
5143 struct drm_i915_private *dev_priv = dev->dev_private;
5145 if (!HAS_CORE_RING_FREQ(dev))
5148 mutex_lock(&dev_priv->rps.hw_lock);
5149 __gen6_update_ring_freq(dev);
5150 mutex_unlock(&dev_priv->rps.hw_lock);
5153 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5155 struct drm_device *dev = dev_priv->dev;
5158 if (dev->pdev->revision >= 0x20) {
5159 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5161 switch (INTEL_INFO(dev)->eu_total) {
5163 /* (2 * 4) config */
5164 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5167 /* (2 * 6) config */
5168 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5171 /* (2 * 8) config */
5173 /* Setting (2 * 8) Min RP0 for any other combination */
5174 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5177 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5179 /* For pre-production hardware */
5180 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5181 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5182 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5187 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5191 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5192 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5197 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5199 struct drm_device *dev = dev_priv->dev;
5202 if (dev->pdev->revision >= 0x20) {
5203 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5204 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5206 /* For pre-production hardware */
5207 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5208 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5209 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5214 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5218 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5220 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5225 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5229 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5231 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5233 rp0 = min_t(u32, rp0, 0xea);
5238 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5242 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5243 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5244 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5245 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5250 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5252 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5255 /* Check that the pctx buffer wasn't move under us. */
5256 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5258 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5260 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5261 dev_priv->vlv_pctx->stolen->start);
5265 /* Check that the pcbr address is not empty. */
5266 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5268 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5270 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5273 static void cherryview_setup_pctx(struct drm_device *dev)
5275 struct drm_i915_private *dev_priv = dev->dev_private;
5276 unsigned long pctx_paddr, paddr;
5277 struct i915_gtt *gtt = &dev_priv->gtt;
5279 int pctx_size = 32*1024;
5281 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5283 pcbr = I915_READ(VLV_PCBR);
5284 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5285 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5286 paddr = (dev_priv->mm.stolen_base +
5287 (gtt->stolen_size - pctx_size));
5289 pctx_paddr = (paddr & (~4095));
5290 I915_WRITE(VLV_PCBR, pctx_paddr);
5293 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5296 static void valleyview_setup_pctx(struct drm_device *dev)
5298 struct drm_i915_private *dev_priv = dev->dev_private;
5299 struct drm_i915_gem_object *pctx;
5300 unsigned long pctx_paddr;
5302 int pctx_size = 24*1024;
5304 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5306 pcbr = I915_READ(VLV_PCBR);
5308 /* BIOS set it up already, grab the pre-alloc'd space */
5311 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5312 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5314 I915_GTT_OFFSET_NONE,
5319 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5322 * From the Gunit register HAS:
5323 * The Gfx driver is expected to program this register and ensure
5324 * proper allocation within Gfx stolen memory. For example, this
5325 * register should be programmed such than the PCBR range does not
5326 * overlap with other ranges, such as the frame buffer, protected
5327 * memory, or any other relevant ranges.
5329 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5331 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5335 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5336 I915_WRITE(VLV_PCBR, pctx_paddr);
5339 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5340 dev_priv->vlv_pctx = pctx;
5343 static void valleyview_cleanup_pctx(struct drm_device *dev)
5345 struct drm_i915_private *dev_priv = dev->dev_private;
5347 if (WARN_ON(!dev_priv->vlv_pctx))
5350 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5351 dev_priv->vlv_pctx = NULL;
5354 static void valleyview_init_gt_powersave(struct drm_device *dev)
5356 struct drm_i915_private *dev_priv = dev->dev_private;
5359 valleyview_setup_pctx(dev);
5361 mutex_lock(&dev_priv->rps.hw_lock);
5363 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5364 switch ((val >> 6) & 3) {
5367 dev_priv->mem_freq = 800;
5370 dev_priv->mem_freq = 1066;
5373 dev_priv->mem_freq = 1333;
5376 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5378 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5379 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5380 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5381 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5382 dev_priv->rps.max_freq);
5384 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5385 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5386 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5387 dev_priv->rps.efficient_freq);
5389 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5390 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5391 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5392 dev_priv->rps.rp1_freq);
5394 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5395 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5396 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5397 dev_priv->rps.min_freq);
5399 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5401 /* Preserve min/max settings in case of re-init */
5402 if (dev_priv->rps.max_freq_softlimit == 0)
5403 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5405 if (dev_priv->rps.min_freq_softlimit == 0)
5406 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5408 mutex_unlock(&dev_priv->rps.hw_lock);
5411 static void cherryview_init_gt_powersave(struct drm_device *dev)
5413 struct drm_i915_private *dev_priv = dev->dev_private;
5416 cherryview_setup_pctx(dev);
5418 mutex_lock(&dev_priv->rps.hw_lock);
5420 mutex_lock(&dev_priv->sb_lock);
5421 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5422 mutex_unlock(&dev_priv->sb_lock);
5424 switch ((val >> 2) & 0x7) {
5427 dev_priv->rps.cz_freq = 200;
5428 dev_priv->mem_freq = 1600;
5431 dev_priv->rps.cz_freq = 267;
5432 dev_priv->mem_freq = 1600;
5435 dev_priv->rps.cz_freq = 333;
5436 dev_priv->mem_freq = 2000;
5439 dev_priv->rps.cz_freq = 320;
5440 dev_priv->mem_freq = 1600;
5443 dev_priv->rps.cz_freq = 400;
5444 dev_priv->mem_freq = 1600;
5447 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5449 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5450 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5451 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5452 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5453 dev_priv->rps.max_freq);
5455 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5456 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5457 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5458 dev_priv->rps.efficient_freq);
5460 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5461 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5462 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5463 dev_priv->rps.rp1_freq);
5465 /* PUnit validated range is only [RPe, RP0] */
5466 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5467 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5468 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5469 dev_priv->rps.min_freq);
5471 WARN_ONCE((dev_priv->rps.max_freq |
5472 dev_priv->rps.efficient_freq |
5473 dev_priv->rps.rp1_freq |
5474 dev_priv->rps.min_freq) & 1,
5475 "Odd GPU freq values\n");
5477 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5479 /* Preserve min/max settings in case of re-init */
5480 if (dev_priv->rps.max_freq_softlimit == 0)
5481 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5483 if (dev_priv->rps.min_freq_softlimit == 0)
5484 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5486 mutex_unlock(&dev_priv->rps.hw_lock);
5489 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5491 valleyview_cleanup_pctx(dev);
5494 static void cherryview_enable_rps(struct drm_device *dev)
5496 struct drm_i915_private *dev_priv = dev->dev_private;
5497 struct intel_engine_cs *ring;
5498 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5501 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5503 gtfifodbg = I915_READ(GTFIFODBG);
5505 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5507 I915_WRITE(GTFIFODBG, gtfifodbg);
5510 cherryview_check_pctx(dev_priv);
5512 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5513 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5514 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5516 /* Disable RC states. */
5517 I915_WRITE(GEN6_RC_CONTROL, 0);
5519 /* 2a: Program RC6 thresholds.*/
5520 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5521 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5522 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5524 for_each_ring(ring, dev_priv, i)
5525 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5526 I915_WRITE(GEN6_RC_SLEEP, 0);
5528 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5529 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5531 /* allows RC6 residency counter to work */
5532 I915_WRITE(VLV_COUNTER_CONTROL,
5533 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5534 VLV_MEDIA_RC6_COUNT_EN |
5535 VLV_RENDER_RC6_COUNT_EN));
5537 /* For now we assume BIOS is allocating and populating the PCBR */
5538 pcbr = I915_READ(VLV_PCBR);
5541 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5542 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5543 rc6_mode = GEN7_RC_CTL_TO_MODE;
5545 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5547 /* 4 Program defaults and thresholds for RPS*/
5548 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5549 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5550 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5551 I915_WRITE(GEN6_RP_UP_EI, 66000);
5552 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5554 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5557 I915_WRITE(GEN6_RP_CONTROL,
5558 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5559 GEN6_RP_MEDIA_IS_GFX |
5561 GEN6_RP_UP_BUSY_AVG |
5562 GEN6_RP_DOWN_IDLE_AVG);
5564 /* Setting Fixed Bias */
5565 val = VLV_OVERRIDE_EN |
5567 CHV_BIAS_CPU_50_SOC_50;
5568 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5570 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5572 /* RPS code assumes GPLL is used */
5573 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5575 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5576 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5578 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5579 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5580 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5581 dev_priv->rps.cur_freq);
5583 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5584 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5585 dev_priv->rps.efficient_freq);
5587 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5589 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5592 static void valleyview_enable_rps(struct drm_device *dev)
5594 struct drm_i915_private *dev_priv = dev->dev_private;
5595 struct intel_engine_cs *ring;
5596 u32 gtfifodbg, val, rc6_mode = 0;
5599 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5601 valleyview_check_pctx(dev_priv);
5603 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5604 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5606 I915_WRITE(GTFIFODBG, gtfifodbg);
5609 /* If VLV, Forcewake all wells, else re-direct to regular path */
5610 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5612 /* Disable RC states. */
5613 I915_WRITE(GEN6_RC_CONTROL, 0);
5615 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5616 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5617 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5618 I915_WRITE(GEN6_RP_UP_EI, 66000);
5619 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5621 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5623 I915_WRITE(GEN6_RP_CONTROL,
5624 GEN6_RP_MEDIA_TURBO |
5625 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5626 GEN6_RP_MEDIA_IS_GFX |
5628 GEN6_RP_UP_BUSY_AVG |
5629 GEN6_RP_DOWN_IDLE_CONT);
5631 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5632 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5633 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5635 for_each_ring(ring, dev_priv, i)
5636 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5638 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5640 /* allows RC6 residency counter to work */
5641 I915_WRITE(VLV_COUNTER_CONTROL,
5642 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5643 VLV_RENDER_RC0_COUNT_EN |
5644 VLV_MEDIA_RC6_COUNT_EN |
5645 VLV_RENDER_RC6_COUNT_EN));
5647 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5648 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5650 intel_print_rc6_info(dev, rc6_mode);
5652 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5654 /* Setting Fixed Bias */
5655 val = VLV_OVERRIDE_EN |
5657 VLV_BIAS_CPU_125_SOC_875;
5658 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5660 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5662 /* RPS code assumes GPLL is used */
5663 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5665 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5666 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5668 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5669 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5670 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5671 dev_priv->rps.cur_freq);
5673 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5674 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5675 dev_priv->rps.efficient_freq);
5677 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5679 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5682 static unsigned long intel_pxfreq(u32 vidfreq)
5685 int div = (vidfreq & 0x3f0000) >> 16;
5686 int post = (vidfreq & 0x3000) >> 12;
5687 int pre = (vidfreq & 0x7);
5692 freq = ((div * 133333) / ((1<<post) * pre));
5697 static const struct cparams {
5703 { 1, 1333, 301, 28664 },
5704 { 1, 1066, 294, 24460 },
5705 { 1, 800, 294, 25192 },
5706 { 0, 1333, 276, 27605 },
5707 { 0, 1066, 276, 27605 },
5708 { 0, 800, 231, 23784 },
5711 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5713 u64 total_count, diff, ret;
5714 u32 count1, count2, count3, m = 0, c = 0;
5715 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5718 assert_spin_locked(&mchdev_lock);
5720 diff1 = now - dev_priv->ips.last_time1;
5722 /* Prevent division-by-zero if we are asking too fast.
5723 * Also, we don't get interesting results if we are polling
5724 * faster than once in 10ms, so just return the saved value
5728 return dev_priv->ips.chipset_power;
5730 count1 = I915_READ(DMIEC);
5731 count2 = I915_READ(DDREC);
5732 count3 = I915_READ(CSIEC);
5734 total_count = count1 + count2 + count3;
5736 /* FIXME: handle per-counter overflow */
5737 if (total_count < dev_priv->ips.last_count1) {
5738 diff = ~0UL - dev_priv->ips.last_count1;
5739 diff += total_count;
5741 diff = total_count - dev_priv->ips.last_count1;
5744 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5745 if (cparams[i].i == dev_priv->ips.c_m &&
5746 cparams[i].t == dev_priv->ips.r_t) {
5753 diff = div_u64(diff, diff1);
5754 ret = ((m * diff) + c);
5755 ret = div_u64(ret, 10);
5757 dev_priv->ips.last_count1 = total_count;
5758 dev_priv->ips.last_time1 = now;
5760 dev_priv->ips.chipset_power = ret;
5765 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5767 struct drm_device *dev = dev_priv->dev;
5770 if (INTEL_INFO(dev)->gen != 5)
5773 spin_lock_irq(&mchdev_lock);
5775 val = __i915_chipset_val(dev_priv);
5777 spin_unlock_irq(&mchdev_lock);
5782 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5784 unsigned long m, x, b;
5787 tsfs = I915_READ(TSFS);
5789 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5790 x = I915_READ8(TR1);
5792 b = tsfs & TSFS_INTR_MASK;
5794 return ((m * x) / 127) - b;
5797 static int _pxvid_to_vd(u8 pxvid)
5802 if (pxvid >= 8 && pxvid < 31)
5805 return (pxvid + 2) * 125;
5808 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5810 struct drm_device *dev = dev_priv->dev;
5811 const int vd = _pxvid_to_vd(pxvid);
5812 const int vm = vd - 1125;
5814 if (INTEL_INFO(dev)->is_mobile)
5815 return vm > 0 ? vm : 0;
5820 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5822 u64 now, diff, diffms;
5825 assert_spin_locked(&mchdev_lock);
5827 now = ktime_get_raw_ns();
5828 diffms = now - dev_priv->ips.last_time2;
5829 do_div(diffms, NSEC_PER_MSEC);
5831 /* Don't divide by 0 */
5835 count = I915_READ(GFXEC);
5837 if (count < dev_priv->ips.last_count2) {
5838 diff = ~0UL - dev_priv->ips.last_count2;
5841 diff = count - dev_priv->ips.last_count2;
5844 dev_priv->ips.last_count2 = count;
5845 dev_priv->ips.last_time2 = now;
5847 /* More magic constants... */
5849 diff = div_u64(diff, diffms * 10);
5850 dev_priv->ips.gfx_power = diff;
5853 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5855 struct drm_device *dev = dev_priv->dev;
5857 if (INTEL_INFO(dev)->gen != 5)
5860 spin_lock_irq(&mchdev_lock);
5862 __i915_update_gfx_val(dev_priv);
5864 spin_unlock_irq(&mchdev_lock);
5867 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5869 unsigned long t, corr, state1, corr2, state2;
5872 assert_spin_locked(&mchdev_lock);
5874 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
5875 pxvid = (pxvid >> 24) & 0x7f;
5876 ext_v = pvid_to_extvid(dev_priv, pxvid);
5880 t = i915_mch_val(dev_priv);
5882 /* Revel in the empirically derived constants */
5884 /* Correction factor in 1/100000 units */
5886 corr = ((t * 2349) + 135940);
5888 corr = ((t * 964) + 29317);
5890 corr = ((t * 301) + 1004);
5892 corr = corr * ((150142 * state1) / 10000 - 78642);
5894 corr2 = (corr * dev_priv->ips.corr);
5896 state2 = (corr2 * state1) / 10000;
5897 state2 /= 100; /* convert to mW */
5899 __i915_update_gfx_val(dev_priv);
5901 return dev_priv->ips.gfx_power + state2;
5904 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5906 struct drm_device *dev = dev_priv->dev;
5909 if (INTEL_INFO(dev)->gen != 5)
5912 spin_lock_irq(&mchdev_lock);
5914 val = __i915_gfx_val(dev_priv);
5916 spin_unlock_irq(&mchdev_lock);
5922 * i915_read_mch_val - return value for IPS use
5924 * Calculate and return a value for the IPS driver to use when deciding whether
5925 * we have thermal and power headroom to increase CPU or GPU power budget.
5927 unsigned long i915_read_mch_val(void)
5929 struct drm_i915_private *dev_priv;
5930 unsigned long chipset_val, graphics_val, ret = 0;
5932 spin_lock_irq(&mchdev_lock);
5935 dev_priv = i915_mch_dev;
5937 chipset_val = __i915_chipset_val(dev_priv);
5938 graphics_val = __i915_gfx_val(dev_priv);
5940 ret = chipset_val + graphics_val;
5943 spin_unlock_irq(&mchdev_lock);
5947 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5950 * i915_gpu_raise - raise GPU frequency limit
5952 * Raise the limit; IPS indicates we have thermal headroom.
5954 bool i915_gpu_raise(void)
5956 struct drm_i915_private *dev_priv;
5959 spin_lock_irq(&mchdev_lock);
5960 if (!i915_mch_dev) {
5964 dev_priv = i915_mch_dev;
5966 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5967 dev_priv->ips.max_delay--;
5970 spin_unlock_irq(&mchdev_lock);
5974 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5977 * i915_gpu_lower - lower GPU frequency limit
5979 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5980 * frequency maximum.
5982 bool i915_gpu_lower(void)
5984 struct drm_i915_private *dev_priv;
5987 spin_lock_irq(&mchdev_lock);
5988 if (!i915_mch_dev) {
5992 dev_priv = i915_mch_dev;
5994 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5995 dev_priv->ips.max_delay++;
5998 spin_unlock_irq(&mchdev_lock);
6002 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6005 * i915_gpu_busy - indicate GPU business to IPS
6007 * Tell the IPS driver whether or not the GPU is busy.
6009 bool i915_gpu_busy(void)
6011 struct drm_i915_private *dev_priv;
6012 struct intel_engine_cs *ring;
6016 spin_lock_irq(&mchdev_lock);
6019 dev_priv = i915_mch_dev;
6021 for_each_ring(ring, dev_priv, i)
6022 ret |= !list_empty(&ring->request_list);
6025 spin_unlock_irq(&mchdev_lock);
6029 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6032 * i915_gpu_turbo_disable - disable graphics turbo
6034 * Disable graphics turbo by resetting the max frequency and setting the
6035 * current frequency to the default.
6037 bool i915_gpu_turbo_disable(void)
6039 struct drm_i915_private *dev_priv;
6042 spin_lock_irq(&mchdev_lock);
6043 if (!i915_mch_dev) {
6047 dev_priv = i915_mch_dev;
6049 dev_priv->ips.max_delay = dev_priv->ips.fstart;
6051 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6055 spin_unlock_irq(&mchdev_lock);
6059 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6062 * Tells the intel_ips driver that the i915 driver is now loaded, if
6063 * IPS got loaded first.
6065 * This awkward dance is so that neither module has to depend on the
6066 * other in order for IPS to do the appropriate communication of
6067 * GPU turbo limits to i915.
6070 ips_ping_for_i915_load(void)
6074 link = symbol_get(ips_link_to_i915_driver);
6077 symbol_put(ips_link_to_i915_driver);
6081 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6083 /* We only register the i915 ips part with intel-ips once everything is
6084 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6085 spin_lock_irq(&mchdev_lock);
6086 i915_mch_dev = dev_priv;
6087 spin_unlock_irq(&mchdev_lock);
6089 ips_ping_for_i915_load();
6092 void intel_gpu_ips_teardown(void)
6094 spin_lock_irq(&mchdev_lock);
6095 i915_mch_dev = NULL;
6096 spin_unlock_irq(&mchdev_lock);
6099 static void intel_init_emon(struct drm_device *dev)
6101 struct drm_i915_private *dev_priv = dev->dev_private;
6106 /* Disable to program */
6110 /* Program energy weights for various events */
6111 I915_WRITE(SDEW, 0x15040d00);
6112 I915_WRITE(CSIEW0, 0x007f0000);
6113 I915_WRITE(CSIEW1, 0x1e220004);
6114 I915_WRITE(CSIEW2, 0x04000004);
6116 for (i = 0; i < 5; i++)
6117 I915_WRITE(PEW + (i * 4), 0);
6118 for (i = 0; i < 3; i++)
6119 I915_WRITE(DEW + (i * 4), 0);
6121 /* Program P-state weights to account for frequency power adjustment */
6122 for (i = 0; i < 16; i++) {
6123 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6124 unsigned long freq = intel_pxfreq(pxvidfreq);
6125 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6130 val *= (freq / 1000);
6132 val /= (127*127*900);
6134 DRM_ERROR("bad pxval: %ld\n", val);
6137 /* Render standby states get 0 weight */
6141 for (i = 0; i < 4; i++) {
6142 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6143 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6144 I915_WRITE(PXW + (i * 4), val);
6147 /* Adjust magic regs to magic values (more experimental results) */
6148 I915_WRITE(OGW0, 0);
6149 I915_WRITE(OGW1, 0);
6150 I915_WRITE(EG0, 0x00007f00);
6151 I915_WRITE(EG1, 0x0000000e);
6152 I915_WRITE(EG2, 0x000e0000);
6153 I915_WRITE(EG3, 0x68000300);
6154 I915_WRITE(EG4, 0x42000000);
6155 I915_WRITE(EG5, 0x00140031);
6159 for (i = 0; i < 8; i++)
6160 I915_WRITE(PXWL + (i * 4), 0);
6162 /* Enable PMON + select events */
6163 I915_WRITE(ECR, 0x80000019);
6165 lcfuse = I915_READ(LCFUSE02);
6167 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6170 void intel_init_gt_powersave(struct drm_device *dev)
6172 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6174 if (IS_CHERRYVIEW(dev))
6175 cherryview_init_gt_powersave(dev);
6176 else if (IS_VALLEYVIEW(dev))
6177 valleyview_init_gt_powersave(dev);
6180 void intel_cleanup_gt_powersave(struct drm_device *dev)
6182 if (IS_CHERRYVIEW(dev))
6184 else if (IS_VALLEYVIEW(dev))
6185 valleyview_cleanup_gt_powersave(dev);
6188 static void gen6_suspend_rps(struct drm_device *dev)
6190 struct drm_i915_private *dev_priv = dev->dev_private;
6192 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6194 gen6_disable_rps_interrupts(dev);
6198 * intel_suspend_gt_powersave - suspend PM work and helper threads
6201 * We don't want to disable RC6 or other features here, we just want
6202 * to make sure any work we've queued has finished and won't bother
6203 * us while we're suspended.
6205 void intel_suspend_gt_powersave(struct drm_device *dev)
6207 struct drm_i915_private *dev_priv = dev->dev_private;
6209 if (INTEL_INFO(dev)->gen < 6)
6212 gen6_suspend_rps(dev);
6214 /* Force GPU to min freq during suspend */
6215 gen6_rps_idle(dev_priv);
6218 void intel_disable_gt_powersave(struct drm_device *dev)
6220 struct drm_i915_private *dev_priv = dev->dev_private;
6222 if (IS_IRONLAKE_M(dev)) {
6223 ironlake_disable_drps(dev);
6224 } else if (INTEL_INFO(dev)->gen >= 6) {
6225 intel_suspend_gt_powersave(dev);
6227 mutex_lock(&dev_priv->rps.hw_lock);
6228 if (INTEL_INFO(dev)->gen >= 9)
6229 gen9_disable_rps(dev);
6230 else if (IS_CHERRYVIEW(dev))
6231 cherryview_disable_rps(dev);
6232 else if (IS_VALLEYVIEW(dev))
6233 valleyview_disable_rps(dev);
6235 gen6_disable_rps(dev);
6237 dev_priv->rps.enabled = false;
6238 mutex_unlock(&dev_priv->rps.hw_lock);
6242 static void intel_gen6_powersave_work(struct work_struct *work)
6244 struct drm_i915_private *dev_priv =
6245 container_of(work, struct drm_i915_private,
6246 rps.delayed_resume_work.work);
6247 struct drm_device *dev = dev_priv->dev;
6249 mutex_lock(&dev_priv->rps.hw_lock);
6251 gen6_reset_rps_interrupts(dev);
6253 if (IS_CHERRYVIEW(dev)) {
6254 cherryview_enable_rps(dev);
6255 } else if (IS_VALLEYVIEW(dev)) {
6256 valleyview_enable_rps(dev);
6257 } else if (INTEL_INFO(dev)->gen >= 9) {
6258 gen9_enable_rc6(dev);
6259 gen9_enable_rps(dev);
6260 if (IS_SKYLAKE(dev))
6261 __gen6_update_ring_freq(dev);
6262 } else if (IS_BROADWELL(dev)) {
6263 gen8_enable_rps(dev);
6264 __gen6_update_ring_freq(dev);
6266 gen6_enable_rps(dev);
6267 __gen6_update_ring_freq(dev);
6270 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6271 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6273 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6274 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6276 dev_priv->rps.enabled = true;
6278 gen6_enable_rps_interrupts(dev);
6280 mutex_unlock(&dev_priv->rps.hw_lock);
6282 intel_runtime_pm_put(dev_priv);
6285 void intel_enable_gt_powersave(struct drm_device *dev)
6287 struct drm_i915_private *dev_priv = dev->dev_private;
6289 /* Powersaving is controlled by the host when inside a VM */
6290 if (intel_vgpu_active(dev))
6293 if (IS_IRONLAKE_M(dev)) {
6294 mutex_lock(&dev->struct_mutex);
6295 ironlake_enable_drps(dev);
6296 intel_init_emon(dev);
6297 mutex_unlock(&dev->struct_mutex);
6298 } else if (INTEL_INFO(dev)->gen >= 6) {
6300 * PCU communication is slow and this doesn't need to be
6301 * done at any specific time, so do this out of our fast path
6302 * to make resume and init faster.
6304 * We depend on the HW RC6 power context save/restore
6305 * mechanism when entering D3 through runtime PM suspend. So
6306 * disable RPM until RPS/RC6 is properly setup. We can only
6307 * get here via the driver load/system resume/runtime resume
6308 * paths, so the _noresume version is enough (and in case of
6309 * runtime resume it's necessary).
6311 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6312 round_jiffies_up_relative(HZ)))
6313 intel_runtime_pm_get_noresume(dev_priv);
6317 void intel_reset_gt_powersave(struct drm_device *dev)
6319 struct drm_i915_private *dev_priv = dev->dev_private;
6321 if (INTEL_INFO(dev)->gen < 6)
6324 gen6_suspend_rps(dev);
6325 dev_priv->rps.enabled = false;
6328 static void ibx_init_clock_gating(struct drm_device *dev)
6330 struct drm_i915_private *dev_priv = dev->dev_private;
6333 * On Ibex Peak and Cougar Point, we need to disable clock
6334 * gating for the panel power sequencer or it will fail to
6335 * start up when no ports are active.
6337 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6340 static void g4x_disable_trickle_feed(struct drm_device *dev)
6342 struct drm_i915_private *dev_priv = dev->dev_private;
6345 for_each_pipe(dev_priv, pipe) {
6346 I915_WRITE(DSPCNTR(pipe),
6347 I915_READ(DSPCNTR(pipe)) |
6348 DISPPLANE_TRICKLE_FEED_DISABLE);
6350 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6351 POSTING_READ(DSPSURF(pipe));
6355 static void ilk_init_lp_watermarks(struct drm_device *dev)
6357 struct drm_i915_private *dev_priv = dev->dev_private;
6359 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6360 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6361 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6364 * Don't touch WM1S_LP_EN here.
6365 * Doing so could cause underruns.
6369 static void ironlake_init_clock_gating(struct drm_device *dev)
6371 struct drm_i915_private *dev_priv = dev->dev_private;
6372 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6376 * WaFbcDisableDpfcClockGating:ilk
6378 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6379 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6380 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6382 I915_WRITE(PCH_3DCGDIS0,
6383 MARIUNIT_CLOCK_GATE_DISABLE |
6384 SVSMUNIT_CLOCK_GATE_DISABLE);
6385 I915_WRITE(PCH_3DCGDIS1,
6386 VFMUNIT_CLOCK_GATE_DISABLE);
6389 * According to the spec the following bits should be set in
6390 * order to enable memory self-refresh
6391 * The bit 22/21 of 0x42004
6392 * The bit 5 of 0x42020
6393 * The bit 15 of 0x45000
6395 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6396 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6397 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6398 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6399 I915_WRITE(DISP_ARB_CTL,
6400 (I915_READ(DISP_ARB_CTL) |
6403 ilk_init_lp_watermarks(dev);
6406 * Based on the document from hardware guys the following bits
6407 * should be set unconditionally in order to enable FBC.
6408 * The bit 22 of 0x42000
6409 * The bit 22 of 0x42004
6410 * The bit 7,8,9 of 0x42020.
6412 if (IS_IRONLAKE_M(dev)) {
6413 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6414 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6415 I915_READ(ILK_DISPLAY_CHICKEN1) |
6417 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6418 I915_READ(ILK_DISPLAY_CHICKEN2) |
6422 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6424 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6425 I915_READ(ILK_DISPLAY_CHICKEN2) |
6426 ILK_ELPIN_409_SELECT);
6427 I915_WRITE(_3D_CHICKEN2,
6428 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6429 _3D_CHICKEN2_WM_READ_PIPELINED);
6431 /* WaDisableRenderCachePipelinedFlush:ilk */
6432 I915_WRITE(CACHE_MODE_0,
6433 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6435 /* WaDisable_RenderCache_OperationalFlush:ilk */
6436 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6438 g4x_disable_trickle_feed(dev);
6440 ibx_init_clock_gating(dev);
6443 static void cpt_init_clock_gating(struct drm_device *dev)
6445 struct drm_i915_private *dev_priv = dev->dev_private;
6450 * On Ibex Peak and Cougar Point, we need to disable clock
6451 * gating for the panel power sequencer or it will fail to
6452 * start up when no ports are active.
6454 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6455 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6456 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6457 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6458 DPLS_EDP_PPS_FIX_DIS);
6459 /* The below fixes the weird display corruption, a few pixels shifted
6460 * downward, on (only) LVDS of some HP laptops with IVY.
6462 for_each_pipe(dev_priv, pipe) {
6463 val = I915_READ(TRANS_CHICKEN2(pipe));
6464 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6465 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6466 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6467 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6468 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6469 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6470 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6471 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6473 /* WADP0ClockGatingDisable */
6474 for_each_pipe(dev_priv, pipe) {
6475 I915_WRITE(TRANS_CHICKEN1(pipe),
6476 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6480 static void gen6_check_mch_setup(struct drm_device *dev)
6482 struct drm_i915_private *dev_priv = dev->dev_private;
6485 tmp = I915_READ(MCH_SSKPD);
6486 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6487 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6491 static void gen6_init_clock_gating(struct drm_device *dev)
6493 struct drm_i915_private *dev_priv = dev->dev_private;
6494 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6496 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6498 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6499 I915_READ(ILK_DISPLAY_CHICKEN2) |
6500 ILK_ELPIN_409_SELECT);
6502 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6503 I915_WRITE(_3D_CHICKEN,
6504 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6506 /* WaDisable_RenderCache_OperationalFlush:snb */
6507 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6510 * BSpec recoomends 8x4 when MSAA is used,
6511 * however in practice 16x4 seems fastest.
6513 * Note that PS/WM thread counts depend on the WIZ hashing
6514 * disable bit, which we don't touch here, but it's good
6515 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6517 I915_WRITE(GEN6_GT_MODE,
6518 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6520 ilk_init_lp_watermarks(dev);
6522 I915_WRITE(CACHE_MODE_0,
6523 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6525 I915_WRITE(GEN6_UCGCTL1,
6526 I915_READ(GEN6_UCGCTL1) |
6527 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6528 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6530 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6531 * gating disable must be set. Failure to set it results in
6532 * flickering pixels due to Z write ordering failures after
6533 * some amount of runtime in the Mesa "fire" demo, and Unigine
6534 * Sanctuary and Tropics, and apparently anything else with
6535 * alpha test or pixel discard.
6537 * According to the spec, bit 11 (RCCUNIT) must also be set,
6538 * but we didn't debug actual testcases to find it out.
6540 * WaDisableRCCUnitClockGating:snb
6541 * WaDisableRCPBUnitClockGating:snb
6543 I915_WRITE(GEN6_UCGCTL2,
6544 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6545 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6547 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6548 I915_WRITE(_3D_CHICKEN3,
6549 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6553 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6554 * 3DSTATE_SF number of SF output attributes is more than 16."
6556 I915_WRITE(_3D_CHICKEN3,
6557 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6560 * According to the spec the following bits should be
6561 * set in order to enable memory self-refresh and fbc:
6562 * The bit21 and bit22 of 0x42000
6563 * The bit21 and bit22 of 0x42004
6564 * The bit5 and bit7 of 0x42020
6565 * The bit14 of 0x70180
6566 * The bit14 of 0x71180
6568 * WaFbcAsynchFlipDisableFbcQueue:snb
6570 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6571 I915_READ(ILK_DISPLAY_CHICKEN1) |
6572 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6573 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6574 I915_READ(ILK_DISPLAY_CHICKEN2) |
6575 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6576 I915_WRITE(ILK_DSPCLK_GATE_D,
6577 I915_READ(ILK_DSPCLK_GATE_D) |
6578 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6579 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6581 g4x_disable_trickle_feed(dev);
6583 cpt_init_clock_gating(dev);
6585 gen6_check_mch_setup(dev);
6588 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6590 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6593 * WaVSThreadDispatchOverride:ivb,vlv
6595 * This actually overrides the dispatch
6596 * mode for all thread types.
6598 reg &= ~GEN7_FF_SCHED_MASK;
6599 reg |= GEN7_FF_TS_SCHED_HW;
6600 reg |= GEN7_FF_VS_SCHED_HW;
6601 reg |= GEN7_FF_DS_SCHED_HW;
6603 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6606 static void lpt_init_clock_gating(struct drm_device *dev)
6608 struct drm_i915_private *dev_priv = dev->dev_private;
6611 * TODO: this bit should only be enabled when really needed, then
6612 * disabled when not needed anymore in order to save power.
6614 if (HAS_PCH_LPT_LP(dev))
6615 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6616 I915_READ(SOUTH_DSPCLK_GATE_D) |
6617 PCH_LP_PARTITION_LEVEL_DISABLE);
6619 /* WADPOClockGatingDisable:hsw */
6620 I915_WRITE(_TRANSA_CHICKEN1,
6621 I915_READ(_TRANSA_CHICKEN1) |
6622 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6625 static void lpt_suspend_hw(struct drm_device *dev)
6627 struct drm_i915_private *dev_priv = dev->dev_private;
6629 if (HAS_PCH_LPT_LP(dev)) {
6630 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6632 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6633 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6637 static void broadwell_init_clock_gating(struct drm_device *dev)
6639 struct drm_i915_private *dev_priv = dev->dev_private;
6643 ilk_init_lp_watermarks(dev);
6645 /* WaSwitchSolVfFArbitrationPriority:bdw */
6646 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6648 /* WaPsrDPAMaskVBlankInSRD:bdw */
6649 I915_WRITE(CHICKEN_PAR1_1,
6650 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6652 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6653 for_each_pipe(dev_priv, pipe) {
6654 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6655 I915_READ(CHICKEN_PIPESL_1(pipe)) |
6656 BDW_DPRS_MASK_VBLANK_SRD);
6659 /* WaVSRefCountFullforceMissDisable:bdw */
6660 /* WaDSRefCountFullforceMissDisable:bdw */
6661 I915_WRITE(GEN7_FF_THREAD_MODE,
6662 I915_READ(GEN7_FF_THREAD_MODE) &
6663 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6665 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6666 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6668 /* WaDisableSDEUnitClockGating:bdw */
6669 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6670 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6673 * WaProgramL3SqcReg1Default:bdw
6674 * WaTempDisableDOPClkGating:bdw
6676 misccpctl = I915_READ(GEN7_MISCCPCTL);
6677 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6678 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6679 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6682 * WaGttCachingOffByDefault:bdw
6683 * GTT cache may not work with big pages, so if those
6684 * are ever enabled GTT cache may need to be disabled.
6686 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6688 lpt_init_clock_gating(dev);
6691 static void haswell_init_clock_gating(struct drm_device *dev)
6693 struct drm_i915_private *dev_priv = dev->dev_private;
6695 ilk_init_lp_watermarks(dev);
6697 /* L3 caching of data atomics doesn't work -- disable it. */
6698 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6699 I915_WRITE(HSW_ROW_CHICKEN3,
6700 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6702 /* This is required by WaCatErrorRejectionIssue:hsw */
6703 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6704 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6705 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6707 /* WaVSRefCountFullforceMissDisable:hsw */
6708 I915_WRITE(GEN7_FF_THREAD_MODE,
6709 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6711 /* WaDisable_RenderCache_OperationalFlush:hsw */
6712 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6714 /* enable HiZ Raw Stall Optimization */
6715 I915_WRITE(CACHE_MODE_0_GEN7,
6716 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6718 /* WaDisable4x2SubspanOptimization:hsw */
6719 I915_WRITE(CACHE_MODE_1,
6720 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6723 * BSpec recommends 8x4 when MSAA is used,
6724 * however in practice 16x4 seems fastest.
6726 * Note that PS/WM thread counts depend on the WIZ hashing
6727 * disable bit, which we don't touch here, but it's good
6728 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6730 I915_WRITE(GEN7_GT_MODE,
6731 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6733 /* WaSampleCChickenBitEnable:hsw */
6734 I915_WRITE(HALF_SLICE_CHICKEN3,
6735 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6737 /* WaSwitchSolVfFArbitrationPriority:hsw */
6738 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6740 /* WaRsPkgCStateDisplayPMReq:hsw */
6741 I915_WRITE(CHICKEN_PAR1_1,
6742 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6744 lpt_init_clock_gating(dev);
6747 static void ivybridge_init_clock_gating(struct drm_device *dev)
6749 struct drm_i915_private *dev_priv = dev->dev_private;
6752 ilk_init_lp_watermarks(dev);
6754 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6756 /* WaDisableEarlyCull:ivb */
6757 I915_WRITE(_3D_CHICKEN3,
6758 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6760 /* WaDisableBackToBackFlipFix:ivb */
6761 I915_WRITE(IVB_CHICKEN3,
6762 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6763 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6765 /* WaDisablePSDDualDispatchEnable:ivb */
6766 if (IS_IVB_GT1(dev))
6767 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6768 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6770 /* WaDisable_RenderCache_OperationalFlush:ivb */
6771 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6773 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6774 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6775 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6777 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6778 I915_WRITE(GEN7_L3CNTLREG1,
6779 GEN7_WA_FOR_GEN7_L3_CONTROL);
6780 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6781 GEN7_WA_L3_CHICKEN_MODE);
6782 if (IS_IVB_GT1(dev))
6783 I915_WRITE(GEN7_ROW_CHICKEN2,
6784 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6786 /* must write both registers */
6787 I915_WRITE(GEN7_ROW_CHICKEN2,
6788 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6789 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6790 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6793 /* WaForceL3Serialization:ivb */
6794 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6795 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6798 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6799 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6801 I915_WRITE(GEN6_UCGCTL2,
6802 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6804 /* This is required by WaCatErrorRejectionIssue:ivb */
6805 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6806 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6807 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6809 g4x_disable_trickle_feed(dev);
6811 gen7_setup_fixed_func_scheduler(dev_priv);
6813 if (0) { /* causes HiZ corruption on ivb:gt1 */
6814 /* enable HiZ Raw Stall Optimization */
6815 I915_WRITE(CACHE_MODE_0_GEN7,
6816 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6819 /* WaDisable4x2SubspanOptimization:ivb */
6820 I915_WRITE(CACHE_MODE_1,
6821 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6824 * BSpec recommends 8x4 when MSAA is used,
6825 * however in practice 16x4 seems fastest.
6827 * Note that PS/WM thread counts depend on the WIZ hashing
6828 * disable bit, which we don't touch here, but it's good
6829 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6831 I915_WRITE(GEN7_GT_MODE,
6832 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6834 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6835 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6836 snpcr |= GEN6_MBC_SNPCR_MED;
6837 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6839 if (!HAS_PCH_NOP(dev))
6840 cpt_init_clock_gating(dev);
6842 gen6_check_mch_setup(dev);
6845 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6847 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6850 * Disable trickle feed and enable pnd deadline calculation
6852 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6853 I915_WRITE(CBR1_VLV, 0);
6856 static void valleyview_init_clock_gating(struct drm_device *dev)
6858 struct drm_i915_private *dev_priv = dev->dev_private;
6860 vlv_init_display_clock_gating(dev_priv);
6862 /* WaDisableEarlyCull:vlv */
6863 I915_WRITE(_3D_CHICKEN3,
6864 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6866 /* WaDisableBackToBackFlipFix:vlv */
6867 I915_WRITE(IVB_CHICKEN3,
6868 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6869 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6871 /* WaPsdDispatchEnable:vlv */
6872 /* WaDisablePSDDualDispatchEnable:vlv */
6873 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6874 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6875 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6877 /* WaDisable_RenderCache_OperationalFlush:vlv */
6878 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6880 /* WaForceL3Serialization:vlv */
6881 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6882 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6884 /* WaDisableDopClockGating:vlv */
6885 I915_WRITE(GEN7_ROW_CHICKEN2,
6886 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6888 /* This is required by WaCatErrorRejectionIssue:vlv */
6889 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6890 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6891 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6893 gen7_setup_fixed_func_scheduler(dev_priv);
6896 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6897 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6899 I915_WRITE(GEN6_UCGCTL2,
6900 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6902 /* WaDisableL3Bank2xClockGate:vlv
6903 * Disabling L3 clock gating- MMIO 940c[25] = 1
6904 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6905 I915_WRITE(GEN7_UCGCTL4,
6906 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6909 * BSpec says this must be set, even though
6910 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6912 I915_WRITE(CACHE_MODE_1,
6913 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6916 * BSpec recommends 8x4 when MSAA is used,
6917 * however in practice 16x4 seems fastest.
6919 * Note that PS/WM thread counts depend on the WIZ hashing
6920 * disable bit, which we don't touch here, but it's good
6921 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6923 I915_WRITE(GEN7_GT_MODE,
6924 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6927 * WaIncreaseL3CreditsForVLVB0:vlv
6928 * This is the hardware default actually.
6930 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6933 * WaDisableVLVClockGating_VBIIssue:vlv
6934 * Disable clock gating on th GCFG unit to prevent a delay
6935 * in the reporting of vblank events.
6937 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6940 static void cherryview_init_clock_gating(struct drm_device *dev)
6942 struct drm_i915_private *dev_priv = dev->dev_private;
6944 vlv_init_display_clock_gating(dev_priv);
6946 /* WaVSRefCountFullforceMissDisable:chv */
6947 /* WaDSRefCountFullforceMissDisable:chv */
6948 I915_WRITE(GEN7_FF_THREAD_MODE,
6949 I915_READ(GEN7_FF_THREAD_MODE) &
6950 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6952 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6953 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6954 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6956 /* WaDisableCSUnitClockGating:chv */
6957 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6958 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6960 /* WaDisableSDEUnitClockGating:chv */
6961 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6962 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6965 * GTT cache may not work with big pages, so if those
6966 * are ever enabled GTT cache may need to be disabled.
6968 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6971 static void g4x_init_clock_gating(struct drm_device *dev)
6973 struct drm_i915_private *dev_priv = dev->dev_private;
6974 uint32_t dspclk_gate;
6976 I915_WRITE(RENCLK_GATE_D1, 0);
6977 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6978 GS_UNIT_CLOCK_GATE_DISABLE |
6979 CL_UNIT_CLOCK_GATE_DISABLE);
6980 I915_WRITE(RAMCLK_GATE_D, 0);
6981 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6982 OVRUNIT_CLOCK_GATE_DISABLE |
6983 OVCUNIT_CLOCK_GATE_DISABLE;
6985 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6986 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6988 /* WaDisableRenderCachePipelinedFlush */
6989 I915_WRITE(CACHE_MODE_0,
6990 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6992 /* WaDisable_RenderCache_OperationalFlush:g4x */
6993 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6995 g4x_disable_trickle_feed(dev);
6998 static void crestline_init_clock_gating(struct drm_device *dev)
7000 struct drm_i915_private *dev_priv = dev->dev_private;
7002 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7003 I915_WRITE(RENCLK_GATE_D2, 0);
7004 I915_WRITE(DSPCLK_GATE_D, 0);
7005 I915_WRITE(RAMCLK_GATE_D, 0);
7006 I915_WRITE16(DEUC, 0);
7007 I915_WRITE(MI_ARB_STATE,
7008 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7010 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7011 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7014 static void broadwater_init_clock_gating(struct drm_device *dev)
7016 struct drm_i915_private *dev_priv = dev->dev_private;
7018 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7019 I965_RCC_CLOCK_GATE_DISABLE |
7020 I965_RCPB_CLOCK_GATE_DISABLE |
7021 I965_ISC_CLOCK_GATE_DISABLE |
7022 I965_FBC_CLOCK_GATE_DISABLE);
7023 I915_WRITE(RENCLK_GATE_D2, 0);
7024 I915_WRITE(MI_ARB_STATE,
7025 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7027 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7028 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7031 static void gen3_init_clock_gating(struct drm_device *dev)
7033 struct drm_i915_private *dev_priv = dev->dev_private;
7034 u32 dstate = I915_READ(D_STATE);
7036 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7037 DSTATE_DOT_CLOCK_GATING;
7038 I915_WRITE(D_STATE, dstate);
7040 if (IS_PINEVIEW(dev))
7041 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7043 /* IIR "flip pending" means done if this bit is set */
7044 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7046 /* interrupts should cause a wake up from C3 */
7047 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7049 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7050 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7052 I915_WRITE(MI_ARB_STATE,
7053 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7056 static void i85x_init_clock_gating(struct drm_device *dev)
7058 struct drm_i915_private *dev_priv = dev->dev_private;
7060 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7062 /* interrupts should cause a wake up from C3 */
7063 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7064 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7066 I915_WRITE(MEM_MODE,
7067 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7070 static void i830_init_clock_gating(struct drm_device *dev)
7072 struct drm_i915_private *dev_priv = dev->dev_private;
7074 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7076 I915_WRITE(MEM_MODE,
7077 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7078 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7081 void intel_init_clock_gating(struct drm_device *dev)
7083 struct drm_i915_private *dev_priv = dev->dev_private;
7085 if (dev_priv->display.init_clock_gating)
7086 dev_priv->display.init_clock_gating(dev);
7089 void intel_suspend_hw(struct drm_device *dev)
7091 if (HAS_PCH_LPT(dev))
7092 lpt_suspend_hw(dev);
7095 /* Set up chip specific power management-related functions */
7096 void intel_init_pm(struct drm_device *dev)
7098 struct drm_i915_private *dev_priv = dev->dev_private;
7100 intel_fbc_init(dev_priv);
7103 if (IS_PINEVIEW(dev))
7104 i915_pineview_get_mem_freq(dev);
7105 else if (IS_GEN5(dev))
7106 i915_ironlake_get_mem_freq(dev);
7108 /* For FIFO watermark updates */
7109 if (INTEL_INFO(dev)->gen >= 9) {
7110 skl_setup_wm_latency(dev);
7112 if (IS_BROXTON(dev))
7113 dev_priv->display.init_clock_gating =
7114 bxt_init_clock_gating;
7115 else if (IS_SKYLAKE(dev))
7116 dev_priv->display.init_clock_gating =
7117 skl_init_clock_gating;
7118 dev_priv->display.update_wm = skl_update_wm;
7119 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
7120 } else if (HAS_PCH_SPLIT(dev)) {
7121 ilk_setup_wm_latency(dev);
7123 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7124 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7125 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7126 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7127 dev_priv->display.update_wm = ilk_update_wm;
7128 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7130 DRM_DEBUG_KMS("Failed to read display plane latency. "
7135 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7136 else if (IS_GEN6(dev))
7137 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7138 else if (IS_IVYBRIDGE(dev))
7139 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7140 else if (IS_HASWELL(dev))
7141 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7142 else if (INTEL_INFO(dev)->gen == 8)
7143 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7144 } else if (IS_CHERRYVIEW(dev)) {
7145 vlv_setup_wm_latency(dev);
7147 dev_priv->display.update_wm = vlv_update_wm;
7148 dev_priv->display.init_clock_gating =
7149 cherryview_init_clock_gating;
7150 } else if (IS_VALLEYVIEW(dev)) {
7151 vlv_setup_wm_latency(dev);
7153 dev_priv->display.update_wm = vlv_update_wm;
7154 dev_priv->display.init_clock_gating =
7155 valleyview_init_clock_gating;
7156 } else if (IS_PINEVIEW(dev)) {
7157 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7160 dev_priv->mem_freq)) {
7161 DRM_INFO("failed to find known CxSR latency "
7162 "(found ddr%s fsb freq %d, mem freq %d), "
7164 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7165 dev_priv->fsb_freq, dev_priv->mem_freq);
7166 /* Disable CxSR and never update its watermark again */
7167 intel_set_memory_cxsr(dev_priv, false);
7168 dev_priv->display.update_wm = NULL;
7170 dev_priv->display.update_wm = pineview_update_wm;
7171 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7172 } else if (IS_G4X(dev)) {
7173 dev_priv->display.update_wm = g4x_update_wm;
7174 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7175 } else if (IS_GEN4(dev)) {
7176 dev_priv->display.update_wm = i965_update_wm;
7177 if (IS_CRESTLINE(dev))
7178 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7179 else if (IS_BROADWATER(dev))
7180 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7181 } else if (IS_GEN3(dev)) {
7182 dev_priv->display.update_wm = i9xx_update_wm;
7183 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7184 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7185 } else if (IS_GEN2(dev)) {
7186 if (INTEL_INFO(dev)->num_pipes == 1) {
7187 dev_priv->display.update_wm = i845_update_wm;
7188 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7190 dev_priv->display.update_wm = i9xx_update_wm;
7191 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7194 if (IS_I85X(dev) || IS_I865G(dev))
7195 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7197 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7199 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7203 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7205 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7207 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7208 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7212 I915_WRITE(GEN6_PCODE_DATA, *val);
7213 I915_WRITE(GEN6_PCODE_DATA1, 0);
7214 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7216 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7218 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7222 *val = I915_READ(GEN6_PCODE_DATA);
7223 I915_WRITE(GEN6_PCODE_DATA, 0);
7228 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7230 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7232 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7233 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7237 I915_WRITE(GEN6_PCODE_DATA, val);
7238 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7240 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7242 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7246 I915_WRITE(GEN6_PCODE_DATA, 0);
7251 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7253 switch (czclk_freq) {
7268 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7270 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7272 div = vlv_gpu_freq_div(czclk_freq);
7276 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7279 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7281 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7283 mul = vlv_gpu_freq_div(czclk_freq);
7287 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7290 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7292 int div, czclk_freq = dev_priv->rps.cz_freq;
7294 div = vlv_gpu_freq_div(czclk_freq) / 2;
7298 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7301 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7303 int mul, czclk_freq = dev_priv->rps.cz_freq;
7305 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7309 /* CHV needs even values */
7310 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7313 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7315 if (IS_GEN9(dev_priv->dev))
7316 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7317 else if (IS_CHERRYVIEW(dev_priv->dev))
7318 return chv_gpu_freq(dev_priv, val);
7319 else if (IS_VALLEYVIEW(dev_priv->dev))
7320 return byt_gpu_freq(dev_priv, val);
7322 return val * GT_FREQUENCY_MULTIPLIER;
7325 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7327 if (IS_GEN9(dev_priv->dev))
7328 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7329 else if (IS_CHERRYVIEW(dev_priv->dev))
7330 return chv_freq_opcode(dev_priv, val);
7331 else if (IS_VALLEYVIEW(dev_priv->dev))
7332 return byt_freq_opcode(dev_priv, val);
7334 return val / GT_FREQUENCY_MULTIPLIER;
7337 struct request_boost {
7338 struct work_struct work;
7339 struct drm_i915_gem_request *req;
7342 static void __intel_rps_boost_work(struct work_struct *work)
7344 struct request_boost *boost = container_of(work, struct request_boost, work);
7345 struct drm_i915_gem_request *req = boost->req;
7347 if (!i915_gem_request_completed(req, true))
7348 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7349 req->emitted_jiffies);
7351 i915_gem_request_unreference__unlocked(req);
7355 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7356 struct drm_i915_gem_request *req)
7358 struct request_boost *boost;
7360 if (req == NULL || INTEL_INFO(dev)->gen < 6)
7363 if (i915_gem_request_completed(req, true))
7366 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7370 i915_gem_request_reference(req);
7373 INIT_WORK(&boost->work, __intel_rps_boost_work);
7374 queue_work(to_i915(dev)->wq, &boost->work);
7377 void intel_pm_setup(struct drm_device *dev)
7379 struct drm_i915_private *dev_priv = dev->dev_private;
7381 mutex_init(&dev_priv->rps.hw_lock);
7382 spin_lock_init(&dev_priv->rps.client_lock);
7384 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7385 intel_gen6_powersave_work);
7386 INIT_LIST_HEAD(&dev_priv->rps.clients);
7387 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7388 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7390 dev_priv->pm.suspended = false;