drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct intel_engine_cs *ring,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         u32 cmd;
  99         int ret;
 100
 101         cmd = MI_FLUSH;
 102         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 103                 cmd |= MI_NO_WRITE_FLUSH;
 104
 105         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 106                 cmd |= MI_READ_FLUSH;
 107
 108         ret = intel_ring_begin(ring, 2);
 109         if (ret)
 110                 return ret;
 111
 112         intel_ring_emit(ring, cmd);
 113         intel_ring_emit(ring, MI_NOOP);
 114         intel_ring_advance(ring);
 115
 116         return 0;
 117 }
 118
 119 static int
 120 gen4_render_ring_flush(struct intel_engine_cs *ring,
 121                        u32      invalidate_domains,
 122                        u32      flush_domains)
 123 {
 124         struct drm_device *dev = ring->dev;
 125         u32 cmd;
 126         int ret;
 127
 128         /*
 129          * read/write caches:
 130          *
 131          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 132          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 133          * also flushed at 2d versus 3d pipeline switches.
 134          *
 135          * read-only caches:
 136          *
 137          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 138          * MI_READ_FLUSH is set, and is always flushed on 965.
 139          *
 140          * I915_GEM_DOMAIN_COMMAND may not exist?
 141          *
 142          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 143          * invalidated when MI_EXE_FLUSH is set.
 144          *
 145          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 146          * invalidated with every MI_FLUSH.
 147          *
 148          * TLBs:
 149          *
 150          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 151          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 152          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 153          * are flushed at any MI_FLUSH.
 154          */
 155
 156         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 157         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 158                 cmd &= ~MI_NO_WRITE_FLUSH;
 159         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 160                 cmd |= MI_EXE_FLUSH;
 161
 162         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 163             (IS_G4X(dev) || IS_GEN5(dev)))
 164                 cmd |= MI_INVALIDATE_ISP;
 165
 166         ret = intel_ring_begin(ring, 2);
 167         if (ret)
 168                 return ret;
 169
 170         intel_ring_emit(ring, cmd);
 171         intel_ring_emit(ring, MI_NOOP);
 172         intel_ring_advance(ring);
 173
 174         return 0;
 175 }
 176
 177 /**
 178  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 179  * implementing two workarounds on gen6.  From section 1.4.7.1
 180  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 181  *
 182  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 183  * produced by non-pipelined state commands), software needs to first
 184  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 185  * 0.
 186  *
 187  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 188  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 189  *
 190  * And the workaround for these two requires this workaround first:
 191  *
 192  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 193  * BEFORE the pipe-control with a post-sync op and no write-cache
 194  * flushes.
 195  *
 196  * And this last workaround is tricky because of the requirements on
 197  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 198  * volume 2 part 1:
 199  *
 200  *     "1 of the following must also be set:
 201  *      - Render Target Cache Flush Enable ([12] of DW1)
 202  *      - Depth Cache Flush Enable ([0] of DW1)
 203  *      - Stall at Pixel Scoreboard ([1] of DW1)
 204  *      - Depth Stall ([13] of DW1)
 205  *      - Post-Sync Operation ([13] of DW1)
 206  *      - Notify Enable ([8] of DW1)"
 207  *
 208  * The cache flushes require the workaround flush that triggered this
 209  * one, so we can't use it.  Depth stall would trigger the same.
 210  * Post-sync nonzero is what triggered this second workaround, so we
 211  * can't use that one either.  Notify enable is IRQs, which aren't
 212  * really our business.  That leaves only stall at scoreboard.
 213  */
 214 static int
 215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
 216 {
 217         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 218         int ret;
 219
 220
 221         ret = intel_ring_begin(ring, 6);
 222         if (ret)
 223                 return ret;
 224
 225         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 226         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 227                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 228         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 229         intel_ring_emit(ring, 0); /* low dword */
 230         intel_ring_emit(ring, 0); /* high dword */
 231         intel_ring_emit(ring, MI_NOOP);
 232         intel_ring_advance(ring);
 233
 234         ret = intel_ring_begin(ring, 6);
 235         if (ret)
 236                 return ret;
 237
 238         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 239         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 240         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 241         intel_ring_emit(ring, 0);
 242         intel_ring_emit(ring, 0);
 243         intel_ring_emit(ring, MI_NOOP);
 244         intel_ring_advance(ring);
 245
 246         return 0;
 247 }
 248
 249 static int
 250 gen6_render_ring_flush(struct intel_engine_cs *ring,
 251                          u32 invalidate_domains, u32 flush_domains)
 252 {
 253         u32 flags = 0;
 254         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 255         int ret;
 256
 257         /* Force SNB workarounds for PIPE_CONTROL flushes */
 258         ret = intel_emit_post_sync_nonzero_flush(ring);
 259         if (ret)
 260                 return ret;
 261
 262         /* Just flush everything.  Experiments have shown that reducing the
 263          * number of bits based on the write domains has little performance
 264          * impact.
 265          */
 266         if (flush_domains) {
 267                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 268                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 269                 /*
 270                  * Ensure that any following seqno writes only happen
 271                  * when the render cache is indeed flushed.
 272                  */
 273                 flags |= PIPE_CONTROL_CS_STALL;
 274         }
 275         if (invalidate_domains) {
 276                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 277                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 278                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 279                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 280                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 281                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 282                 /*
 283                  * TLB invalidate requires a post-sync write.
 284                  */
 285                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 286         }
 287
 288         ret = intel_ring_begin(ring, 4);
 289         if (ret)
 290                 return ret;
 291
 292         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 293         intel_ring_emit(ring, flags);
 294         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 295         intel_ring_emit(ring, 0);
 296         intel_ring_advance(ring);
 297
 298         return 0;
 299 }
 300
 301 static int
 302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
 303 {
 304         int ret;
 305
 306         ret = intel_ring_begin(ring, 4);
 307         if (ret)
 308                 return ret;
 309
 310         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 311         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 312                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 313         intel_ring_emit(ring, 0);
 314         intel_ring_emit(ring, 0);
 315         intel_ring_advance(ring);
 316
 317         return 0;
 318 }
 319
 320 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
 321 {
 322         int ret;
 323
 324         if (!ring->fbc_dirty)
 325                 return 0;
 326
 327         ret = intel_ring_begin(ring, 6);
 328         if (ret)
 329                 return ret;
 330         /* WaFbcNukeOn3DBlt:ivb/hsw */
 331         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 332         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 333         intel_ring_emit(ring, value);
 334         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
 335         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 336         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 337         intel_ring_advance(ring);
 338
 339         ring->fbc_dirty = false;
 340         return 0;
 341 }
 342
 343 static int
 344 gen7_render_ring_flush(struct intel_engine_cs *ring,
 345                        u32 invalidate_domains, u32 flush_domains)
 346 {
 347         u32 flags = 0;
 348         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 349         int ret;
 350
 351         /*
 352          * Ensure that any following seqno writes only happen when the render
 353          * cache is indeed flushed.
 354          *
 355          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 356          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 357          * don't try to be clever and just set it unconditionally.
 358          */
 359         flags |= PIPE_CONTROL_CS_STALL;
 360
 361         /* Just flush everything.  Experiments have shown that reducing the
 362          * number of bits based on the write domains has little performance
 363          * impact.
 364          */
 365         if (flush_domains) {
 366                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 367                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 368         }
 369         if (invalidate_domains) {
 370                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 371                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 372                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 373                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 374                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 375                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 376                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 377                 /*
 378                  * TLB invalidate requires a post-sync write.
 379                  */
 380                 flags |= PIPE_CONTROL_QW_WRITE;
 381                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 382
 383                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 384
 385                 /* Workaround: we must issue a pipe_control with CS-stall bit
 386                  * set before a pipe_control command that has the state cache
 387                  * invalidate bit set. */
 388                 gen7_render_ring_cs_stall_wa(ring);
 389         }
 390
 391         ret = intel_ring_begin(ring, 4);
 392         if (ret)
 393                 return ret;
 394
 395         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 396         intel_ring_emit(ring, flags);
 397         intel_ring_emit(ring, scratch_addr);
 398         intel_ring_emit(ring, 0);
 399         intel_ring_advance(ring);
 400
 401         if (!invalidate_domains && flush_domains)
 402                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 403
 404         return 0;
 405 }
 406
 407 static int
 408 gen8_emit_pipe_control(struct intel_engine_cs *ring,
 409                        u32 flags, u32 scratch_addr)
 410 {
 411         int ret;
 412
 413         ret = intel_ring_begin(ring, 6);
 414         if (ret)
 415                 return ret;
 416
 417         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 418         intel_ring_emit(ring, flags);
 419         intel_ring_emit(ring, scratch_addr);
 420         intel_ring_emit(ring, 0);
 421         intel_ring_emit(ring, 0);
 422         intel_ring_emit(ring, 0);
 423         intel_ring_advance(ring);
 424
 425         return 0;
 426 }
 427
 428 static int
 429 gen8_render_ring_flush(struct intel_engine_cs *ring,
 430                        u32 invalidate_domains, u32 flush_domains)
 431 {
 432         u32 flags = 0;
 433         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 434         int ret;
 435
 436         flags |= PIPE_CONTROL_CS_STALL;
 437
 438         if (flush_domains) {
 439                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 440                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 441         }
 442         if (invalidate_domains) {
 443                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 444                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 445                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 446                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 447                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 448                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 449                 flags |= PIPE_CONTROL_QW_WRITE;
 450                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 451
 452                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 453                 ret = gen8_emit_pipe_control(ring,
 454                                              PIPE_CONTROL_CS_STALL |
 455                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 456                                              0);
 457                 if (ret)
 458                         return ret;
 459         }
 460
 461         ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
 462         if (ret)
 463                 return ret;
 464
 465         if (!invalidate_domains && flush_domains)
 466                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 467
 468         return 0;
 469 }
 470
 471 static void ring_write_tail(struct intel_engine_cs *ring,
 472                             u32 value)
 473 {
 474         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 475         I915_WRITE_TAIL(ring, value);
 476 }
 477
 478 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 479 {
 480         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 481         u64 acthd;
 482
 483         if (INTEL_INFO(ring->dev)->gen >= 8)
 484                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 485                                          RING_ACTHD_UDW(ring->mmio_base));
 486         else if (INTEL_INFO(ring->dev)->gen >= 4)
 487                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 488         else
 489                 acthd = I915_READ(ACTHD);
 490
 491         return acthd;
 492 }
 493
 494 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 495 {
 496         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 497         u32 addr;
 498
 499         addr = dev_priv->status_page_dmah->busaddr;
 500         if (INTEL_INFO(ring->dev)->gen >= 4)
 501                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 502         I915_WRITE(HWS_PGA, addr);
 503 }
 504
 505 static bool stop_ring(struct intel_engine_cs *ring)
 506 {
 507         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 508
 509         if (!IS_GEN2(ring->dev)) {
 510                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 511                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 512                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 513                         /* Sometimes we observe that the idle flag is not
 514                          * set even though the ring is empty. So double
 515                          * check before giving up.
 516                          */
 517                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 518                                 return false;
 519                 }
 520         }
 521
 522         I915_WRITE_CTL(ring, 0);
 523         I915_WRITE_HEAD(ring, 0);
 524         ring->write_tail(ring, 0);
 525
 526         if (!IS_GEN2(ring->dev)) {
 527                 (void)I915_READ_CTL(ring);
 528                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 529         }
 530
 531         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 532 }
 533
 534 static int init_ring_common(struct intel_engine_cs *ring)
 535 {
 536         struct drm_device *dev = ring->dev;
 537         struct drm_i915_private *dev_priv = dev->dev_private;
 538         struct intel_ringbuffer *ringbuf = ring->buffer;
 539         struct drm_i915_gem_object *obj = ringbuf->obj;
 540         int ret = 0;
 541
 542         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 543
 544         if (!stop_ring(ring)) {
 545                 /* G45 ring initialization often fails to reset head to zero */
 546                 DRM_DEBUG_KMS("%s head not reset to zero "
 547                               "ctl %08x head %08x tail %08x start %08x\n",
 548                               ring->name,
 549                               I915_READ_CTL(ring),
 550                               I915_READ_HEAD(ring),
 551                               I915_READ_TAIL(ring),
 552                               I915_READ_START(ring));
 553
 554                 if (!stop_ring(ring)) {
 555                         DRM_ERROR("failed to set %s head to zero "
 556                                   "ctl %08x head %08x tail %08x start %08x\n",
 557                                   ring->name,
 558                                   I915_READ_CTL(ring),
 559                                   I915_READ_HEAD(ring),
 560                                   I915_READ_TAIL(ring),
 561                                   I915_READ_START(ring));
 562                         ret = -EIO;
 563                         goto out;
 564                 }
 565         }
 566
 567         if (I915_NEED_GFX_HWS(dev))
 568                 intel_ring_setup_status_page(ring);
 569         else
 570                 ring_setup_phys_status_page(ring);
 571
 572         /* Enforce ordering by reading HEAD register back */
 573         I915_READ_HEAD(ring);
 574
 575         /* Initialize the ring. This must happen _after_ we've cleared the ring
 576          * registers with the above sequence (the readback of the HEAD registers
 577          * also enforces ordering), otherwise the hw might lose the new ring
 578          * register values. */
 579         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 580
 581         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 582         if (I915_READ_HEAD(ring))
 583                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 584                           ring->name, I915_READ_HEAD(ring));
 585         I915_WRITE_HEAD(ring, 0);
 586         (void)I915_READ_HEAD(ring);
 587
 588         I915_WRITE_CTL(ring,
 589                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 590                         | RING_VALID);
 591
 592         /* If the head is still not zero, the ring is dead */
 593         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 594                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 595                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 596                 DRM_ERROR("%s initialization failed "
 597                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 598                           ring->name,
 599                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 600                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 601                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 602                 ret = -EIO;
 603                 goto out;
 604         }
 605
 606         ringbuf->last_retired_head = -1;
 607         ringbuf->head = I915_READ_HEAD(ring);
 608         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 609         intel_ring_update_space(ringbuf);
 610
 611         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 612
 613 out:
 614         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 615
 616         return ret;
 617 }
 618
 619 void
 620 intel_fini_pipe_control(struct intel_engine_cs *ring)
 621 {
 622         struct drm_device *dev = ring->dev;
 623
 624         if (ring->scratch.obj == NULL)
 625                 return;
 626
 627         if (INTEL_INFO(dev)->gen >= 5) {
 628                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 629                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 630         }
 631
 632         drm_gem_object_unreference(&ring->scratch.obj->base);
 633         ring->scratch.obj = NULL;
 634 }
 635
 636 int
 637 intel_init_pipe_control(struct intel_engine_cs *ring)
 638 {
 639         int ret;
 640
 641         WARN_ON(ring->scratch.obj);
 642
 643         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 644         if (ring->scratch.obj == NULL) {
 645                 DRM_ERROR("Failed to allocate seqno page\n");
 646                 ret = -ENOMEM;
 647                 goto err;
 648         }
 649
 650         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 651         if (ret)
 652                 goto err_unref;
 653
 654         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 655         if (ret)
 656                 goto err_unref;
 657
 658         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 659         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 660         if (ring->scratch.cpu_page == NULL) {
 661                 ret = -ENOMEM;
 662                 goto err_unpin;
 663         }
 664
 665         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 666                          ring->name, ring->scratch.gtt_offset);
 667         return 0;
 668
 669 err_unpin:
 670         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 671 err_unref:
 672         drm_gem_object_unreference(&ring->scratch.obj->base);
 673 err:
 674         return ret;
 675 }
 676
 677 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
 678                                        struct intel_context *ctx)
 679 {
 680         int ret, i;
 681         struct drm_device *dev = ring->dev;
 682         struct drm_i915_private *dev_priv = dev->dev_private;
 683         struct i915_workarounds *w = &dev_priv->workarounds;
 684
 685         if (WARN_ON_ONCE(w->count == 0))
 686                 return 0;
 687
 688         ring->gpu_caches_dirty = true;
 689         ret = intel_ring_flush_all_caches(ring);
 690         if (ret)
 691                 return ret;
 692
 693         ret = intel_ring_begin(ring, (w->count * 2 + 2));
 694         if (ret)
 695                 return ret;
 696
 697         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 698         for (i = 0; i < w->count; i++) {
 699                 intel_ring_emit(ring, w->reg[i].addr);
 700                 intel_ring_emit(ring, w->reg[i].value);
 701         }
 702         intel_ring_emit(ring, MI_NOOP);
 703
 704         intel_ring_advance(ring);
 705
 706         ring->gpu_caches_dirty = true;
 707         ret = intel_ring_flush_all_caches(ring);
 708         if (ret)
 709                 return ret;
 710
 711         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 712
 713         return 0;
 714 }
 715
 716 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
 717                               struct intel_context *ctx)
 718 {
 719         int ret;
 720
 721         ret = intel_ring_workarounds_emit(ring, ctx);
 722         if (ret != 0)
 723                 return ret;
 724
 725         ret = i915_gem_render_state_init(ring);
 726         if (ret)
 727                 DRM_ERROR("init render state: %d\n", ret);
 728
 729         return ret;
 730 }
 731
 732 static int wa_add(struct drm_i915_private *dev_priv,
 733                   const u32 addr, const u32 mask, const u32 val)
 734 {
 735         const u32 idx = dev_priv->workarounds.count;
 736
 737         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 738                 return -ENOSPC;
 739
 740         dev_priv->workarounds.reg[idx].addr = addr;
 741         dev_priv->workarounds.reg[idx].value = val;
 742         dev_priv->workarounds.reg[idx].mask = mask;
 743
 744         dev_priv->workarounds.count++;
 745
 746         return 0;
 747 }
 748
 749 #define WA_REG(addr, mask, val) { \
 750                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 751                 if (r) \
 752                         return r; \
 753         }
 754
 755 #define WA_SET_BIT_MASKED(addr, mask) \
 756         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 757
 758 #define WA_CLR_BIT_MASKED(addr, mask) \
 759         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 760
 761 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 762         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 763
 764 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 765 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 766
 767 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 768
 769 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 770 {
 771         struct drm_device *dev = ring->dev;
 772         struct drm_i915_private *dev_priv = dev->dev_private;
 773
 774         /* WaDisablePartialInstShootdown:bdw */
 775         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 776         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 777                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 778                           STALL_DOP_GATING_DISABLE);
 779
 780         /* WaDisableDopClockGating:bdw */
 781         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 782                           DOP_CLOCK_GATING_DISABLE);
 783
 784         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 785                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 786
 787         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 788          * workaround for for a possible hang in the unlikely event a TLB
 789          * invalidation occurs during a PSD flush.
 790          */
 791         /* WaForceEnableNonCoherent:bdw */
 792         /* WaHdcDisableFetchWhenMasked:bdw */
 793         /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
 794         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 795                           HDC_FORCE_NON_COHERENT |
 796                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 797                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 798
 799         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 800          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 801          *  polygons in the same 8x4 pixel/sample area to be processed without
 802          *  stalling waiting for the earlier ones to write to Hierarchical Z
 803          *  buffer."
 804          *
 805          * This optimization is off by default for Broadwell; turn it on.
 806          */
 807         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 808
 809         /* Wa4x4STCOptimizationDisable:bdw */
 810         WA_SET_BIT_MASKED(CACHE_MODE_1,
 811                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 812
 813         /*
 814          * BSpec recommends 8x4 when MSAA is used,
 815          * however in practice 16x4 seems fastest.
 816          *
 817          * Note that PS/WM thread counts depend on the WIZ hashing
 818          * disable bit, which we don't touch here, but it's good
 819          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 820          */
 821         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 822                             GEN6_WIZ_HASHING_MASK,
 823                             GEN6_WIZ_HASHING_16x4);
 824
 825         return 0;
 826 }
 827
 828 static int chv_init_workarounds(struct intel_engine_cs *ring)
 829 {
 830         struct drm_device *dev = ring->dev;
 831         struct drm_i915_private *dev_priv = dev->dev_private;
 832
 833         /* WaDisablePartialInstShootdown:chv */
 834         /* WaDisableThreadStallDopClockGating:chv */
 835         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 836                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 837                           STALL_DOP_GATING_DISABLE);
 838
 839         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 840          * workaround for a possible hang in the unlikely event a TLB
 841          * invalidation occurs during a PSD flush.
 842          */
 843         /* WaForceEnableNonCoherent:chv */
 844         /* WaHdcDisableFetchWhenMasked:chv */
 845         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 846                           HDC_FORCE_NON_COHERENT |
 847                           HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 848
 849         /* According to the CACHE_MODE_0 default value documentation, some
 850          * CHV platforms disable this optimization by default.  Turn it on.
 851          */
 852         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 853
 854         /* Improve HiZ throughput on CHV. */
 855         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 856
 857         return 0;
 858 }
 859
 860 int init_workarounds_ring(struct intel_engine_cs *ring)
 861 {
 862         struct drm_device *dev = ring->dev;
 863         struct drm_i915_private *dev_priv = dev->dev_private;
 864
 865         WARN_ON(ring->id != RCS);
 866
 867         dev_priv->workarounds.count = 0;
 868
 869         if (IS_BROADWELL(dev))
 870                 return bdw_init_workarounds(ring);
 871
 872         if (IS_CHERRYVIEW(dev))
 873                 return chv_init_workarounds(ring);
 874
 875         return 0;
 876 }
 877
 878 static int init_render_ring(struct intel_engine_cs *ring)
 879 {
 880         struct drm_device *dev = ring->dev;
 881         struct drm_i915_private *dev_priv = dev->dev_private;
 882         int ret = init_ring_common(ring);
 883         if (ret)
 884                 return ret;
 885
 886         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 887         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
 888                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 889
 890         /* We need to disable the AsyncFlip performance optimisations in order
 891          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 892          * programmed to '1' on all products.
 893          *
 894          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
 895          */
 896         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
 897                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 898
 899         /* Required for the hardware to program scanline values for waiting */
 900         /* WaEnableFlushTlbInvalidationMode:snb */
 901         if (INTEL_INFO(dev)->gen == 6)
 902                 I915_WRITE(GFX_MODE,
 903                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 904
 905         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
 906         if (IS_GEN7(dev))
 907                 I915_WRITE(GFX_MODE_GEN7,
 908                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
 909                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 910
 911         if (IS_GEN6(dev)) {
 912                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 913                  * "If this bit is set, STCunit will have LRA as replacement
 914                  *  policy. [...] This bit must be reset.  LRA replacement
 915                  *  policy is not supported."
 916                  */
 917                 I915_WRITE(CACHE_MODE_0,
 918                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 919         }
 920
 921         if (INTEL_INFO(dev)->gen >= 6)
 922                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 923
 924         if (HAS_L3_DPF(dev))
 925                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 926
 927         return init_workarounds_ring(ring);
 928 }
 929
 930 static void render_ring_cleanup(struct intel_engine_cs *ring)
 931 {
 932         struct drm_device *dev = ring->dev;
 933         struct drm_i915_private *dev_priv = dev->dev_private;
 934
 935         if (dev_priv->semaphore_obj) {
 936                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
 937                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
 938                 dev_priv->semaphore_obj = NULL;
 939         }
 940
 941         intel_fini_pipe_control(ring);
 942 }
 943
 944 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
 945                            unsigned int num_dwords)
 946 {
 947 #define MBOX_UPDATE_DWORDS 8
 948         struct drm_device *dev = signaller->dev;
 949         struct drm_i915_private *dev_priv = dev->dev_private;
 950         struct intel_engine_cs *waiter;
 951         int i, ret, num_rings;
 952
 953         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 954         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
 955 #undef MBOX_UPDATE_DWORDS
 956
 957         ret = intel_ring_begin(signaller, num_dwords);
 958         if (ret)
 959                 return ret;
 960
 961         for_each_ring(waiter, dev_priv, i) {
 962                 u32 seqno;
 963                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
 964                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
 965                         continue;
 966
 967                 seqno = i915_gem_request_get_seqno(
 968                                            signaller->outstanding_lazy_request);
 969                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
 970                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
 971                                            PIPE_CONTROL_QW_WRITE |
 972                                            PIPE_CONTROL_FLUSH_ENABLE);
 973                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
 974                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
 975                 intel_ring_emit(signaller, seqno);
 976                 intel_ring_emit(signaller, 0);
 977                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
 978                                            MI_SEMAPHORE_TARGET(waiter->id));
 979                 intel_ring_emit(signaller, 0);
 980         }
 981
 982         return 0;
 983 }
 984
 985 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
 986                            unsigned int num_dwords)
 987 {
 988 #define MBOX_UPDATE_DWORDS 6
 989         struct drm_device *dev = signaller->dev;
 990         struct drm_i915_private *dev_priv = dev->dev_private;
 991         struct intel_engine_cs *waiter;
 992         int i, ret, num_rings;
 993
 994         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 995         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
 996 #undef MBOX_UPDATE_DWORDS
 997
 998         ret = intel_ring_begin(signaller, num_dwords);
 999         if (ret)
1000                 return ret;
1001
1002         for_each_ring(waiter, dev_priv, i) {
1003                 u32 seqno;
1004                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1005                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1006                         continue;
1007
1008                 seqno = i915_gem_request_get_seqno(
1009                                            signaller->outstanding_lazy_request);
1010                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1011                                            MI_FLUSH_DW_OP_STOREDW);
1012                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1013                                            MI_FLUSH_DW_USE_GTT);
1014                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1015                 intel_ring_emit(signaller, seqno);
1016                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1017                                            MI_SEMAPHORE_TARGET(waiter->id));
1018                 intel_ring_emit(signaller, 0);
1019         }
1020
1021         return 0;
1022 }
1023
1024 static int gen6_signal(struct intel_engine_cs *signaller,
1025                        unsigned int num_dwords)
1026 {
1027         struct drm_device *dev = signaller->dev;
1028         struct drm_i915_private *dev_priv = dev->dev_private;
1029         struct intel_engine_cs *useless;
1030         int i, ret, num_rings;
1031
1032 #define MBOX_UPDATE_DWORDS 3
1033         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1034         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1035 #undef MBOX_UPDATE_DWORDS
1036
1037         ret = intel_ring_begin(signaller, num_dwords);
1038         if (ret)
1039                 return ret;
1040
1041         for_each_ring(useless, dev_priv, i) {
1042                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1043                 if (mbox_reg != GEN6_NOSYNC) {
1044                         u32 seqno = i915_gem_request_get_seqno(
1045                                            signaller->outstanding_lazy_request);
1046                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1047                         intel_ring_emit(signaller, mbox_reg);
1048                         intel_ring_emit(signaller, seqno);
1049                 }
1050         }
1051
1052         /* If num_dwords was rounded, make sure the tail pointer is correct */
1053         if (num_rings % 2 == 0)
1054                 intel_ring_emit(signaller, MI_NOOP);
1055
1056         return 0;
1057 }
1058
1059 /**
1060  * gen6_add_request - Update the semaphore mailbox registers
1061  *
1062  * @ring - ring that is adding a request
1063  * @seqno - return seqno stuck into the ring
1064  *
1065  * Update the mailbox registers in the *other* rings with the current seqno.
1066  * This acts like a signal in the canonical semaphore.
1067  */
1068 static int
1069 gen6_add_request(struct intel_engine_cs *ring)
1070 {
1071         int ret;
1072
1073         if (ring->semaphore.signal)
1074                 ret = ring->semaphore.signal(ring, 4);
1075         else
1076                 ret = intel_ring_begin(ring, 4);
1077
1078         if (ret)
1079                 return ret;
1080
1081         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1082         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1083         intel_ring_emit(ring,
1084                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1085         intel_ring_emit(ring, MI_USER_INTERRUPT);
1086         __intel_ring_advance(ring);
1087
1088         return 0;
1089 }
1090
1091 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1092                                               u32 seqno)
1093 {
1094         struct drm_i915_private *dev_priv = dev->dev_private;
1095         return dev_priv->last_seqno < seqno;
1096 }
1097
1098 /**
1099  * intel_ring_sync - sync the waiter to the signaller on seqno
1100  *
1101  * @waiter - ring that is waiting
1102  * @signaller - ring which has, or will signal
1103  * @seqno - seqno which the waiter will block on
1104  */
1105
1106 static int
1107 gen8_ring_sync(struct intel_engine_cs *waiter,
1108                struct intel_engine_cs *signaller,
1109                u32 seqno)
1110 {
1111         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1112         int ret;
1113
1114         ret = intel_ring_begin(waiter, 4);
1115         if (ret)
1116                 return ret;
1117
1118         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1119                                 MI_SEMAPHORE_GLOBAL_GTT |
1120                                 MI_SEMAPHORE_POLL |
1121                                 MI_SEMAPHORE_SAD_GTE_SDD);
1122         intel_ring_emit(waiter, seqno);
1123         intel_ring_emit(waiter,
1124                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1125         intel_ring_emit(waiter,
1126                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1127         intel_ring_advance(waiter);
1128         return 0;
1129 }
1130
1131 static int
1132 gen6_ring_sync(struct intel_engine_cs *waiter,
1133                struct intel_engine_cs *signaller,
1134                u32 seqno)
1135 {
1136         u32 dw1 = MI_SEMAPHORE_MBOX |
1137                   MI_SEMAPHORE_COMPARE |
1138                   MI_SEMAPHORE_REGISTER;
1139         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1140         int ret;
1141
1142         /* Throughout all of the GEM code, seqno passed implies our current
1143          * seqno is >= the last seqno executed. However for hardware the
1144          * comparison is strictly greater than.
1145          */
1146         seqno -= 1;
1147
1148         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1149
1150         ret = intel_ring_begin(waiter, 4);
1151         if (ret)
1152                 return ret;
1153
1154         /* If seqno wrap happened, omit the wait with no-ops */
1155         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1156                 intel_ring_emit(waiter, dw1 | wait_mbox);
1157                 intel_ring_emit(waiter, seqno);
1158                 intel_ring_emit(waiter, 0);
1159                 intel_ring_emit(waiter, MI_NOOP);
1160         } else {
1161                 intel_ring_emit(waiter, MI_NOOP);
1162                 intel_ring_emit(waiter, MI_NOOP);
1163                 intel_ring_emit(waiter, MI_NOOP);
1164                 intel_ring_emit(waiter, MI_NOOP);
1165         }
1166         intel_ring_advance(waiter);
1167
1168         return 0;
1169 }
1170
1171 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1172 do {                                                                    \
1173         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1174                  PIPE_CONTROL_DEPTH_STALL);                             \
1175         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1176         intel_ring_emit(ring__, 0);                                                     \
1177         intel_ring_emit(ring__, 0);                                                     \
1178 } while (0)
1179
1180 static int
1181 pc_render_add_request(struct intel_engine_cs *ring)
1182 {
1183         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1184         int ret;
1185
1186         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1187          * incoherent with writes to memory, i.e. completely fubar,
1188          * so we need to use PIPE_NOTIFY instead.
1189          *
1190          * However, we also need to workaround the qword write
1191          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1192          * memory before requesting an interrupt.
1193          */
1194         ret = intel_ring_begin(ring, 32);
1195         if (ret)
1196                 return ret;
1197
1198         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1199                         PIPE_CONTROL_WRITE_FLUSH |
1200                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1201         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1202         intel_ring_emit(ring,
1203                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1204         intel_ring_emit(ring, 0);
1205         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1206         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1207         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1208         scratch_addr += 2 * CACHELINE_BYTES;
1209         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1210         scratch_addr += 2 * CACHELINE_BYTES;
1211         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1212         scratch_addr += 2 * CACHELINE_BYTES;
1213         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1214         scratch_addr += 2 * CACHELINE_BYTES;
1215         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1216
1217         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1218                         PIPE_CONTROL_WRITE_FLUSH |
1219                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1220                         PIPE_CONTROL_NOTIFY);
1221         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1222         intel_ring_emit(ring,
1223                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1224         intel_ring_emit(ring, 0);
1225         __intel_ring_advance(ring);
1226
1227         return 0;
1228 }
1229
1230 static u32
1231 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1232 {
1233         /* Workaround to force correct ordering between irq and seqno writes on
1234          * ivb (and maybe also on snb) by reading from a CS register (like
1235          * ACTHD) before reading the status page. */
1236         if (!lazy_coherency) {
1237                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1238                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1239         }
1240
1241         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1242 }
1243
1244 static u32
1245 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1246 {
1247         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1248 }
1249
1250 static void
1251 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1252 {
1253         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1254 }
1255
1256 static u32
1257 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1258 {
1259         return ring->scratch.cpu_page[0];
1260 }
1261
1262 static void
1263 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1264 {
1265         ring->scratch.cpu_page[0] = seqno;
1266 }
1267
1268 static bool
1269 gen5_ring_get_irq(struct intel_engine_cs *ring)
1270 {
1271         struct drm_device *dev = ring->dev;
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         unsigned long flags;
1274
1275         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1276                 return false;
1277
1278         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1279         if (ring->irq_refcount++ == 0)
1280                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1281         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1282
1283         return true;
1284 }
1285
1286 static void
1287 gen5_ring_put_irq(struct intel_engine_cs *ring)
1288 {
1289         struct drm_device *dev = ring->dev;
1290         struct drm_i915_private *dev_priv = dev->dev_private;
1291         unsigned long flags;
1292
1293         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1294         if (--ring->irq_refcount == 0)
1295                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1296         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1297 }
1298
1299 static bool
1300 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1301 {
1302         struct drm_device *dev = ring->dev;
1303         struct drm_i915_private *dev_priv = dev->dev_private;
1304         unsigned long flags;
1305
1306         if (!intel_irqs_enabled(dev_priv))
1307                 return false;
1308
1309         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1310         if (ring->irq_refcount++ == 0) {
1311                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1312                 I915_WRITE(IMR, dev_priv->irq_mask);
1313                 POSTING_READ(IMR);
1314         }
1315         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1316
1317         return true;
1318 }
1319
1320 static void
1321 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1322 {
1323         struct drm_device *dev = ring->dev;
1324         struct drm_i915_private *dev_priv = dev->dev_private;
1325         unsigned long flags;
1326
1327         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1328         if (--ring->irq_refcount == 0) {
1329                 dev_priv->irq_mask |= ring->irq_enable_mask;
1330                 I915_WRITE(IMR, dev_priv->irq_mask);
1331                 POSTING_READ(IMR);
1332         }
1333         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1334 }
1335
1336 static bool
1337 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1338 {
1339         struct drm_device *dev = ring->dev;
1340         struct drm_i915_private *dev_priv = dev->dev_private;
1341         unsigned long flags;
1342
1343         if (!intel_irqs_enabled(dev_priv))
1344                 return false;
1345
1346         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1347         if (ring->irq_refcount++ == 0) {
1348                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1349                 I915_WRITE16(IMR, dev_priv->irq_mask);
1350                 POSTING_READ16(IMR);
1351         }
1352         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1353
1354         return true;
1355 }
1356
1357 static void
1358 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1359 {
1360         struct drm_device *dev = ring->dev;
1361         struct drm_i915_private *dev_priv = dev->dev_private;
1362         unsigned long flags;
1363
1364         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1365         if (--ring->irq_refcount == 0) {
1366                 dev_priv->irq_mask |= ring->irq_enable_mask;
1367                 I915_WRITE16(IMR, dev_priv->irq_mask);
1368                 POSTING_READ16(IMR);
1369         }
1370         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1371 }
1372
1373 void intel_ring_setup_status_page(struct intel_engine_cs *ring)
1374 {
1375         struct drm_device *dev = ring->dev;
1376         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1377         u32 mmio = 0;
1378
1379         /* The ring status page addresses are no longer next to the rest of
1380          * the ring registers as of gen7.
1381          */
1382         if (IS_GEN7(dev)) {
1383                 switch (ring->id) {
1384                 case RCS:
1385                         mmio = RENDER_HWS_PGA_GEN7;
1386                         break;
1387                 case BCS:
1388                         mmio = BLT_HWS_PGA_GEN7;
1389                         break;
1390                 /*
1391                  * VCS2 actually doesn't exist on Gen7. Only shut up
1392                  * gcc switch check warning
1393                  */
1394                 case VCS2:
1395                 case VCS:
1396                         mmio = BSD_HWS_PGA_GEN7;
1397                         break;
1398                 case VECS:
1399                         mmio = VEBOX_HWS_PGA_GEN7;
1400                         break;
1401                 }
1402         } else if (IS_GEN6(ring->dev)) {
1403                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1404         } else {
1405                 /* XXX: gen8 returns to sanity */
1406                 mmio = RING_HWS_PGA(ring->mmio_base);
1407         }
1408
1409         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1410         POSTING_READ(mmio);
1411
1412         /*
1413          * Flush the TLB for this page
1414          *
1415          * FIXME: These two bits have disappeared on gen8, so a question
1416          * arises: do we still need this and if so how should we go about
1417          * invalidating the TLB?
1418          */
1419         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1420                 u32 reg = RING_INSTPM(ring->mmio_base);
1421
1422                 /* ring should be idle before issuing a sync flush*/
1423                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1424
1425                 I915_WRITE(reg,
1426                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1427                                               INSTPM_SYNC_FLUSH));
1428                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1429                              1000))
1430                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1431                                   ring->name);
1432         }
1433 }
1434
1435 static int
1436 bsd_ring_flush(struct intel_engine_cs *ring,
1437                u32     invalidate_domains,
1438                u32     flush_domains)
1439 {
1440         int ret;
1441
1442         ret = intel_ring_begin(ring, 2);
1443         if (ret)
1444                 return ret;
1445
1446         intel_ring_emit(ring, MI_FLUSH);
1447         intel_ring_emit(ring, MI_NOOP);
1448         intel_ring_advance(ring);
1449         return 0;
1450 }
1451
1452 static int
1453 i9xx_add_request(struct intel_engine_cs *ring)
1454 {
1455         int ret;
1456
1457         ret = intel_ring_begin(ring, 4);
1458         if (ret)
1459                 return ret;
1460
1461         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1462         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1463         intel_ring_emit(ring,
1464                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1465         intel_ring_emit(ring, MI_USER_INTERRUPT);
1466         __intel_ring_advance(ring);
1467
1468         return 0;
1469 }
1470
1471 static bool
1472 gen6_ring_get_irq(struct intel_engine_cs *ring)
1473 {
1474         struct drm_device *dev = ring->dev;
1475         struct drm_i915_private *dev_priv = dev->dev_private;
1476         unsigned long flags;
1477
1478         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1479                 return false;
1480
1481         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1482         if (ring->irq_refcount++ == 0) {
1483                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1484                         I915_WRITE_IMR(ring,
1485                                        ~(ring->irq_enable_mask |
1486                                          GT_PARITY_ERROR(dev)));
1487                 else
1488                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1489                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1490         }
1491         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1492
1493         return true;
1494 }
1495
1496 static void
1497 gen6_ring_put_irq(struct intel_engine_cs *ring)
1498 {
1499         struct drm_device *dev = ring->dev;
1500         struct drm_i915_private *dev_priv = dev->dev_private;
1501         unsigned long flags;
1502
1503         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1504         if (--ring->irq_refcount == 0) {
1505                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1506                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1507                 else
1508                         I915_WRITE_IMR(ring, ~0);
1509                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1510         }
1511         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1512 }
1513
1514 static bool
1515 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1516 {
1517         struct drm_device *dev = ring->dev;
1518         struct drm_i915_private *dev_priv = dev->dev_private;
1519         unsigned long flags;
1520
1521         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1522                 return false;
1523
1524         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1525         if (ring->irq_refcount++ == 0) {
1526                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1527                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1528         }
1529         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1530
1531         return true;
1532 }
1533
1534 static void
1535 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1536 {
1537         struct drm_device *dev = ring->dev;
1538         struct drm_i915_private *dev_priv = dev->dev_private;
1539         unsigned long flags;
1540
1541         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1542         if (--ring->irq_refcount == 0) {
1543                 I915_WRITE_IMR(ring, ~0);
1544                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1545         }
1546         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1547 }
1548
1549 static bool
1550 gen8_ring_get_irq(struct intel_engine_cs *ring)
1551 {
1552         struct drm_device *dev = ring->dev;
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         unsigned long flags;
1555
1556         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1557                 return false;
1558
1559         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1560         if (ring->irq_refcount++ == 0) {
1561                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1562                         I915_WRITE_IMR(ring,
1563                                        ~(ring->irq_enable_mask |
1564                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1565                 } else {
1566                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1567                 }
1568                 POSTING_READ(RING_IMR(ring->mmio_base));
1569         }
1570         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1571
1572         return true;
1573 }
1574
1575 static void
1576 gen8_ring_put_irq(struct intel_engine_cs *ring)
1577 {
1578         struct drm_device *dev = ring->dev;
1579         struct drm_i915_private *dev_priv = dev->dev_private;
1580         unsigned long flags;
1581
1582         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1583         if (--ring->irq_refcount == 0) {
1584                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1585                         I915_WRITE_IMR(ring,
1586                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1587                 } else {
1588                         I915_WRITE_IMR(ring, ~0);
1589                 }
1590                 POSTING_READ(RING_IMR(ring->mmio_base));
1591         }
1592         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1593 }
1594
1595 static int
1596 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1597                          u64 offset, u32 length,
1598                          unsigned flags)
1599 {
1600         int ret;
1601
1602         ret = intel_ring_begin(ring, 2);
1603         if (ret)
1604                 return ret;
1605
1606         intel_ring_emit(ring,
1607                         MI_BATCH_BUFFER_START |
1608                         MI_BATCH_GTT |
1609                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1610         intel_ring_emit(ring, offset);
1611         intel_ring_advance(ring);
1612
1613         return 0;
1614 }
1615
1616 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1617 #define I830_BATCH_LIMIT (256*1024)
1618 #define I830_TLB_ENTRIES (2)
1619 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1620 static int
1621 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1622                                 u64 offset, u32 len,
1623                                 unsigned flags)
1624 {
1625         u32 cs_offset = ring->scratch.gtt_offset;
1626         int ret;
1627
1628         ret = intel_ring_begin(ring, 6);
1629         if (ret)
1630                 return ret;
1631
1632         /* Evict the invalid PTE TLBs */
1633         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1634         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1635         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1636         intel_ring_emit(ring, cs_offset);
1637         intel_ring_emit(ring, 0xdeadbeef);
1638         intel_ring_emit(ring, MI_NOOP);
1639         intel_ring_advance(ring);
1640
1641         if ((flags & I915_DISPATCH_PINNED) == 0) {
1642                 if (len > I830_BATCH_LIMIT)
1643                         return -ENOSPC;
1644
1645                 ret = intel_ring_begin(ring, 6 + 2);
1646                 if (ret)
1647                         return ret;
1648
1649                 /* Blit the batch (which has now all relocs applied) to the
1650                  * stable batch scratch bo area (so that the CS never
1651                  * stumbles over its tlb invalidation bug) ...
1652                  */
1653                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1654                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1655                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1656                 intel_ring_emit(ring, cs_offset);
1657                 intel_ring_emit(ring, 4096);
1658                 intel_ring_emit(ring, offset);
1659
1660                 intel_ring_emit(ring, MI_FLUSH);
1661                 intel_ring_emit(ring, MI_NOOP);
1662                 intel_ring_advance(ring);
1663
1664                 /* ... and execute it. */
1665                 offset = cs_offset;
1666         }
1667
1668         ret = intel_ring_begin(ring, 4);
1669         if (ret)
1670                 return ret;
1671
1672         intel_ring_emit(ring, MI_BATCH_BUFFER);
1673         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1674         intel_ring_emit(ring, offset + len - 8);
1675         intel_ring_emit(ring, MI_NOOP);
1676         intel_ring_advance(ring);
1677
1678         return 0;
1679 }
1680
1681 static int
1682 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1683                          u64 offset, u32 len,
1684                          unsigned flags)
1685 {
1686         int ret;
1687
1688         ret = intel_ring_begin(ring, 2);
1689         if (ret)
1690                 return ret;
1691
1692         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1693         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1694         intel_ring_advance(ring);
1695
1696         return 0;
1697 }
1698
1699 static void cleanup_status_page(struct intel_engine_cs *ring)
1700 {
1701         struct drm_i915_gem_object *obj;
1702
1703         obj = ring->status_page.obj;
1704         if (obj == NULL)
1705                 return;
1706
1707         kunmap(sg_page(obj->pages->sgl));
1708         i915_gem_object_ggtt_unpin(obj);
1709         drm_gem_object_unreference(&obj->base);
1710         ring->status_page.obj = NULL;
1711 }
1712
1713 static int init_status_page(struct intel_engine_cs *ring)
1714 {
1715         struct drm_i915_gem_object *obj;
1716
1717         if ((obj = ring->status_page.obj) == NULL) {
1718                 unsigned flags;
1719                 int ret;
1720
1721                 obj = i915_gem_alloc_object(ring->dev, 4096);
1722                 if (obj == NULL) {
1723                         DRM_ERROR("Failed to allocate status page\n");
1724                         return -ENOMEM;
1725                 }
1726
1727                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1728                 if (ret)
1729                         goto err_unref;
1730
1731                 flags = 0;
1732                 if (!HAS_LLC(ring->dev))
1733                         /* On g33, we cannot place HWS above 256MiB, so
1734                          * restrict its pinning to the low mappable arena.
1735                          * Though this restriction is not documented for
1736                          * gen4, gen5, or byt, they also behave similarly
1737                          * and hang if the HWS is placed at the top of the
1738                          * GTT. To generalise, it appears that all !llc
1739                          * platforms have issues with us placing the HWS
1740                          * above the mappable region (even though we never
1741                          * actualy map it).
1742                          */
1743                         flags |= PIN_MAPPABLE;
1744                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1745                 if (ret) {
1746 err_unref:
1747                         drm_gem_object_unreference(&obj->base);
1748                         return ret;
1749                 }
1750
1751                 ring->status_page.obj = obj;
1752         }
1753
1754         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1755         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1756         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1757
1758         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1759                         ring->name, ring->status_page.gfx_addr);
1760
1761         return 0;
1762 }
1763
1764 static int init_phys_status_page(struct intel_engine_cs *ring)
1765 {
1766         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1767
1768         if (!dev_priv->status_page_dmah) {
1769                 dev_priv->status_page_dmah =
1770                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1771                 if (!dev_priv->status_page_dmah)
1772                         return -ENOMEM;
1773         }
1774
1775         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1776         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1777
1778         return 0;
1779 }
1780
1781 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1782 {
1783         iounmap(ringbuf->virtual_start);
1784         ringbuf->virtual_start = NULL;
1785         i915_gem_object_ggtt_unpin(ringbuf->obj);
1786 }
1787
1788 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1789                                      struct intel_ringbuffer *ringbuf)
1790 {
1791         struct drm_i915_private *dev_priv = to_i915(dev);
1792         struct drm_i915_gem_object *obj = ringbuf->obj;
1793         int ret;
1794
1795         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1796         if (ret)
1797                 return ret;
1798
1799         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1800         if (ret) {
1801                 i915_gem_object_ggtt_unpin(obj);
1802                 return ret;
1803         }
1804
1805         ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1806                         i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1807         if (ringbuf->virtual_start == NULL) {
1808                 i915_gem_object_ggtt_unpin(obj);
1809                 return -EINVAL;
1810         }
1811
1812         return 0;
1813 }
1814
1815 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1816 {
1817         drm_gem_object_unreference(&ringbuf->obj->base);
1818         ringbuf->obj = NULL;
1819 }
1820
1821 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1822                                struct intel_ringbuffer *ringbuf)
1823 {
1824         struct drm_i915_gem_object *obj;
1825
1826         obj = NULL;
1827         if (!HAS_LLC(dev))
1828                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1829         if (obj == NULL)
1830                 obj = i915_gem_alloc_object(dev, ringbuf->size);
1831         if (obj == NULL)
1832                 return -ENOMEM;
1833
1834         /* mark ring buffers as read-only from GPU side by default */
1835         obj->gt_ro = 1;
1836
1837         ringbuf->obj = obj;
1838
1839         return 0;
1840 }
1841
1842 static int intel_init_ring_buffer(struct drm_device *dev,
1843                                   struct intel_engine_cs *ring)
1844 {
1845         struct intel_ringbuffer *ringbuf;
1846         int ret;
1847
1848         WARN_ON(ring->buffer);
1849
1850         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1851         if (!ringbuf)
1852                 return -ENOMEM;
1853         ring->buffer = ringbuf;
1854
1855         ring->dev = dev;
1856         INIT_LIST_HEAD(&ring->active_list);
1857         INIT_LIST_HEAD(&ring->request_list);
1858         INIT_LIST_HEAD(&ring->execlist_queue);
1859         ringbuf->size = 32 * PAGE_SIZE;
1860         ringbuf->ring = ring;
1861         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1862
1863         init_waitqueue_head(&ring->irq_queue);
1864
1865         if (I915_NEED_GFX_HWS(dev)) {
1866                 ret = init_status_page(ring);
1867                 if (ret)
1868                         goto error;
1869         } else {
1870                 BUG_ON(ring->id != RCS);
1871                 ret = init_phys_status_page(ring);
1872                 if (ret)
1873                         goto error;
1874         }
1875
1876         WARN_ON(ringbuf->obj);
1877
1878         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1879         if (ret) {
1880                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1881                                 ring->name, ret);
1882                 goto error;
1883         }
1884
1885         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1886         if (ret) {
1887                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1888                                 ring->name, ret);
1889                 intel_destroy_ringbuffer_obj(ringbuf);
1890                 goto error;
1891         }
1892
1893         /* Workaround an erratum on the i830 which causes a hang if
1894          * the TAIL pointer points to within the last 2 cachelines
1895          * of the buffer.
1896          */
1897         ringbuf->effective_size = ringbuf->size;
1898         if (IS_I830(dev) || IS_845G(dev))
1899                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1900
1901         ret = i915_cmd_parser_init_ring(ring);
1902         if (ret)
1903                 goto error;
1904
1905         return 0;
1906
1907 error:
1908         kfree(ringbuf);
1909         ring->buffer = NULL;
1910         return ret;
1911 }
1912
1913 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1914 {
1915         struct drm_i915_private *dev_priv;
1916         struct intel_ringbuffer *ringbuf;
1917
1918         if (!intel_ring_initialized(ring))
1919                 return;
1920
1921         dev_priv = to_i915(ring->dev);
1922         ringbuf = ring->buffer;
1923
1924         intel_stop_ring_buffer(ring);
1925         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1926
1927         intel_unpin_ringbuffer_obj(ringbuf);
1928         intel_destroy_ringbuffer_obj(ringbuf);
1929         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1930
1931         if (ring->cleanup)
1932                 ring->cleanup(ring);
1933
1934         cleanup_status_page(ring);
1935
1936         i915_cmd_parser_fini_ring(ring);
1937
1938         kfree(ringbuf);
1939         ring->buffer = NULL;
1940 }
1941
1942 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
1943 {
1944         struct intel_ringbuffer *ringbuf = ring->buffer;
1945         struct drm_i915_gem_request *request;
1946         int ret;
1947
1948         if (intel_ring_space(ringbuf) >= n)
1949                 return 0;
1950
1951         list_for_each_entry(request, &ring->request_list, list) {
1952                 if (__intel_ring_space(request->tail, ringbuf->tail,
1953                                        ringbuf->size) >= n) {
1954                         break;
1955                 }
1956         }
1957
1958         if (&request->list == &ring->request_list)
1959                 return -ENOSPC;
1960
1961         ret = i915_wait_request(request);
1962         if (ret)
1963                 return ret;
1964
1965         i915_gem_retire_requests_ring(ring);
1966
1967         return 0;
1968 }
1969
1970 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
1971 {
1972         struct drm_device *dev = ring->dev;
1973         struct drm_i915_private *dev_priv = dev->dev_private;
1974         struct intel_ringbuffer *ringbuf = ring->buffer;
1975         unsigned long end;
1976         int ret;
1977
1978         ret = intel_ring_wait_request(ring, n);
1979         if (ret != -ENOSPC)
1980                 return ret;
1981
1982         /* force the tail write in case we have been skipping them */
1983         __intel_ring_advance(ring);
1984
1985         /* With GEM the hangcheck timer should kick us out of the loop,
1986          * leaving it early runs the risk of corrupting GEM state (due
1987          * to running on almost untested codepaths). But on resume
1988          * timers don't work yet, so prevent a complete hang in that
1989          * case by choosing an insanely large timeout. */
1990         end = jiffies + 60 * HZ;
1991
1992         ret = 0;
1993         trace_i915_ring_wait_begin(ring);
1994         do {
1995                 if (intel_ring_space(ringbuf) >= n)
1996                         break;
1997                 ringbuf->head = I915_READ_HEAD(ring);
1998                 if (intel_ring_space(ringbuf) >= n)
1999                         break;
2000
2001                 msleep(1);
2002
2003                 if (dev_priv->mm.interruptible && signal_pending(current)) {
2004                         ret = -ERESTARTSYS;
2005                         break;
2006                 }
2007
2008                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2009                                            dev_priv->mm.interruptible);
2010                 if (ret)
2011                         break;
2012
2013                 if (time_after(jiffies, end)) {
2014                         ret = -EBUSY;
2015                         break;
2016                 }
2017         } while (1);
2018         trace_i915_ring_wait_end(ring);
2019         return ret;
2020 }
2021
2022 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2023 {
2024         uint32_t __iomem *virt;
2025         struct intel_ringbuffer *ringbuf = ring->buffer;
2026         int rem = ringbuf->size - ringbuf->tail;
2027
2028         if (ringbuf->space < rem) {
2029                 int ret = ring_wait_for_space(ring, rem);
2030                 if (ret)
2031                         return ret;
2032         }
2033
2034         virt = ringbuf->virtual_start + ringbuf->tail;
2035         rem /= 4;
2036         while (rem--)
2037                 iowrite32(MI_NOOP, virt++);
2038
2039         ringbuf->tail = 0;
2040         intel_ring_update_space(ringbuf);
2041
2042         return 0;
2043 }
2044
2045 int intel_ring_idle(struct intel_engine_cs *ring)
2046 {
2047         struct drm_i915_gem_request *req;
2048         int ret;
2049
2050         /* We need to add any requests required to flush the objects and ring */
2051         if (ring->outstanding_lazy_request) {
2052                 ret = i915_add_request(ring);
2053                 if (ret)
2054                         return ret;
2055         }
2056
2057         /* Wait upon the last request to be completed */
2058         if (list_empty(&ring->request_list))
2059                 return 0;
2060
2061         req = list_entry(ring->request_list.prev,
2062                            struct drm_i915_gem_request,
2063                            list);
2064
2065         return i915_wait_request(req);
2066 }
2067
2068 static int
2069 intel_ring_alloc_request(struct intel_engine_cs *ring)
2070 {
2071         int ret;
2072         struct drm_i915_gem_request *request;
2073         struct drm_i915_private *dev_private = ring->dev->dev_private;
2074
2075         if (ring->outstanding_lazy_request)
2076                 return 0;
2077
2078         request = kzalloc(sizeof(*request), GFP_KERNEL);
2079         if (request == NULL)
2080                 return -ENOMEM;
2081
2082         kref_init(&request->ref);
2083         request->ring = ring;
2084         request->uniq = dev_private->request_uniq++;
2085
2086         ret = i915_gem_get_seqno(ring->dev, &request->seqno);
2087         if (ret) {
2088                 kfree(request);
2089                 return ret;
2090         }
2091
2092         ring->outstanding_lazy_request = request;
2093         return 0;
2094 }
2095
2096 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2097                                 int bytes)
2098 {
2099         struct intel_ringbuffer *ringbuf = ring->buffer;
2100         int ret;
2101
2102         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2103                 ret = intel_wrap_ring_buffer(ring);
2104                 if (unlikely(ret))
2105                         return ret;
2106         }
2107
2108         if (unlikely(ringbuf->space < bytes)) {
2109                 ret = ring_wait_for_space(ring, bytes);
2110                 if (unlikely(ret))
2111                         return ret;
2112         }
2113
2114         return 0;
2115 }
2116
2117 int intel_ring_begin(struct intel_engine_cs *ring,
2118                      int num_dwords)
2119 {
2120         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2121         int ret;
2122
2123         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2124                                    dev_priv->mm.interruptible);
2125         if (ret)
2126                 return ret;
2127
2128         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2129         if (ret)
2130                 return ret;
2131
2132         /* Preallocate the olr before touching the ring */
2133         ret = intel_ring_alloc_request(ring);
2134         if (ret)
2135                 return ret;
2136
2137         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2138         return 0;
2139 }
2140
2141 /* Align the ring tail to a cacheline boundary */
2142 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2143 {
2144         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2145         int ret;
2146
2147         if (num_dwords == 0)
2148                 return 0;
2149
2150         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2151         ret = intel_ring_begin(ring, num_dwords);
2152         if (ret)
2153                 return ret;
2154
2155         while (num_dwords--)
2156                 intel_ring_emit(ring, MI_NOOP);
2157
2158         intel_ring_advance(ring);
2159
2160         return 0;
2161 }
2162
2163 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2164 {
2165         struct drm_device *dev = ring->dev;
2166         struct drm_i915_private *dev_priv = dev->dev_private;
2167
2168         BUG_ON(ring->outstanding_lazy_request);
2169
2170         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2171                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2172                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2173                 if (HAS_VEBOX(dev))
2174                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2175         }
2176
2177         ring->set_seqno(ring, seqno);
2178         ring->hangcheck.seqno = seqno;
2179 }
2180
2181 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2182                                      u32 value)
2183 {
2184         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2185
2186        /* Every tail move must follow the sequence below */
2187
2188         /* Disable notification that the ring is IDLE. The GT
2189          * will then assume that it is busy and bring it out of rc6.
2190          */
2191         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2192                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2193
2194         /* Clear the context id. Here be magic! */
2195         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2196
2197         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2198         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2199                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2200                      50))
2201                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2202
2203         /* Now that the ring is fully powered up, update the tail */
2204         I915_WRITE_TAIL(ring, value);
2205         POSTING_READ(RING_TAIL(ring->mmio_base));
2206
2207         /* Let the ring send IDLE messages to the GT again,
2208          * and so let it sleep to conserve power when idle.
2209          */
2210         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2211                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2212 }
2213
2214 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2215                                u32 invalidate, u32 flush)
2216 {
2217         uint32_t cmd;
2218         int ret;
2219
2220         ret = intel_ring_begin(ring, 4);
2221         if (ret)
2222                 return ret;
2223
2224         cmd = MI_FLUSH_DW;
2225         if (INTEL_INFO(ring->dev)->gen >= 8)
2226                 cmd += 1;
2227         /*
2228          * Bspec vol 1c.5 - video engine command streamer:
2229          * "If ENABLED, all TLBs will be invalidated once the flush
2230          * operation is complete. This bit is only valid when the
2231          * Post-Sync Operation field is a value of 1h or 3h."
2232          */
2233         if (invalidate & I915_GEM_GPU_DOMAINS)
2234                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2235                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2236         intel_ring_emit(ring, cmd);
2237         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2238         if (INTEL_INFO(ring->dev)->gen >= 8) {
2239                 intel_ring_emit(ring, 0); /* upper addr */
2240                 intel_ring_emit(ring, 0); /* value */
2241         } else  {
2242                 intel_ring_emit(ring, 0);
2243                 intel_ring_emit(ring, MI_NOOP);
2244         }
2245         intel_ring_advance(ring);
2246         return 0;
2247 }
2248
2249 static int
2250 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2251                               u64 offset, u32 len,
2252                               unsigned flags)
2253 {
2254         bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
2255         int ret;
2256
2257         ret = intel_ring_begin(ring, 4);
2258         if (ret)
2259                 return ret;
2260
2261         /* FIXME(BDW): Address space and security selectors. */
2262         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2263         intel_ring_emit(ring, lower_32_bits(offset));
2264         intel_ring_emit(ring, upper_32_bits(offset));
2265         intel_ring_emit(ring, MI_NOOP);
2266         intel_ring_advance(ring);
2267
2268         return 0;
2269 }
2270
2271 static int
2272 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2273                               u64 offset, u32 len,
2274                               unsigned flags)
2275 {
2276         int ret;
2277
2278         ret = intel_ring_begin(ring, 2);
2279         if (ret)
2280                 return ret;
2281
2282         intel_ring_emit(ring,
2283                         MI_BATCH_BUFFER_START |
2284                         (flags & I915_DISPATCH_SECURE ?
2285                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2286         /* bit0-7 is the length on GEN6+ */
2287         intel_ring_emit(ring, offset);
2288         intel_ring_advance(ring);
2289
2290         return 0;
2291 }
2292
2293 static int
2294 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2295                               u64 offset, u32 len,
2296                               unsigned flags)
2297 {
2298         int ret;
2299
2300         ret = intel_ring_begin(ring, 2);
2301         if (ret)
2302                 return ret;
2303
2304         intel_ring_emit(ring,
2305                         MI_BATCH_BUFFER_START |
2306                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2307         /* bit0-7 is the length on GEN6+ */
2308         intel_ring_emit(ring, offset);
2309         intel_ring_advance(ring);
2310
2311         return 0;
2312 }
2313
2314 /* Blitter support (SandyBridge+) */
2315
2316 static int gen6_ring_flush(struct intel_engine_cs *ring,
2317                            u32 invalidate, u32 flush)
2318 {
2319         struct drm_device *dev = ring->dev;
2320         struct drm_i915_private *dev_priv = dev->dev_private;
2321         uint32_t cmd;
2322         int ret;
2323
2324         ret = intel_ring_begin(ring, 4);
2325         if (ret)
2326                 return ret;
2327
2328         cmd = MI_FLUSH_DW;
2329         if (INTEL_INFO(ring->dev)->gen >= 8)
2330                 cmd += 1;
2331         /*
2332          * Bspec vol 1c.3 - blitter engine command streamer:
2333          * "If ENABLED, all TLBs will be invalidated once the flush
2334          * operation is complete. This bit is only valid when the
2335          * Post-Sync Operation field is a value of 1h or 3h."
2336          */
2337         if (invalidate & I915_GEM_DOMAIN_RENDER)
2338                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
2339                         MI_FLUSH_DW_OP_STOREDW;
2340         intel_ring_emit(ring, cmd);
2341         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2342         if (INTEL_INFO(ring->dev)->gen >= 8) {
2343                 intel_ring_emit(ring, 0); /* upper addr */
2344                 intel_ring_emit(ring, 0); /* value */
2345         } else  {
2346                 intel_ring_emit(ring, 0);
2347                 intel_ring_emit(ring, MI_NOOP);
2348         }
2349         intel_ring_advance(ring);
2350
2351         if (!invalidate && flush) {
2352                 if (IS_GEN7(dev))
2353                         return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2354                 else if (IS_BROADWELL(dev))
2355                         dev_priv->fbc.need_sw_cache_clean = true;
2356         }
2357
2358         return 0;
2359 }
2360
2361 int intel_init_render_ring_buffer(struct drm_device *dev)
2362 {
2363         struct drm_i915_private *dev_priv = dev->dev_private;
2364         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2365         struct drm_i915_gem_object *obj;
2366         int ret;
2367
2368         ring->name = "render ring";
2369         ring->id = RCS;
2370         ring->mmio_base = RENDER_RING_BASE;
2371
2372         if (INTEL_INFO(dev)->gen >= 8) {
2373                 if (i915_semaphore_is_enabled(dev)) {
2374                         obj = i915_gem_alloc_object(dev, 4096);
2375                         if (obj == NULL) {
2376                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2377                                 i915.semaphores = 0;
2378                         } else {
2379                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2380                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2381                                 if (ret != 0) {
2382                                         drm_gem_object_unreference(&obj->base);
2383                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2384                                         i915.semaphores = 0;
2385                                 } else
2386                                         dev_priv->semaphore_obj = obj;
2387                         }
2388                 }
2389
2390                 ring->init_context = intel_rcs_ctx_init;
2391                 ring->add_request = gen6_add_request;
2392                 ring->flush = gen8_render_ring_flush;
2393                 ring->irq_get = gen8_ring_get_irq;
2394                 ring->irq_put = gen8_ring_put_irq;
2395                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2396                 ring->get_seqno = gen6_ring_get_seqno;
2397                 ring->set_seqno = ring_set_seqno;
2398                 if (i915_semaphore_is_enabled(dev)) {
2399                         WARN_ON(!dev_priv->semaphore_obj);
2400                         ring->semaphore.sync_to = gen8_ring_sync;
2401                         ring->semaphore.signal = gen8_rcs_signal;
2402                         GEN8_RING_SEMAPHORE_INIT;
2403                 }
2404         } else if (INTEL_INFO(dev)->gen >= 6) {
2405                 ring->add_request = gen6_add_request;
2406                 ring->flush = gen7_render_ring_flush;
2407                 if (INTEL_INFO(dev)->gen == 6)
2408                         ring->flush = gen6_render_ring_flush;
2409                 ring->irq_get = gen6_ring_get_irq;
2410                 ring->irq_put = gen6_ring_put_irq;
2411                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2412                 ring->get_seqno = gen6_ring_get_seqno;
2413                 ring->set_seqno = ring_set_seqno;
2414                 if (i915_semaphore_is_enabled(dev)) {
2415                         ring->semaphore.sync_to = gen6_ring_sync;
2416                         ring->semaphore.signal = gen6_signal;
2417                         /*
2418                          * The current semaphore is only applied on pre-gen8
2419                          * platform.  And there is no VCS2 ring on the pre-gen8
2420                          * platform. So the semaphore between RCS and VCS2 is
2421                          * initialized as INVALID.  Gen8 will initialize the
2422                          * sema between VCS2 and RCS later.
2423                          */
2424                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2425                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2426                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2427                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2428                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2429                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2430                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2431                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2432                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2433                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2434                 }
2435         } else if (IS_GEN5(dev)) {
2436                 ring->add_request = pc_render_add_request;
2437                 ring->flush = gen4_render_ring_flush;
2438                 ring->get_seqno = pc_render_get_seqno;
2439                 ring->set_seqno = pc_render_set_seqno;
2440                 ring->irq_get = gen5_ring_get_irq;
2441                 ring->irq_put = gen5_ring_put_irq;
2442                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2443                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2444         } else {
2445                 ring->add_request = i9xx_add_request;
2446                 if (INTEL_INFO(dev)->gen < 4)
2447                         ring->flush = gen2_render_ring_flush;
2448                 else
2449                         ring->flush = gen4_render_ring_flush;
2450                 ring->get_seqno = ring_get_seqno;
2451                 ring->set_seqno = ring_set_seqno;
2452                 if (IS_GEN2(dev)) {
2453                         ring->irq_get = i8xx_ring_get_irq;
2454                         ring->irq_put = i8xx_ring_put_irq;
2455                 } else {
2456                         ring->irq_get = i9xx_ring_get_irq;
2457                         ring->irq_put = i9xx_ring_put_irq;
2458                 }
2459                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2460         }
2461         ring->write_tail = ring_write_tail;
2462
2463         if (IS_HASWELL(dev))
2464                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2465         else if (IS_GEN8(dev))
2466                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2467         else if (INTEL_INFO(dev)->gen >= 6)
2468                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2469         else if (INTEL_INFO(dev)->gen >= 4)
2470                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2471         else if (IS_I830(dev) || IS_845G(dev))
2472                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2473         else
2474                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2475         ring->init_hw = init_render_ring;
2476         ring->cleanup = render_ring_cleanup;
2477
2478         /* Workaround batchbuffer to combat CS tlb bug. */
2479         if (HAS_BROKEN_CS_TLB(dev)) {
2480                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2481                 if (obj == NULL) {
2482                         DRM_ERROR("Failed to allocate batch bo\n");
2483                         return -ENOMEM;
2484                 }
2485
2486                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2487                 if (ret != 0) {
2488                         drm_gem_object_unreference(&obj->base);
2489                         DRM_ERROR("Failed to ping batch bo\n");
2490                         return ret;
2491                 }
2492
2493                 ring->scratch.obj = obj;
2494                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2495         }
2496
2497         ret = intel_init_ring_buffer(dev, ring);
2498         if (ret)
2499                 return ret;
2500
2501         if (INTEL_INFO(dev)->gen >= 5) {
2502                 ret = intel_init_pipe_control(ring);
2503                 if (ret)
2504                         return ret;
2505         }
2506
2507         return 0;
2508 }
2509
2510 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2511 {
2512         struct drm_i915_private *dev_priv = dev->dev_private;
2513         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2514
2515         ring->name = "bsd ring";
2516         ring->id = VCS;
2517
2518         ring->write_tail = ring_write_tail;
2519         if (INTEL_INFO(dev)->gen >= 6) {
2520                 ring->mmio_base = GEN6_BSD_RING_BASE;
2521                 /* gen6 bsd needs a special wa for tail updates */
2522                 if (IS_GEN6(dev))
2523                         ring->write_tail = gen6_bsd_ring_write_tail;
2524                 ring->flush = gen6_bsd_ring_flush;
2525                 ring->add_request = gen6_add_request;
2526                 ring->get_seqno = gen6_ring_get_seqno;
2527                 ring->set_seqno = ring_set_seqno;
2528                 if (INTEL_INFO(dev)->gen >= 8) {
2529                         ring->irq_enable_mask =
2530                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2531                         ring->irq_get = gen8_ring_get_irq;
2532                         ring->irq_put = gen8_ring_put_irq;
2533                         ring->dispatch_execbuffer =
2534                                 gen8_ring_dispatch_execbuffer;
2535                         if (i915_semaphore_is_enabled(dev)) {
2536                                 ring->semaphore.sync_to = gen8_ring_sync;
2537                                 ring->semaphore.signal = gen8_xcs_signal;
2538                                 GEN8_RING_SEMAPHORE_INIT;
2539                         }
2540                 } else {
2541                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2542                         ring->irq_get = gen6_ring_get_irq;
2543                         ring->irq_put = gen6_ring_put_irq;
2544                         ring->dispatch_execbuffer =
2545                                 gen6_ring_dispatch_execbuffer;
2546                         if (i915_semaphore_is_enabled(dev)) {
2547                                 ring->semaphore.sync_to = gen6_ring_sync;
2548                                 ring->semaphore.signal = gen6_signal;
2549                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2550                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2551                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2552                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2553                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2554                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2555                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2556                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2557                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2558                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2559                         }
2560                 }
2561         } else {
2562                 ring->mmio_base = BSD_RING_BASE;
2563                 ring->flush = bsd_ring_flush;
2564                 ring->add_request = i9xx_add_request;
2565                 ring->get_seqno = ring_get_seqno;
2566                 ring->set_seqno = ring_set_seqno;
2567                 if (IS_GEN5(dev)) {
2568                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2569                         ring->irq_get = gen5_ring_get_irq;
2570                         ring->irq_put = gen5_ring_put_irq;
2571                 } else {
2572                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2573                         ring->irq_get = i9xx_ring_get_irq;
2574                         ring->irq_put = i9xx_ring_put_irq;
2575                 }
2576                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2577         }
2578         ring->init_hw = init_ring_common;
2579
2580         return intel_init_ring_buffer(dev, ring);
2581 }
2582
2583 /**
2584  * Initialize the second BSD ring for Broadwell GT3.
2585  * It is noted that this only exists on Broadwell GT3.
2586  */
2587 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2588 {
2589         struct drm_i915_private *dev_priv = dev->dev_private;
2590         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2591
2592         if ((INTEL_INFO(dev)->gen != 8)) {
2593                 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2594                 return -EINVAL;
2595         }
2596
2597         ring->name = "bsd2 ring";
2598         ring->id = VCS2;
2599
2600         ring->write_tail = ring_write_tail;
2601         ring->mmio_base = GEN8_BSD2_RING_BASE;
2602         ring->flush = gen6_bsd_ring_flush;
2603         ring->add_request = gen6_add_request;
2604         ring->get_seqno = gen6_ring_get_seqno;
2605         ring->set_seqno = ring_set_seqno;
2606         ring->irq_enable_mask =
2607                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2608         ring->irq_get = gen8_ring_get_irq;
2609         ring->irq_put = gen8_ring_put_irq;
2610         ring->dispatch_execbuffer =
2611                         gen8_ring_dispatch_execbuffer;
2612         if (i915_semaphore_is_enabled(dev)) {
2613                 ring->semaphore.sync_to = gen8_ring_sync;
2614                 ring->semaphore.signal = gen8_xcs_signal;
2615                 GEN8_RING_SEMAPHORE_INIT;
2616         }
2617         ring->init_hw = init_ring_common;
2618
2619         return intel_init_ring_buffer(dev, ring);
2620 }
2621
2622 int intel_init_blt_ring_buffer(struct drm_device *dev)
2623 {
2624         struct drm_i915_private *dev_priv = dev->dev_private;
2625         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2626
2627         ring->name = "blitter ring";
2628         ring->id = BCS;
2629
2630         ring->mmio_base = BLT_RING_BASE;
2631         ring->write_tail = ring_write_tail;
2632         ring->flush = gen6_ring_flush;
2633         ring->add_request = gen6_add_request;
2634         ring->get_seqno = gen6_ring_get_seqno;
2635         ring->set_seqno = ring_set_seqno;
2636         if (INTEL_INFO(dev)->gen >= 8) {
2637                 ring->irq_enable_mask =
2638                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2639                 ring->irq_get = gen8_ring_get_irq;
2640                 ring->irq_put = gen8_ring_put_irq;
2641                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2642                 if (i915_semaphore_is_enabled(dev)) {
2643                         ring->semaphore.sync_to = gen8_ring_sync;
2644                         ring->semaphore.signal = gen8_xcs_signal;
2645                         GEN8_RING_SEMAPHORE_INIT;
2646                 }
2647         } else {
2648                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2649                 ring->irq_get = gen6_ring_get_irq;
2650                 ring->irq_put = gen6_ring_put_irq;
2651                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2652                 if (i915_semaphore_is_enabled(dev)) {
2653                         ring->semaphore.signal = gen6_signal;
2654                         ring->semaphore.sync_to = gen6_ring_sync;
2655                         /*
2656                          * The current semaphore is only applied on pre-gen8
2657                          * platform.  And there is no VCS2 ring on the pre-gen8
2658                          * platform. So the semaphore between BCS and VCS2 is
2659                          * initialized as INVALID.  Gen8 will initialize the
2660                          * sema between BCS and VCS2 later.
2661                          */
2662                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2663                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2664                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2665                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2666                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2667                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2668                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2669                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2670                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2671                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2672                 }
2673         }
2674         ring->init_hw = init_ring_common;
2675
2676         return intel_init_ring_buffer(dev, ring);
2677 }
2678
2679 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2680 {
2681         struct drm_i915_private *dev_priv = dev->dev_private;
2682         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2683
2684         ring->name = "video enhancement ring";
2685         ring->id = VECS;
2686
2687         ring->mmio_base = VEBOX_RING_BASE;
2688         ring->write_tail = ring_write_tail;
2689         ring->flush = gen6_ring_flush;
2690         ring->add_request = gen6_add_request;
2691         ring->get_seqno = gen6_ring_get_seqno;
2692         ring->set_seqno = ring_set_seqno;
2693
2694         if (INTEL_INFO(dev)->gen >= 8) {
2695                 ring->irq_enable_mask =
2696                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2697                 ring->irq_get = gen8_ring_get_irq;
2698                 ring->irq_put = gen8_ring_put_irq;
2699                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2700                 if (i915_semaphore_is_enabled(dev)) {
2701                         ring->semaphore.sync_to = gen8_ring_sync;
2702                         ring->semaphore.signal = gen8_xcs_signal;
2703                         GEN8_RING_SEMAPHORE_INIT;
2704                 }
2705         } else {
2706                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2707                 ring->irq_get = hsw_vebox_get_irq;
2708                 ring->irq_put = hsw_vebox_put_irq;
2709                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2710                 if (i915_semaphore_is_enabled(dev)) {
2711                         ring->semaphore.sync_to = gen6_ring_sync;
2712                         ring->semaphore.signal = gen6_signal;
2713                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2714                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2715                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2716                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2717                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2718                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2719                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2720                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2721                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2722                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2723                 }
2724         }
2725         ring->init_hw = init_ring_common;
2726
2727         return intel_init_ring_buffer(dev, ring);
2728 }
2729
2730 int
2731 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2732 {
2733         int ret;
2734
2735         if (!ring->gpu_caches_dirty)
2736                 return 0;
2737
2738         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2739         if (ret)
2740                 return ret;
2741
2742         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2743
2744         ring->gpu_caches_dirty = false;
2745         return 0;
2746 }
2747
2748 int
2749 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2750 {
2751         uint32_t flush_domains;
2752         int ret;
2753
2754         flush_domains = 0;
2755         if (ring->gpu_caches_dirty)
2756                 flush_domains = I915_GEM_GPU_DOMAINS;
2757
2758         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2759         if (ret)
2760                 return ret;
2761
2762         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2763
2764         ring->gpu_caches_dirty = false;
2765         return 0;
2766 }
2767
2768 void
2769 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2770 {
2771         int ret;
2772
2773         if (!intel_ring_initialized(ring))
2774                 return;
2775
2776         ret = intel_ring_idle(ring);
2777         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2778                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2779                           ring->name, ret);
2780
2781         stop_ring(ring);
2782 }