drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 /*
  37  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  38  * over cache flushing.
  39  */
  40 struct pipe_control {
  41         struct drm_i915_gem_object *obj;
  42         volatile u32 *cpu_page;
  43         u32 gtt_offset;
  44 };
  45
  46 static inline int ring_space(struct intel_ring_buffer *ring)
  47 {
  48         int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
  49         if (space < 0)
  50                 space += ring->size;
  51         return space;
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         struct pipe_control *pc = ring->private;
 179         u32 scratch_addr = pc->gtt_offset + 128;
 180         int ret;
 181
 182
 183         ret = intel_ring_begin(ring, 6);
 184         if (ret)
 185                 return ret;
 186
 187         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 188         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 189                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 190         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 191         intel_ring_emit(ring, 0); /* low dword */
 192         intel_ring_emit(ring, 0); /* high dword */
 193         intel_ring_emit(ring, MI_NOOP);
 194         intel_ring_advance(ring);
 195
 196         ret = intel_ring_begin(ring, 6);
 197         if (ret)
 198                 return ret;
 199
 200         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 201         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 202         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, 0);
 205         intel_ring_emit(ring, MI_NOOP);
 206         intel_ring_advance(ring);
 207
 208         return 0;
 209 }
 210
 211 static int
 212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 213                          u32 invalidate_domains, u32 flush_domains)
 214 {
 215         u32 flags = 0;
 216         struct pipe_control *pc = ring->private;
 217         u32 scratch_addr = pc->gtt_offset + 128;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(ring);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (flush_domains) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (invalidate_domains) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         ret = intel_ring_begin(ring, 4);
 252         if (ret)
 253                 return ret;
 254
 255         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 256         intel_ring_emit(ring, flags);
 257         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 258         intel_ring_emit(ring, 0);
 259         intel_ring_advance(ring);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 266 {
 267         int ret;
 268
 269         ret = intel_ring_begin(ring, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 275                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 276         intel_ring_emit(ring, 0);
 277         intel_ring_emit(ring, 0);
 278         intel_ring_advance(ring);
 279
 280         return 0;
 281 }
 282
 283 static int
 284 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 285                        u32 invalidate_domains, u32 flush_domains)
 286 {
 287         u32 flags = 0;
 288         struct pipe_control *pc = ring->private;
 289         u32 scratch_addr = pc->gtt_offset + 128;
 290         int ret;
 291
 292         /*
 293          * Ensure that any following seqno writes only happen when the render
 294          * cache is indeed flushed.
 295          *
 296          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 297          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 298          * don't try to be clever and just set it unconditionally.
 299          */
 300         flags |= PIPE_CONTROL_CS_STALL;
 301
 302         /* Just flush everything.  Experiments have shown that reducing the
 303          * number of bits based on the write domains has little performance
 304          * impact.
 305          */
 306         if (flush_domains) {
 307                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 308                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 309         }
 310         if (invalidate_domains) {
 311                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 312                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 313                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 314                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 315                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 316                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 317                 /*
 318                  * TLB invalidate requires a post-sync write.
 319                  */
 320                 flags |= PIPE_CONTROL_QW_WRITE;
 321
 322                 /* Workaround: we must issue a pipe_control with CS-stall bit
 323                  * set before a pipe_control command that has the state cache
 324                  * invalidate bit set. */
 325                 gen7_render_ring_cs_stall_wa(ring);
 326         }
 327
 328         ret = intel_ring_begin(ring, 4);
 329         if (ret)
 330                 return ret;
 331
 332         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 333         intel_ring_emit(ring, flags);
 334         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 335         intel_ring_emit(ring, 0);
 336         intel_ring_advance(ring);
 337
 338         return 0;
 339 }
 340
 341 static void ring_write_tail(struct intel_ring_buffer *ring,
 342                             u32 value)
 343 {
 344         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 345         I915_WRITE_TAIL(ring, value);
 346 }
 347
 348 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 349 {
 350         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 351         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 352                         RING_ACTHD(ring->mmio_base) : ACTHD;
 353
 354         return I915_READ(acthd_reg);
 355 }
 356
 357 static int init_ring_common(struct intel_ring_buffer *ring)
 358 {
 359         struct drm_device *dev = ring->dev;
 360         drm_i915_private_t *dev_priv = dev->dev_private;
 361         struct drm_i915_gem_object *obj = ring->obj;
 362         int ret = 0;
 363         u32 head;
 364
 365         if (HAS_FORCE_WAKE(dev))
 366                 gen6_gt_force_wake_get(dev_priv);
 367
 368         /* Stop the ring if it's running. */
 369         I915_WRITE_CTL(ring, 0);
 370         I915_WRITE_HEAD(ring, 0);
 371         ring->write_tail(ring, 0);
 372
 373         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 374
 375         /* G45 ring initialization fails to reset head to zero */
 376         if (head != 0) {
 377                 DRM_DEBUG_KMS("%s head not reset to zero "
 378                               "ctl %08x head %08x tail %08x start %08x\n",
 379                               ring->name,
 380                               I915_READ_CTL(ring),
 381                               I915_READ_HEAD(ring),
 382                               I915_READ_TAIL(ring),
 383                               I915_READ_START(ring));
 384
 385                 I915_WRITE_HEAD(ring, 0);
 386
 387                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 388                         DRM_ERROR("failed to set %s head to zero "
 389                                   "ctl %08x head %08x tail %08x start %08x\n",
 390                                   ring->name,
 391                                   I915_READ_CTL(ring),
 392                                   I915_READ_HEAD(ring),
 393                                   I915_READ_TAIL(ring),
 394                                   I915_READ_START(ring));
 395                 }
 396         }
 397
 398         /* Initialize the ring. This must happen _after_ we've cleared the ring
 399          * registers with the above sequence (the readback of the HEAD registers
 400          * also enforces ordering), otherwise the hw might lose the new ring
 401          * register values. */
 402         I915_WRITE_START(ring, obj->gtt_offset);
 403         I915_WRITE_CTL(ring,
 404                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 405                         | RING_VALID);
 406
 407         /* If the head is still not zero, the ring is dead */
 408         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 409                      I915_READ_START(ring) == obj->gtt_offset &&
 410                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 411                 DRM_ERROR("%s initialization failed "
 412                                 "ctl %08x head %08x tail %08x start %08x\n",
 413                                 ring->name,
 414                                 I915_READ_CTL(ring),
 415                                 I915_READ_HEAD(ring),
 416                                 I915_READ_TAIL(ring),
 417                                 I915_READ_START(ring));
 418                 ret = -EIO;
 419                 goto out;
 420         }
 421
 422         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 423                 i915_kernel_lost_context(ring->dev);
 424         else {
 425                 ring->head = I915_READ_HEAD(ring);
 426                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 427                 ring->space = ring_space(ring);
 428                 ring->last_retired_head = -1;
 429         }
 430
 431 out:
 432         if (HAS_FORCE_WAKE(dev))
 433                 gen6_gt_force_wake_put(dev_priv);
 434
 435         return ret;
 436 }
 437
 438 static int
 439 init_pipe_control(struct intel_ring_buffer *ring)
 440 {
 441         struct pipe_control *pc;
 442         struct drm_i915_gem_object *obj;
 443         int ret;
 444
 445         if (ring->private)
 446                 return 0;
 447
 448         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 449         if (!pc)
 450                 return -ENOMEM;
 451
 452         obj = i915_gem_alloc_object(ring->dev, 4096);
 453         if (obj == NULL) {
 454                 DRM_ERROR("Failed to allocate seqno page\n");
 455                 ret = -ENOMEM;
 456                 goto err;
 457         }
 458
 459         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 460
 461         ret = i915_gem_object_pin(obj, 4096, true, false);
 462         if (ret)
 463                 goto err_unref;
 464
 465         pc->gtt_offset = obj->gtt_offset;
 466         pc->cpu_page =  kmap(sg_page(obj->pages->sgl));
 467         if (pc->cpu_page == NULL)
 468                 goto err_unpin;
 469
 470         pc->obj = obj;
 471         ring->private = pc;
 472         return 0;
 473
 474 err_unpin:
 475         i915_gem_object_unpin(obj);
 476 err_unref:
 477         drm_gem_object_unreference(&obj->base);
 478 err:
 479         kfree(pc);
 480         return ret;
 481 }
 482
 483 static void
 484 cleanup_pipe_control(struct intel_ring_buffer *ring)
 485 {
 486         struct pipe_control *pc = ring->private;
 487         struct drm_i915_gem_object *obj;
 488
 489         if (!ring->private)
 490                 return;
 491
 492         obj = pc->obj;
 493
 494         kunmap(sg_page(obj->pages->sgl));
 495         i915_gem_object_unpin(obj);
 496         drm_gem_object_unreference(&obj->base);
 497
 498         kfree(pc);
 499         ring->private = NULL;
 500 }
 501
 502 static int init_render_ring(struct intel_ring_buffer *ring)
 503 {
 504         struct drm_device *dev = ring->dev;
 505         struct drm_i915_private *dev_priv = dev->dev_private;
 506         int ret = init_ring_common(ring);
 507
 508         if (INTEL_INFO(dev)->gen > 3) {
 509                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 510                 if (IS_GEN7(dev))
 511                         I915_WRITE(GFX_MODE_GEN7,
 512                                    _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 513                                    _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 514         }
 515
 516         if (INTEL_INFO(dev)->gen >= 5) {
 517                 ret = init_pipe_control(ring);
 518                 if (ret)
 519                         return ret;
 520         }
 521
 522         if (IS_GEN6(dev)) {
 523                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 524                  * "If this bit is set, STCunit will have LRA as replacement
 525                  *  policy. [...] This bit must be reset.  LRA replacement
 526                  *  policy is not supported."
 527                  */
 528                 I915_WRITE(CACHE_MODE_0,
 529                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 530
 531                 /* This is not explicitly set for GEN6, so read the register.
 532                  * see intel_ring_mi_set_context() for why we care.
 533                  * TODO: consider explicitly setting the bit for GEN5
 534                  */
 535                 ring->itlb_before_ctx_switch =
 536                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 537         }
 538
 539         if (INTEL_INFO(dev)->gen >= 6)
 540                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 541
 542         if (HAS_L3_GPU_CACHE(dev))
 543                 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
 544
 545         return ret;
 546 }
 547
 548 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 549 {
 550         if (!ring->private)
 551                 return;
 552
 553         cleanup_pipe_control(ring);
 554 }
 555
 556 static void
 557 update_mboxes(struct intel_ring_buffer *ring,
 558               u32 mmio_offset)
 559 {
 560         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 561         intel_ring_emit(ring, mmio_offset);
 562         intel_ring_emit(ring, ring->outstanding_lazy_request);
 563 }
 564
 565 /**
 566  * gen6_add_request - Update the semaphore mailbox registers
 567  *
 568  * @ring - ring that is adding a request
 569  * @seqno - return seqno stuck into the ring
 570  *
 571  * Update the mailbox registers in the *other* rings with the current seqno.
 572  * This acts like a signal in the canonical semaphore.
 573  */
 574 static int
 575 gen6_add_request(struct intel_ring_buffer *ring)
 576 {
 577         u32 mbox1_reg;
 578         u32 mbox2_reg;
 579         int ret;
 580
 581         ret = intel_ring_begin(ring, 10);
 582         if (ret)
 583                 return ret;
 584
 585         mbox1_reg = ring->signal_mbox[0];
 586         mbox2_reg = ring->signal_mbox[1];
 587
 588         update_mboxes(ring, mbox1_reg);
 589         update_mboxes(ring, mbox2_reg);
 590         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 591         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 592         intel_ring_emit(ring, ring->outstanding_lazy_request);
 593         intel_ring_emit(ring, MI_USER_INTERRUPT);
 594         intel_ring_advance(ring);
 595
 596         return 0;
 597 }
 598
 599 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 600                                               u32 seqno)
 601 {
 602         struct drm_i915_private *dev_priv = dev->dev_private;
 603         return dev_priv->last_seqno < seqno;
 604 }
 605
 606 /**
 607  * intel_ring_sync - sync the waiter to the signaller on seqno
 608  *
 609  * @waiter - ring that is waiting
 610  * @signaller - ring which has, or will signal
 611  * @seqno - seqno which the waiter will block on
 612  */
 613 static int
 614 gen6_ring_sync(struct intel_ring_buffer *waiter,
 615                struct intel_ring_buffer *signaller,
 616                u32 seqno)
 617 {
 618         int ret;
 619         u32 dw1 = MI_SEMAPHORE_MBOX |
 620                   MI_SEMAPHORE_COMPARE |
 621                   MI_SEMAPHORE_REGISTER;
 622
 623         /* Throughout all of the GEM code, seqno passed implies our current
 624          * seqno is >= the last seqno executed. However for hardware the
 625          * comparison is strictly greater than.
 626          */
 627         seqno -= 1;
 628
 629         WARN_ON(signaller->semaphore_register[waiter->id] ==
 630                 MI_SEMAPHORE_SYNC_INVALID);
 631
 632         ret = intel_ring_begin(waiter, 4);
 633         if (ret)
 634                 return ret;
 635
 636         /* If seqno wrap happened, omit the wait with no-ops */
 637         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 638                 intel_ring_emit(waiter,
 639                                 dw1 |
 640                                 signaller->semaphore_register[waiter->id]);
 641                 intel_ring_emit(waiter, seqno);
 642                 intel_ring_emit(waiter, 0);
 643                 intel_ring_emit(waiter, MI_NOOP);
 644         } else {
 645                 intel_ring_emit(waiter, MI_NOOP);
 646                 intel_ring_emit(waiter, MI_NOOP);
 647                 intel_ring_emit(waiter, MI_NOOP);
 648                 intel_ring_emit(waiter, MI_NOOP);
 649         }
 650         intel_ring_advance(waiter);
 651
 652         return 0;
 653 }
 654
 655 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 656 do {                                                                    \
 657         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 658                  PIPE_CONTROL_DEPTH_STALL);                             \
 659         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 660         intel_ring_emit(ring__, 0);                                                     \
 661         intel_ring_emit(ring__, 0);                                                     \
 662 } while (0)
 663
 664 static int
 665 pc_render_add_request(struct intel_ring_buffer *ring)
 666 {
 667         struct pipe_control *pc = ring->private;
 668         u32 scratch_addr = pc->gtt_offset + 128;
 669         int ret;
 670
 671         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 672          * incoherent with writes to memory, i.e. completely fubar,
 673          * so we need to use PIPE_NOTIFY instead.
 674          *
 675          * However, we also need to workaround the qword write
 676          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 677          * memory before requesting an interrupt.
 678          */
 679         ret = intel_ring_begin(ring, 32);
 680         if (ret)
 681                 return ret;
 682
 683         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 684                         PIPE_CONTROL_WRITE_FLUSH |
 685                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 686         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 687         intel_ring_emit(ring, ring->outstanding_lazy_request);
 688         intel_ring_emit(ring, 0);
 689         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 690         scratch_addr += 128; /* write to separate cachelines */
 691         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 692         scratch_addr += 128;
 693         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 694         scratch_addr += 128;
 695         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 696         scratch_addr += 128;
 697         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 698         scratch_addr += 128;
 699         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 700
 701         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 702                         PIPE_CONTROL_WRITE_FLUSH |
 703                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 704                         PIPE_CONTROL_NOTIFY);
 705         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 706         intel_ring_emit(ring, ring->outstanding_lazy_request);
 707         intel_ring_emit(ring, 0);
 708         intel_ring_advance(ring);
 709
 710         return 0;
 711 }
 712
 713 static u32
 714 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 715 {
 716         /* Workaround to force correct ordering between irq and seqno writes on
 717          * ivb (and maybe also on snb) by reading from a CS register (like
 718          * ACTHD) before reading the status page. */
 719         if (!lazy_coherency)
 720                 intel_ring_get_active_head(ring);
 721         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 722 }
 723
 724 static u32
 725 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 726 {
 727         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 728 }
 729
 730 static u32
 731 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 732 {
 733         struct pipe_control *pc = ring->private;
 734         return pc->cpu_page[0];
 735 }
 736
 737 static bool
 738 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 739 {
 740         struct drm_device *dev = ring->dev;
 741         drm_i915_private_t *dev_priv = dev->dev_private;
 742         unsigned long flags;
 743
 744         if (!dev->irq_enabled)
 745                 return false;
 746
 747         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 748         if (ring->irq_refcount++ == 0) {
 749                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 750                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 751                 POSTING_READ(GTIMR);
 752         }
 753         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 754
 755         return true;
 756 }
 757
 758 static void
 759 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 760 {
 761         struct drm_device *dev = ring->dev;
 762         drm_i915_private_t *dev_priv = dev->dev_private;
 763         unsigned long flags;
 764
 765         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 766         if (--ring->irq_refcount == 0) {
 767                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 768                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 769                 POSTING_READ(GTIMR);
 770         }
 771         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 772 }
 773
 774 static bool
 775 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 776 {
 777         struct drm_device *dev = ring->dev;
 778         drm_i915_private_t *dev_priv = dev->dev_private;
 779         unsigned long flags;
 780
 781         if (!dev->irq_enabled)
 782                 return false;
 783
 784         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 785         if (ring->irq_refcount++ == 0) {
 786                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 787                 I915_WRITE(IMR, dev_priv->irq_mask);
 788                 POSTING_READ(IMR);
 789         }
 790         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 791
 792         return true;
 793 }
 794
 795 static void
 796 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 797 {
 798         struct drm_device *dev = ring->dev;
 799         drm_i915_private_t *dev_priv = dev->dev_private;
 800         unsigned long flags;
 801
 802         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 803         if (--ring->irq_refcount == 0) {
 804                 dev_priv->irq_mask |= ring->irq_enable_mask;
 805                 I915_WRITE(IMR, dev_priv->irq_mask);
 806                 POSTING_READ(IMR);
 807         }
 808         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 809 }
 810
 811 static bool
 812 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 813 {
 814         struct drm_device *dev = ring->dev;
 815         drm_i915_private_t *dev_priv = dev->dev_private;
 816         unsigned long flags;
 817
 818         if (!dev->irq_enabled)
 819                 return false;
 820
 821         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 822         if (ring->irq_refcount++ == 0) {
 823                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 824                 I915_WRITE16(IMR, dev_priv->irq_mask);
 825                 POSTING_READ16(IMR);
 826         }
 827         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 828
 829         return true;
 830 }
 831
 832 static void
 833 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 834 {
 835         struct drm_device *dev = ring->dev;
 836         drm_i915_private_t *dev_priv = dev->dev_private;
 837         unsigned long flags;
 838
 839         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 840         if (--ring->irq_refcount == 0) {
 841                 dev_priv->irq_mask |= ring->irq_enable_mask;
 842                 I915_WRITE16(IMR, dev_priv->irq_mask);
 843                 POSTING_READ16(IMR);
 844         }
 845         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 846 }
 847
 848 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 849 {
 850         struct drm_device *dev = ring->dev;
 851         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 852         u32 mmio = 0;
 853
 854         /* The ring status page addresses are no longer next to the rest of
 855          * the ring registers as of gen7.
 856          */
 857         if (IS_GEN7(dev)) {
 858                 switch (ring->id) {
 859                 case RCS:
 860                         mmio = RENDER_HWS_PGA_GEN7;
 861                         break;
 862                 case BCS:
 863                         mmio = BLT_HWS_PGA_GEN7;
 864                         break;
 865                 case VCS:
 866                         mmio = BSD_HWS_PGA_GEN7;
 867                         break;
 868                 }
 869         } else if (IS_GEN6(ring->dev)) {
 870                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 871         } else {
 872                 mmio = RING_HWS_PGA(ring->mmio_base);
 873         }
 874
 875         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 876         POSTING_READ(mmio);
 877 }
 878
 879 static int
 880 bsd_ring_flush(struct intel_ring_buffer *ring,
 881                u32     invalidate_domains,
 882                u32     flush_domains)
 883 {
 884         int ret;
 885
 886         ret = intel_ring_begin(ring, 2);
 887         if (ret)
 888                 return ret;
 889
 890         intel_ring_emit(ring, MI_FLUSH);
 891         intel_ring_emit(ring, MI_NOOP);
 892         intel_ring_advance(ring);
 893         return 0;
 894 }
 895
 896 static int
 897 i9xx_add_request(struct intel_ring_buffer *ring)
 898 {
 899         int ret;
 900
 901         ret = intel_ring_begin(ring, 4);
 902         if (ret)
 903                 return ret;
 904
 905         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 906         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 907         intel_ring_emit(ring, ring->outstanding_lazy_request);
 908         intel_ring_emit(ring, MI_USER_INTERRUPT);
 909         intel_ring_advance(ring);
 910
 911         return 0;
 912 }
 913
 914 static bool
 915 gen6_ring_get_irq(struct intel_ring_buffer *ring)
 916 {
 917         struct drm_device *dev = ring->dev;
 918         drm_i915_private_t *dev_priv = dev->dev_private;
 919         unsigned long flags;
 920
 921         if (!dev->irq_enabled)
 922                return false;
 923
 924         /* It looks like we need to prevent the gt from suspending while waiting
 925          * for an notifiy irq, otherwise irqs seem to get lost on at least the
 926          * blt/bsd rings on ivb. */
 927         gen6_gt_force_wake_get(dev_priv);
 928
 929         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 930         if (ring->irq_refcount++ == 0) {
 931                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
 932                         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
 933                                                 GEN6_RENDER_L3_PARITY_ERROR));
 934                 else
 935                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
 936                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 937                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 938                 POSTING_READ(GTIMR);
 939         }
 940         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 941
 942         return true;
 943 }
 944
 945 static void
 946 gen6_ring_put_irq(struct intel_ring_buffer *ring)
 947 {
 948         struct drm_device *dev = ring->dev;
 949         drm_i915_private_t *dev_priv = dev->dev_private;
 950         unsigned long flags;
 951
 952         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 953         if (--ring->irq_refcount == 0) {
 954                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
 955                         I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
 956                 else
 957                         I915_WRITE_IMR(ring, ~0);
 958                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 959                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 960                 POSTING_READ(GTIMR);
 961         }
 962         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 963
 964         gen6_gt_force_wake_put(dev_priv);
 965 }
 966
 967 static int
 968 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
 969                          u32 offset, u32 length,
 970                          unsigned flags)
 971 {
 972         int ret;
 973
 974         ret = intel_ring_begin(ring, 2);
 975         if (ret)
 976                 return ret;
 977
 978         intel_ring_emit(ring,
 979                         MI_BATCH_BUFFER_START |
 980                         MI_BATCH_GTT |
 981                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
 982         intel_ring_emit(ring, offset);
 983         intel_ring_advance(ring);
 984
 985         return 0;
 986 }
 987
 988 static int
 989 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
 990                                 u32 offset, u32 len,
 991                                 unsigned flags)
 992 {
 993         int ret;
 994
 995         ret = intel_ring_begin(ring, 4);
 996         if (ret)
 997                 return ret;
 998
 999         intel_ring_emit(ring, MI_BATCH_BUFFER);
1000         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1001         intel_ring_emit(ring, offset + len - 8);
1002         intel_ring_emit(ring, 0);
1003         intel_ring_advance(ring);
1004
1005         return 0;
1006 }
1007
1008 static int
1009 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1010                          u32 offset, u32 len,
1011                          unsigned flags)
1012 {
1013         int ret;
1014
1015         ret = intel_ring_begin(ring, 2);
1016         if (ret)
1017                 return ret;
1018
1019         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1020         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1021         intel_ring_advance(ring);
1022
1023         return 0;
1024 }
1025
1026 static void cleanup_status_page(struct intel_ring_buffer *ring)
1027 {
1028         struct drm_i915_gem_object *obj;
1029
1030         obj = ring->status_page.obj;
1031         if (obj == NULL)
1032                 return;
1033
1034         kunmap(sg_page(obj->pages->sgl));
1035         i915_gem_object_unpin(obj);
1036         drm_gem_object_unreference(&obj->base);
1037         ring->status_page.obj = NULL;
1038 }
1039
1040 static int init_status_page(struct intel_ring_buffer *ring)
1041 {
1042         struct drm_device *dev = ring->dev;
1043         struct drm_i915_gem_object *obj;
1044         int ret;
1045
1046         obj = i915_gem_alloc_object(dev, 4096);
1047         if (obj == NULL) {
1048                 DRM_ERROR("Failed to allocate status page\n");
1049                 ret = -ENOMEM;
1050                 goto err;
1051         }
1052
1053         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1054
1055         ret = i915_gem_object_pin(obj, 4096, true, false);
1056         if (ret != 0) {
1057                 goto err_unref;
1058         }
1059
1060         ring->status_page.gfx_addr = obj->gtt_offset;
1061         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1062         if (ring->status_page.page_addr == NULL) {
1063                 ret = -ENOMEM;
1064                 goto err_unpin;
1065         }
1066         ring->status_page.obj = obj;
1067         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1068
1069         intel_ring_setup_status_page(ring);
1070         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1071                         ring->name, ring->status_page.gfx_addr);
1072
1073         return 0;
1074
1075 err_unpin:
1076         i915_gem_object_unpin(obj);
1077 err_unref:
1078         drm_gem_object_unreference(&obj->base);
1079 err:
1080         return ret;
1081 }
1082
1083 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
1084 {
1085         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1086         u32 addr;
1087
1088         if (!dev_priv->status_page_dmah) {
1089                 dev_priv->status_page_dmah =
1090                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1091                 if (!dev_priv->status_page_dmah)
1092                         return -ENOMEM;
1093         }
1094
1095         addr = dev_priv->status_page_dmah->busaddr;
1096         if (INTEL_INFO(ring->dev)->gen >= 4)
1097                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
1098         I915_WRITE(HWS_PGA, addr);
1099
1100         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1101         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1102
1103         return 0;
1104 }
1105
1106 static int intel_init_ring_buffer(struct drm_device *dev,
1107                                   struct intel_ring_buffer *ring)
1108 {
1109         struct drm_i915_gem_object *obj;
1110         struct drm_i915_private *dev_priv = dev->dev_private;
1111         int ret;
1112
1113         ring->dev = dev;
1114         INIT_LIST_HEAD(&ring->active_list);
1115         INIT_LIST_HEAD(&ring->request_list);
1116         ring->size = 32 * PAGE_SIZE;
1117         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1118
1119         init_waitqueue_head(&ring->irq_queue);
1120
1121         if (I915_NEED_GFX_HWS(dev)) {
1122                 ret = init_status_page(ring);
1123                 if (ret)
1124                         return ret;
1125         } else {
1126                 BUG_ON(ring->id != RCS);
1127                 ret = init_phys_hws_pga(ring);
1128                 if (ret)
1129                         return ret;
1130         }
1131
1132         obj = NULL;
1133         if (!HAS_LLC(dev))
1134                 obj = i915_gem_object_create_stolen(dev, ring->size);
1135         if (obj == NULL)
1136                 obj = i915_gem_alloc_object(dev, ring->size);
1137         if (obj == NULL) {
1138                 DRM_ERROR("Failed to allocate ringbuffer\n");
1139                 ret = -ENOMEM;
1140                 goto err_hws;
1141         }
1142
1143         ring->obj = obj;
1144
1145         ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1146         if (ret)
1147                 goto err_unref;
1148
1149         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1150         if (ret)
1151                 goto err_unpin;
1152
1153         ring->virtual_start =
1154                 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1155                            ring->size);
1156         if (ring->virtual_start == NULL) {
1157                 DRM_ERROR("Failed to map ringbuffer.\n");
1158                 ret = -EINVAL;
1159                 goto err_unpin;
1160         }
1161
1162         ret = ring->init(ring);
1163         if (ret)
1164                 goto err_unmap;
1165
1166         /* Workaround an erratum on the i830 which causes a hang if
1167          * the TAIL pointer points to within the last 2 cachelines
1168          * of the buffer.
1169          */
1170         ring->effective_size = ring->size;
1171         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1172                 ring->effective_size -= 128;
1173
1174         return 0;
1175
1176 err_unmap:
1177         iounmap(ring->virtual_start);
1178 err_unpin:
1179         i915_gem_object_unpin(obj);
1180 err_unref:
1181         drm_gem_object_unreference(&obj->base);
1182         ring->obj = NULL;
1183 err_hws:
1184         cleanup_status_page(ring);
1185         return ret;
1186 }
1187
1188 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1189 {
1190         struct drm_i915_private *dev_priv;
1191         int ret;
1192
1193         if (ring->obj == NULL)
1194                 return;
1195
1196         /* Disable the ring buffer. The ring must be idle at this point */
1197         dev_priv = ring->dev->dev_private;
1198         ret = intel_ring_idle(ring);
1199         if (ret)
1200                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1201                           ring->name, ret);
1202
1203         I915_WRITE_CTL(ring, 0);
1204
1205         iounmap(ring->virtual_start);
1206
1207         i915_gem_object_unpin(ring->obj);
1208         drm_gem_object_unreference(&ring->obj->base);
1209         ring->obj = NULL;
1210
1211         if (ring->cleanup)
1212                 ring->cleanup(ring);
1213
1214         cleanup_status_page(ring);
1215 }
1216
1217 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1218 {
1219         int ret;
1220
1221         ret = i915_wait_seqno(ring, seqno);
1222         if (!ret)
1223                 i915_gem_retire_requests_ring(ring);
1224
1225         return ret;
1226 }
1227
1228 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1229 {
1230         struct drm_i915_gem_request *request;
1231         u32 seqno = 0;
1232         int ret;
1233
1234         i915_gem_retire_requests_ring(ring);
1235
1236         if (ring->last_retired_head != -1) {
1237                 ring->head = ring->last_retired_head;
1238                 ring->last_retired_head = -1;
1239                 ring->space = ring_space(ring);
1240                 if (ring->space >= n)
1241                         return 0;
1242         }
1243
1244         list_for_each_entry(request, &ring->request_list, list) {
1245                 int space;
1246
1247                 if (request->tail == -1)
1248                         continue;
1249
1250                 space = request->tail - (ring->tail + 8);
1251                 if (space < 0)
1252                         space += ring->size;
1253                 if (space >= n) {
1254                         seqno = request->seqno;
1255                         break;
1256                 }
1257
1258                 /* Consume this request in case we need more space than
1259                  * is available and so need to prevent a race between
1260                  * updating last_retired_head and direct reads of
1261                  * I915_RING_HEAD. It also provides a nice sanity check.
1262                  */
1263                 request->tail = -1;
1264         }
1265
1266         if (seqno == 0)
1267                 return -ENOSPC;
1268
1269         ret = intel_ring_wait_seqno(ring, seqno);
1270         if (ret)
1271                 return ret;
1272
1273         if (WARN_ON(ring->last_retired_head == -1))
1274                 return -ENOSPC;
1275
1276         ring->head = ring->last_retired_head;
1277         ring->last_retired_head = -1;
1278         ring->space = ring_space(ring);
1279         if (WARN_ON(ring->space < n))
1280                 return -ENOSPC;
1281
1282         return 0;
1283 }
1284
1285 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1286 {
1287         struct drm_device *dev = ring->dev;
1288         struct drm_i915_private *dev_priv = dev->dev_private;
1289         unsigned long end;
1290         int ret;
1291
1292         ret = intel_ring_wait_request(ring, n);
1293         if (ret != -ENOSPC)
1294                 return ret;
1295
1296         trace_i915_ring_wait_begin(ring);
1297         /* With GEM the hangcheck timer should kick us out of the loop,
1298          * leaving it early runs the risk of corrupting GEM state (due
1299          * to running on almost untested codepaths). But on resume
1300          * timers don't work yet, so prevent a complete hang in that
1301          * case by choosing an insanely large timeout. */
1302         end = jiffies + 60 * HZ;
1303
1304         do {
1305                 ring->head = I915_READ_HEAD(ring);
1306                 ring->space = ring_space(ring);
1307                 if (ring->space >= n) {
1308                         trace_i915_ring_wait_end(ring);
1309                         return 0;
1310                 }
1311
1312                 if (dev->primary->master) {
1313                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1314                         if (master_priv->sarea_priv)
1315                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1316                 }
1317
1318                 msleep(1);
1319
1320                 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1321                 if (ret)
1322                         return ret;
1323         } while (!time_after(jiffies, end));
1324         trace_i915_ring_wait_end(ring);
1325         return -EBUSY;
1326 }
1327
1328 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1329 {
1330         uint32_t __iomem *virt;
1331         int rem = ring->size - ring->tail;
1332
1333         if (ring->space < rem) {
1334                 int ret = ring_wait_for_space(ring, rem);
1335                 if (ret)
1336                         return ret;
1337         }
1338
1339         virt = ring->virtual_start + ring->tail;
1340         rem /= 4;
1341         while (rem--)
1342                 iowrite32(MI_NOOP, virt++);
1343
1344         ring->tail = 0;
1345         ring->space = ring_space(ring);
1346
1347         return 0;
1348 }
1349
1350 int intel_ring_idle(struct intel_ring_buffer *ring)
1351 {
1352         u32 seqno;
1353         int ret;
1354
1355         /* We need to add any requests required to flush the objects and ring */
1356         if (ring->outstanding_lazy_request) {
1357                 ret = i915_add_request(ring, NULL, NULL);
1358                 if (ret)
1359                         return ret;
1360         }
1361
1362         /* Wait upon the last request to be completed */
1363         if (list_empty(&ring->request_list))
1364                 return 0;
1365
1366         seqno = list_entry(ring->request_list.prev,
1367                            struct drm_i915_gem_request,
1368                            list)->seqno;
1369
1370         return i915_wait_seqno(ring, seqno);
1371 }
1372
1373 static int
1374 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1375 {
1376         if (ring->outstanding_lazy_request)
1377                 return 0;
1378
1379         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1380 }
1381
1382 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1383                               int bytes)
1384 {
1385         int ret;
1386
1387         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1388                 ret = intel_wrap_ring_buffer(ring);
1389                 if (unlikely(ret))
1390                         return ret;
1391         }
1392
1393         if (unlikely(ring->space < bytes)) {
1394                 ret = ring_wait_for_space(ring, bytes);
1395                 if (unlikely(ret))
1396                         return ret;
1397         }
1398
1399         ring->space -= bytes;
1400         return 0;
1401 }
1402
1403 int intel_ring_begin(struct intel_ring_buffer *ring,
1404                      int num_dwords)
1405 {
1406         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1407         int ret;
1408
1409         ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1410         if (ret)
1411                 return ret;
1412
1413         /* Preallocate the olr before touching the ring */
1414         ret = intel_ring_alloc_seqno(ring);
1415         if (ret)
1416                 return ret;
1417
1418         return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1419 }
1420
1421 int intel_ring_handle_seqno_wrap(struct intel_ring_buffer *ring)
1422 {
1423         int ret;
1424
1425         BUG_ON(ring->outstanding_lazy_request);
1426
1427         if (INTEL_INFO(ring->dev)->gen < 6)
1428                 return 0;
1429
1430         ret = __intel_ring_begin(ring, 6 * sizeof(uint32_t));
1431         if (ret)
1432                 return ret;
1433
1434         /* Leaving a stale, pre-wrap seqno behind in the mboxes will result in
1435          * post-wrap semaphore waits completing immediately. Clear them. */
1436         update_mboxes(ring, ring->signal_mbox[0]);
1437         update_mboxes(ring, ring->signal_mbox[1]);
1438         intel_ring_advance(ring);
1439
1440         return 0;
1441 }
1442
1443 void intel_ring_advance(struct intel_ring_buffer *ring)
1444 {
1445         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1446
1447         ring->tail &= ring->size - 1;
1448         if (dev_priv->stop_rings & intel_ring_flag(ring))
1449                 return;
1450         ring->write_tail(ring, ring->tail);
1451 }
1452
1453
1454 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1455                                      u32 value)
1456 {
1457         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1458
1459        /* Every tail move must follow the sequence below */
1460
1461         /* Disable notification that the ring is IDLE. The GT
1462          * will then assume that it is busy and bring it out of rc6.
1463          */
1464         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1465                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1466
1467         /* Clear the context id. Here be magic! */
1468         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1469
1470         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1471         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1472                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1473                      50))
1474                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1475
1476         /* Now that the ring is fully powered up, update the tail */
1477         I915_WRITE_TAIL(ring, value);
1478         POSTING_READ(RING_TAIL(ring->mmio_base));
1479
1480         /* Let the ring send IDLE messages to the GT again,
1481          * and so let it sleep to conserve power when idle.
1482          */
1483         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1484                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1485 }
1486
1487 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1488                            u32 invalidate, u32 flush)
1489 {
1490         uint32_t cmd;
1491         int ret;
1492
1493         ret = intel_ring_begin(ring, 4);
1494         if (ret)
1495                 return ret;
1496
1497         cmd = MI_FLUSH_DW;
1498         /*
1499          * Bspec vol 1c.5 - video engine command streamer:
1500          * "If ENABLED, all TLBs will be invalidated once the flush
1501          * operation is complete. This bit is only valid when the
1502          * Post-Sync Operation field is a value of 1h or 3h."
1503          */
1504         if (invalidate & I915_GEM_GPU_DOMAINS)
1505                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1506                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1507         intel_ring_emit(ring, cmd);
1508         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1509         intel_ring_emit(ring, 0);
1510         intel_ring_emit(ring, MI_NOOP);
1511         intel_ring_advance(ring);
1512         return 0;
1513 }
1514
1515 static int
1516 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1517                               u32 offset, u32 len,
1518                               unsigned flags)
1519 {
1520         int ret;
1521
1522         ret = intel_ring_begin(ring, 2);
1523         if (ret)
1524                 return ret;
1525
1526         intel_ring_emit(ring,
1527                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1528                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1529         /* bit0-7 is the length on GEN6+ */
1530         intel_ring_emit(ring, offset);
1531         intel_ring_advance(ring);
1532
1533         return 0;
1534 }
1535
1536 static int
1537 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1538                               u32 offset, u32 len,
1539                               unsigned flags)
1540 {
1541         int ret;
1542
1543         ret = intel_ring_begin(ring, 2);
1544         if (ret)
1545                 return ret;
1546
1547         intel_ring_emit(ring,
1548                         MI_BATCH_BUFFER_START |
1549                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1550         /* bit0-7 is the length on GEN6+ */
1551         intel_ring_emit(ring, offset);
1552         intel_ring_advance(ring);
1553
1554         return 0;
1555 }
1556
1557 /* Blitter support (SandyBridge+) */
1558
1559 static int blt_ring_flush(struct intel_ring_buffer *ring,
1560                           u32 invalidate, u32 flush)
1561 {
1562         uint32_t cmd;
1563         int ret;
1564
1565         ret = intel_ring_begin(ring, 4);
1566         if (ret)
1567                 return ret;
1568
1569         cmd = MI_FLUSH_DW;
1570         /*
1571          * Bspec vol 1c.3 - blitter engine command streamer:
1572          * "If ENABLED, all TLBs will be invalidated once the flush
1573          * operation is complete. This bit is only valid when the
1574          * Post-Sync Operation field is a value of 1h or 3h."
1575          */
1576         if (invalidate & I915_GEM_DOMAIN_RENDER)
1577                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1578                         MI_FLUSH_DW_OP_STOREDW;
1579         intel_ring_emit(ring, cmd);
1580         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1581         intel_ring_emit(ring, 0);
1582         intel_ring_emit(ring, MI_NOOP);
1583         intel_ring_advance(ring);
1584         return 0;
1585 }
1586
1587 int intel_init_render_ring_buffer(struct drm_device *dev)
1588 {
1589         drm_i915_private_t *dev_priv = dev->dev_private;
1590         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1591
1592         ring->name = "render ring";
1593         ring->id = RCS;
1594         ring->mmio_base = RENDER_RING_BASE;
1595
1596         if (INTEL_INFO(dev)->gen >= 6) {
1597                 ring->add_request = gen6_add_request;
1598                 ring->flush = gen7_render_ring_flush;
1599                 if (INTEL_INFO(dev)->gen == 6)
1600                         ring->flush = gen6_render_ring_flush;
1601                 ring->irq_get = gen6_ring_get_irq;
1602                 ring->irq_put = gen6_ring_put_irq;
1603                 ring->irq_enable_mask = GT_USER_INTERRUPT;
1604                 ring->get_seqno = gen6_ring_get_seqno;
1605                 ring->sync_to = gen6_ring_sync;
1606                 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1607                 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1608                 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1609                 ring->signal_mbox[0] = GEN6_VRSYNC;
1610                 ring->signal_mbox[1] = GEN6_BRSYNC;
1611         } else if (IS_GEN5(dev)) {
1612                 ring->add_request = pc_render_add_request;
1613                 ring->flush = gen4_render_ring_flush;
1614                 ring->get_seqno = pc_render_get_seqno;
1615                 ring->irq_get = gen5_ring_get_irq;
1616                 ring->irq_put = gen5_ring_put_irq;
1617                 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1618         } else {
1619                 ring->add_request = i9xx_add_request;
1620                 if (INTEL_INFO(dev)->gen < 4)
1621                         ring->flush = gen2_render_ring_flush;
1622                 else
1623                         ring->flush = gen4_render_ring_flush;
1624                 ring->get_seqno = ring_get_seqno;
1625                 if (IS_GEN2(dev)) {
1626                         ring->irq_get = i8xx_ring_get_irq;
1627                         ring->irq_put = i8xx_ring_put_irq;
1628                 } else {
1629                         ring->irq_get = i9xx_ring_get_irq;
1630                         ring->irq_put = i9xx_ring_put_irq;
1631                 }
1632                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1633         }
1634         ring->write_tail = ring_write_tail;
1635         if (IS_HASWELL(dev))
1636                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1637         else if (INTEL_INFO(dev)->gen >= 6)
1638                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1639         else if (INTEL_INFO(dev)->gen >= 4)
1640                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1641         else if (IS_I830(dev) || IS_845G(dev))
1642                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1643         else
1644                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1645         ring->init = init_render_ring;
1646         ring->cleanup = render_ring_cleanup;
1647
1648         return intel_init_ring_buffer(dev, ring);
1649 }
1650
1651 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1652 {
1653         drm_i915_private_t *dev_priv = dev->dev_private;
1654         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1655         int ret;
1656
1657         ring->name = "render ring";
1658         ring->id = RCS;
1659         ring->mmio_base = RENDER_RING_BASE;
1660
1661         if (INTEL_INFO(dev)->gen >= 6) {
1662                 /* non-kms not supported on gen6+ */
1663                 return -ENODEV;
1664         }
1665
1666         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1667          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1668          * the special gen5 functions. */
1669         ring->add_request = i9xx_add_request;
1670         if (INTEL_INFO(dev)->gen < 4)
1671                 ring->flush = gen2_render_ring_flush;
1672         else
1673                 ring->flush = gen4_render_ring_flush;
1674         ring->get_seqno = ring_get_seqno;
1675         if (IS_GEN2(dev)) {
1676                 ring->irq_get = i8xx_ring_get_irq;
1677                 ring->irq_put = i8xx_ring_put_irq;
1678         } else {
1679                 ring->irq_get = i9xx_ring_get_irq;
1680                 ring->irq_put = i9xx_ring_put_irq;
1681         }
1682         ring->irq_enable_mask = I915_USER_INTERRUPT;
1683         ring->write_tail = ring_write_tail;
1684         if (INTEL_INFO(dev)->gen >= 4)
1685                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1686         else if (IS_I830(dev) || IS_845G(dev))
1687                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1688         else
1689                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1690         ring->init = init_render_ring;
1691         ring->cleanup = render_ring_cleanup;
1692
1693         ring->dev = dev;
1694         INIT_LIST_HEAD(&ring->active_list);
1695         INIT_LIST_HEAD(&ring->request_list);
1696
1697         ring->size = size;
1698         ring->effective_size = ring->size;
1699         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1700                 ring->effective_size -= 128;
1701
1702         ring->virtual_start = ioremap_wc(start, size);
1703         if (ring->virtual_start == NULL) {
1704                 DRM_ERROR("can not ioremap virtual address for"
1705                           " ring buffer\n");
1706                 return -ENOMEM;
1707         }
1708
1709         if (!I915_NEED_GFX_HWS(dev)) {
1710                 ret = init_phys_hws_pga(ring);
1711                 if (ret)
1712                         return ret;
1713         }
1714
1715         return 0;
1716 }
1717
1718 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1719 {
1720         drm_i915_private_t *dev_priv = dev->dev_private;
1721         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1722
1723         ring->name = "bsd ring";
1724         ring->id = VCS;
1725
1726         ring->write_tail = ring_write_tail;
1727         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1728                 ring->mmio_base = GEN6_BSD_RING_BASE;
1729                 /* gen6 bsd needs a special wa for tail updates */
1730                 if (IS_GEN6(dev))
1731                         ring->write_tail = gen6_bsd_ring_write_tail;
1732                 ring->flush = gen6_ring_flush;
1733                 ring->add_request = gen6_add_request;
1734                 ring->get_seqno = gen6_ring_get_seqno;
1735                 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1736                 ring->irq_get = gen6_ring_get_irq;
1737                 ring->irq_put = gen6_ring_put_irq;
1738                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1739                 ring->sync_to = gen6_ring_sync;
1740                 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1741                 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1742                 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1743                 ring->signal_mbox[0] = GEN6_RVSYNC;
1744                 ring->signal_mbox[1] = GEN6_BVSYNC;
1745         } else {
1746                 ring->mmio_base = BSD_RING_BASE;
1747                 ring->flush = bsd_ring_flush;
1748                 ring->add_request = i9xx_add_request;
1749                 ring->get_seqno = ring_get_seqno;
1750                 if (IS_GEN5(dev)) {
1751                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1752                         ring->irq_get = gen5_ring_get_irq;
1753                         ring->irq_put = gen5_ring_put_irq;
1754                 } else {
1755                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1756                         ring->irq_get = i9xx_ring_get_irq;
1757                         ring->irq_put = i9xx_ring_put_irq;
1758                 }
1759                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1760         }
1761         ring->init = init_ring_common;
1762
1763         return intel_init_ring_buffer(dev, ring);
1764 }
1765
1766 int intel_init_blt_ring_buffer(struct drm_device *dev)
1767 {
1768         drm_i915_private_t *dev_priv = dev->dev_private;
1769         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1770
1771         ring->name = "blitter ring";
1772         ring->id = BCS;
1773
1774         ring->mmio_base = BLT_RING_BASE;
1775         ring->write_tail = ring_write_tail;
1776         ring->flush = blt_ring_flush;
1777         ring->add_request = gen6_add_request;
1778         ring->get_seqno = gen6_ring_get_seqno;
1779         ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1780         ring->irq_get = gen6_ring_get_irq;
1781         ring->irq_put = gen6_ring_put_irq;
1782         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1783         ring->sync_to = gen6_ring_sync;
1784         ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1785         ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1786         ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1787         ring->signal_mbox[0] = GEN6_RBSYNC;
1788         ring->signal_mbox[1] = GEN6_VBSYNC;
1789         ring->init = init_ring_common;
1790
1791         return intel_init_ring_buffer(dev, ring);
1792 }
1793
1794 int
1795 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1796 {
1797         int ret;
1798
1799         if (!ring->gpu_caches_dirty)
1800                 return 0;
1801
1802         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1803         if (ret)
1804                 return ret;
1805
1806         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1807
1808         ring->gpu_caches_dirty = false;
1809         return 0;
1810 }
1811
1812 int
1813 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1814 {
1815         uint32_t flush_domains;
1816         int ret;
1817
1818         flush_domains = 0;
1819         if (ring->gpu_caches_dirty)
1820                 flush_domains = I915_GEM_GPU_DOMAINS;
1821
1822         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1823         if (ret)
1824                 return ret;
1825
1826         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1827
1828         ring->gpu_caches_dirty = false;
1829         return 0;
1830 }