drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 /*
  38  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  39  * over cache flushing.
  40  */
  41 struct pipe_control {
  42         struct drm_i915_gem_object *obj;
  43         volatile u32 *cpu_page;
  44         u32 gtt_offset;
  45 };
  46
  47 static inline int ring_space(struct intel_ring_buffer *ring)
  48 {
  49         int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
  50         if (space < 0)
  51                 space += ring->size;
  52         return space;
  53 }
  54
  55 static u32 i915_gem_get_seqno(struct drm_device *dev)
  56 {
  57         drm_i915_private_t *dev_priv = dev->dev_private;
  58         u32 seqno;
  59
  60         seqno = dev_priv->next_seqno;
  61
  62         /* reserve 0 for non-seqno */
  63         if (++dev_priv->next_seqno == 0)
  64                 dev_priv->next_seqno = 1;
  65
  66         return seqno;
  67 }
  68
  69 static int
  70 render_ring_flush(struct intel_ring_buffer *ring,
  71                   u32   invalidate_domains,
  72                   u32   flush_domains)
  73 {
  74         struct drm_device *dev = ring->dev;
  75         u32 cmd;
  76         int ret;
  77
  78         /*
  79          * read/write caches:
  80          *
  81          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  82          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  83          * also flushed at 2d versus 3d pipeline switches.
  84          *
  85          * read-only caches:
  86          *
  87          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  88          * MI_READ_FLUSH is set, and is always flushed on 965.
  89          *
  90          * I915_GEM_DOMAIN_COMMAND may not exist?
  91          *
  92          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
  93          * invalidated when MI_EXE_FLUSH is set.
  94          *
  95          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
  96          * invalidated with every MI_FLUSH.
  97          *
  98          * TLBs:
  99          *
 100          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 101          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 102          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 103          * are flushed at any MI_FLUSH.
 104          */
 105
 106         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 107         if ((invalidate_domains|flush_domains) &
 108             I915_GEM_DOMAIN_RENDER)
 109                 cmd &= ~MI_NO_WRITE_FLUSH;
 110         if (INTEL_INFO(dev)->gen < 4) {
 111                 /*
 112                  * On the 965, the sampler cache always gets flushed
 113                  * and this bit is reserved.
 114                  */
 115                 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 116                         cmd |= MI_READ_FLUSH;
 117         }
 118         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 119                 cmd |= MI_EXE_FLUSH;
 120
 121         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 122             (IS_G4X(dev) || IS_GEN5(dev)))
 123                 cmd |= MI_INVALIDATE_ISP;
 124
 125         ret = intel_ring_begin(ring, 2);
 126         if (ret)
 127                 return ret;
 128
 129         intel_ring_emit(ring, cmd);
 130         intel_ring_emit(ring, MI_NOOP);
 131         intel_ring_advance(ring);
 132
 133         return 0;
 134 }
 135
 136 /**
 137  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 138  * implementing two workarounds on gen6.  From section 1.4.7.1
 139  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 140  *
 141  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 142  * produced by non-pipelined state commands), software needs to first
 143  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 144  * 0.
 145  *
 146  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 147  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 148  *
 149  * And the workaround for these two requires this workaround first:
 150  *
 151  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 152  * BEFORE the pipe-control with a post-sync op and no write-cache
 153  * flushes.
 154  *
 155  * And this last workaround is tricky because of the requirements on
 156  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 157  * volume 2 part 1:
 158  *
 159  *     "1 of the following must also be set:
 160  *      - Render Target Cache Flush Enable ([12] of DW1)
 161  *      - Depth Cache Flush Enable ([0] of DW1)
 162  *      - Stall at Pixel Scoreboard ([1] of DW1)
 163  *      - Depth Stall ([13] of DW1)
 164  *      - Post-Sync Operation ([13] of DW1)
 165  *      - Notify Enable ([8] of DW1)"
 166  *
 167  * The cache flushes require the workaround flush that triggered this
 168  * one, so we can't use it.  Depth stall would trigger the same.
 169  * Post-sync nonzero is what triggered this second workaround, so we
 170  * can't use that one either.  Notify enable is IRQs, which aren't
 171  * really our business.  That leaves only stall at scoreboard.
 172  */
 173 static int
 174 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 175 {
 176         struct pipe_control *pc = ring->private;
 177         u32 scratch_addr = pc->gtt_offset + 128;
 178         int ret;
 179
 180
 181         ret = intel_ring_begin(ring, 6);
 182         if (ret)
 183                 return ret;
 184
 185         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 186         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 187                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 188         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 189         intel_ring_emit(ring, 0); /* low dword */
 190         intel_ring_emit(ring, 0); /* high dword */
 191         intel_ring_emit(ring, MI_NOOP);
 192         intel_ring_advance(ring);
 193
 194         ret = intel_ring_begin(ring, 6);
 195         if (ret)
 196                 return ret;
 197
 198         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 199         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 200         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 201         intel_ring_emit(ring, 0);
 202         intel_ring_emit(ring, 0);
 203         intel_ring_emit(ring, MI_NOOP);
 204         intel_ring_advance(ring);
 205
 206         return 0;
 207 }
 208
 209 static int
 210 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 211                          u32 invalidate_domains, u32 flush_domains)
 212 {
 213         u32 flags = 0;
 214         struct pipe_control *pc = ring->private;
 215         u32 scratch_addr = pc->gtt_offset + 128;
 216         int ret;
 217
 218         /* Force SNB workarounds for PIPE_CONTROL flushes */
 219         intel_emit_post_sync_nonzero_flush(ring);
 220
 221         /* Just flush everything.  Experiments have shown that reducing the
 222          * number of bits based on the write domains has little performance
 223          * impact.
 224          */
 225         flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 226         flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 227         flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 228         flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 229         flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 230         flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 231         flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 232
 233         ret = intel_ring_begin(ring, 6);
 234         if (ret)
 235                 return ret;
 236
 237         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 238         intel_ring_emit(ring, flags);
 239         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 240         intel_ring_emit(ring, 0); /* lower dword */
 241         intel_ring_emit(ring, 0); /* uppwer dword */
 242         intel_ring_emit(ring, MI_NOOP);
 243         intel_ring_advance(ring);
 244
 245         return 0;
 246 }
 247
 248 static void ring_write_tail(struct intel_ring_buffer *ring,
 249                             u32 value)
 250 {
 251         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 252         I915_WRITE_TAIL(ring, value);
 253 }
 254
 255 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 256 {
 257         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 258         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 259                         RING_ACTHD(ring->mmio_base) : ACTHD;
 260
 261         return I915_READ(acthd_reg);
 262 }
 263
 264 static int init_ring_common(struct intel_ring_buffer *ring)
 265 {
 266         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 267         struct drm_i915_gem_object *obj = ring->obj;
 268         u32 head;
 269
 270         /* Stop the ring if it's running. */
 271         I915_WRITE_CTL(ring, 0);
 272         I915_WRITE_HEAD(ring, 0);
 273         ring->write_tail(ring, 0);
 274
 275         /* Initialize the ring. */
 276         I915_WRITE_START(ring, obj->gtt_offset);
 277         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 278
 279         /* G45 ring initialization fails to reset head to zero */
 280         if (head != 0) {
 281                 DRM_DEBUG_KMS("%s head not reset to zero "
 282                               "ctl %08x head %08x tail %08x start %08x\n",
 283                               ring->name,
 284                               I915_READ_CTL(ring),
 285                               I915_READ_HEAD(ring),
 286                               I915_READ_TAIL(ring),
 287                               I915_READ_START(ring));
 288
 289                 I915_WRITE_HEAD(ring, 0);
 290
 291                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 292                         DRM_ERROR("failed to set %s head to zero "
 293                                   "ctl %08x head %08x tail %08x start %08x\n",
 294                                   ring->name,
 295                                   I915_READ_CTL(ring),
 296                                   I915_READ_HEAD(ring),
 297                                   I915_READ_TAIL(ring),
 298                                   I915_READ_START(ring));
 299                 }
 300         }
 301
 302         I915_WRITE_CTL(ring,
 303                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 304                         | RING_REPORT_64K | RING_VALID);
 305
 306         /* If the head is still not zero, the ring is dead */
 307         if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
 308             I915_READ_START(ring) != obj->gtt_offset ||
 309             (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
 310                 DRM_ERROR("%s initialization failed "
 311                                 "ctl %08x head %08x tail %08x start %08x\n",
 312                                 ring->name,
 313                                 I915_READ_CTL(ring),
 314                                 I915_READ_HEAD(ring),
 315                                 I915_READ_TAIL(ring),
 316                                 I915_READ_START(ring));
 317                 return -EIO;
 318         }
 319
 320         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 321                 i915_kernel_lost_context(ring->dev);
 322         else {
 323                 ring->head = I915_READ_HEAD(ring);
 324                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 325                 ring->space = ring_space(ring);
 326         }
 327
 328         return 0;
 329 }
 330
 331 static int
 332 init_pipe_control(struct intel_ring_buffer *ring)
 333 {
 334         struct pipe_control *pc;
 335         struct drm_i915_gem_object *obj;
 336         int ret;
 337
 338         if (ring->private)
 339                 return 0;
 340
 341         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 342         if (!pc)
 343                 return -ENOMEM;
 344
 345         obj = i915_gem_alloc_object(ring->dev, 4096);
 346         if (obj == NULL) {
 347                 DRM_ERROR("Failed to allocate seqno page\n");
 348                 ret = -ENOMEM;
 349                 goto err;
 350         }
 351
 352         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 353
 354         ret = i915_gem_object_pin(obj, 4096, true);
 355         if (ret)
 356                 goto err_unref;
 357
 358         pc->gtt_offset = obj->gtt_offset;
 359         pc->cpu_page =  kmap(obj->pages[0]);
 360         if (pc->cpu_page == NULL)
 361                 goto err_unpin;
 362
 363         pc->obj = obj;
 364         ring->private = pc;
 365         return 0;
 366
 367 err_unpin:
 368         i915_gem_object_unpin(obj);
 369 err_unref:
 370         drm_gem_object_unreference(&obj->base);
 371 err:
 372         kfree(pc);
 373         return ret;
 374 }
 375
 376 static void
 377 cleanup_pipe_control(struct intel_ring_buffer *ring)
 378 {
 379         struct pipe_control *pc = ring->private;
 380         struct drm_i915_gem_object *obj;
 381
 382         if (!ring->private)
 383                 return;
 384
 385         obj = pc->obj;
 386         kunmap(obj->pages[0]);
 387         i915_gem_object_unpin(obj);
 388         drm_gem_object_unreference(&obj->base);
 389
 390         kfree(pc);
 391         ring->private = NULL;
 392 }
 393
 394 static int init_render_ring(struct intel_ring_buffer *ring)
 395 {
 396         struct drm_device *dev = ring->dev;
 397         struct drm_i915_private *dev_priv = dev->dev_private;
 398         int ret = init_ring_common(ring);
 399
 400         if (INTEL_INFO(dev)->gen > 3) {
 401                 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
 402                 I915_WRITE(MI_MODE, mode);
 403                 if (IS_GEN7(dev))
 404                         I915_WRITE(GFX_MODE_GEN7,
 405                                    GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 406                                    GFX_MODE_ENABLE(GFX_REPLAY_MODE));
 407         }
 408
 409         if (INTEL_INFO(dev)->gen >= 5) {
 410                 ret = init_pipe_control(ring);
 411                 if (ret)
 412                         return ret;
 413         }
 414
 415         if (INTEL_INFO(dev)->gen >= 6) {
 416                 I915_WRITE(INSTPM,
 417                            INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
 418         }
 419
 420         return ret;
 421 }
 422
 423 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 424 {
 425         if (!ring->private)
 426                 return;
 427
 428         cleanup_pipe_control(ring);
 429 }
 430
 431 static void
 432 update_mboxes(struct intel_ring_buffer *ring,
 433             u32 seqno,
 434             u32 mmio_offset)
 435 {
 436         intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
 437                               MI_SEMAPHORE_GLOBAL_GTT |
 438                               MI_SEMAPHORE_REGISTER |
 439                               MI_SEMAPHORE_UPDATE);
 440         intel_ring_emit(ring, seqno);
 441         intel_ring_emit(ring, mmio_offset);
 442 }
 443
 444 /**
 445  * gen6_add_request - Update the semaphore mailbox registers
 446  *
 447  * @ring - ring that is adding a request
 448  * @seqno - return seqno stuck into the ring
 449  *
 450  * Update the mailbox registers in the *other* rings with the current seqno.
 451  * This acts like a signal in the canonical semaphore.
 452  */
 453 static int
 454 gen6_add_request(struct intel_ring_buffer *ring,
 455                  u32 *seqno)
 456 {
 457         u32 mbox1_reg;
 458         u32 mbox2_reg;
 459         int ret;
 460
 461         ret = intel_ring_begin(ring, 10);
 462         if (ret)
 463                 return ret;
 464
 465         mbox1_reg = ring->signal_mbox[0];
 466         mbox2_reg = ring->signal_mbox[1];
 467
 468         *seqno = i915_gem_get_seqno(ring->dev);
 469
 470         update_mboxes(ring, *seqno, mbox1_reg);
 471         update_mboxes(ring, *seqno, mbox2_reg);
 472         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 473         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 474         intel_ring_emit(ring, *seqno);
 475         intel_ring_emit(ring, MI_USER_INTERRUPT);
 476         intel_ring_advance(ring);
 477
 478         return 0;
 479 }
 480
 481 /**
 482  * intel_ring_sync - sync the waiter to the signaller on seqno
 483  *
 484  * @waiter - ring that is waiting
 485  * @signaller - ring which has, or will signal
 486  * @seqno - seqno which the waiter will block on
 487  */
 488 static int
 489 intel_ring_sync(struct intel_ring_buffer *waiter,
 490                 struct intel_ring_buffer *signaller,
 491                 int ring,
 492                 u32 seqno)
 493 {
 494         int ret;
 495         u32 dw1 = MI_SEMAPHORE_MBOX |
 496                   MI_SEMAPHORE_COMPARE |
 497                   MI_SEMAPHORE_REGISTER;
 498
 499         ret = intel_ring_begin(waiter, 4);
 500         if (ret)
 501                 return ret;
 502
 503         intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
 504         intel_ring_emit(waiter, seqno);
 505         intel_ring_emit(waiter, 0);
 506         intel_ring_emit(waiter, MI_NOOP);
 507         intel_ring_advance(waiter);
 508
 509         return 0;
 510 }
 511
 512 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
 513 int
 514 render_ring_sync_to(struct intel_ring_buffer *waiter,
 515                     struct intel_ring_buffer *signaller,
 516                     u32 seqno)
 517 {
 518         WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
 519         return intel_ring_sync(waiter,
 520                                signaller,
 521                                RCS,
 522                                seqno);
 523 }
 524
 525 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
 526 int
 527 gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
 528                       struct intel_ring_buffer *signaller,
 529                       u32 seqno)
 530 {
 531         WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
 532         return intel_ring_sync(waiter,
 533                                signaller,
 534                                VCS,
 535                                seqno);
 536 }
 537
 538 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
 539 int
 540 gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
 541                       struct intel_ring_buffer *signaller,
 542                       u32 seqno)
 543 {
 544         WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
 545         return intel_ring_sync(waiter,
 546                                signaller,
 547                                BCS,
 548                                seqno);
 549 }
 550
 551
 552
 553 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 554 do {                                                                    \
 555         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 556                  PIPE_CONTROL_DEPTH_STALL);                             \
 557         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 558         intel_ring_emit(ring__, 0);                                                     \
 559         intel_ring_emit(ring__, 0);                                                     \
 560 } while (0)
 561
 562 static int
 563 pc_render_add_request(struct intel_ring_buffer *ring,
 564                       u32 *result)
 565 {
 566         struct drm_device *dev = ring->dev;
 567         u32 seqno = i915_gem_get_seqno(dev);
 568         struct pipe_control *pc = ring->private;
 569         u32 scratch_addr = pc->gtt_offset + 128;
 570         int ret;
 571
 572         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 573          * incoherent with writes to memory, i.e. completely fubar,
 574          * so we need to use PIPE_NOTIFY instead.
 575          *
 576          * However, we also need to workaround the qword write
 577          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 578          * memory before requesting an interrupt.
 579          */
 580         ret = intel_ring_begin(ring, 32);
 581         if (ret)
 582                 return ret;
 583
 584         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 585                         PIPE_CONTROL_WRITE_FLUSH |
 586                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 587         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 588         intel_ring_emit(ring, seqno);
 589         intel_ring_emit(ring, 0);
 590         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 591         scratch_addr += 128; /* write to separate cachelines */
 592         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 593         scratch_addr += 128;
 594         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 595         scratch_addr += 128;
 596         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 597         scratch_addr += 128;
 598         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 599         scratch_addr += 128;
 600         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 601         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 602                         PIPE_CONTROL_WRITE_FLUSH |
 603                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 604                         PIPE_CONTROL_NOTIFY);
 605         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 606         intel_ring_emit(ring, seqno);
 607         intel_ring_emit(ring, 0);
 608         intel_ring_advance(ring);
 609
 610         *result = seqno;
 611         return 0;
 612 }
 613
 614 static int
 615 render_ring_add_request(struct intel_ring_buffer *ring,
 616                         u32 *result)
 617 {
 618         struct drm_device *dev = ring->dev;
 619         u32 seqno = i915_gem_get_seqno(dev);
 620         int ret;
 621
 622         ret = intel_ring_begin(ring, 4);
 623         if (ret)
 624                 return ret;
 625
 626         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 627         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 628         intel_ring_emit(ring, seqno);
 629         intel_ring_emit(ring, MI_USER_INTERRUPT);
 630         intel_ring_advance(ring);
 631
 632         *result = seqno;
 633         return 0;
 634 }
 635
 636 static u32
 637 ring_get_seqno(struct intel_ring_buffer *ring)
 638 {
 639         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 640 }
 641
 642 static u32
 643 pc_render_get_seqno(struct intel_ring_buffer *ring)
 644 {
 645         struct pipe_control *pc = ring->private;
 646         return pc->cpu_page[0];
 647 }
 648
 649 static void
 650 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 651 {
 652         dev_priv->gt_irq_mask &= ~mask;
 653         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 654         POSTING_READ(GTIMR);
 655 }
 656
 657 static void
 658 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 659 {
 660         dev_priv->gt_irq_mask |= mask;
 661         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 662         POSTING_READ(GTIMR);
 663 }
 664
 665 static void
 666 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 667 {
 668         dev_priv->irq_mask &= ~mask;
 669         I915_WRITE(IMR, dev_priv->irq_mask);
 670         POSTING_READ(IMR);
 671 }
 672
 673 static void
 674 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 675 {
 676         dev_priv->irq_mask |= mask;
 677         I915_WRITE(IMR, dev_priv->irq_mask);
 678         POSTING_READ(IMR);
 679 }
 680
 681 static bool
 682 render_ring_get_irq(struct intel_ring_buffer *ring)
 683 {
 684         struct drm_device *dev = ring->dev;
 685         drm_i915_private_t *dev_priv = dev->dev_private;
 686
 687         if (!dev->irq_enabled)
 688                 return false;
 689
 690         spin_lock(&ring->irq_lock);
 691         if (ring->irq_refcount++ == 0) {
 692                 if (HAS_PCH_SPLIT(dev))
 693                         ironlake_enable_irq(dev_priv,
 694                                             GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
 695                 else
 696                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 697         }
 698         spin_unlock(&ring->irq_lock);
 699
 700         return true;
 701 }
 702
 703 static void
 704 render_ring_put_irq(struct intel_ring_buffer *ring)
 705 {
 706         struct drm_device *dev = ring->dev;
 707         drm_i915_private_t *dev_priv = dev->dev_private;
 708
 709         spin_lock(&ring->irq_lock);
 710         if (--ring->irq_refcount == 0) {
 711                 if (HAS_PCH_SPLIT(dev))
 712                         ironlake_disable_irq(dev_priv,
 713                                              GT_USER_INTERRUPT |
 714                                              GT_PIPE_NOTIFY);
 715                 else
 716                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 717         }
 718         spin_unlock(&ring->irq_lock);
 719 }
 720
 721 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 722 {
 723         struct drm_device *dev = ring->dev;
 724         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 725         u32 mmio = 0;
 726
 727         /* The ring status page addresses are no longer next to the rest of
 728          * the ring registers as of gen7.
 729          */
 730         if (IS_GEN7(dev)) {
 731                 switch (ring->id) {
 732                 case RCS:
 733                         mmio = RENDER_HWS_PGA_GEN7;
 734                         break;
 735                 case BCS:
 736                         mmio = BLT_HWS_PGA_GEN7;
 737                         break;
 738                 case VCS:
 739                         mmio = BSD_HWS_PGA_GEN7;
 740                         break;
 741                 }
 742         } else if (IS_GEN6(ring->dev)) {
 743                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 744         } else {
 745                 mmio = RING_HWS_PGA(ring->mmio_base);
 746         }
 747
 748         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 749         POSTING_READ(mmio);
 750 }
 751
 752 static int
 753 bsd_ring_flush(struct intel_ring_buffer *ring,
 754                u32     invalidate_domains,
 755                u32     flush_domains)
 756 {
 757         int ret;
 758
 759         ret = intel_ring_begin(ring, 2);
 760         if (ret)
 761                 return ret;
 762
 763         intel_ring_emit(ring, MI_FLUSH);
 764         intel_ring_emit(ring, MI_NOOP);
 765         intel_ring_advance(ring);
 766         return 0;
 767 }
 768
 769 static int
 770 ring_add_request(struct intel_ring_buffer *ring,
 771                  u32 *result)
 772 {
 773         u32 seqno;
 774         int ret;
 775
 776         ret = intel_ring_begin(ring, 4);
 777         if (ret)
 778                 return ret;
 779
 780         seqno = i915_gem_get_seqno(ring->dev);
 781
 782         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 783         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 784         intel_ring_emit(ring, seqno);
 785         intel_ring_emit(ring, MI_USER_INTERRUPT);
 786         intel_ring_advance(ring);
 787
 788         *result = seqno;
 789         return 0;
 790 }
 791
 792 static bool
 793 gen7_blt_ring_get_irq(struct intel_ring_buffer *ring)
 794 {
 795         /* The BLT ring on IVB appears to have broken synchronization
 796          * between the seqno write and the interrupt, so that the
 797          * interrupt appears first.  Returning false here makes
 798          * i915_wait_request() do a polling loop, instead.
 799          */
 800         return false;
 801 }
 802
 803 static bool
 804 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 805 {
 806         struct drm_device *dev = ring->dev;
 807         drm_i915_private_t *dev_priv = dev->dev_private;
 808
 809         if (!dev->irq_enabled)
 810                return false;
 811
 812         spin_lock(&ring->irq_lock);
 813         if (ring->irq_refcount++ == 0) {
 814                 ring->irq_mask &= ~rflag;
 815                 I915_WRITE_IMR(ring, ring->irq_mask);
 816                 ironlake_enable_irq(dev_priv, gflag);
 817         }
 818         spin_unlock(&ring->irq_lock);
 819
 820         return true;
 821 }
 822
 823 static void
 824 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 825 {
 826         struct drm_device *dev = ring->dev;
 827         drm_i915_private_t *dev_priv = dev->dev_private;
 828
 829         spin_lock(&ring->irq_lock);
 830         if (--ring->irq_refcount == 0) {
 831                 ring->irq_mask |= rflag;
 832                 I915_WRITE_IMR(ring, ring->irq_mask);
 833                 ironlake_disable_irq(dev_priv, gflag);
 834         }
 835         spin_unlock(&ring->irq_lock);
 836 }
 837
 838 static bool
 839 bsd_ring_get_irq(struct intel_ring_buffer *ring)
 840 {
 841         struct drm_device *dev = ring->dev;
 842         drm_i915_private_t *dev_priv = dev->dev_private;
 843
 844         if (!dev->irq_enabled)
 845                 return false;
 846
 847         spin_lock(&ring->irq_lock);
 848         if (ring->irq_refcount++ == 0) {
 849                 if (IS_G4X(dev))
 850                         i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
 851                 else
 852                         ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
 853         }
 854         spin_unlock(&ring->irq_lock);
 855
 856         return true;
 857 }
 858 static void
 859 bsd_ring_put_irq(struct intel_ring_buffer *ring)
 860 {
 861         struct drm_device *dev = ring->dev;
 862         drm_i915_private_t *dev_priv = dev->dev_private;
 863
 864         spin_lock(&ring->irq_lock);
 865         if (--ring->irq_refcount == 0) {
 866                 if (IS_G4X(dev))
 867                         i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
 868                 else
 869                         ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
 870         }
 871         spin_unlock(&ring->irq_lock);
 872 }
 873
 874 static int
 875 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
 876 {
 877         int ret;
 878
 879         ret = intel_ring_begin(ring, 2);
 880         if (ret)
 881                 return ret;
 882
 883         intel_ring_emit(ring,
 884                         MI_BATCH_BUFFER_START | (2 << 6) |
 885                         MI_BATCH_NON_SECURE_I965);
 886         intel_ring_emit(ring, offset);
 887         intel_ring_advance(ring);
 888
 889         return 0;
 890 }
 891
 892 static int
 893 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 894                                 u32 offset, u32 len)
 895 {
 896         struct drm_device *dev = ring->dev;
 897         int ret;
 898
 899         if (IS_I830(dev) || IS_845G(dev)) {
 900                 ret = intel_ring_begin(ring, 4);
 901                 if (ret)
 902                         return ret;
 903
 904                 intel_ring_emit(ring, MI_BATCH_BUFFER);
 905                 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 906                 intel_ring_emit(ring, offset + len - 8);
 907                 intel_ring_emit(ring, 0);
 908         } else {
 909                 ret = intel_ring_begin(ring, 2);
 910                 if (ret)
 911                         return ret;
 912
 913                 if (INTEL_INFO(dev)->gen >= 4) {
 914                         intel_ring_emit(ring,
 915                                         MI_BATCH_BUFFER_START | (2 << 6) |
 916                                         MI_BATCH_NON_SECURE_I965);
 917                         intel_ring_emit(ring, offset);
 918                 } else {
 919                         intel_ring_emit(ring,
 920                                         MI_BATCH_BUFFER_START | (2 << 6));
 921                         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 922                 }
 923         }
 924         intel_ring_advance(ring);
 925
 926         return 0;
 927 }
 928
 929 static void cleanup_status_page(struct intel_ring_buffer *ring)
 930 {
 931         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 932         struct drm_i915_gem_object *obj;
 933
 934         obj = ring->status_page.obj;
 935         if (obj == NULL)
 936                 return;
 937
 938         kunmap(obj->pages[0]);
 939         i915_gem_object_unpin(obj);
 940         drm_gem_object_unreference(&obj->base);
 941         ring->status_page.obj = NULL;
 942
 943         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 944 }
 945
 946 static int init_status_page(struct intel_ring_buffer *ring)
 947 {
 948         struct drm_device *dev = ring->dev;
 949         drm_i915_private_t *dev_priv = dev->dev_private;
 950         struct drm_i915_gem_object *obj;
 951         int ret;
 952
 953         obj = i915_gem_alloc_object(dev, 4096);
 954         if (obj == NULL) {
 955                 DRM_ERROR("Failed to allocate status page\n");
 956                 ret = -ENOMEM;
 957                 goto err;
 958         }
 959
 960         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 961
 962         ret = i915_gem_object_pin(obj, 4096, true);
 963         if (ret != 0) {
 964                 goto err_unref;
 965         }
 966
 967         ring->status_page.gfx_addr = obj->gtt_offset;
 968         ring->status_page.page_addr = kmap(obj->pages[0]);
 969         if (ring->status_page.page_addr == NULL) {
 970                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 971                 goto err_unpin;
 972         }
 973         ring->status_page.obj = obj;
 974         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 975
 976         intel_ring_setup_status_page(ring);
 977         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 978                         ring->name, ring->status_page.gfx_addr);
 979
 980         return 0;
 981
 982 err_unpin:
 983         i915_gem_object_unpin(obj);
 984 err_unref:
 985         drm_gem_object_unreference(&obj->base);
 986 err:
 987         return ret;
 988 }
 989
 990 int intel_init_ring_buffer(struct drm_device *dev,
 991                            struct intel_ring_buffer *ring)
 992 {
 993         struct drm_i915_gem_object *obj;
 994         int ret;
 995
 996         ring->dev = dev;
 997         INIT_LIST_HEAD(&ring->active_list);
 998         INIT_LIST_HEAD(&ring->request_list);
 999         INIT_LIST_HEAD(&ring->gpu_write_list);
1000
1001         init_waitqueue_head(&ring->irq_queue);
1002         spin_lock_init(&ring->irq_lock);
1003         ring->irq_mask = ~0;
1004
1005         if (I915_NEED_GFX_HWS(dev)) {
1006                 ret = init_status_page(ring);
1007                 if (ret)
1008                         return ret;
1009         }
1010
1011         obj = i915_gem_alloc_object(dev, ring->size);
1012         if (obj == NULL) {
1013                 DRM_ERROR("Failed to allocate ringbuffer\n");
1014                 ret = -ENOMEM;
1015                 goto err_hws;
1016         }
1017
1018         ring->obj = obj;
1019
1020         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1021         if (ret)
1022                 goto err_unref;
1023
1024         ring->map.size = ring->size;
1025         ring->map.offset = dev->agp->base + obj->gtt_offset;
1026         ring->map.type = 0;
1027         ring->map.flags = 0;
1028         ring->map.mtrr = 0;
1029
1030         drm_core_ioremap_wc(&ring->map, dev);
1031         if (ring->map.handle == NULL) {
1032                 DRM_ERROR("Failed to map ringbuffer.\n");
1033                 ret = -EINVAL;
1034                 goto err_unpin;
1035         }
1036
1037         ring->virtual_start = ring->map.handle;
1038         ret = ring->init(ring);
1039         if (ret)
1040                 goto err_unmap;
1041
1042         /* Workaround an erratum on the i830 which causes a hang if
1043          * the TAIL pointer points to within the last 2 cachelines
1044          * of the buffer.
1045          */
1046         ring->effective_size = ring->size;
1047         if (IS_I830(ring->dev))
1048                 ring->effective_size -= 128;
1049
1050         return 0;
1051
1052 err_unmap:
1053         drm_core_ioremapfree(&ring->map, dev);
1054 err_unpin:
1055         i915_gem_object_unpin(obj);
1056 err_unref:
1057         drm_gem_object_unreference(&obj->base);
1058         ring->obj = NULL;
1059 err_hws:
1060         cleanup_status_page(ring);
1061         return ret;
1062 }
1063
1064 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1065 {
1066         struct drm_i915_private *dev_priv;
1067         int ret;
1068
1069         if (ring->obj == NULL)
1070                 return;
1071
1072         /* Disable the ring buffer. The ring must be idle at this point */
1073         dev_priv = ring->dev->dev_private;
1074         ret = intel_wait_ring_idle(ring);
1075         if (ret)
1076                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1077                           ring->name, ret);
1078
1079         I915_WRITE_CTL(ring, 0);
1080
1081         drm_core_ioremapfree(&ring->map, ring->dev);
1082
1083         i915_gem_object_unpin(ring->obj);
1084         drm_gem_object_unreference(&ring->obj->base);
1085         ring->obj = NULL;
1086
1087         if (ring->cleanup)
1088                 ring->cleanup(ring);
1089
1090         cleanup_status_page(ring);
1091 }
1092
1093 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1094 {
1095         unsigned int *virt;
1096         int rem = ring->size - ring->tail;
1097
1098         if (ring->space < rem) {
1099                 int ret = intel_wait_ring_buffer(ring, rem);
1100                 if (ret)
1101                         return ret;
1102         }
1103
1104         virt = (unsigned int *)(ring->virtual_start + ring->tail);
1105         rem /= 8;
1106         while (rem--) {
1107                 *virt++ = MI_NOOP;
1108                 *virt++ = MI_NOOP;
1109         }
1110
1111         ring->tail = 0;
1112         ring->space = ring_space(ring);
1113
1114         return 0;
1115 }
1116
1117 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1118 {
1119         struct drm_device *dev = ring->dev;
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121         unsigned long end;
1122         u32 head;
1123
1124         /* If the reported head position has wrapped or hasn't advanced,
1125          * fallback to the slow and accurate path.
1126          */
1127         head = intel_read_status_page(ring, 4);
1128         if (head > ring->head) {
1129                 ring->head = head;
1130                 ring->space = ring_space(ring);
1131                 if (ring->space >= n)
1132                         return 0;
1133         }
1134
1135         trace_i915_ring_wait_begin(ring);
1136         if (drm_core_check_feature(dev, DRIVER_GEM))
1137                 /* With GEM the hangcheck timer should kick us out of the loop,
1138                  * leaving it early runs the risk of corrupting GEM state (due
1139                  * to running on almost untested codepaths). But on resume
1140                  * timers don't work yet, so prevent a complete hang in that
1141                  * case by choosing an insanely large timeout. */
1142                 end = jiffies + 60 * HZ;
1143         else
1144                 end = jiffies + 3 * HZ;
1145
1146         do {
1147                 ring->head = I915_READ_HEAD(ring);
1148                 ring->space = ring_space(ring);
1149                 if (ring->space >= n) {
1150                         trace_i915_ring_wait_end(ring);
1151                         return 0;
1152                 }
1153
1154                 if (dev->primary->master) {
1155                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1156                         if (master_priv->sarea_priv)
1157                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1158                 }
1159
1160                 msleep(1);
1161                 if (atomic_read(&dev_priv->mm.wedged))
1162                         return -EAGAIN;
1163         } while (!time_after(jiffies, end));
1164         trace_i915_ring_wait_end(ring);
1165         return -EBUSY;
1166 }
1167
1168 int intel_ring_begin(struct intel_ring_buffer *ring,
1169                      int num_dwords)
1170 {
1171         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1172         int n = 4*num_dwords;
1173         int ret;
1174
1175         if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1176                 return -EIO;
1177
1178         if (unlikely(ring->tail + n > ring->effective_size)) {
1179                 ret = intel_wrap_ring_buffer(ring);
1180                 if (unlikely(ret))
1181                         return ret;
1182         }
1183
1184         if (unlikely(ring->space < n)) {
1185                 ret = intel_wait_ring_buffer(ring, n);
1186                 if (unlikely(ret))
1187                         return ret;
1188         }
1189
1190         ring->space -= n;
1191         return 0;
1192 }
1193
1194 void intel_ring_advance(struct intel_ring_buffer *ring)
1195 {
1196         ring->tail &= ring->size - 1;
1197         ring->write_tail(ring, ring->tail);
1198 }
1199
1200 static const struct intel_ring_buffer render_ring = {
1201         .name                   = "render ring",
1202         .id                     = RCS,
1203         .mmio_base              = RENDER_RING_BASE,
1204         .size                   = 32 * PAGE_SIZE,
1205         .init                   = init_render_ring,
1206         .write_tail             = ring_write_tail,
1207         .flush                  = render_ring_flush,
1208         .add_request            = render_ring_add_request,
1209         .get_seqno              = ring_get_seqno,
1210         .irq_get                = render_ring_get_irq,
1211         .irq_put                = render_ring_put_irq,
1212         .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
1213         .cleanup                = render_ring_cleanup,
1214         .sync_to                = render_ring_sync_to,
1215         .semaphore_register     = {MI_SEMAPHORE_SYNC_INVALID,
1216                                    MI_SEMAPHORE_SYNC_RV,
1217                                    MI_SEMAPHORE_SYNC_RB},
1218         .signal_mbox            = {GEN6_VRSYNC, GEN6_BRSYNC},
1219 };
1220
1221 /* ring buffer for bit-stream decoder */
1222
1223 static const struct intel_ring_buffer bsd_ring = {
1224         .name                   = "bsd ring",
1225         .id                     = VCS,
1226         .mmio_base              = BSD_RING_BASE,
1227         .size                   = 32 * PAGE_SIZE,
1228         .init                   = init_ring_common,
1229         .write_tail             = ring_write_tail,
1230         .flush                  = bsd_ring_flush,
1231         .add_request            = ring_add_request,
1232         .get_seqno              = ring_get_seqno,
1233         .irq_get                = bsd_ring_get_irq,
1234         .irq_put                = bsd_ring_put_irq,
1235         .dispatch_execbuffer    = ring_dispatch_execbuffer,
1236 };
1237
1238
1239 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1240                                      u32 value)
1241 {
1242         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1243
1244        /* Every tail move must follow the sequence below */
1245         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1246                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1247                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1248         I915_WRITE(GEN6_BSD_RNCID, 0x0);
1249
1250         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1251                 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1252                 50))
1253         DRM_ERROR("timed out waiting for IDLE Indicator\n");
1254
1255         I915_WRITE_TAIL(ring, value);
1256         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1257                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1258                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1259 }
1260
1261 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1262                            u32 invalidate, u32 flush)
1263 {
1264         uint32_t cmd;
1265         int ret;
1266
1267         ret = intel_ring_begin(ring, 4);
1268         if (ret)
1269                 return ret;
1270
1271         cmd = MI_FLUSH_DW;
1272         if (invalidate & I915_GEM_GPU_DOMAINS)
1273                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1274         intel_ring_emit(ring, cmd);
1275         intel_ring_emit(ring, 0);
1276         intel_ring_emit(ring, 0);
1277         intel_ring_emit(ring, MI_NOOP);
1278         intel_ring_advance(ring);
1279         return 0;
1280 }
1281
1282 static int
1283 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1284                               u32 offset, u32 len)
1285 {
1286         int ret;
1287
1288         ret = intel_ring_begin(ring, 2);
1289         if (ret)
1290                 return ret;
1291
1292         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1293         /* bit0-7 is the length on GEN6+ */
1294         intel_ring_emit(ring, offset);
1295         intel_ring_advance(ring);
1296
1297         return 0;
1298 }
1299
1300 static bool
1301 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1302 {
1303         return gen6_ring_get_irq(ring,
1304                                  GT_USER_INTERRUPT,
1305                                  GEN6_RENDER_USER_INTERRUPT);
1306 }
1307
1308 static void
1309 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1310 {
1311         return gen6_ring_put_irq(ring,
1312                                  GT_USER_INTERRUPT,
1313                                  GEN6_RENDER_USER_INTERRUPT);
1314 }
1315
1316 static bool
1317 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1318 {
1319         return gen6_ring_get_irq(ring,
1320                                  GT_GEN6_BSD_USER_INTERRUPT,
1321                                  GEN6_BSD_USER_INTERRUPT);
1322 }
1323
1324 static void
1325 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1326 {
1327         return gen6_ring_put_irq(ring,
1328                                  GT_GEN6_BSD_USER_INTERRUPT,
1329                                  GEN6_BSD_USER_INTERRUPT);
1330 }
1331
1332 /* ring buffer for Video Codec for Gen6+ */
1333 static const struct intel_ring_buffer gen6_bsd_ring = {
1334         .name                   = "gen6 bsd ring",
1335         .id                     = VCS,
1336         .mmio_base              = GEN6_BSD_RING_BASE,
1337         .size                   = 32 * PAGE_SIZE,
1338         .init                   = init_ring_common,
1339         .write_tail             = gen6_bsd_ring_write_tail,
1340         .flush                  = gen6_ring_flush,
1341         .add_request            = gen6_add_request,
1342         .get_seqno              = ring_get_seqno,
1343         .irq_get                = gen6_bsd_ring_get_irq,
1344         .irq_put                = gen6_bsd_ring_put_irq,
1345         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1346         .sync_to                = gen6_bsd_ring_sync_to,
1347         .semaphore_register     = {MI_SEMAPHORE_SYNC_VR,
1348                                    MI_SEMAPHORE_SYNC_INVALID,
1349                                    MI_SEMAPHORE_SYNC_VB},
1350         .signal_mbox            = {GEN6_RVSYNC, GEN6_BVSYNC},
1351 };
1352
1353 /* Blitter support (SandyBridge+) */
1354
1355 static bool
1356 blt_ring_get_irq(struct intel_ring_buffer *ring)
1357 {
1358         return gen6_ring_get_irq(ring,
1359                                  GT_BLT_USER_INTERRUPT,
1360                                  GEN6_BLITTER_USER_INTERRUPT);
1361 }
1362
1363 static void
1364 blt_ring_put_irq(struct intel_ring_buffer *ring)
1365 {
1366         gen6_ring_put_irq(ring,
1367                           GT_BLT_USER_INTERRUPT,
1368                           GEN6_BLITTER_USER_INTERRUPT);
1369 }
1370
1371 static int blt_ring_flush(struct intel_ring_buffer *ring,
1372                           u32 invalidate, u32 flush)
1373 {
1374         uint32_t cmd;
1375         int ret;
1376
1377         ret = intel_ring_begin(ring, 4);
1378         if (ret)
1379                 return ret;
1380
1381         cmd = MI_FLUSH_DW;
1382         if (invalidate & I915_GEM_DOMAIN_RENDER)
1383                 cmd |= MI_INVALIDATE_TLB;
1384         intel_ring_emit(ring, cmd);
1385         intel_ring_emit(ring, 0);
1386         intel_ring_emit(ring, 0);
1387         intel_ring_emit(ring, MI_NOOP);
1388         intel_ring_advance(ring);
1389         return 0;
1390 }
1391
1392 static const struct intel_ring_buffer gen6_blt_ring = {
1393         .name                   = "blt ring",
1394         .id                     = BCS,
1395         .mmio_base              = BLT_RING_BASE,
1396         .size                   = 32 * PAGE_SIZE,
1397         .init                   = init_ring_common,
1398         .write_tail             = ring_write_tail,
1399         .flush                  = blt_ring_flush,
1400         .add_request            = gen6_add_request,
1401         .get_seqno              = ring_get_seqno,
1402         .irq_get                = blt_ring_get_irq,
1403         .irq_put                = blt_ring_put_irq,
1404         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1405         .sync_to                = gen6_blt_ring_sync_to,
1406         .semaphore_register     = {MI_SEMAPHORE_SYNC_BR,
1407                                    MI_SEMAPHORE_SYNC_BV,
1408                                    MI_SEMAPHORE_SYNC_INVALID},
1409         .signal_mbox            = {GEN6_RBSYNC, GEN6_VBSYNC},
1410 };
1411
1412 int intel_init_render_ring_buffer(struct drm_device *dev)
1413 {
1414         drm_i915_private_t *dev_priv = dev->dev_private;
1415         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1416
1417         *ring = render_ring;
1418         if (INTEL_INFO(dev)->gen >= 6) {
1419                 ring->add_request = gen6_add_request;
1420                 ring->flush = gen6_render_ring_flush;
1421                 ring->irq_get = gen6_render_ring_get_irq;
1422                 ring->irq_put = gen6_render_ring_put_irq;
1423         } else if (IS_GEN5(dev)) {
1424                 ring->add_request = pc_render_add_request;
1425                 ring->get_seqno = pc_render_get_seqno;
1426         }
1427
1428         if (!I915_NEED_GFX_HWS(dev)) {
1429                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1430                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1431         }
1432
1433         return intel_init_ring_buffer(dev, ring);
1434 }
1435
1436 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1437 {
1438         drm_i915_private_t *dev_priv = dev->dev_private;
1439         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1440
1441         *ring = render_ring;
1442         if (INTEL_INFO(dev)->gen >= 6) {
1443                 ring->add_request = gen6_add_request;
1444                 ring->irq_get = gen6_render_ring_get_irq;
1445                 ring->irq_put = gen6_render_ring_put_irq;
1446         } else if (IS_GEN5(dev)) {
1447                 ring->add_request = pc_render_add_request;
1448                 ring->get_seqno = pc_render_get_seqno;
1449         }
1450
1451         if (!I915_NEED_GFX_HWS(dev))
1452                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1453
1454         ring->dev = dev;
1455         INIT_LIST_HEAD(&ring->active_list);
1456         INIT_LIST_HEAD(&ring->request_list);
1457         INIT_LIST_HEAD(&ring->gpu_write_list);
1458
1459         ring->size = size;
1460         ring->effective_size = ring->size;
1461         if (IS_I830(ring->dev))
1462                 ring->effective_size -= 128;
1463
1464         ring->map.offset = start;
1465         ring->map.size = size;
1466         ring->map.type = 0;
1467         ring->map.flags = 0;
1468         ring->map.mtrr = 0;
1469
1470         drm_core_ioremap_wc(&ring->map, dev);
1471         if (ring->map.handle == NULL) {
1472                 DRM_ERROR("can not ioremap virtual address for"
1473                           " ring buffer\n");
1474                 return -ENOMEM;
1475         }
1476
1477         ring->virtual_start = (void __force __iomem *)ring->map.handle;
1478         return 0;
1479 }
1480
1481 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1482 {
1483         drm_i915_private_t *dev_priv = dev->dev_private;
1484         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1485
1486         if (IS_GEN6(dev) || IS_GEN7(dev))
1487                 *ring = gen6_bsd_ring;
1488         else
1489                 *ring = bsd_ring;
1490
1491         return intel_init_ring_buffer(dev, ring);
1492 }
1493
1494 int intel_init_blt_ring_buffer(struct drm_device *dev)
1495 {
1496         drm_i915_private_t *dev_priv = dev->dev_private;
1497         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1498
1499         *ring = gen6_blt_ring;
1500
1501         if (IS_GEN7(dev))
1502                 ring->irq_get = gen7_blt_ring_get_irq;
1503
1504         return intel_init_ring_buffer(dev, ring);
1505 }