drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct intel_engine_cs *ring,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         u32 cmd;
  99         int ret;
 100
 101         cmd = MI_FLUSH;
 102         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 103                 cmd |= MI_NO_WRITE_FLUSH;
 104
 105         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 106                 cmd |= MI_READ_FLUSH;
 107
 108         ret = intel_ring_begin(ring, 2);
 109         if (ret)
 110                 return ret;
 111
 112         intel_ring_emit(ring, cmd);
 113         intel_ring_emit(ring, MI_NOOP);
 114         intel_ring_advance(ring);
 115
 116         return 0;
 117 }
 118
 119 static int
 120 gen4_render_ring_flush(struct intel_engine_cs *ring,
 121                        u32      invalidate_domains,
 122                        u32      flush_domains)
 123 {
 124         struct drm_device *dev = ring->dev;
 125         u32 cmd;
 126         int ret;
 127
 128         /*
 129          * read/write caches:
 130          *
 131          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 132          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 133          * also flushed at 2d versus 3d pipeline switches.
 134          *
 135          * read-only caches:
 136          *
 137          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 138          * MI_READ_FLUSH is set, and is always flushed on 965.
 139          *
 140          * I915_GEM_DOMAIN_COMMAND may not exist?
 141          *
 142          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 143          * invalidated when MI_EXE_FLUSH is set.
 144          *
 145          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 146          * invalidated with every MI_FLUSH.
 147          *
 148          * TLBs:
 149          *
 150          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 151          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 152          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 153          * are flushed at any MI_FLUSH.
 154          */
 155
 156         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 157         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 158                 cmd &= ~MI_NO_WRITE_FLUSH;
 159         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 160                 cmd |= MI_EXE_FLUSH;
 161
 162         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 163             (IS_G4X(dev) || IS_GEN5(dev)))
 164                 cmd |= MI_INVALIDATE_ISP;
 165
 166         ret = intel_ring_begin(ring, 2);
 167         if (ret)
 168                 return ret;
 169
 170         intel_ring_emit(ring, cmd);
 171         intel_ring_emit(ring, MI_NOOP);
 172         intel_ring_advance(ring);
 173
 174         return 0;
 175 }
 176
 177 /**
 178  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 179  * implementing two workarounds on gen6.  From section 1.4.7.1
 180  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 181  *
 182  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 183  * produced by non-pipelined state commands), software needs to first
 184  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 185  * 0.
 186  *
 187  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 188  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 189  *
 190  * And the workaround for these two requires this workaround first:
 191  *
 192  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 193  * BEFORE the pipe-control with a post-sync op and no write-cache
 194  * flushes.
 195  *
 196  * And this last workaround is tricky because of the requirements on
 197  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 198  * volume 2 part 1:
 199  *
 200  *     "1 of the following must also be set:
 201  *      - Render Target Cache Flush Enable ([12] of DW1)
 202  *      - Depth Cache Flush Enable ([0] of DW1)
 203  *      - Stall at Pixel Scoreboard ([1] of DW1)
 204  *      - Depth Stall ([13] of DW1)
 205  *      - Post-Sync Operation ([13] of DW1)
 206  *      - Notify Enable ([8] of DW1)"
 207  *
 208  * The cache flushes require the workaround flush that triggered this
 209  * one, so we can't use it.  Depth stall would trigger the same.
 210  * Post-sync nonzero is what triggered this second workaround, so we
 211  * can't use that one either.  Notify enable is IRQs, which aren't
 212  * really our business.  That leaves only stall at scoreboard.
 213  */
 214 static int
 215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
 216 {
 217         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 218         int ret;
 219
 220
 221         ret = intel_ring_begin(ring, 6);
 222         if (ret)
 223                 return ret;
 224
 225         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 226         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 227                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 228         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 229         intel_ring_emit(ring, 0); /* low dword */
 230         intel_ring_emit(ring, 0); /* high dword */
 231         intel_ring_emit(ring, MI_NOOP);
 232         intel_ring_advance(ring);
 233
 234         ret = intel_ring_begin(ring, 6);
 235         if (ret)
 236                 return ret;
 237
 238         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 239         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 240         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 241         intel_ring_emit(ring, 0);
 242         intel_ring_emit(ring, 0);
 243         intel_ring_emit(ring, MI_NOOP);
 244         intel_ring_advance(ring);
 245
 246         return 0;
 247 }
 248
 249 static int
 250 gen6_render_ring_flush(struct intel_engine_cs *ring,
 251                          u32 invalidate_domains, u32 flush_domains)
 252 {
 253         u32 flags = 0;
 254         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 255         int ret;
 256
 257         /* Force SNB workarounds for PIPE_CONTROL flushes */
 258         ret = intel_emit_post_sync_nonzero_flush(ring);
 259         if (ret)
 260                 return ret;
 261
 262         /* Just flush everything.  Experiments have shown that reducing the
 263          * number of bits based on the write domains has little performance
 264          * impact.
 265          */
 266         if (flush_domains) {
 267                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 268                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 269                 /*
 270                  * Ensure that any following seqno writes only happen
 271                  * when the render cache is indeed flushed.
 272                  */
 273                 flags |= PIPE_CONTROL_CS_STALL;
 274         }
 275         if (invalidate_domains) {
 276                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 277                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 278                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 279                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 280                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 281                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 282                 /*
 283                  * TLB invalidate requires a post-sync write.
 284                  */
 285                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 286         }
 287
 288         ret = intel_ring_begin(ring, 4);
 289         if (ret)
 290                 return ret;
 291
 292         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 293         intel_ring_emit(ring, flags);
 294         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 295         intel_ring_emit(ring, 0);
 296         intel_ring_advance(ring);
 297
 298         return 0;
 299 }
 300
 301 static int
 302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
 303 {
 304         int ret;
 305
 306         ret = intel_ring_begin(ring, 4);
 307         if (ret)
 308                 return ret;
 309
 310         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 311         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 312                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 313         intel_ring_emit(ring, 0);
 314         intel_ring_emit(ring, 0);
 315         intel_ring_advance(ring);
 316
 317         return 0;
 318 }
 319
 320 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
 321 {
 322         int ret;
 323
 324         if (!ring->fbc_dirty)
 325                 return 0;
 326
 327         ret = intel_ring_begin(ring, 6);
 328         if (ret)
 329                 return ret;
 330         /* WaFbcNukeOn3DBlt:ivb/hsw */
 331         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 332         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 333         intel_ring_emit(ring, value);
 334         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
 335         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 336         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 337         intel_ring_advance(ring);
 338
 339         ring->fbc_dirty = false;
 340         return 0;
 341 }
 342
 343 static int
 344 gen7_render_ring_flush(struct intel_engine_cs *ring,
 345                        u32 invalidate_domains, u32 flush_domains)
 346 {
 347         u32 flags = 0;
 348         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 349         int ret;
 350
 351         /*
 352          * Ensure that any following seqno writes only happen when the render
 353          * cache is indeed flushed.
 354          *
 355          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 356          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 357          * don't try to be clever and just set it unconditionally.
 358          */
 359         flags |= PIPE_CONTROL_CS_STALL;
 360
 361         /* Just flush everything.  Experiments have shown that reducing the
 362          * number of bits based on the write domains has little performance
 363          * impact.
 364          */
 365         if (flush_domains) {
 366                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 367                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 368         }
 369         if (invalidate_domains) {
 370                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 371                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 372                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 373                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 374                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 375                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 376                 /*
 377                  * TLB invalidate requires a post-sync write.
 378                  */
 379                 flags |= PIPE_CONTROL_QW_WRITE;
 380                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 381
 382                 /* Workaround: we must issue a pipe_control with CS-stall bit
 383                  * set before a pipe_control command that has the state cache
 384                  * invalidate bit set. */
 385                 gen7_render_ring_cs_stall_wa(ring);
 386         }
 387
 388         ret = intel_ring_begin(ring, 4);
 389         if (ret)
 390                 return ret;
 391
 392         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 393         intel_ring_emit(ring, flags);
 394         intel_ring_emit(ring, scratch_addr);
 395         intel_ring_emit(ring, 0);
 396         intel_ring_advance(ring);
 397
 398         if (!invalidate_domains && flush_domains)
 399                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 400
 401         return 0;
 402 }
 403
 404 static int
 405 gen8_emit_pipe_control(struct intel_engine_cs *ring,
 406                        u32 flags, u32 scratch_addr)
 407 {
 408         int ret;
 409
 410         ret = intel_ring_begin(ring, 6);
 411         if (ret)
 412                 return ret;
 413
 414         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 415         intel_ring_emit(ring, flags);
 416         intel_ring_emit(ring, scratch_addr);
 417         intel_ring_emit(ring, 0);
 418         intel_ring_emit(ring, 0);
 419         intel_ring_emit(ring, 0);
 420         intel_ring_advance(ring);
 421
 422         return 0;
 423 }
 424
 425 static int
 426 gen8_render_ring_flush(struct intel_engine_cs *ring,
 427                        u32 invalidate_domains, u32 flush_domains)
 428 {
 429         u32 flags = 0;
 430         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 431         int ret;
 432
 433         flags |= PIPE_CONTROL_CS_STALL;
 434
 435         if (flush_domains) {
 436                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 437                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 438         }
 439         if (invalidate_domains) {
 440                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 441                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 442                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 443                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 444                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 445                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 446                 flags |= PIPE_CONTROL_QW_WRITE;
 447                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 448
 449                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 450                 ret = gen8_emit_pipe_control(ring,
 451                                              PIPE_CONTROL_CS_STALL |
 452                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 453                                              0);
 454                 if (ret)
 455                         return ret;
 456         }
 457
 458         ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
 459         if (ret)
 460                 return ret;
 461
 462         if (!invalidate_domains && flush_domains)
 463                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 464
 465         return 0;
 466 }
 467
 468 static void ring_write_tail(struct intel_engine_cs *ring,
 469                             u32 value)
 470 {
 471         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 472         I915_WRITE_TAIL(ring, value);
 473 }
 474
 475 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 476 {
 477         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 478         u64 acthd;
 479
 480         if (INTEL_INFO(ring->dev)->gen >= 8)
 481                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 482                                          RING_ACTHD_UDW(ring->mmio_base));
 483         else if (INTEL_INFO(ring->dev)->gen >= 4)
 484                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 485         else
 486                 acthd = I915_READ(ACTHD);
 487
 488         return acthd;
 489 }
 490
 491 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 492 {
 493         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 494         u32 addr;
 495
 496         addr = dev_priv->status_page_dmah->busaddr;
 497         if (INTEL_INFO(ring->dev)->gen >= 4)
 498                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 499         I915_WRITE(HWS_PGA, addr);
 500 }
 501
 502 static bool stop_ring(struct intel_engine_cs *ring)
 503 {
 504         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 505
 506         if (!IS_GEN2(ring->dev)) {
 507                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 508                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 509                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 510                         /* Sometimes we observe that the idle flag is not
 511                          * set even though the ring is empty. So double
 512                          * check before giving up.
 513                          */
 514                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 515                                 return false;
 516                 }
 517         }
 518
 519         I915_WRITE_CTL(ring, 0);
 520         I915_WRITE_HEAD(ring, 0);
 521         ring->write_tail(ring, 0);
 522
 523         if (!IS_GEN2(ring->dev)) {
 524                 (void)I915_READ_CTL(ring);
 525                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 526         }
 527
 528         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 529 }
 530
 531 static int init_ring_common(struct intel_engine_cs *ring)
 532 {
 533         struct drm_device *dev = ring->dev;
 534         struct drm_i915_private *dev_priv = dev->dev_private;
 535         struct intel_ringbuffer *ringbuf = ring->buffer;
 536         struct drm_i915_gem_object *obj = ringbuf->obj;
 537         int ret = 0;
 538
 539         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 540
 541         if (!stop_ring(ring)) {
 542                 /* G45 ring initialization often fails to reset head to zero */
 543                 DRM_DEBUG_KMS("%s head not reset to zero "
 544                               "ctl %08x head %08x tail %08x start %08x\n",
 545                               ring->name,
 546                               I915_READ_CTL(ring),
 547                               I915_READ_HEAD(ring),
 548                               I915_READ_TAIL(ring),
 549                               I915_READ_START(ring));
 550
 551                 if (!stop_ring(ring)) {
 552                         DRM_ERROR("failed to set %s head to zero "
 553                                   "ctl %08x head %08x tail %08x start %08x\n",
 554                                   ring->name,
 555                                   I915_READ_CTL(ring),
 556                                   I915_READ_HEAD(ring),
 557                                   I915_READ_TAIL(ring),
 558                                   I915_READ_START(ring));
 559                         ret = -EIO;
 560                         goto out;
 561                 }
 562         }
 563
 564         if (I915_NEED_GFX_HWS(dev))
 565                 intel_ring_setup_status_page(ring);
 566         else
 567                 ring_setup_phys_status_page(ring);
 568
 569         /* Enforce ordering by reading HEAD register back */
 570         I915_READ_HEAD(ring);
 571
 572         /* Initialize the ring. This must happen _after_ we've cleared the ring
 573          * registers with the above sequence (the readback of the HEAD registers
 574          * also enforces ordering), otherwise the hw might lose the new ring
 575          * register values. */
 576         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 577
 578         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 579         if (I915_READ_HEAD(ring))
 580                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 581                           ring->name, I915_READ_HEAD(ring));
 582         I915_WRITE_HEAD(ring, 0);
 583         (void)I915_READ_HEAD(ring);
 584
 585         I915_WRITE_CTL(ring,
 586                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 587                         | RING_VALID);
 588
 589         /* If the head is still not zero, the ring is dead */
 590         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 591                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 592                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 593                 DRM_ERROR("%s initialization failed "
 594                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 595                           ring->name,
 596                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 597                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 598                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 599                 ret = -EIO;
 600                 goto out;
 601         }
 602
 603         ringbuf->last_retired_head = -1;
 604         ringbuf->head = I915_READ_HEAD(ring);
 605         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 606         intel_ring_update_space(ringbuf);
 607
 608         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 609
 610 out:
 611         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 612
 613         return ret;
 614 }
 615
 616 void
 617 intel_fini_pipe_control(struct intel_engine_cs *ring)
 618 {
 619         struct drm_device *dev = ring->dev;
 620
 621         if (ring->scratch.obj == NULL)
 622                 return;
 623
 624         if (INTEL_INFO(dev)->gen >= 5) {
 625                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 626                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 627         }
 628
 629         drm_gem_object_unreference(&ring->scratch.obj->base);
 630         ring->scratch.obj = NULL;
 631 }
 632
 633 int
 634 intel_init_pipe_control(struct intel_engine_cs *ring)
 635 {
 636         int ret;
 637
 638         WARN_ON(ring->scratch.obj);
 639
 640         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 641         if (ring->scratch.obj == NULL) {
 642                 DRM_ERROR("Failed to allocate seqno page\n");
 643                 ret = -ENOMEM;
 644                 goto err;
 645         }
 646
 647         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 648         if (ret)
 649                 goto err_unref;
 650
 651         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 652         if (ret)
 653                 goto err_unref;
 654
 655         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 656         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 657         if (ring->scratch.cpu_page == NULL) {
 658                 ret = -ENOMEM;
 659                 goto err_unpin;
 660         }
 661
 662         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 663                          ring->name, ring->scratch.gtt_offset);
 664         return 0;
 665
 666 err_unpin:
 667         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 668 err_unref:
 669         drm_gem_object_unreference(&ring->scratch.obj->base);
 670 err:
 671         return ret;
 672 }
 673
 674 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
 675                                        struct intel_context *ctx)
 676 {
 677         int ret, i;
 678         struct drm_device *dev = ring->dev;
 679         struct drm_i915_private *dev_priv = dev->dev_private;
 680         struct i915_workarounds *w = &dev_priv->workarounds;
 681
 682         if (WARN_ON(w->count == 0))
 683                 return 0;
 684
 685         ring->gpu_caches_dirty = true;
 686         ret = intel_ring_flush_all_caches(ring);
 687         if (ret)
 688                 return ret;
 689
 690         ret = intel_ring_begin(ring, (w->count * 2 + 2));
 691         if (ret)
 692                 return ret;
 693
 694         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 695         for (i = 0; i < w->count; i++) {
 696                 intel_ring_emit(ring, w->reg[i].addr);
 697                 intel_ring_emit(ring, w->reg[i].value);
 698         }
 699         intel_ring_emit(ring, MI_NOOP);
 700
 701         intel_ring_advance(ring);
 702
 703         ring->gpu_caches_dirty = true;
 704         ret = intel_ring_flush_all_caches(ring);
 705         if (ret)
 706                 return ret;
 707
 708         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 709
 710         return 0;
 711 }
 712
 713 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
 714                               struct intel_context *ctx)
 715 {
 716         int ret;
 717
 718         ret = intel_ring_workarounds_emit(ring, ctx);
 719         if (ret != 0)
 720                 return ret;
 721
 722         ret = i915_gem_render_state_init(ring);
 723         if (ret)
 724                 DRM_ERROR("init render state: %d\n", ret);
 725
 726         return ret;
 727 }
 728
 729 static int wa_add(struct drm_i915_private *dev_priv,
 730                   const u32 addr, const u32 val, const u32 mask)
 731 {
 732         const u32 idx = dev_priv->workarounds.count;
 733
 734         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 735                 return -ENOSPC;
 736
 737         dev_priv->workarounds.reg[idx].addr = addr;
 738         dev_priv->workarounds.reg[idx].value = val;
 739         dev_priv->workarounds.reg[idx].mask = mask;
 740
 741         dev_priv->workarounds.count++;
 742
 743         return 0;
 744 }
 745
 746 #define WA_REG(addr, val, mask) { \
 747                 const int r = wa_add(dev_priv, (addr), (val), (mask)); \
 748                 if (r) \
 749                         return r; \
 750         }
 751
 752 #define WA_SET_BIT_MASKED(addr, mask) \
 753         WA_REG(addr, _MASKED_BIT_ENABLE(mask), (mask) & 0xffff)
 754
 755 #define WA_CLR_BIT_MASKED(addr, mask) \
 756         WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff)
 757
 758 #define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask)
 759 #define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask)
 760
 761 #define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff)
 762
 763 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 764 {
 765         struct drm_device *dev = ring->dev;
 766         struct drm_i915_private *dev_priv = dev->dev_private;
 767
 768         /* WaDisablePartialInstShootdown:bdw */
 769         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 770         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 771                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 772                           STALL_DOP_GATING_DISABLE);
 773
 774         /* WaDisableDopClockGating:bdw */
 775         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 776                           DOP_CLOCK_GATING_DISABLE);
 777
 778         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 779                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 780
 781         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 782          * workaround for for a possible hang in the unlikely event a TLB
 783          * invalidation occurs during a PSD flush.
 784          */
 785         /* WaHdcDisableFetchWhenMasked:bdw */
 786         /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
 787         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 788                           HDC_FORCE_NON_COHERENT |
 789                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 790                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 791
 792         /* Wa4x4STCOptimizationDisable:bdw */
 793         WA_SET_BIT_MASKED(CACHE_MODE_1,
 794                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 795
 796         /*
 797          * BSpec recommends 8x4 when MSAA is used,
 798          * however in practice 16x4 seems fastest.
 799          *
 800          * Note that PS/WM thread counts depend on the WIZ hashing
 801          * disable bit, which we don't touch here, but it's good
 802          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 803          */
 804         WA_SET_BIT_MASKED(GEN7_GT_MODE,
 805                           GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
 806
 807         return 0;
 808 }
 809
 810 static int chv_init_workarounds(struct intel_engine_cs *ring)
 811 {
 812         struct drm_device *dev = ring->dev;
 813         struct drm_i915_private *dev_priv = dev->dev_private;
 814
 815         /* WaDisablePartialInstShootdown:chv */
 816         /* WaDisableThreadStallDopClockGating:chv */
 817         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 818                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 819                           STALL_DOP_GATING_DISABLE);
 820
 821         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 822          * workaround for a possible hang in the unlikely event a TLB
 823          * invalidation occurs during a PSD flush.
 824          */
 825         /* WaForceEnableNonCoherent:chv */
 826         /* WaHdcDisableFetchWhenMasked:chv */
 827         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 828                           HDC_FORCE_NON_COHERENT |
 829                           HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 830
 831         return 0;
 832 }
 833
 834 int init_workarounds_ring(struct intel_engine_cs *ring)
 835 {
 836         struct drm_device *dev = ring->dev;
 837         struct drm_i915_private *dev_priv = dev->dev_private;
 838
 839         WARN_ON(ring->id != RCS);
 840
 841         dev_priv->workarounds.count = 0;
 842
 843         if (IS_BROADWELL(dev))
 844                 return bdw_init_workarounds(ring);
 845
 846         if (IS_CHERRYVIEW(dev))
 847                 return chv_init_workarounds(ring);
 848
 849         return 0;
 850 }
 851
 852 static int init_render_ring(struct intel_engine_cs *ring)
 853 {
 854         struct drm_device *dev = ring->dev;
 855         struct drm_i915_private *dev_priv = dev->dev_private;
 856         int ret = init_ring_common(ring);
 857         if (ret)
 858                 return ret;
 859
 860         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 861         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
 862                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 863
 864         /* We need to disable the AsyncFlip performance optimisations in order
 865          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 866          * programmed to '1' on all products.
 867          *
 868          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
 869          */
 870         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
 871                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 872
 873         /* Required for the hardware to program scanline values for waiting */
 874         /* WaEnableFlushTlbInvalidationMode:snb */
 875         if (INTEL_INFO(dev)->gen == 6)
 876                 I915_WRITE(GFX_MODE,
 877                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 878
 879         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
 880         if (IS_GEN7(dev))
 881                 I915_WRITE(GFX_MODE_GEN7,
 882                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
 883                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 884
 885         if (IS_GEN6(dev)) {
 886                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 887                  * "If this bit is set, STCunit will have LRA as replacement
 888                  *  policy. [...] This bit must be reset.  LRA replacement
 889                  *  policy is not supported."
 890                  */
 891                 I915_WRITE(CACHE_MODE_0,
 892                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 893         }
 894
 895         if (INTEL_INFO(dev)->gen >= 6)
 896                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 897
 898         if (HAS_L3_DPF(dev))
 899                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 900
 901         return init_workarounds_ring(ring);
 902 }
 903
 904 static void render_ring_cleanup(struct intel_engine_cs *ring)
 905 {
 906         struct drm_device *dev = ring->dev;
 907         struct drm_i915_private *dev_priv = dev->dev_private;
 908
 909         if (dev_priv->semaphore_obj) {
 910                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
 911                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
 912                 dev_priv->semaphore_obj = NULL;
 913         }
 914
 915         intel_fini_pipe_control(ring);
 916 }
 917
 918 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
 919                            unsigned int num_dwords)
 920 {
 921 #define MBOX_UPDATE_DWORDS 8
 922         struct drm_device *dev = signaller->dev;
 923         struct drm_i915_private *dev_priv = dev->dev_private;
 924         struct intel_engine_cs *waiter;
 925         int i, ret, num_rings;
 926
 927         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 928         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
 929 #undef MBOX_UPDATE_DWORDS
 930
 931         ret = intel_ring_begin(signaller, num_dwords);
 932         if (ret)
 933                 return ret;
 934
 935         for_each_ring(waiter, dev_priv, i) {
 936                 u32 seqno;
 937                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
 938                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
 939                         continue;
 940
 941                 seqno = i915_gem_request_get_seqno(
 942                                            signaller->outstanding_lazy_request);
 943                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
 944                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
 945                                            PIPE_CONTROL_QW_WRITE |
 946                                            PIPE_CONTROL_FLUSH_ENABLE);
 947                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
 948                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
 949                 intel_ring_emit(signaller, seqno);
 950                 intel_ring_emit(signaller, 0);
 951                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
 952                                            MI_SEMAPHORE_TARGET(waiter->id));
 953                 intel_ring_emit(signaller, 0);
 954         }
 955
 956         return 0;
 957 }
 958
 959 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
 960                            unsigned int num_dwords)
 961 {
 962 #define MBOX_UPDATE_DWORDS 6
 963         struct drm_device *dev = signaller->dev;
 964         struct drm_i915_private *dev_priv = dev->dev_private;
 965         struct intel_engine_cs *waiter;
 966         int i, ret, num_rings;
 967
 968         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 969         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
 970 #undef MBOX_UPDATE_DWORDS
 971
 972         ret = intel_ring_begin(signaller, num_dwords);
 973         if (ret)
 974                 return ret;
 975
 976         for_each_ring(waiter, dev_priv, i) {
 977                 u32 seqno;
 978                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
 979                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
 980                         continue;
 981
 982                 seqno = i915_gem_request_get_seqno(
 983                                            signaller->outstanding_lazy_request);
 984                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
 985                                            MI_FLUSH_DW_OP_STOREDW);
 986                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
 987                                            MI_FLUSH_DW_USE_GTT);
 988                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
 989                 intel_ring_emit(signaller, seqno);
 990                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
 991                                            MI_SEMAPHORE_TARGET(waiter->id));
 992                 intel_ring_emit(signaller, 0);
 993         }
 994
 995         return 0;
 996 }
 997
 998 static int gen6_signal(struct intel_engine_cs *signaller,
 999                        unsigned int num_dwords)
1000 {
1001         struct drm_device *dev = signaller->dev;
1002         struct drm_i915_private *dev_priv = dev->dev_private;
1003         struct intel_engine_cs *useless;
1004         int i, ret, num_rings;
1005
1006 #define MBOX_UPDATE_DWORDS 3
1007         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1008         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1009 #undef MBOX_UPDATE_DWORDS
1010
1011         ret = intel_ring_begin(signaller, num_dwords);
1012         if (ret)
1013                 return ret;
1014
1015         for_each_ring(useless, dev_priv, i) {
1016                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1017                 if (mbox_reg != GEN6_NOSYNC) {
1018                         u32 seqno = i915_gem_request_get_seqno(
1019                                            signaller->outstanding_lazy_request);
1020                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1021                         intel_ring_emit(signaller, mbox_reg);
1022                         intel_ring_emit(signaller, seqno);
1023                 }
1024         }
1025
1026         /* If num_dwords was rounded, make sure the tail pointer is correct */
1027         if (num_rings % 2 == 0)
1028                 intel_ring_emit(signaller, MI_NOOP);
1029
1030         return 0;
1031 }
1032
1033 /**
1034  * gen6_add_request - Update the semaphore mailbox registers
1035  *
1036  * @ring - ring that is adding a request
1037  * @seqno - return seqno stuck into the ring
1038  *
1039  * Update the mailbox registers in the *other* rings with the current seqno.
1040  * This acts like a signal in the canonical semaphore.
1041  */
1042 static int
1043 gen6_add_request(struct intel_engine_cs *ring)
1044 {
1045         int ret;
1046
1047         if (ring->semaphore.signal)
1048                 ret = ring->semaphore.signal(ring, 4);
1049         else
1050                 ret = intel_ring_begin(ring, 4);
1051
1052         if (ret)
1053                 return ret;
1054
1055         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1056         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1057         intel_ring_emit(ring,
1058                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1059         intel_ring_emit(ring, MI_USER_INTERRUPT);
1060         __intel_ring_advance(ring);
1061
1062         return 0;
1063 }
1064
1065 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1066                                               u32 seqno)
1067 {
1068         struct drm_i915_private *dev_priv = dev->dev_private;
1069         return dev_priv->last_seqno < seqno;
1070 }
1071
1072 /**
1073  * intel_ring_sync - sync the waiter to the signaller on seqno
1074  *
1075  * @waiter - ring that is waiting
1076  * @signaller - ring which has, or will signal
1077  * @seqno - seqno which the waiter will block on
1078  */
1079
1080 static int
1081 gen8_ring_sync(struct intel_engine_cs *waiter,
1082                struct intel_engine_cs *signaller,
1083                u32 seqno)
1084 {
1085         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1086         int ret;
1087
1088         ret = intel_ring_begin(waiter, 4);
1089         if (ret)
1090                 return ret;
1091
1092         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1093                                 MI_SEMAPHORE_GLOBAL_GTT |
1094                                 MI_SEMAPHORE_POLL |
1095                                 MI_SEMAPHORE_SAD_GTE_SDD);
1096         intel_ring_emit(waiter, seqno);
1097         intel_ring_emit(waiter,
1098                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1099         intel_ring_emit(waiter,
1100                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1101         intel_ring_advance(waiter);
1102         return 0;
1103 }
1104
1105 static int
1106 gen6_ring_sync(struct intel_engine_cs *waiter,
1107                struct intel_engine_cs *signaller,
1108                u32 seqno)
1109 {
1110         u32 dw1 = MI_SEMAPHORE_MBOX |
1111                   MI_SEMAPHORE_COMPARE |
1112                   MI_SEMAPHORE_REGISTER;
1113         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1114         int ret;
1115
1116         /* Throughout all of the GEM code, seqno passed implies our current
1117          * seqno is >= the last seqno executed. However for hardware the
1118          * comparison is strictly greater than.
1119          */
1120         seqno -= 1;
1121
1122         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1123
1124         ret = intel_ring_begin(waiter, 4);
1125         if (ret)
1126                 return ret;
1127
1128         /* If seqno wrap happened, omit the wait with no-ops */
1129         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1130                 intel_ring_emit(waiter, dw1 | wait_mbox);
1131                 intel_ring_emit(waiter, seqno);
1132                 intel_ring_emit(waiter, 0);
1133                 intel_ring_emit(waiter, MI_NOOP);
1134         } else {
1135                 intel_ring_emit(waiter, MI_NOOP);
1136                 intel_ring_emit(waiter, MI_NOOP);
1137                 intel_ring_emit(waiter, MI_NOOP);
1138                 intel_ring_emit(waiter, MI_NOOP);
1139         }
1140         intel_ring_advance(waiter);
1141
1142         return 0;
1143 }
1144
1145 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1146 do {                                                                    \
1147         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1148                  PIPE_CONTROL_DEPTH_STALL);                             \
1149         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1150         intel_ring_emit(ring__, 0);                                                     \
1151         intel_ring_emit(ring__, 0);                                                     \
1152 } while (0)
1153
1154 static int
1155 pc_render_add_request(struct intel_engine_cs *ring)
1156 {
1157         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1158         int ret;
1159
1160         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1161          * incoherent with writes to memory, i.e. completely fubar,
1162          * so we need to use PIPE_NOTIFY instead.
1163          *
1164          * However, we also need to workaround the qword write
1165          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1166          * memory before requesting an interrupt.
1167          */
1168         ret = intel_ring_begin(ring, 32);
1169         if (ret)
1170                 return ret;
1171
1172         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1173                         PIPE_CONTROL_WRITE_FLUSH |
1174                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1175         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1176         intel_ring_emit(ring,
1177                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1178         intel_ring_emit(ring, 0);
1179         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1180         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1181         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1182         scratch_addr += 2 * CACHELINE_BYTES;
1183         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1184         scratch_addr += 2 * CACHELINE_BYTES;
1185         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1186         scratch_addr += 2 * CACHELINE_BYTES;
1187         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1188         scratch_addr += 2 * CACHELINE_BYTES;
1189         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1190
1191         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1192                         PIPE_CONTROL_WRITE_FLUSH |
1193                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1194                         PIPE_CONTROL_NOTIFY);
1195         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1196         intel_ring_emit(ring,
1197                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1198         intel_ring_emit(ring, 0);
1199         __intel_ring_advance(ring);
1200
1201         return 0;
1202 }
1203
1204 static u32
1205 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1206 {
1207         /* Workaround to force correct ordering between irq and seqno writes on
1208          * ivb (and maybe also on snb) by reading from a CS register (like
1209          * ACTHD) before reading the status page. */
1210         if (!lazy_coherency) {
1211                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1212                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1213         }
1214
1215         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1216 }
1217
1218 static u32
1219 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1220 {
1221         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1222 }
1223
1224 static void
1225 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1226 {
1227         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1228 }
1229
1230 static u32
1231 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1232 {
1233         return ring->scratch.cpu_page[0];
1234 }
1235
1236 static void
1237 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1238 {
1239         ring->scratch.cpu_page[0] = seqno;
1240 }
1241
1242 static bool
1243 gen5_ring_get_irq(struct intel_engine_cs *ring)
1244 {
1245         struct drm_device *dev = ring->dev;
1246         struct drm_i915_private *dev_priv = dev->dev_private;
1247         unsigned long flags;
1248
1249         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1250                 return false;
1251
1252         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1253         if (ring->irq_refcount++ == 0)
1254                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1255         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1256
1257         return true;
1258 }
1259
1260 static void
1261 gen5_ring_put_irq(struct intel_engine_cs *ring)
1262 {
1263         struct drm_device *dev = ring->dev;
1264         struct drm_i915_private *dev_priv = dev->dev_private;
1265         unsigned long flags;
1266
1267         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1268         if (--ring->irq_refcount == 0)
1269                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1270         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1271 }
1272
1273 static bool
1274 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1275 {
1276         struct drm_device *dev = ring->dev;
1277         struct drm_i915_private *dev_priv = dev->dev_private;
1278         unsigned long flags;
1279
1280         if (!intel_irqs_enabled(dev_priv))
1281                 return false;
1282
1283         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1284         if (ring->irq_refcount++ == 0) {
1285                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1286                 I915_WRITE(IMR, dev_priv->irq_mask);
1287                 POSTING_READ(IMR);
1288         }
1289         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1290
1291         return true;
1292 }
1293
1294 static void
1295 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1296 {
1297         struct drm_device *dev = ring->dev;
1298         struct drm_i915_private *dev_priv = dev->dev_private;
1299         unsigned long flags;
1300
1301         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1302         if (--ring->irq_refcount == 0) {
1303                 dev_priv->irq_mask |= ring->irq_enable_mask;
1304                 I915_WRITE(IMR, dev_priv->irq_mask);
1305                 POSTING_READ(IMR);
1306         }
1307         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1308 }
1309
1310 static bool
1311 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1312 {
1313         struct drm_device *dev = ring->dev;
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315         unsigned long flags;
1316
1317         if (!intel_irqs_enabled(dev_priv))
1318                 return false;
1319
1320         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1321         if (ring->irq_refcount++ == 0) {
1322                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1323                 I915_WRITE16(IMR, dev_priv->irq_mask);
1324                 POSTING_READ16(IMR);
1325         }
1326         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1327
1328         return true;
1329 }
1330
1331 static void
1332 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1333 {
1334         struct drm_device *dev = ring->dev;
1335         struct drm_i915_private *dev_priv = dev->dev_private;
1336         unsigned long flags;
1337
1338         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1339         if (--ring->irq_refcount == 0) {
1340                 dev_priv->irq_mask |= ring->irq_enable_mask;
1341                 I915_WRITE16(IMR, dev_priv->irq_mask);
1342                 POSTING_READ16(IMR);
1343         }
1344         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1345 }
1346
1347 void intel_ring_setup_status_page(struct intel_engine_cs *ring)
1348 {
1349         struct drm_device *dev = ring->dev;
1350         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1351         u32 mmio = 0;
1352
1353         /* The ring status page addresses are no longer next to the rest of
1354          * the ring registers as of gen7.
1355          */
1356         if (IS_GEN7(dev)) {
1357                 switch (ring->id) {
1358                 case RCS:
1359                         mmio = RENDER_HWS_PGA_GEN7;
1360                         break;
1361                 case BCS:
1362                         mmio = BLT_HWS_PGA_GEN7;
1363                         break;
1364                 /*
1365                  * VCS2 actually doesn't exist on Gen7. Only shut up
1366                  * gcc switch check warning
1367                  */
1368                 case VCS2:
1369                 case VCS:
1370                         mmio = BSD_HWS_PGA_GEN7;
1371                         break;
1372                 case VECS:
1373                         mmio = VEBOX_HWS_PGA_GEN7;
1374                         break;
1375                 }
1376         } else if (IS_GEN6(ring->dev)) {
1377                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1378         } else {
1379                 /* XXX: gen8 returns to sanity */
1380                 mmio = RING_HWS_PGA(ring->mmio_base);
1381         }
1382
1383         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1384         POSTING_READ(mmio);
1385
1386         /*
1387          * Flush the TLB for this page
1388          *
1389          * FIXME: These two bits have disappeared on gen8, so a question
1390          * arises: do we still need this and if so how should we go about
1391          * invalidating the TLB?
1392          */
1393         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1394                 u32 reg = RING_INSTPM(ring->mmio_base);
1395
1396                 /* ring should be idle before issuing a sync flush*/
1397                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1398
1399                 I915_WRITE(reg,
1400                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1401                                               INSTPM_SYNC_FLUSH));
1402                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1403                              1000))
1404                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1405                                   ring->name);
1406         }
1407 }
1408
1409 static int
1410 bsd_ring_flush(struct intel_engine_cs *ring,
1411                u32     invalidate_domains,
1412                u32     flush_domains)
1413 {
1414         int ret;
1415
1416         ret = intel_ring_begin(ring, 2);
1417         if (ret)
1418                 return ret;
1419
1420         intel_ring_emit(ring, MI_FLUSH);
1421         intel_ring_emit(ring, MI_NOOP);
1422         intel_ring_advance(ring);
1423         return 0;
1424 }
1425
1426 static int
1427 i9xx_add_request(struct intel_engine_cs *ring)
1428 {
1429         int ret;
1430
1431         ret = intel_ring_begin(ring, 4);
1432         if (ret)
1433                 return ret;
1434
1435         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1436         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1437         intel_ring_emit(ring,
1438                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1439         intel_ring_emit(ring, MI_USER_INTERRUPT);
1440         __intel_ring_advance(ring);
1441
1442         return 0;
1443 }
1444
1445 static bool
1446 gen6_ring_get_irq(struct intel_engine_cs *ring)
1447 {
1448         struct drm_device *dev = ring->dev;
1449         struct drm_i915_private *dev_priv = dev->dev_private;
1450         unsigned long flags;
1451
1452         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1453                 return false;
1454
1455         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1456         if (ring->irq_refcount++ == 0) {
1457                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1458                         I915_WRITE_IMR(ring,
1459                                        ~(ring->irq_enable_mask |
1460                                          GT_PARITY_ERROR(dev)));
1461                 else
1462                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1463                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1464         }
1465         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1466
1467         return true;
1468 }
1469
1470 static void
1471 gen6_ring_put_irq(struct intel_engine_cs *ring)
1472 {
1473         struct drm_device *dev = ring->dev;
1474         struct drm_i915_private *dev_priv = dev->dev_private;
1475         unsigned long flags;
1476
1477         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1478         if (--ring->irq_refcount == 0) {
1479                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1480                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1481                 else
1482                         I915_WRITE_IMR(ring, ~0);
1483                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1484         }
1485         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1486 }
1487
1488 static bool
1489 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1490 {
1491         struct drm_device *dev = ring->dev;
1492         struct drm_i915_private *dev_priv = dev->dev_private;
1493         unsigned long flags;
1494
1495         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1496                 return false;
1497
1498         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1499         if (ring->irq_refcount++ == 0) {
1500                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1501                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1502         }
1503         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1504
1505         return true;
1506 }
1507
1508 static void
1509 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1510 {
1511         struct drm_device *dev = ring->dev;
1512         struct drm_i915_private *dev_priv = dev->dev_private;
1513         unsigned long flags;
1514
1515         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1516         if (--ring->irq_refcount == 0) {
1517                 I915_WRITE_IMR(ring, ~0);
1518                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1519         }
1520         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1521 }
1522
1523 static bool
1524 gen8_ring_get_irq(struct intel_engine_cs *ring)
1525 {
1526         struct drm_device *dev = ring->dev;
1527         struct drm_i915_private *dev_priv = dev->dev_private;
1528         unsigned long flags;
1529
1530         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1531                 return false;
1532
1533         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1534         if (ring->irq_refcount++ == 0) {
1535                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1536                         I915_WRITE_IMR(ring,
1537                                        ~(ring->irq_enable_mask |
1538                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1539                 } else {
1540                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1541                 }
1542                 POSTING_READ(RING_IMR(ring->mmio_base));
1543         }
1544         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1545
1546         return true;
1547 }
1548
1549 static void
1550 gen8_ring_put_irq(struct intel_engine_cs *ring)
1551 {
1552         struct drm_device *dev = ring->dev;
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         unsigned long flags;
1555
1556         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1557         if (--ring->irq_refcount == 0) {
1558                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1559                         I915_WRITE_IMR(ring,
1560                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1561                 } else {
1562                         I915_WRITE_IMR(ring, ~0);
1563                 }
1564                 POSTING_READ(RING_IMR(ring->mmio_base));
1565         }
1566         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1567 }
1568
1569 static int
1570 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1571                          u64 offset, u32 length,
1572                          unsigned flags)
1573 {
1574         int ret;
1575
1576         ret = intel_ring_begin(ring, 2);
1577         if (ret)
1578                 return ret;
1579
1580         intel_ring_emit(ring,
1581                         MI_BATCH_BUFFER_START |
1582                         MI_BATCH_GTT |
1583                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1584         intel_ring_emit(ring, offset);
1585         intel_ring_advance(ring);
1586
1587         return 0;
1588 }
1589
1590 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1591 #define I830_BATCH_LIMIT (256*1024)
1592 #define I830_TLB_ENTRIES (2)
1593 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1594 static int
1595 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1596                                 u64 offset, u32 len,
1597                                 unsigned flags)
1598 {
1599         u32 cs_offset = ring->scratch.gtt_offset;
1600         int ret;
1601
1602         ret = intel_ring_begin(ring, 6);
1603         if (ret)
1604                 return ret;
1605
1606         /* Evict the invalid PTE TLBs */
1607         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1608         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1609         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1610         intel_ring_emit(ring, cs_offset);
1611         intel_ring_emit(ring, 0xdeadbeef);
1612         intel_ring_emit(ring, MI_NOOP);
1613         intel_ring_advance(ring);
1614
1615         if ((flags & I915_DISPATCH_PINNED) == 0) {
1616                 if (len > I830_BATCH_LIMIT)
1617                         return -ENOSPC;
1618
1619                 ret = intel_ring_begin(ring, 6 + 2);
1620                 if (ret)
1621                         return ret;
1622
1623                 /* Blit the batch (which has now all relocs applied) to the
1624                  * stable batch scratch bo area (so that the CS never
1625                  * stumbles over its tlb invalidation bug) ...
1626                  */
1627                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1628                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1629                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1630                 intel_ring_emit(ring, cs_offset);
1631                 intel_ring_emit(ring, 4096);
1632                 intel_ring_emit(ring, offset);
1633
1634                 intel_ring_emit(ring, MI_FLUSH);
1635                 intel_ring_emit(ring, MI_NOOP);
1636                 intel_ring_advance(ring);
1637
1638                 /* ... and execute it. */
1639                 offset = cs_offset;
1640         }
1641
1642         ret = intel_ring_begin(ring, 4);
1643         if (ret)
1644                 return ret;
1645
1646         intel_ring_emit(ring, MI_BATCH_BUFFER);
1647         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1648         intel_ring_emit(ring, offset + len - 8);
1649         intel_ring_emit(ring, MI_NOOP);
1650         intel_ring_advance(ring);
1651
1652         return 0;
1653 }
1654
1655 static int
1656 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1657                          u64 offset, u32 len,
1658                          unsigned flags)
1659 {
1660         int ret;
1661
1662         ret = intel_ring_begin(ring, 2);
1663         if (ret)
1664                 return ret;
1665
1666         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1667         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1668         intel_ring_advance(ring);
1669
1670         return 0;
1671 }
1672
1673 static void cleanup_status_page(struct intel_engine_cs *ring)
1674 {
1675         struct drm_i915_gem_object *obj;
1676
1677         obj = ring->status_page.obj;
1678         if (obj == NULL)
1679                 return;
1680
1681         kunmap(sg_page(obj->pages->sgl));
1682         i915_gem_object_ggtt_unpin(obj);
1683         drm_gem_object_unreference(&obj->base);
1684         ring->status_page.obj = NULL;
1685 }
1686
1687 static int init_status_page(struct intel_engine_cs *ring)
1688 {
1689         struct drm_i915_gem_object *obj;
1690
1691         if ((obj = ring->status_page.obj) == NULL) {
1692                 unsigned flags;
1693                 int ret;
1694
1695                 obj = i915_gem_alloc_object(ring->dev, 4096);
1696                 if (obj == NULL) {
1697                         DRM_ERROR("Failed to allocate status page\n");
1698                         return -ENOMEM;
1699                 }
1700
1701                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1702                 if (ret)
1703                         goto err_unref;
1704
1705                 flags = 0;
1706                 if (!HAS_LLC(ring->dev))
1707                         /* On g33, we cannot place HWS above 256MiB, so
1708                          * restrict its pinning to the low mappable arena.
1709                          * Though this restriction is not documented for
1710                          * gen4, gen5, or byt, they also behave similarly
1711                          * and hang if the HWS is placed at the top of the
1712                          * GTT. To generalise, it appears that all !llc
1713                          * platforms have issues with us placing the HWS
1714                          * above the mappable region (even though we never
1715                          * actualy map it).
1716                          */
1717                         flags |= PIN_MAPPABLE;
1718                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1719                 if (ret) {
1720 err_unref:
1721                         drm_gem_object_unreference(&obj->base);
1722                         return ret;
1723                 }
1724
1725                 ring->status_page.obj = obj;
1726         }
1727
1728         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1729         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1730         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1731
1732         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1733                         ring->name, ring->status_page.gfx_addr);
1734
1735         return 0;
1736 }
1737
1738 static int init_phys_status_page(struct intel_engine_cs *ring)
1739 {
1740         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1741
1742         if (!dev_priv->status_page_dmah) {
1743                 dev_priv->status_page_dmah =
1744                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1745                 if (!dev_priv->status_page_dmah)
1746                         return -ENOMEM;
1747         }
1748
1749         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1750         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1751
1752         return 0;
1753 }
1754
1755 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1756 {
1757         iounmap(ringbuf->virtual_start);
1758         ringbuf->virtual_start = NULL;
1759         i915_gem_object_ggtt_unpin(ringbuf->obj);
1760 }
1761
1762 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1763                                      struct intel_ringbuffer *ringbuf)
1764 {
1765         struct drm_i915_private *dev_priv = to_i915(dev);
1766         struct drm_i915_gem_object *obj = ringbuf->obj;
1767         int ret;
1768
1769         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1770         if (ret)
1771                 return ret;
1772
1773         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1774         if (ret) {
1775                 i915_gem_object_ggtt_unpin(obj);
1776                 return ret;
1777         }
1778
1779         ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1780                         i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1781         if (ringbuf->virtual_start == NULL) {
1782                 i915_gem_object_ggtt_unpin(obj);
1783                 return -EINVAL;
1784         }
1785
1786         return 0;
1787 }
1788
1789 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1790 {
1791         drm_gem_object_unreference(&ringbuf->obj->base);
1792         ringbuf->obj = NULL;
1793 }
1794
1795 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1796                                struct intel_ringbuffer *ringbuf)
1797 {
1798         struct drm_i915_gem_object *obj;
1799
1800         obj = NULL;
1801         if (!HAS_LLC(dev))
1802                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1803         if (obj == NULL)
1804                 obj = i915_gem_alloc_object(dev, ringbuf->size);
1805         if (obj == NULL)
1806                 return -ENOMEM;
1807
1808         /* mark ring buffers as read-only from GPU side by default */
1809         obj->gt_ro = 1;
1810
1811         ringbuf->obj = obj;
1812
1813         return 0;
1814 }
1815
1816 static int intel_init_ring_buffer(struct drm_device *dev,
1817                                   struct intel_engine_cs *ring)
1818 {
1819         struct intel_ringbuffer *ringbuf;
1820         int ret;
1821
1822         WARN_ON(ring->buffer);
1823
1824         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1825         if (!ringbuf)
1826                 return -ENOMEM;
1827         ring->buffer = ringbuf;
1828
1829         ring->dev = dev;
1830         INIT_LIST_HEAD(&ring->active_list);
1831         INIT_LIST_HEAD(&ring->request_list);
1832         INIT_LIST_HEAD(&ring->execlist_queue);
1833         ringbuf->size = 32 * PAGE_SIZE;
1834         ringbuf->ring = ring;
1835         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1836
1837         init_waitqueue_head(&ring->irq_queue);
1838
1839         if (I915_NEED_GFX_HWS(dev)) {
1840                 ret = init_status_page(ring);
1841                 if (ret)
1842                         goto error;
1843         } else {
1844                 BUG_ON(ring->id != RCS);
1845                 ret = init_phys_status_page(ring);
1846                 if (ret)
1847                         goto error;
1848         }
1849
1850         WARN_ON(ringbuf->obj);
1851
1852         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1853         if (ret) {
1854                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1855                                 ring->name, ret);
1856                 goto error;
1857         }
1858
1859         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1860         if (ret) {
1861                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1862                                 ring->name, ret);
1863                 intel_destroy_ringbuffer_obj(ringbuf);
1864                 goto error;
1865         }
1866
1867         /* Workaround an erratum on the i830 which causes a hang if
1868          * the TAIL pointer points to within the last 2 cachelines
1869          * of the buffer.
1870          */
1871         ringbuf->effective_size = ringbuf->size;
1872         if (IS_I830(dev) || IS_845G(dev))
1873                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1874
1875         ret = i915_cmd_parser_init_ring(ring);
1876         if (ret)
1877                 goto error;
1878
1879         return 0;
1880
1881 error:
1882         kfree(ringbuf);
1883         ring->buffer = NULL;
1884         return ret;
1885 }
1886
1887 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1888 {
1889         struct drm_i915_private *dev_priv;
1890         struct intel_ringbuffer *ringbuf;
1891
1892         if (!intel_ring_initialized(ring))
1893                 return;
1894
1895         dev_priv = to_i915(ring->dev);
1896         ringbuf = ring->buffer;
1897
1898         intel_stop_ring_buffer(ring);
1899         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1900
1901         intel_unpin_ringbuffer_obj(ringbuf);
1902         intel_destroy_ringbuffer_obj(ringbuf);
1903         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1904
1905         if (ring->cleanup)
1906                 ring->cleanup(ring);
1907
1908         cleanup_status_page(ring);
1909
1910         i915_cmd_parser_fini_ring(ring);
1911
1912         kfree(ringbuf);
1913         ring->buffer = NULL;
1914 }
1915
1916 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
1917 {
1918         struct intel_ringbuffer *ringbuf = ring->buffer;
1919         struct drm_i915_gem_request *request;
1920         int ret;
1921
1922         if (intel_ring_space(ringbuf) >= n)
1923                 return 0;
1924
1925         list_for_each_entry(request, &ring->request_list, list) {
1926                 if (__intel_ring_space(request->tail, ringbuf->tail,
1927                                        ringbuf->size) >= n) {
1928                         break;
1929                 }
1930         }
1931
1932         if (&request->list == &ring->request_list)
1933                 return -ENOSPC;
1934
1935         ret = i915_wait_request(request);
1936         if (ret)
1937                 return ret;
1938
1939         i915_gem_retire_requests_ring(ring);
1940
1941         return 0;
1942 }
1943
1944 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
1945 {
1946         struct drm_device *dev = ring->dev;
1947         struct drm_i915_private *dev_priv = dev->dev_private;
1948         struct intel_ringbuffer *ringbuf = ring->buffer;
1949         unsigned long end;
1950         int ret;
1951
1952         ret = intel_ring_wait_request(ring, n);
1953         if (ret != -ENOSPC)
1954                 return ret;
1955
1956         /* force the tail write in case we have been skipping them */
1957         __intel_ring_advance(ring);
1958
1959         /* With GEM the hangcheck timer should kick us out of the loop,
1960          * leaving it early runs the risk of corrupting GEM state (due
1961          * to running on almost untested codepaths). But on resume
1962          * timers don't work yet, so prevent a complete hang in that
1963          * case by choosing an insanely large timeout. */
1964         end = jiffies + 60 * HZ;
1965
1966         ret = 0;
1967         trace_i915_ring_wait_begin(ring);
1968         do {
1969                 if (intel_ring_space(ringbuf) >= n)
1970                         break;
1971                 ringbuf->head = I915_READ_HEAD(ring);
1972                 if (intel_ring_space(ringbuf) >= n)
1973                         break;
1974
1975                 msleep(1);
1976
1977                 if (dev_priv->mm.interruptible && signal_pending(current)) {
1978                         ret = -ERESTARTSYS;
1979                         break;
1980                 }
1981
1982                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1983                                            dev_priv->mm.interruptible);
1984                 if (ret)
1985                         break;
1986
1987                 if (time_after(jiffies, end)) {
1988                         ret = -EBUSY;
1989                         break;
1990                 }
1991         } while (1);
1992         trace_i915_ring_wait_end(ring);
1993         return ret;
1994 }
1995
1996 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
1997 {
1998         uint32_t __iomem *virt;
1999         struct intel_ringbuffer *ringbuf = ring->buffer;
2000         int rem = ringbuf->size - ringbuf->tail;
2001
2002         if (ringbuf->space < rem) {
2003                 int ret = ring_wait_for_space(ring, rem);
2004                 if (ret)
2005                         return ret;
2006         }
2007
2008         virt = ringbuf->virtual_start + ringbuf->tail;
2009         rem /= 4;
2010         while (rem--)
2011                 iowrite32(MI_NOOP, virt++);
2012
2013         ringbuf->tail = 0;
2014         intel_ring_update_space(ringbuf);
2015
2016         return 0;
2017 }
2018
2019 int intel_ring_idle(struct intel_engine_cs *ring)
2020 {
2021         struct drm_i915_gem_request *req;
2022         int ret;
2023
2024         /* We need to add any requests required to flush the objects and ring */
2025         if (ring->outstanding_lazy_request) {
2026                 ret = i915_add_request(ring);
2027                 if (ret)
2028                         return ret;
2029         }
2030
2031         /* Wait upon the last request to be completed */
2032         if (list_empty(&ring->request_list))
2033                 return 0;
2034
2035         req = list_entry(ring->request_list.prev,
2036                            struct drm_i915_gem_request,
2037                            list);
2038
2039         return i915_wait_request(req);
2040 }
2041
2042 static int
2043 intel_ring_alloc_request(struct intel_engine_cs *ring)
2044 {
2045         int ret;
2046         struct drm_i915_gem_request *request;
2047         struct drm_i915_private *dev_private = ring->dev->dev_private;
2048
2049         if (ring->outstanding_lazy_request)
2050                 return 0;
2051
2052         request = kzalloc(sizeof(*request), GFP_KERNEL);
2053         if (request == NULL)
2054                 return -ENOMEM;
2055
2056         kref_init(&request->ref);
2057         request->ring = ring;
2058         request->uniq = dev_private->request_uniq++;
2059
2060         ret = i915_gem_get_seqno(ring->dev, &request->seqno);
2061         if (ret) {
2062                 kfree(request);
2063                 return ret;
2064         }
2065
2066         ring->outstanding_lazy_request = request;
2067         return 0;
2068 }
2069
2070 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2071                                 int bytes)
2072 {
2073         struct intel_ringbuffer *ringbuf = ring->buffer;
2074         int ret;
2075
2076         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2077                 ret = intel_wrap_ring_buffer(ring);
2078                 if (unlikely(ret))
2079                         return ret;
2080         }
2081
2082         if (unlikely(ringbuf->space < bytes)) {
2083                 ret = ring_wait_for_space(ring, bytes);
2084                 if (unlikely(ret))
2085                         return ret;
2086         }
2087
2088         return 0;
2089 }
2090
2091 int intel_ring_begin(struct intel_engine_cs *ring,
2092                      int num_dwords)
2093 {
2094         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2095         int ret;
2096
2097         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2098                                    dev_priv->mm.interruptible);
2099         if (ret)
2100                 return ret;
2101
2102         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2103         if (ret)
2104                 return ret;
2105
2106         /* Preallocate the olr before touching the ring */
2107         ret = intel_ring_alloc_request(ring);
2108         if (ret)
2109                 return ret;
2110
2111         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2112         return 0;
2113 }
2114
2115 /* Align the ring tail to a cacheline boundary */
2116 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2117 {
2118         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2119         int ret;
2120
2121         if (num_dwords == 0)
2122                 return 0;
2123
2124         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2125         ret = intel_ring_begin(ring, num_dwords);
2126         if (ret)
2127                 return ret;
2128
2129         while (num_dwords--)
2130                 intel_ring_emit(ring, MI_NOOP);
2131
2132         intel_ring_advance(ring);
2133
2134         return 0;
2135 }
2136
2137 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2138 {
2139         struct drm_device *dev = ring->dev;
2140         struct drm_i915_private *dev_priv = dev->dev_private;
2141
2142         BUG_ON(ring->outstanding_lazy_request);
2143
2144         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2145                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2146                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2147                 if (HAS_VEBOX(dev))
2148                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2149         }
2150
2151         ring->set_seqno(ring, seqno);
2152         ring->hangcheck.seqno = seqno;
2153 }
2154
2155 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2156                                      u32 value)
2157 {
2158         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2159
2160        /* Every tail move must follow the sequence below */
2161
2162         /* Disable notification that the ring is IDLE. The GT
2163          * will then assume that it is busy and bring it out of rc6.
2164          */
2165         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2166                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2167
2168         /* Clear the context id. Here be magic! */
2169         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2170
2171         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2172         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2173                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2174                      50))
2175                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2176
2177         /* Now that the ring is fully powered up, update the tail */
2178         I915_WRITE_TAIL(ring, value);
2179         POSTING_READ(RING_TAIL(ring->mmio_base));
2180
2181         /* Let the ring send IDLE messages to the GT again,
2182          * and so let it sleep to conserve power when idle.
2183          */
2184         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2185                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2186 }
2187
2188 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2189                                u32 invalidate, u32 flush)
2190 {
2191         uint32_t cmd;
2192         int ret;
2193
2194         ret = intel_ring_begin(ring, 4);
2195         if (ret)
2196                 return ret;
2197
2198         cmd = MI_FLUSH_DW;
2199         if (INTEL_INFO(ring->dev)->gen >= 8)
2200                 cmd += 1;
2201         /*
2202          * Bspec vol 1c.5 - video engine command streamer:
2203          * "If ENABLED, all TLBs will be invalidated once the flush
2204          * operation is complete. This bit is only valid when the
2205          * Post-Sync Operation field is a value of 1h or 3h."
2206          */
2207         if (invalidate & I915_GEM_GPU_DOMAINS)
2208                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2209                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2210         intel_ring_emit(ring, cmd);
2211         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2212         if (INTEL_INFO(ring->dev)->gen >= 8) {
2213                 intel_ring_emit(ring, 0); /* upper addr */
2214                 intel_ring_emit(ring, 0); /* value */
2215         } else  {
2216                 intel_ring_emit(ring, 0);
2217                 intel_ring_emit(ring, MI_NOOP);
2218         }
2219         intel_ring_advance(ring);
2220         return 0;
2221 }
2222
2223 static int
2224 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2225                               u64 offset, u32 len,
2226                               unsigned flags)
2227 {
2228         bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
2229         int ret;
2230
2231         ret = intel_ring_begin(ring, 4);
2232         if (ret)
2233                 return ret;
2234
2235         /* FIXME(BDW): Address space and security selectors. */
2236         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2237         intel_ring_emit(ring, lower_32_bits(offset));
2238         intel_ring_emit(ring, upper_32_bits(offset));
2239         intel_ring_emit(ring, MI_NOOP);
2240         intel_ring_advance(ring);
2241
2242         return 0;
2243 }
2244
2245 static int
2246 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2247                               u64 offset, u32 len,
2248                               unsigned flags)
2249 {
2250         int ret;
2251
2252         ret = intel_ring_begin(ring, 2);
2253         if (ret)
2254                 return ret;
2255
2256         intel_ring_emit(ring,
2257                         MI_BATCH_BUFFER_START |
2258                         (flags & I915_DISPATCH_SECURE ?
2259                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2260         /* bit0-7 is the length on GEN6+ */
2261         intel_ring_emit(ring, offset);
2262         intel_ring_advance(ring);
2263
2264         return 0;
2265 }
2266
2267 static int
2268 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2269                               u64 offset, u32 len,
2270                               unsigned flags)
2271 {
2272         int ret;
2273
2274         ret = intel_ring_begin(ring, 2);
2275         if (ret)
2276                 return ret;
2277
2278         intel_ring_emit(ring,
2279                         MI_BATCH_BUFFER_START |
2280                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2281         /* bit0-7 is the length on GEN6+ */
2282         intel_ring_emit(ring, offset);
2283         intel_ring_advance(ring);
2284
2285         return 0;
2286 }
2287
2288 /* Blitter support (SandyBridge+) */
2289
2290 static int gen6_ring_flush(struct intel_engine_cs *ring,
2291                            u32 invalidate, u32 flush)
2292 {
2293         struct drm_device *dev = ring->dev;
2294         struct drm_i915_private *dev_priv = dev->dev_private;
2295         uint32_t cmd;
2296         int ret;
2297
2298         ret = intel_ring_begin(ring, 4);
2299         if (ret)
2300                 return ret;
2301
2302         cmd = MI_FLUSH_DW;
2303         if (INTEL_INFO(ring->dev)->gen >= 8)
2304                 cmd += 1;
2305         /*
2306          * Bspec vol 1c.3 - blitter engine command streamer:
2307          * "If ENABLED, all TLBs will be invalidated once the flush
2308          * operation is complete. This bit is only valid when the
2309          * Post-Sync Operation field is a value of 1h or 3h."
2310          */
2311         if (invalidate & I915_GEM_DOMAIN_RENDER)
2312                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
2313                         MI_FLUSH_DW_OP_STOREDW;
2314         intel_ring_emit(ring, cmd);
2315         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2316         if (INTEL_INFO(ring->dev)->gen >= 8) {
2317                 intel_ring_emit(ring, 0); /* upper addr */
2318                 intel_ring_emit(ring, 0); /* value */
2319         } else  {
2320                 intel_ring_emit(ring, 0);
2321                 intel_ring_emit(ring, MI_NOOP);
2322         }
2323         intel_ring_advance(ring);
2324
2325         if (!invalidate && flush) {
2326                 if (IS_GEN7(dev))
2327                         return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2328                 else if (IS_BROADWELL(dev))
2329                         dev_priv->fbc.need_sw_cache_clean = true;
2330         }
2331
2332         return 0;
2333 }
2334
2335 int intel_init_render_ring_buffer(struct drm_device *dev)
2336 {
2337         struct drm_i915_private *dev_priv = dev->dev_private;
2338         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2339         struct drm_i915_gem_object *obj;
2340         int ret;
2341
2342         ring->name = "render ring";
2343         ring->id = RCS;
2344         ring->mmio_base = RENDER_RING_BASE;
2345
2346         if (INTEL_INFO(dev)->gen >= 8) {
2347                 if (i915_semaphore_is_enabled(dev)) {
2348                         obj = i915_gem_alloc_object(dev, 4096);
2349                         if (obj == NULL) {
2350                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2351                                 i915.semaphores = 0;
2352                         } else {
2353                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2354                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2355                                 if (ret != 0) {
2356                                         drm_gem_object_unreference(&obj->base);
2357                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2358                                         i915.semaphores = 0;
2359                                 } else
2360                                         dev_priv->semaphore_obj = obj;
2361                         }
2362                 }
2363
2364                 ring->init_context = intel_rcs_ctx_init;
2365                 ring->add_request = gen6_add_request;
2366                 ring->flush = gen8_render_ring_flush;
2367                 ring->irq_get = gen8_ring_get_irq;
2368                 ring->irq_put = gen8_ring_put_irq;
2369                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2370                 ring->get_seqno = gen6_ring_get_seqno;
2371                 ring->set_seqno = ring_set_seqno;
2372                 if (i915_semaphore_is_enabled(dev)) {
2373                         WARN_ON(!dev_priv->semaphore_obj);
2374                         ring->semaphore.sync_to = gen8_ring_sync;
2375                         ring->semaphore.signal = gen8_rcs_signal;
2376                         GEN8_RING_SEMAPHORE_INIT;
2377                 }
2378         } else if (INTEL_INFO(dev)->gen >= 6) {
2379                 ring->add_request = gen6_add_request;
2380                 ring->flush = gen7_render_ring_flush;
2381                 if (INTEL_INFO(dev)->gen == 6)
2382                         ring->flush = gen6_render_ring_flush;
2383                 ring->irq_get = gen6_ring_get_irq;
2384                 ring->irq_put = gen6_ring_put_irq;
2385                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2386                 ring->get_seqno = gen6_ring_get_seqno;
2387                 ring->set_seqno = ring_set_seqno;
2388                 if (i915_semaphore_is_enabled(dev)) {
2389                         ring->semaphore.sync_to = gen6_ring_sync;
2390                         ring->semaphore.signal = gen6_signal;
2391                         /*
2392                          * The current semaphore is only applied on pre-gen8
2393                          * platform.  And there is no VCS2 ring on the pre-gen8
2394                          * platform. So the semaphore between RCS and VCS2 is
2395                          * initialized as INVALID.  Gen8 will initialize the
2396                          * sema between VCS2 and RCS later.
2397                          */
2398                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2399                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2400                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2401                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2402                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2403                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2404                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2405                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2406                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2407                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2408                 }
2409         } else if (IS_GEN5(dev)) {
2410                 ring->add_request = pc_render_add_request;
2411                 ring->flush = gen4_render_ring_flush;
2412                 ring->get_seqno = pc_render_get_seqno;
2413                 ring->set_seqno = pc_render_set_seqno;
2414                 ring->irq_get = gen5_ring_get_irq;
2415                 ring->irq_put = gen5_ring_put_irq;
2416                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2417                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2418         } else {
2419                 ring->add_request = i9xx_add_request;
2420                 if (INTEL_INFO(dev)->gen < 4)
2421                         ring->flush = gen2_render_ring_flush;
2422                 else
2423                         ring->flush = gen4_render_ring_flush;
2424                 ring->get_seqno = ring_get_seqno;
2425                 ring->set_seqno = ring_set_seqno;
2426                 if (IS_GEN2(dev)) {
2427                         ring->irq_get = i8xx_ring_get_irq;
2428                         ring->irq_put = i8xx_ring_put_irq;
2429                 } else {
2430                         ring->irq_get = i9xx_ring_get_irq;
2431                         ring->irq_put = i9xx_ring_put_irq;
2432                 }
2433                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2434         }
2435         ring->write_tail = ring_write_tail;
2436
2437         if (IS_HASWELL(dev))
2438                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2439         else if (IS_GEN8(dev))
2440                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2441         else if (INTEL_INFO(dev)->gen >= 6)
2442                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2443         else if (INTEL_INFO(dev)->gen >= 4)
2444                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2445         else if (IS_I830(dev) || IS_845G(dev))
2446                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2447         else
2448                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2449         ring->init_hw = init_render_ring;
2450         ring->cleanup = render_ring_cleanup;
2451
2452         /* Workaround batchbuffer to combat CS tlb bug. */
2453         if (HAS_BROKEN_CS_TLB(dev)) {
2454                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2455                 if (obj == NULL) {
2456                         DRM_ERROR("Failed to allocate batch bo\n");
2457                         return -ENOMEM;
2458                 }
2459
2460                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2461                 if (ret != 0) {
2462                         drm_gem_object_unreference(&obj->base);
2463                         DRM_ERROR("Failed to ping batch bo\n");
2464                         return ret;
2465                 }
2466
2467                 ring->scratch.obj = obj;
2468                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2469         }
2470
2471         ret = intel_init_ring_buffer(dev, ring);
2472         if (ret)
2473                 return ret;
2474
2475         if (INTEL_INFO(dev)->gen >= 5) {
2476                 ret = intel_init_pipe_control(ring);
2477                 if (ret)
2478                         return ret;
2479         }
2480
2481         return 0;
2482 }
2483
2484 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2485 {
2486         struct drm_i915_private *dev_priv = dev->dev_private;
2487         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2488
2489         ring->name = "bsd ring";
2490         ring->id = VCS;
2491
2492         ring->write_tail = ring_write_tail;
2493         if (INTEL_INFO(dev)->gen >= 6) {
2494                 ring->mmio_base = GEN6_BSD_RING_BASE;
2495                 /* gen6 bsd needs a special wa for tail updates */
2496                 if (IS_GEN6(dev))
2497                         ring->write_tail = gen6_bsd_ring_write_tail;
2498                 ring->flush = gen6_bsd_ring_flush;
2499                 ring->add_request = gen6_add_request;
2500                 ring->get_seqno = gen6_ring_get_seqno;
2501                 ring->set_seqno = ring_set_seqno;
2502                 if (INTEL_INFO(dev)->gen >= 8) {
2503                         ring->irq_enable_mask =
2504                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2505                         ring->irq_get = gen8_ring_get_irq;
2506                         ring->irq_put = gen8_ring_put_irq;
2507                         ring->dispatch_execbuffer =
2508                                 gen8_ring_dispatch_execbuffer;
2509                         if (i915_semaphore_is_enabled(dev)) {
2510                                 ring->semaphore.sync_to = gen8_ring_sync;
2511                                 ring->semaphore.signal = gen8_xcs_signal;
2512                                 GEN8_RING_SEMAPHORE_INIT;
2513                         }
2514                 } else {
2515                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2516                         ring->irq_get = gen6_ring_get_irq;
2517                         ring->irq_put = gen6_ring_put_irq;
2518                         ring->dispatch_execbuffer =
2519                                 gen6_ring_dispatch_execbuffer;
2520                         if (i915_semaphore_is_enabled(dev)) {
2521                                 ring->semaphore.sync_to = gen6_ring_sync;
2522                                 ring->semaphore.signal = gen6_signal;
2523                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2524                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2525                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2526                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2527                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2528                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2529                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2530                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2531                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2532                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2533                         }
2534                 }
2535         } else {
2536                 ring->mmio_base = BSD_RING_BASE;
2537                 ring->flush = bsd_ring_flush;
2538                 ring->add_request = i9xx_add_request;
2539                 ring->get_seqno = ring_get_seqno;
2540                 ring->set_seqno = ring_set_seqno;
2541                 if (IS_GEN5(dev)) {
2542                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2543                         ring->irq_get = gen5_ring_get_irq;
2544                         ring->irq_put = gen5_ring_put_irq;
2545                 } else {
2546                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2547                         ring->irq_get = i9xx_ring_get_irq;
2548                         ring->irq_put = i9xx_ring_put_irq;
2549                 }
2550                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2551         }
2552         ring->init_hw = init_ring_common;
2553
2554         return intel_init_ring_buffer(dev, ring);
2555 }
2556
2557 /**
2558  * Initialize the second BSD ring for Broadwell GT3.
2559  * It is noted that this only exists on Broadwell GT3.
2560  */
2561 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2562 {
2563         struct drm_i915_private *dev_priv = dev->dev_private;
2564         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2565
2566         if ((INTEL_INFO(dev)->gen != 8)) {
2567                 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2568                 return -EINVAL;
2569         }
2570
2571         ring->name = "bsd2 ring";
2572         ring->id = VCS2;
2573
2574         ring->write_tail = ring_write_tail;
2575         ring->mmio_base = GEN8_BSD2_RING_BASE;
2576         ring->flush = gen6_bsd_ring_flush;
2577         ring->add_request = gen6_add_request;
2578         ring->get_seqno = gen6_ring_get_seqno;
2579         ring->set_seqno = ring_set_seqno;
2580         ring->irq_enable_mask =
2581                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2582         ring->irq_get = gen8_ring_get_irq;
2583         ring->irq_put = gen8_ring_put_irq;
2584         ring->dispatch_execbuffer =
2585                         gen8_ring_dispatch_execbuffer;
2586         if (i915_semaphore_is_enabled(dev)) {
2587                 ring->semaphore.sync_to = gen8_ring_sync;
2588                 ring->semaphore.signal = gen8_xcs_signal;
2589                 GEN8_RING_SEMAPHORE_INIT;
2590         }
2591         ring->init_hw = init_ring_common;
2592
2593         return intel_init_ring_buffer(dev, ring);
2594 }
2595
2596 int intel_init_blt_ring_buffer(struct drm_device *dev)
2597 {
2598         struct drm_i915_private *dev_priv = dev->dev_private;
2599         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2600
2601         ring->name = "blitter ring";
2602         ring->id = BCS;
2603
2604         ring->mmio_base = BLT_RING_BASE;
2605         ring->write_tail = ring_write_tail;
2606         ring->flush = gen6_ring_flush;
2607         ring->add_request = gen6_add_request;
2608         ring->get_seqno = gen6_ring_get_seqno;
2609         ring->set_seqno = ring_set_seqno;
2610         if (INTEL_INFO(dev)->gen >= 8) {
2611                 ring->irq_enable_mask =
2612                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2613                 ring->irq_get = gen8_ring_get_irq;
2614                 ring->irq_put = gen8_ring_put_irq;
2615                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2616                 if (i915_semaphore_is_enabled(dev)) {
2617                         ring->semaphore.sync_to = gen8_ring_sync;
2618                         ring->semaphore.signal = gen8_xcs_signal;
2619                         GEN8_RING_SEMAPHORE_INIT;
2620                 }
2621         } else {
2622                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2623                 ring->irq_get = gen6_ring_get_irq;
2624                 ring->irq_put = gen6_ring_put_irq;
2625                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2626                 if (i915_semaphore_is_enabled(dev)) {
2627                         ring->semaphore.signal = gen6_signal;
2628                         ring->semaphore.sync_to = gen6_ring_sync;
2629                         /*
2630                          * The current semaphore is only applied on pre-gen8
2631                          * platform.  And there is no VCS2 ring on the pre-gen8
2632                          * platform. So the semaphore between BCS and VCS2 is
2633                          * initialized as INVALID.  Gen8 will initialize the
2634                          * sema between BCS and VCS2 later.
2635                          */
2636                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2637                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2638                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2639                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2640                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2641                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2642                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2643                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2644                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2645                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2646                 }
2647         }
2648         ring->init_hw = init_ring_common;
2649
2650         return intel_init_ring_buffer(dev, ring);
2651 }
2652
2653 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2654 {
2655         struct drm_i915_private *dev_priv = dev->dev_private;
2656         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2657
2658         ring->name = "video enhancement ring";
2659         ring->id = VECS;
2660
2661         ring->mmio_base = VEBOX_RING_BASE;
2662         ring->write_tail = ring_write_tail;
2663         ring->flush = gen6_ring_flush;
2664         ring->add_request = gen6_add_request;
2665         ring->get_seqno = gen6_ring_get_seqno;
2666         ring->set_seqno = ring_set_seqno;
2667
2668         if (INTEL_INFO(dev)->gen >= 8) {
2669                 ring->irq_enable_mask =
2670                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2671                 ring->irq_get = gen8_ring_get_irq;
2672                 ring->irq_put = gen8_ring_put_irq;
2673                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2674                 if (i915_semaphore_is_enabled(dev)) {
2675                         ring->semaphore.sync_to = gen8_ring_sync;
2676                         ring->semaphore.signal = gen8_xcs_signal;
2677                         GEN8_RING_SEMAPHORE_INIT;
2678                 }
2679         } else {
2680                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2681                 ring->irq_get = hsw_vebox_get_irq;
2682                 ring->irq_put = hsw_vebox_put_irq;
2683                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2684                 if (i915_semaphore_is_enabled(dev)) {
2685                         ring->semaphore.sync_to = gen6_ring_sync;
2686                         ring->semaphore.signal = gen6_signal;
2687                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2688                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2689                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2690                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2691                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2692                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2693                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2694                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2695                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2696                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2697                 }
2698         }
2699         ring->init_hw = init_ring_common;
2700
2701         return intel_init_ring_buffer(dev, ring);
2702 }
2703
2704 int
2705 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2706 {
2707         int ret;
2708
2709         if (!ring->gpu_caches_dirty)
2710                 return 0;
2711
2712         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2713         if (ret)
2714                 return ret;
2715
2716         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2717
2718         ring->gpu_caches_dirty = false;
2719         return 0;
2720 }
2721
2722 int
2723 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2724 {
2725         uint32_t flush_domains;
2726         int ret;
2727
2728         flush_domains = 0;
2729         if (ring->gpu_caches_dirty)
2730                 flush_domains = I915_GEM_GPU_DOMAINS;
2731
2732         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2733         if (ret)
2734                 return ret;
2735
2736         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2737
2738         ring->gpu_caches_dirty = false;
2739         return 0;
2740 }
2741
2742 void
2743 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2744 {
2745         int ret;
2746
2747         if (!intel_ring_initialized(ring))
2748                 return;
2749
2750         ret = intel_ring_idle(ring);
2751         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2752                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2753                           ring->name, ret);
2754
2755         stop_ring(ring);
2756 }