2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
36 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
37 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
38 * to give some inclination as to some of the magic values used in the various
41 #define CACHELINE_BYTES 64
43 static inline int ring_space(struct intel_ring_buffer *ring)
45 int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
51 static bool intel_ring_stopped(struct intel_ring_buffer *ring)
53 struct drm_i915_private *dev_priv = ring->dev->dev_private;
54 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
57 void __intel_ring_advance(struct intel_ring_buffer *ring)
59 ring->tail &= ring->size - 1;
60 if (intel_ring_stopped(ring))
62 ring->write_tail(ring, ring->tail);
66 gen2_render_ring_flush(struct intel_ring_buffer *ring,
67 u32 invalidate_domains,
74 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
75 cmd |= MI_NO_WRITE_FLUSH;
77 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
80 ret = intel_ring_begin(ring, 2);
84 intel_ring_emit(ring, cmd);
85 intel_ring_emit(ring, MI_NOOP);
86 intel_ring_advance(ring);
92 gen4_render_ring_flush(struct intel_ring_buffer *ring,
93 u32 invalidate_domains,
96 struct drm_device *dev = ring->dev;
103 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
104 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
105 * also flushed at 2d versus 3d pipeline switches.
109 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
110 * MI_READ_FLUSH is set, and is always flushed on 965.
112 * I915_GEM_DOMAIN_COMMAND may not exist?
114 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
115 * invalidated when MI_EXE_FLUSH is set.
117 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
118 * invalidated with every MI_FLUSH.
122 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
123 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
124 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
125 * are flushed at any MI_FLUSH.
128 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
129 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
130 cmd &= ~MI_NO_WRITE_FLUSH;
131 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
134 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
135 (IS_G4X(dev) || IS_GEN5(dev)))
136 cmd |= MI_INVALIDATE_ISP;
138 ret = intel_ring_begin(ring, 2);
142 intel_ring_emit(ring, cmd);
143 intel_ring_emit(ring, MI_NOOP);
144 intel_ring_advance(ring);
150 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
151 * implementing two workarounds on gen6. From section 1.4.7.1
152 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
154 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
155 * produced by non-pipelined state commands), software needs to first
156 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
159 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
160 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
162 * And the workaround for these two requires this workaround first:
164 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
165 * BEFORE the pipe-control with a post-sync op and no write-cache
168 * And this last workaround is tricky because of the requirements on
169 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
172 * "1 of the following must also be set:
173 * - Render Target Cache Flush Enable ([12] of DW1)
174 * - Depth Cache Flush Enable ([0] of DW1)
175 * - Stall at Pixel Scoreboard ([1] of DW1)
176 * - Depth Stall ([13] of DW1)
177 * - Post-Sync Operation ([13] of DW1)
178 * - Notify Enable ([8] of DW1)"
180 * The cache flushes require the workaround flush that triggered this
181 * one, so we can't use it. Depth stall would trigger the same.
182 * Post-sync nonzero is what triggered this second workaround, so we
183 * can't use that one either. Notify enable is IRQs, which aren't
184 * really our business. That leaves only stall at scoreboard.
187 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
189 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
193 ret = intel_ring_begin(ring, 6);
197 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
198 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
199 PIPE_CONTROL_STALL_AT_SCOREBOARD);
200 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
201 intel_ring_emit(ring, 0); /* low dword */
202 intel_ring_emit(ring, 0); /* high dword */
203 intel_ring_emit(ring, MI_NOOP);
204 intel_ring_advance(ring);
206 ret = intel_ring_begin(ring, 6);
210 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
211 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
212 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
213 intel_ring_emit(ring, 0);
214 intel_ring_emit(ring, 0);
215 intel_ring_emit(ring, MI_NOOP);
216 intel_ring_advance(ring);
222 gen6_render_ring_flush(struct intel_ring_buffer *ring,
223 u32 invalidate_domains, u32 flush_domains)
226 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
229 /* Force SNB workarounds for PIPE_CONTROL flushes */
230 ret = intel_emit_post_sync_nonzero_flush(ring);
234 /* Just flush everything. Experiments have shown that reducing the
235 * number of bits based on the write domains has little performance
239 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
240 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
242 * Ensure that any following seqno writes only happen
243 * when the render cache is indeed flushed.
245 flags |= PIPE_CONTROL_CS_STALL;
247 if (invalidate_domains) {
248 flags |= PIPE_CONTROL_TLB_INVALIDATE;
249 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
250 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
251 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
252 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
253 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
255 * TLB invalidate requires a post-sync write.
257 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
260 ret = intel_ring_begin(ring, 4);
264 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
265 intel_ring_emit(ring, flags);
266 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
267 intel_ring_emit(ring, 0);
268 intel_ring_advance(ring);
274 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
278 ret = intel_ring_begin(ring, 4);
282 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
283 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
284 PIPE_CONTROL_STALL_AT_SCOREBOARD);
285 intel_ring_emit(ring, 0);
286 intel_ring_emit(ring, 0);
287 intel_ring_advance(ring);
292 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
296 if (!ring->fbc_dirty)
299 ret = intel_ring_begin(ring, 6);
302 /* WaFbcNukeOn3DBlt:ivb/hsw */
303 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
304 intel_ring_emit(ring, MSG_FBC_REND_STATE);
305 intel_ring_emit(ring, value);
306 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
307 intel_ring_emit(ring, MSG_FBC_REND_STATE);
308 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
309 intel_ring_advance(ring);
311 ring->fbc_dirty = false;
316 gen7_render_ring_flush(struct intel_ring_buffer *ring,
317 u32 invalidate_domains, u32 flush_domains)
320 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
324 * Ensure that any following seqno writes only happen when the render
325 * cache is indeed flushed.
327 * Workaround: 4th PIPE_CONTROL command (except the ones with only
328 * read-cache invalidate bits set) must have the CS_STALL bit set. We
329 * don't try to be clever and just set it unconditionally.
331 flags |= PIPE_CONTROL_CS_STALL;
333 /* Just flush everything. Experiments have shown that reducing the
334 * number of bits based on the write domains has little performance
338 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
339 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
341 if (invalidate_domains) {
342 flags |= PIPE_CONTROL_TLB_INVALIDATE;
343 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
344 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
345 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
346 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
347 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
349 * TLB invalidate requires a post-sync write.
351 flags |= PIPE_CONTROL_QW_WRITE;
352 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
354 /* Workaround: we must issue a pipe_control with CS-stall bit
355 * set before a pipe_control command that has the state cache
356 * invalidate bit set. */
357 gen7_render_ring_cs_stall_wa(ring);
360 ret = intel_ring_begin(ring, 4);
364 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
365 intel_ring_emit(ring, flags);
366 intel_ring_emit(ring, scratch_addr);
367 intel_ring_emit(ring, 0);
368 intel_ring_advance(ring);
370 if (!invalidate_domains && flush_domains)
371 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
377 gen8_render_ring_flush(struct intel_ring_buffer *ring,
378 u32 invalidate_domains, u32 flush_domains)
381 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
384 flags |= PIPE_CONTROL_CS_STALL;
387 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
388 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
390 if (invalidate_domains) {
391 flags |= PIPE_CONTROL_TLB_INVALIDATE;
392 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
393 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
394 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
395 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
396 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
397 flags |= PIPE_CONTROL_QW_WRITE;
398 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
401 ret = intel_ring_begin(ring, 6);
405 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
406 intel_ring_emit(ring, flags);
407 intel_ring_emit(ring, scratch_addr);
408 intel_ring_emit(ring, 0);
409 intel_ring_emit(ring, 0);
410 intel_ring_emit(ring, 0);
411 intel_ring_advance(ring);
417 static void ring_write_tail(struct intel_ring_buffer *ring,
420 struct drm_i915_private *dev_priv = ring->dev->dev_private;
421 I915_WRITE_TAIL(ring, value);
424 u64 intel_ring_get_active_head(struct intel_ring_buffer *ring)
426 struct drm_i915_private *dev_priv = ring->dev->dev_private;
429 if (INTEL_INFO(ring->dev)->gen >= 8)
430 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
431 RING_ACTHD_UDW(ring->mmio_base));
432 else if (INTEL_INFO(ring->dev)->gen >= 4)
433 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
435 acthd = I915_READ(ACTHD);
440 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
442 struct drm_i915_private *dev_priv = ring->dev->dev_private;
445 addr = dev_priv->status_page_dmah->busaddr;
446 if (INTEL_INFO(ring->dev)->gen >= 4)
447 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
448 I915_WRITE(HWS_PGA, addr);
451 static bool stop_ring(struct intel_ring_buffer *ring)
453 struct drm_i915_private *dev_priv = to_i915(ring->dev);
455 if (!IS_GEN2(ring->dev)) {
456 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
457 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
458 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
463 I915_WRITE_CTL(ring, 0);
464 I915_WRITE_HEAD(ring, 0);
465 ring->write_tail(ring, 0);
467 if (!IS_GEN2(ring->dev)) {
468 (void)I915_READ_CTL(ring);
469 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
472 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
475 static int init_ring_common(struct intel_ring_buffer *ring)
477 struct drm_device *dev = ring->dev;
478 struct drm_i915_private *dev_priv = dev->dev_private;
479 struct drm_i915_gem_object *obj = ring->obj;
482 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
484 if (!stop_ring(ring)) {
485 /* G45 ring initialization often fails to reset head to zero */
486 DRM_DEBUG_KMS("%s head not reset to zero "
487 "ctl %08x head %08x tail %08x start %08x\n",
490 I915_READ_HEAD(ring),
491 I915_READ_TAIL(ring),
492 I915_READ_START(ring));
494 if (!stop_ring(ring)) {
495 DRM_ERROR("failed to set %s head to zero "
496 "ctl %08x head %08x tail %08x start %08x\n",
499 I915_READ_HEAD(ring),
500 I915_READ_TAIL(ring),
501 I915_READ_START(ring));
507 if (I915_NEED_GFX_HWS(dev))
508 intel_ring_setup_status_page(ring);
510 ring_setup_phys_status_page(ring);
512 /* Initialize the ring. This must happen _after_ we've cleared the ring
513 * registers with the above sequence (the readback of the HEAD registers
514 * also enforces ordering), otherwise the hw might lose the new ring
515 * register values. */
516 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
518 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
521 /* If the head is still not zero, the ring is dead */
522 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
523 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
524 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
525 DRM_ERROR("%s initialization failed "
526 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
528 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
529 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
530 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
535 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
536 i915_kernel_lost_context(ring->dev);
538 ring->head = I915_READ_HEAD(ring);
539 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
540 ring->space = ring_space(ring);
541 ring->last_retired_head = -1;
544 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
547 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
553 init_pipe_control(struct intel_ring_buffer *ring)
557 if (ring->scratch.obj)
560 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
561 if (ring->scratch.obj == NULL) {
562 DRM_ERROR("Failed to allocate seqno page\n");
567 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
571 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
575 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
576 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
577 if (ring->scratch.cpu_page == NULL) {
582 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
583 ring->name, ring->scratch.gtt_offset);
587 i915_gem_object_ggtt_unpin(ring->scratch.obj);
589 drm_gem_object_unreference(&ring->scratch.obj->base);
594 static int init_render_ring(struct intel_ring_buffer *ring)
596 struct drm_device *dev = ring->dev;
597 struct drm_i915_private *dev_priv = dev->dev_private;
598 int ret = init_ring_common(ring);
600 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
601 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
602 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
604 /* We need to disable the AsyncFlip performance optimisations in order
605 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
606 * programmed to '1' on all products.
608 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
610 if (INTEL_INFO(dev)->gen >= 6)
611 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
613 /* Required for the hardware to program scanline values for waiting */
614 /* WaEnableFlushTlbInvalidationMode:snb */
615 if (INTEL_INFO(dev)->gen == 6)
617 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
619 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
621 I915_WRITE(GFX_MODE_GEN7,
622 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
623 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
625 if (INTEL_INFO(dev)->gen >= 5) {
626 ret = init_pipe_control(ring);
632 /* From the Sandybridge PRM, volume 1 part 3, page 24:
633 * "If this bit is set, STCunit will have LRA as replacement
634 * policy. [...] This bit must be reset. LRA replacement
635 * policy is not supported."
637 I915_WRITE(CACHE_MODE_0,
638 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
641 if (INTEL_INFO(dev)->gen >= 6)
642 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
645 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
650 static void render_ring_cleanup(struct intel_ring_buffer *ring)
652 struct drm_device *dev = ring->dev;
654 if (ring->scratch.obj == NULL)
657 if (INTEL_INFO(dev)->gen >= 5) {
658 kunmap(sg_page(ring->scratch.obj->pages->sgl));
659 i915_gem_object_ggtt_unpin(ring->scratch.obj);
662 drm_gem_object_unreference(&ring->scratch.obj->base);
663 ring->scratch.obj = NULL;
667 update_mboxes(struct intel_ring_buffer *ring,
670 /* NB: In order to be able to do semaphore MBOX updates for varying number
671 * of rings, it's easiest if we round up each individual update to a
672 * multiple of 2 (since ring updates must always be a multiple of 2)
673 * even though the actual update only requires 3 dwords.
675 #define MBOX_UPDATE_DWORDS 4
676 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
677 intel_ring_emit(ring, mmio_offset);
678 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
679 intel_ring_emit(ring, MI_NOOP);
683 * gen6_add_request - Update the semaphore mailbox registers
685 * @ring - ring that is adding a request
686 * @seqno - return seqno stuck into the ring
688 * Update the mailbox registers in the *other* rings with the current seqno.
689 * This acts like a signal in the canonical semaphore.
692 gen6_add_request(struct intel_ring_buffer *ring)
694 struct drm_device *dev = ring->dev;
695 struct drm_i915_private *dev_priv = dev->dev_private;
696 struct intel_ring_buffer *useless;
697 int i, ret, num_dwords = 4;
699 if (i915_semaphore_is_enabled(dev))
700 num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
701 #undef MBOX_UPDATE_DWORDS
703 ret = intel_ring_begin(ring, num_dwords);
707 if (i915_semaphore_is_enabled(dev)) {
708 for_each_ring(useless, dev_priv, i) {
709 u32 mbox_reg = ring->signal_mbox[i];
710 if (mbox_reg != GEN6_NOSYNC)
711 update_mboxes(ring, mbox_reg);
715 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
716 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
717 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
718 intel_ring_emit(ring, MI_USER_INTERRUPT);
719 __intel_ring_advance(ring);
724 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
727 struct drm_i915_private *dev_priv = dev->dev_private;
728 return dev_priv->last_seqno < seqno;
732 * intel_ring_sync - sync the waiter to the signaller on seqno
734 * @waiter - ring that is waiting
735 * @signaller - ring which has, or will signal
736 * @seqno - seqno which the waiter will block on
739 gen6_ring_sync(struct intel_ring_buffer *waiter,
740 struct intel_ring_buffer *signaller,
744 u32 dw1 = MI_SEMAPHORE_MBOX |
745 MI_SEMAPHORE_COMPARE |
746 MI_SEMAPHORE_REGISTER;
748 /* Throughout all of the GEM code, seqno passed implies our current
749 * seqno is >= the last seqno executed. However for hardware the
750 * comparison is strictly greater than.
754 WARN_ON(signaller->semaphore_register[waiter->id] ==
755 MI_SEMAPHORE_SYNC_INVALID);
757 ret = intel_ring_begin(waiter, 4);
761 /* If seqno wrap happened, omit the wait with no-ops */
762 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
763 intel_ring_emit(waiter,
765 signaller->semaphore_register[waiter->id]);
766 intel_ring_emit(waiter, seqno);
767 intel_ring_emit(waiter, 0);
768 intel_ring_emit(waiter, MI_NOOP);
770 intel_ring_emit(waiter, MI_NOOP);
771 intel_ring_emit(waiter, MI_NOOP);
772 intel_ring_emit(waiter, MI_NOOP);
773 intel_ring_emit(waiter, MI_NOOP);
775 intel_ring_advance(waiter);
780 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
782 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
783 PIPE_CONTROL_DEPTH_STALL); \
784 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
785 intel_ring_emit(ring__, 0); \
786 intel_ring_emit(ring__, 0); \
790 pc_render_add_request(struct intel_ring_buffer *ring)
792 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
795 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
796 * incoherent with writes to memory, i.e. completely fubar,
797 * so we need to use PIPE_NOTIFY instead.
799 * However, we also need to workaround the qword write
800 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
801 * memory before requesting an interrupt.
803 ret = intel_ring_begin(ring, 32);
807 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
808 PIPE_CONTROL_WRITE_FLUSH |
809 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
810 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
811 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
812 intel_ring_emit(ring, 0);
813 PIPE_CONTROL_FLUSH(ring, scratch_addr);
814 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
815 PIPE_CONTROL_FLUSH(ring, scratch_addr);
816 scratch_addr += 2 * CACHELINE_BYTES;
817 PIPE_CONTROL_FLUSH(ring, scratch_addr);
818 scratch_addr += 2 * CACHELINE_BYTES;
819 PIPE_CONTROL_FLUSH(ring, scratch_addr);
820 scratch_addr += 2 * CACHELINE_BYTES;
821 PIPE_CONTROL_FLUSH(ring, scratch_addr);
822 scratch_addr += 2 * CACHELINE_BYTES;
823 PIPE_CONTROL_FLUSH(ring, scratch_addr);
825 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
826 PIPE_CONTROL_WRITE_FLUSH |
827 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
828 PIPE_CONTROL_NOTIFY);
829 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
830 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
831 intel_ring_emit(ring, 0);
832 __intel_ring_advance(ring);
838 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
840 /* Workaround to force correct ordering between irq and seqno writes on
841 * ivb (and maybe also on snb) by reading from a CS register (like
842 * ACTHD) before reading the status page. */
843 if (!lazy_coherency) {
844 struct drm_i915_private *dev_priv = ring->dev->dev_private;
845 POSTING_READ(RING_ACTHD(ring->mmio_base));
848 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
852 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
854 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
858 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
860 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
864 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
866 return ring->scratch.cpu_page[0];
870 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
872 ring->scratch.cpu_page[0] = seqno;
876 gen5_ring_get_irq(struct intel_ring_buffer *ring)
878 struct drm_device *dev = ring->dev;
879 struct drm_i915_private *dev_priv = dev->dev_private;
882 if (!dev->irq_enabled)
885 spin_lock_irqsave(&dev_priv->irq_lock, flags);
886 if (ring->irq_refcount++ == 0)
887 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
888 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
894 gen5_ring_put_irq(struct intel_ring_buffer *ring)
896 struct drm_device *dev = ring->dev;
897 struct drm_i915_private *dev_priv = dev->dev_private;
900 spin_lock_irqsave(&dev_priv->irq_lock, flags);
901 if (--ring->irq_refcount == 0)
902 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
903 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
907 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
909 struct drm_device *dev = ring->dev;
910 struct drm_i915_private *dev_priv = dev->dev_private;
913 if (!dev->irq_enabled)
916 spin_lock_irqsave(&dev_priv->irq_lock, flags);
917 if (ring->irq_refcount++ == 0) {
918 dev_priv->irq_mask &= ~ring->irq_enable_mask;
919 I915_WRITE(IMR, dev_priv->irq_mask);
922 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
928 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
930 struct drm_device *dev = ring->dev;
931 struct drm_i915_private *dev_priv = dev->dev_private;
934 spin_lock_irqsave(&dev_priv->irq_lock, flags);
935 if (--ring->irq_refcount == 0) {
936 dev_priv->irq_mask |= ring->irq_enable_mask;
937 I915_WRITE(IMR, dev_priv->irq_mask);
940 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
944 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
946 struct drm_device *dev = ring->dev;
947 struct drm_i915_private *dev_priv = dev->dev_private;
950 if (!dev->irq_enabled)
953 spin_lock_irqsave(&dev_priv->irq_lock, flags);
954 if (ring->irq_refcount++ == 0) {
955 dev_priv->irq_mask &= ~ring->irq_enable_mask;
956 I915_WRITE16(IMR, dev_priv->irq_mask);
959 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
965 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
967 struct drm_device *dev = ring->dev;
968 struct drm_i915_private *dev_priv = dev->dev_private;
971 spin_lock_irqsave(&dev_priv->irq_lock, flags);
972 if (--ring->irq_refcount == 0) {
973 dev_priv->irq_mask |= ring->irq_enable_mask;
974 I915_WRITE16(IMR, dev_priv->irq_mask);
977 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
980 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
982 struct drm_device *dev = ring->dev;
983 struct drm_i915_private *dev_priv = ring->dev->dev_private;
986 /* The ring status page addresses are no longer next to the rest of
987 * the ring registers as of gen7.
992 mmio = RENDER_HWS_PGA_GEN7;
995 mmio = BLT_HWS_PGA_GEN7;
998 mmio = BSD_HWS_PGA_GEN7;
1001 mmio = VEBOX_HWS_PGA_GEN7;
1004 } else if (IS_GEN6(ring->dev)) {
1005 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1007 /* XXX: gen8 returns to sanity */
1008 mmio = RING_HWS_PGA(ring->mmio_base);
1011 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1015 * Flush the TLB for this page
1017 * FIXME: These two bits have disappeared on gen8, so a question
1018 * arises: do we still need this and if so how should we go about
1019 * invalidating the TLB?
1021 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1022 u32 reg = RING_INSTPM(ring->mmio_base);
1024 /* ring should be idle before issuing a sync flush*/
1025 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1028 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1029 INSTPM_SYNC_FLUSH));
1030 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1032 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1038 bsd_ring_flush(struct intel_ring_buffer *ring,
1039 u32 invalidate_domains,
1044 ret = intel_ring_begin(ring, 2);
1048 intel_ring_emit(ring, MI_FLUSH);
1049 intel_ring_emit(ring, MI_NOOP);
1050 intel_ring_advance(ring);
1055 i9xx_add_request(struct intel_ring_buffer *ring)
1059 ret = intel_ring_begin(ring, 4);
1063 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1064 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1065 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1066 intel_ring_emit(ring, MI_USER_INTERRUPT);
1067 __intel_ring_advance(ring);
1073 gen6_ring_get_irq(struct intel_ring_buffer *ring)
1075 struct drm_device *dev = ring->dev;
1076 struct drm_i915_private *dev_priv = dev->dev_private;
1077 unsigned long flags;
1079 if (!dev->irq_enabled)
1082 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1083 if (ring->irq_refcount++ == 0) {
1084 if (HAS_L3_DPF(dev) && ring->id == RCS)
1085 I915_WRITE_IMR(ring,
1086 ~(ring->irq_enable_mask |
1087 GT_PARITY_ERROR(dev)));
1089 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1090 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1092 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1098 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1100 struct drm_device *dev = ring->dev;
1101 struct drm_i915_private *dev_priv = dev->dev_private;
1102 unsigned long flags;
1104 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1105 if (--ring->irq_refcount == 0) {
1106 if (HAS_L3_DPF(dev) && ring->id == RCS)
1107 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1109 I915_WRITE_IMR(ring, ~0);
1110 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1112 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1116 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1118 struct drm_device *dev = ring->dev;
1119 struct drm_i915_private *dev_priv = dev->dev_private;
1120 unsigned long flags;
1122 if (!dev->irq_enabled)
1125 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1126 if (ring->irq_refcount++ == 0) {
1127 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1128 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1130 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1136 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1138 struct drm_device *dev = ring->dev;
1139 struct drm_i915_private *dev_priv = dev->dev_private;
1140 unsigned long flags;
1142 if (!dev->irq_enabled)
1145 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1146 if (--ring->irq_refcount == 0) {
1147 I915_WRITE_IMR(ring, ~0);
1148 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1150 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1154 gen8_ring_get_irq(struct intel_ring_buffer *ring)
1156 struct drm_device *dev = ring->dev;
1157 struct drm_i915_private *dev_priv = dev->dev_private;
1158 unsigned long flags;
1160 if (!dev->irq_enabled)
1163 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1164 if (ring->irq_refcount++ == 0) {
1165 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1166 I915_WRITE_IMR(ring,
1167 ~(ring->irq_enable_mask |
1168 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1170 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1172 POSTING_READ(RING_IMR(ring->mmio_base));
1174 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1180 gen8_ring_put_irq(struct intel_ring_buffer *ring)
1182 struct drm_device *dev = ring->dev;
1183 struct drm_i915_private *dev_priv = dev->dev_private;
1184 unsigned long flags;
1186 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1187 if (--ring->irq_refcount == 0) {
1188 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1189 I915_WRITE_IMR(ring,
1190 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1192 I915_WRITE_IMR(ring, ~0);
1194 POSTING_READ(RING_IMR(ring->mmio_base));
1196 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1200 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1201 u32 offset, u32 length,
1206 ret = intel_ring_begin(ring, 2);
1210 intel_ring_emit(ring,
1211 MI_BATCH_BUFFER_START |
1213 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1214 intel_ring_emit(ring, offset);
1215 intel_ring_advance(ring);
1220 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1221 #define I830_BATCH_LIMIT (256*1024)
1223 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1224 u32 offset, u32 len,
1229 if (flags & I915_DISPATCH_PINNED) {
1230 ret = intel_ring_begin(ring, 4);
1234 intel_ring_emit(ring, MI_BATCH_BUFFER);
1235 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1236 intel_ring_emit(ring, offset + len - 8);
1237 intel_ring_emit(ring, MI_NOOP);
1238 intel_ring_advance(ring);
1240 u32 cs_offset = ring->scratch.gtt_offset;
1242 if (len > I830_BATCH_LIMIT)
1245 ret = intel_ring_begin(ring, 9+3);
1248 /* Blit the batch (which has now all relocs applied) to the stable batch
1249 * scratch bo area (so that the CS never stumbles over its tlb
1250 * invalidation bug) ... */
1251 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1252 XY_SRC_COPY_BLT_WRITE_ALPHA |
1253 XY_SRC_COPY_BLT_WRITE_RGB);
1254 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1255 intel_ring_emit(ring, 0);
1256 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1257 intel_ring_emit(ring, cs_offset);
1258 intel_ring_emit(ring, 0);
1259 intel_ring_emit(ring, 4096);
1260 intel_ring_emit(ring, offset);
1261 intel_ring_emit(ring, MI_FLUSH);
1263 /* ... and execute it. */
1264 intel_ring_emit(ring, MI_BATCH_BUFFER);
1265 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1266 intel_ring_emit(ring, cs_offset + len - 8);
1267 intel_ring_advance(ring);
1274 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1275 u32 offset, u32 len,
1280 ret = intel_ring_begin(ring, 2);
1284 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1285 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1286 intel_ring_advance(ring);
1291 static void cleanup_status_page(struct intel_ring_buffer *ring)
1293 struct drm_i915_gem_object *obj;
1295 obj = ring->status_page.obj;
1299 kunmap(sg_page(obj->pages->sgl));
1300 i915_gem_object_ggtt_unpin(obj);
1301 drm_gem_object_unreference(&obj->base);
1302 ring->status_page.obj = NULL;
1305 static int init_status_page(struct intel_ring_buffer *ring)
1307 struct drm_i915_gem_object *obj;
1309 if ((obj = ring->status_page.obj) == NULL) {
1312 obj = i915_gem_alloc_object(ring->dev, 4096);
1314 DRM_ERROR("Failed to allocate status page\n");
1318 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1322 ret = i915_gem_obj_ggtt_pin(obj, 4096, 0);
1325 drm_gem_object_unreference(&obj->base);
1329 ring->status_page.obj = obj;
1332 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1333 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1334 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1336 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1337 ring->name, ring->status_page.gfx_addr);
1342 static int init_phys_status_page(struct intel_ring_buffer *ring)
1344 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1346 if (!dev_priv->status_page_dmah) {
1347 dev_priv->status_page_dmah =
1348 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1349 if (!dev_priv->status_page_dmah)
1353 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1354 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1359 static int allocate_ring_buffer(struct intel_ring_buffer *ring)
1361 struct drm_device *dev = ring->dev;
1362 struct drm_i915_private *dev_priv = to_i915(dev);
1363 struct drm_i915_gem_object *obj;
1371 obj = i915_gem_object_create_stolen(dev, ring->size);
1373 obj = i915_gem_alloc_object(dev, ring->size);
1377 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1381 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1385 ring->virtual_start =
1386 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1388 if (ring->virtual_start == NULL) {
1397 i915_gem_object_ggtt_unpin(obj);
1399 drm_gem_object_unreference(&obj->base);
1403 static int intel_init_ring_buffer(struct drm_device *dev,
1404 struct intel_ring_buffer *ring)
1409 INIT_LIST_HEAD(&ring->active_list);
1410 INIT_LIST_HEAD(&ring->request_list);
1411 ring->size = 32 * PAGE_SIZE;
1412 memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1414 init_waitqueue_head(&ring->irq_queue);
1416 if (I915_NEED_GFX_HWS(dev)) {
1417 ret = init_status_page(ring);
1421 BUG_ON(ring->id != RCS);
1422 ret = init_phys_status_page(ring);
1427 ret = allocate_ring_buffer(ring);
1429 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
1433 /* Workaround an erratum on the i830 which causes a hang if
1434 * the TAIL pointer points to within the last 2 cachelines
1437 ring->effective_size = ring->size;
1438 if (IS_I830(dev) || IS_845G(dev))
1439 ring->effective_size -= 2 * CACHELINE_BYTES;
1441 i915_cmd_parser_init_ring(ring);
1443 return ring->init(ring);
1446 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1448 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1450 if (ring->obj == NULL)
1453 intel_stop_ring_buffer(ring);
1454 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1456 iounmap(ring->virtual_start);
1458 i915_gem_object_ggtt_unpin(ring->obj);
1459 drm_gem_object_unreference(&ring->obj->base);
1461 ring->preallocated_lazy_request = NULL;
1462 ring->outstanding_lazy_seqno = 0;
1465 ring->cleanup(ring);
1467 cleanup_status_page(ring);
1470 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1472 struct drm_i915_gem_request *request;
1473 u32 seqno = 0, tail;
1476 if (ring->last_retired_head != -1) {
1477 ring->head = ring->last_retired_head;
1478 ring->last_retired_head = -1;
1480 ring->space = ring_space(ring);
1481 if (ring->space >= n)
1485 list_for_each_entry(request, &ring->request_list, list) {
1488 if (request->tail == -1)
1491 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1493 space += ring->size;
1495 seqno = request->seqno;
1496 tail = request->tail;
1500 /* Consume this request in case we need more space than
1501 * is available and so need to prevent a race between
1502 * updating last_retired_head and direct reads of
1503 * I915_RING_HEAD. It also provides a nice sanity check.
1511 ret = i915_wait_seqno(ring, seqno);
1516 ring->space = ring_space(ring);
1517 if (WARN_ON(ring->space < n))
1523 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1525 struct drm_device *dev = ring->dev;
1526 struct drm_i915_private *dev_priv = dev->dev_private;
1530 ret = intel_ring_wait_request(ring, n);
1534 /* force the tail write in case we have been skipping them */
1535 __intel_ring_advance(ring);
1537 trace_i915_ring_wait_begin(ring);
1538 /* With GEM the hangcheck timer should kick us out of the loop,
1539 * leaving it early runs the risk of corrupting GEM state (due
1540 * to running on almost untested codepaths). But on resume
1541 * timers don't work yet, so prevent a complete hang in that
1542 * case by choosing an insanely large timeout. */
1543 end = jiffies + 60 * HZ;
1546 ring->head = I915_READ_HEAD(ring);
1547 ring->space = ring_space(ring);
1548 if (ring->space >= n) {
1549 trace_i915_ring_wait_end(ring);
1553 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1554 dev->primary->master) {
1555 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1556 if (master_priv->sarea_priv)
1557 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1562 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1563 dev_priv->mm.interruptible);
1566 } while (!time_after(jiffies, end));
1567 trace_i915_ring_wait_end(ring);
1571 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1573 uint32_t __iomem *virt;
1574 int rem = ring->size - ring->tail;
1576 if (ring->space < rem) {
1577 int ret = ring_wait_for_space(ring, rem);
1582 virt = ring->virtual_start + ring->tail;
1585 iowrite32(MI_NOOP, virt++);
1588 ring->space = ring_space(ring);
1593 int intel_ring_idle(struct intel_ring_buffer *ring)
1598 /* We need to add any requests required to flush the objects and ring */
1599 if (ring->outstanding_lazy_seqno) {
1600 ret = i915_add_request(ring, NULL);
1605 /* Wait upon the last request to be completed */
1606 if (list_empty(&ring->request_list))
1609 seqno = list_entry(ring->request_list.prev,
1610 struct drm_i915_gem_request,
1613 return i915_wait_seqno(ring, seqno);
1617 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1619 if (ring->outstanding_lazy_seqno)
1622 if (ring->preallocated_lazy_request == NULL) {
1623 struct drm_i915_gem_request *request;
1625 request = kmalloc(sizeof(*request), GFP_KERNEL);
1626 if (request == NULL)
1629 ring->preallocated_lazy_request = request;
1632 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1635 static int __intel_ring_prepare(struct intel_ring_buffer *ring,
1640 if (unlikely(ring->tail + bytes > ring->effective_size)) {
1641 ret = intel_wrap_ring_buffer(ring);
1646 if (unlikely(ring->space < bytes)) {
1647 ret = ring_wait_for_space(ring, bytes);
1655 int intel_ring_begin(struct intel_ring_buffer *ring,
1658 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1661 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1662 dev_priv->mm.interruptible);
1666 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1670 /* Preallocate the olr before touching the ring */
1671 ret = intel_ring_alloc_seqno(ring);
1675 ring->space -= num_dwords * sizeof(uint32_t);
1679 /* Align the ring tail to a cacheline boundary */
1680 int intel_ring_cacheline_align(struct intel_ring_buffer *ring)
1682 int num_dwords = (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
1685 if (num_dwords == 0)
1688 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
1689 ret = intel_ring_begin(ring, num_dwords);
1693 while (num_dwords--)
1694 intel_ring_emit(ring, MI_NOOP);
1696 intel_ring_advance(ring);
1701 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1703 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1705 BUG_ON(ring->outstanding_lazy_seqno);
1707 if (INTEL_INFO(ring->dev)->gen >= 6) {
1708 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1709 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1710 if (HAS_VEBOX(ring->dev))
1711 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1714 ring->set_seqno(ring, seqno);
1715 ring->hangcheck.seqno = seqno;
1718 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1721 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1723 /* Every tail move must follow the sequence below */
1725 /* Disable notification that the ring is IDLE. The GT
1726 * will then assume that it is busy and bring it out of rc6.
1728 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1729 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1731 /* Clear the context id. Here be magic! */
1732 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1734 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1735 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1736 GEN6_BSD_SLEEP_INDICATOR) == 0,
1738 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1740 /* Now that the ring is fully powered up, update the tail */
1741 I915_WRITE_TAIL(ring, value);
1742 POSTING_READ(RING_TAIL(ring->mmio_base));
1744 /* Let the ring send IDLE messages to the GT again,
1745 * and so let it sleep to conserve power when idle.
1747 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1748 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1751 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1752 u32 invalidate, u32 flush)
1757 ret = intel_ring_begin(ring, 4);
1762 if (INTEL_INFO(ring->dev)->gen >= 8)
1765 * Bspec vol 1c.5 - video engine command streamer:
1766 * "If ENABLED, all TLBs will be invalidated once the flush
1767 * operation is complete. This bit is only valid when the
1768 * Post-Sync Operation field is a value of 1h or 3h."
1770 if (invalidate & I915_GEM_GPU_DOMAINS)
1771 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1772 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1773 intel_ring_emit(ring, cmd);
1774 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1775 if (INTEL_INFO(ring->dev)->gen >= 8) {
1776 intel_ring_emit(ring, 0); /* upper addr */
1777 intel_ring_emit(ring, 0); /* value */
1779 intel_ring_emit(ring, 0);
1780 intel_ring_emit(ring, MI_NOOP);
1782 intel_ring_advance(ring);
1787 gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1788 u32 offset, u32 len,
1791 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1792 bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1793 !(flags & I915_DISPATCH_SECURE);
1796 ret = intel_ring_begin(ring, 4);
1800 /* FIXME(BDW): Address space and security selectors. */
1801 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1802 intel_ring_emit(ring, offset);
1803 intel_ring_emit(ring, 0);
1804 intel_ring_emit(ring, MI_NOOP);
1805 intel_ring_advance(ring);
1811 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1812 u32 offset, u32 len,
1817 ret = intel_ring_begin(ring, 2);
1821 intel_ring_emit(ring,
1822 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1823 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1824 /* bit0-7 is the length on GEN6+ */
1825 intel_ring_emit(ring, offset);
1826 intel_ring_advance(ring);
1832 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1833 u32 offset, u32 len,
1838 ret = intel_ring_begin(ring, 2);
1842 intel_ring_emit(ring,
1843 MI_BATCH_BUFFER_START |
1844 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1845 /* bit0-7 is the length on GEN6+ */
1846 intel_ring_emit(ring, offset);
1847 intel_ring_advance(ring);
1852 /* Blitter support (SandyBridge+) */
1854 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1855 u32 invalidate, u32 flush)
1857 struct drm_device *dev = ring->dev;
1861 ret = intel_ring_begin(ring, 4);
1866 if (INTEL_INFO(ring->dev)->gen >= 8)
1869 * Bspec vol 1c.3 - blitter engine command streamer:
1870 * "If ENABLED, all TLBs will be invalidated once the flush
1871 * operation is complete. This bit is only valid when the
1872 * Post-Sync Operation field is a value of 1h or 3h."
1874 if (invalidate & I915_GEM_DOMAIN_RENDER)
1875 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1876 MI_FLUSH_DW_OP_STOREDW;
1877 intel_ring_emit(ring, cmd);
1878 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1879 if (INTEL_INFO(ring->dev)->gen >= 8) {
1880 intel_ring_emit(ring, 0); /* upper addr */
1881 intel_ring_emit(ring, 0); /* value */
1883 intel_ring_emit(ring, 0);
1884 intel_ring_emit(ring, MI_NOOP);
1886 intel_ring_advance(ring);
1888 if (IS_GEN7(dev) && !invalidate && flush)
1889 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1894 int intel_init_render_ring_buffer(struct drm_device *dev)
1896 struct drm_i915_private *dev_priv = dev->dev_private;
1897 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1899 ring->name = "render ring";
1901 ring->mmio_base = RENDER_RING_BASE;
1903 if (INTEL_INFO(dev)->gen >= 6) {
1904 ring->add_request = gen6_add_request;
1905 ring->flush = gen7_render_ring_flush;
1906 if (INTEL_INFO(dev)->gen == 6)
1907 ring->flush = gen6_render_ring_flush;
1908 if (INTEL_INFO(dev)->gen >= 8) {
1909 ring->flush = gen8_render_ring_flush;
1910 ring->irq_get = gen8_ring_get_irq;
1911 ring->irq_put = gen8_ring_put_irq;
1913 ring->irq_get = gen6_ring_get_irq;
1914 ring->irq_put = gen6_ring_put_irq;
1916 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1917 ring->get_seqno = gen6_ring_get_seqno;
1918 ring->set_seqno = ring_set_seqno;
1919 ring->sync_to = gen6_ring_sync;
1921 * The current semaphore is only applied on pre-gen8 platform.
1922 * And there is no VCS2 ring on the pre-gen8 platform. So the
1923 * semaphore between RCS and VCS2 is initialized as INVALID.
1924 * Gen8 will initialize the sema between VCS2 and RCS later.
1926 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1927 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1928 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1929 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1930 ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
1931 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1932 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1933 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1934 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1935 ring->signal_mbox[VCS2] = GEN6_NOSYNC;
1936 } else if (IS_GEN5(dev)) {
1937 ring->add_request = pc_render_add_request;
1938 ring->flush = gen4_render_ring_flush;
1939 ring->get_seqno = pc_render_get_seqno;
1940 ring->set_seqno = pc_render_set_seqno;
1941 ring->irq_get = gen5_ring_get_irq;
1942 ring->irq_put = gen5_ring_put_irq;
1943 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1944 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1946 ring->add_request = i9xx_add_request;
1947 if (INTEL_INFO(dev)->gen < 4)
1948 ring->flush = gen2_render_ring_flush;
1950 ring->flush = gen4_render_ring_flush;
1951 ring->get_seqno = ring_get_seqno;
1952 ring->set_seqno = ring_set_seqno;
1954 ring->irq_get = i8xx_ring_get_irq;
1955 ring->irq_put = i8xx_ring_put_irq;
1957 ring->irq_get = i9xx_ring_get_irq;
1958 ring->irq_put = i9xx_ring_put_irq;
1960 ring->irq_enable_mask = I915_USER_INTERRUPT;
1962 ring->write_tail = ring_write_tail;
1963 if (IS_HASWELL(dev))
1964 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1965 else if (IS_GEN8(dev))
1966 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
1967 else if (INTEL_INFO(dev)->gen >= 6)
1968 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1969 else if (INTEL_INFO(dev)->gen >= 4)
1970 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1971 else if (IS_I830(dev) || IS_845G(dev))
1972 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1974 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1975 ring->init = init_render_ring;
1976 ring->cleanup = render_ring_cleanup;
1978 /* Workaround batchbuffer to combat CS tlb bug. */
1979 if (HAS_BROKEN_CS_TLB(dev)) {
1980 struct drm_i915_gem_object *obj;
1983 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1985 DRM_ERROR("Failed to allocate batch bo\n");
1989 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
1991 drm_gem_object_unreference(&obj->base);
1992 DRM_ERROR("Failed to ping batch bo\n");
1996 ring->scratch.obj = obj;
1997 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2000 return intel_init_ring_buffer(dev, ring);
2003 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2005 struct drm_i915_private *dev_priv = dev->dev_private;
2006 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2009 ring->name = "render ring";
2011 ring->mmio_base = RENDER_RING_BASE;
2013 if (INTEL_INFO(dev)->gen >= 6) {
2014 /* non-kms not supported on gen6+ */
2018 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2019 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2020 * the special gen5 functions. */
2021 ring->add_request = i9xx_add_request;
2022 if (INTEL_INFO(dev)->gen < 4)
2023 ring->flush = gen2_render_ring_flush;
2025 ring->flush = gen4_render_ring_flush;
2026 ring->get_seqno = ring_get_seqno;
2027 ring->set_seqno = ring_set_seqno;
2029 ring->irq_get = i8xx_ring_get_irq;
2030 ring->irq_put = i8xx_ring_put_irq;
2032 ring->irq_get = i9xx_ring_get_irq;
2033 ring->irq_put = i9xx_ring_put_irq;
2035 ring->irq_enable_mask = I915_USER_INTERRUPT;
2036 ring->write_tail = ring_write_tail;
2037 if (INTEL_INFO(dev)->gen >= 4)
2038 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2039 else if (IS_I830(dev) || IS_845G(dev))
2040 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2042 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2043 ring->init = init_render_ring;
2044 ring->cleanup = render_ring_cleanup;
2047 INIT_LIST_HEAD(&ring->active_list);
2048 INIT_LIST_HEAD(&ring->request_list);
2051 ring->effective_size = ring->size;
2052 if (IS_I830(ring->dev) || IS_845G(ring->dev))
2053 ring->effective_size -= 2 * CACHELINE_BYTES;
2055 ring->virtual_start = ioremap_wc(start, size);
2056 if (ring->virtual_start == NULL) {
2057 DRM_ERROR("can not ioremap virtual address for"
2062 if (!I915_NEED_GFX_HWS(dev)) {
2063 ret = init_phys_status_page(ring);
2071 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2073 struct drm_i915_private *dev_priv = dev->dev_private;
2074 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
2076 ring->name = "bsd ring";
2079 ring->write_tail = ring_write_tail;
2080 if (INTEL_INFO(dev)->gen >= 6) {
2081 ring->mmio_base = GEN6_BSD_RING_BASE;
2082 /* gen6 bsd needs a special wa for tail updates */
2084 ring->write_tail = gen6_bsd_ring_write_tail;
2085 ring->flush = gen6_bsd_ring_flush;
2086 ring->add_request = gen6_add_request;
2087 ring->get_seqno = gen6_ring_get_seqno;
2088 ring->set_seqno = ring_set_seqno;
2089 if (INTEL_INFO(dev)->gen >= 8) {
2090 ring->irq_enable_mask =
2091 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2092 ring->irq_get = gen8_ring_get_irq;
2093 ring->irq_put = gen8_ring_put_irq;
2094 ring->dispatch_execbuffer =
2095 gen8_ring_dispatch_execbuffer;
2097 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2098 ring->irq_get = gen6_ring_get_irq;
2099 ring->irq_put = gen6_ring_put_irq;
2100 ring->dispatch_execbuffer =
2101 gen6_ring_dispatch_execbuffer;
2103 ring->sync_to = gen6_ring_sync;
2105 * The current semaphore is only applied on pre-gen8 platform.
2106 * And there is no VCS2 ring on the pre-gen8 platform. So the
2107 * semaphore between VCS and VCS2 is initialized as INVALID.
2108 * Gen8 will initialize the sema between VCS2 and VCS later.
2110 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
2111 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2112 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
2113 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
2114 ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2115 ring->signal_mbox[RCS] = GEN6_RVSYNC;
2116 ring->signal_mbox[VCS] = GEN6_NOSYNC;
2117 ring->signal_mbox[BCS] = GEN6_BVSYNC;
2118 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
2119 ring->signal_mbox[VCS2] = GEN6_NOSYNC;
2121 ring->mmio_base = BSD_RING_BASE;
2122 ring->flush = bsd_ring_flush;
2123 ring->add_request = i9xx_add_request;
2124 ring->get_seqno = ring_get_seqno;
2125 ring->set_seqno = ring_set_seqno;
2127 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2128 ring->irq_get = gen5_ring_get_irq;
2129 ring->irq_put = gen5_ring_put_irq;
2131 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2132 ring->irq_get = i9xx_ring_get_irq;
2133 ring->irq_put = i9xx_ring_put_irq;
2135 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2137 ring->init = init_ring_common;
2139 return intel_init_ring_buffer(dev, ring);
2143 * Initialize the second BSD ring for Broadwell GT3.
2144 * It is noted that this only exists on Broadwell GT3.
2146 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2148 struct drm_i915_private *dev_priv = dev->dev_private;
2149 struct intel_ring_buffer *ring = &dev_priv->ring[VCS2];
2151 if ((INTEL_INFO(dev)->gen != 8)) {
2152 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2156 ring->name = "bds2_ring";
2159 ring->write_tail = ring_write_tail;
2160 ring->mmio_base = GEN8_BSD2_RING_BASE;
2161 ring->flush = gen6_bsd_ring_flush;
2162 ring->add_request = gen6_add_request;
2163 ring->get_seqno = gen6_ring_get_seqno;
2164 ring->set_seqno = ring_set_seqno;
2165 ring->irq_enable_mask =
2166 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2167 ring->irq_get = gen8_ring_get_irq;
2168 ring->irq_put = gen8_ring_put_irq;
2169 ring->dispatch_execbuffer =
2170 gen8_ring_dispatch_execbuffer;
2171 ring->sync_to = gen6_ring_sync;
2173 * The current semaphore is only applied on the pre-gen8. And there
2174 * is no bsd2 ring on the pre-gen8. So now the semaphore_register
2175 * between VCS2 and other ring is initialized as invalid.
2176 * Gen8 will initialize the sema between VCS2 and other ring later.
2178 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2179 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2180 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2181 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2182 ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2183 ring->signal_mbox[RCS] = GEN6_NOSYNC;
2184 ring->signal_mbox[VCS] = GEN6_NOSYNC;
2185 ring->signal_mbox[BCS] = GEN6_NOSYNC;
2186 ring->signal_mbox[VECS] = GEN6_NOSYNC;
2187 ring->signal_mbox[VCS2] = GEN6_NOSYNC;
2189 ring->init = init_ring_common;
2191 return intel_init_ring_buffer(dev, ring);
2194 int intel_init_blt_ring_buffer(struct drm_device *dev)
2196 struct drm_i915_private *dev_priv = dev->dev_private;
2197 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
2199 ring->name = "blitter ring";
2202 ring->mmio_base = BLT_RING_BASE;
2203 ring->write_tail = ring_write_tail;
2204 ring->flush = gen6_ring_flush;
2205 ring->add_request = gen6_add_request;
2206 ring->get_seqno = gen6_ring_get_seqno;
2207 ring->set_seqno = ring_set_seqno;
2208 if (INTEL_INFO(dev)->gen >= 8) {
2209 ring->irq_enable_mask =
2210 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2211 ring->irq_get = gen8_ring_get_irq;
2212 ring->irq_put = gen8_ring_put_irq;
2213 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2215 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2216 ring->irq_get = gen6_ring_get_irq;
2217 ring->irq_put = gen6_ring_put_irq;
2218 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2220 ring->sync_to = gen6_ring_sync;
2222 * The current semaphore is only applied on pre-gen8 platform. And
2223 * there is no VCS2 ring on the pre-gen8 platform. So the semaphore
2224 * between BCS and VCS2 is initialized as INVALID.
2225 * Gen8 will initialize the sema between BCS and VCS2 later.
2227 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
2228 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
2229 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2230 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
2231 ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2232 ring->signal_mbox[RCS] = GEN6_RBSYNC;
2233 ring->signal_mbox[VCS] = GEN6_VBSYNC;
2234 ring->signal_mbox[BCS] = GEN6_NOSYNC;
2235 ring->signal_mbox[VECS] = GEN6_VEBSYNC;
2236 ring->signal_mbox[VCS2] = GEN6_NOSYNC;
2237 ring->init = init_ring_common;
2239 return intel_init_ring_buffer(dev, ring);
2242 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2244 struct drm_i915_private *dev_priv = dev->dev_private;
2245 struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2247 ring->name = "video enhancement ring";
2250 ring->mmio_base = VEBOX_RING_BASE;
2251 ring->write_tail = ring_write_tail;
2252 ring->flush = gen6_ring_flush;
2253 ring->add_request = gen6_add_request;
2254 ring->get_seqno = gen6_ring_get_seqno;
2255 ring->set_seqno = ring_set_seqno;
2257 if (INTEL_INFO(dev)->gen >= 8) {
2258 ring->irq_enable_mask =
2259 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2260 ring->irq_get = gen8_ring_get_irq;
2261 ring->irq_put = gen8_ring_put_irq;
2262 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2264 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2265 ring->irq_get = hsw_vebox_get_irq;
2266 ring->irq_put = hsw_vebox_put_irq;
2267 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2269 ring->sync_to = gen6_ring_sync;
2270 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2271 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2272 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2273 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2274 ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2275 ring->signal_mbox[RCS] = GEN6_RVESYNC;
2276 ring->signal_mbox[VCS] = GEN6_VVESYNC;
2277 ring->signal_mbox[BCS] = GEN6_BVESYNC;
2278 ring->signal_mbox[VECS] = GEN6_NOSYNC;
2279 ring->signal_mbox[VCS2] = GEN6_NOSYNC;
2280 ring->init = init_ring_common;
2282 return intel_init_ring_buffer(dev, ring);
2286 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2290 if (!ring->gpu_caches_dirty)
2293 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2297 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2299 ring->gpu_caches_dirty = false;
2304 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2306 uint32_t flush_domains;
2310 if (ring->gpu_caches_dirty)
2311 flush_domains = I915_GEM_GPU_DOMAINS;
2313 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2317 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2319 ring->gpu_caches_dirty = false;
2324 intel_stop_ring_buffer(struct intel_ring_buffer *ring)
2328 if (!intel_ring_initialized(ring))
2331 ret = intel_ring_idle(ring);
2332 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2333 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",