2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 intel_ring_initialized(struct intel_engine_cs *ring)
39 struct drm_device *dev = ring->dev;
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
50 return ring->buffer && ring->buffer->obj;
53 int __intel_ring_space(int head, int tail, int size)
55 int space = head - tail;
58 return space - I915_RING_FREE_SPACE;
61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
78 bool intel_ring_stopped(struct intel_engine_cs *ring)
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
84 void __intel_ring_advance(struct intel_engine_cs *ring)
86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88 if (intel_ring_stopped(ring))
90 ring->write_tail(ring, ringbuf->tail);
94 gen2_render_ring_flush(struct intel_engine_cs *ring,
95 u32 invalidate_domains,
102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
103 cmd |= MI_NO_WRITE_FLUSH;
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
108 ret = intel_ring_begin(ring, 2);
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
120 gen4_render_ring_flush(struct intel_engine_cs *ring,
121 u32 invalidate_domains,
124 struct drm_device *dev = ring->dev;
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
140 * I915_GEM_DOMAIN_COMMAND may not exist?
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
158 cmd &= ~MI_NO_WRITE_FLUSH;
159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
166 ret = intel_ring_begin(ring, 2);
170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
190 * And the workaround for these two requires this workaround first:
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
221 ret = intel_ring_begin(ring, 6);
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
234 ret = intel_ring_begin(ring, 6);
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
250 gen6_render_ring_flush(struct intel_engine_cs *ring,
251 u32 invalidate_domains, u32 flush_domains)
254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
273 flags |= PIPE_CONTROL_CS_STALL;
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
283 * TLB invalidate requires a post-sync write.
285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
288 ret = intel_ring_begin(ring, 4);
292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
295 intel_ring_emit(ring, 0);
296 intel_ring_advance(ring);
302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
306 ret = intel_ring_begin(ring, 4);
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
321 gen7_render_ring_flush(struct intel_engine_cs *ring,
322 u32 invalidate_domains, u32 flush_domains)
325 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
329 * Ensure that any following seqno writes only happen when the render
330 * cache is indeed flushed.
332 * Workaround: 4th PIPE_CONTROL command (except the ones with only
333 * read-cache invalidate bits set) must have the CS_STALL bit set. We
334 * don't try to be clever and just set it unconditionally.
336 flags |= PIPE_CONTROL_CS_STALL;
338 /* Just flush everything. Experiments have shown that reducing the
339 * number of bits based on the write domains has little performance
343 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
344 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
346 if (invalidate_domains) {
347 flags |= PIPE_CONTROL_TLB_INVALIDATE;
348 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
349 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
350 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
351 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
352 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
353 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
355 * TLB invalidate requires a post-sync write.
357 flags |= PIPE_CONTROL_QW_WRITE;
358 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
360 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
362 /* Workaround: we must issue a pipe_control with CS-stall bit
363 * set before a pipe_control command that has the state cache
364 * invalidate bit set. */
365 gen7_render_ring_cs_stall_wa(ring);
368 ret = intel_ring_begin(ring, 4);
372 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
373 intel_ring_emit(ring, flags);
374 intel_ring_emit(ring, scratch_addr);
375 intel_ring_emit(ring, 0);
376 intel_ring_advance(ring);
382 gen8_emit_pipe_control(struct intel_engine_cs *ring,
383 u32 flags, u32 scratch_addr)
387 ret = intel_ring_begin(ring, 6);
391 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
392 intel_ring_emit(ring, flags);
393 intel_ring_emit(ring, scratch_addr);
394 intel_ring_emit(ring, 0);
395 intel_ring_emit(ring, 0);
396 intel_ring_emit(ring, 0);
397 intel_ring_advance(ring);
403 gen8_render_ring_flush(struct intel_engine_cs *ring,
404 u32 invalidate_domains, u32 flush_domains)
407 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
410 flags |= PIPE_CONTROL_CS_STALL;
413 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
414 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
416 if (invalidate_domains) {
417 flags |= PIPE_CONTROL_TLB_INVALIDATE;
418 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
419 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
420 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
421 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
422 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
423 flags |= PIPE_CONTROL_QW_WRITE;
424 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
426 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
427 ret = gen8_emit_pipe_control(ring,
428 PIPE_CONTROL_CS_STALL |
429 PIPE_CONTROL_STALL_AT_SCOREBOARD,
435 return gen8_emit_pipe_control(ring, flags, scratch_addr);
438 static void ring_write_tail(struct intel_engine_cs *ring,
441 struct drm_i915_private *dev_priv = ring->dev->dev_private;
442 I915_WRITE_TAIL(ring, value);
445 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
450 if (INTEL_INFO(ring->dev)->gen >= 8)
451 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
452 RING_ACTHD_UDW(ring->mmio_base));
453 else if (INTEL_INFO(ring->dev)->gen >= 4)
454 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
456 acthd = I915_READ(ACTHD);
461 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
463 struct drm_i915_private *dev_priv = ring->dev->dev_private;
466 addr = dev_priv->status_page_dmah->busaddr;
467 if (INTEL_INFO(ring->dev)->gen >= 4)
468 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
469 I915_WRITE(HWS_PGA, addr);
472 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
474 struct drm_device *dev = ring->dev;
475 struct drm_i915_private *dev_priv = ring->dev->dev_private;
478 /* The ring status page addresses are no longer next to the rest of
479 * the ring registers as of gen7.
484 mmio = RENDER_HWS_PGA_GEN7;
487 mmio = BLT_HWS_PGA_GEN7;
490 * VCS2 actually doesn't exist on Gen7. Only shut up
491 * gcc switch check warning
495 mmio = BSD_HWS_PGA_GEN7;
498 mmio = VEBOX_HWS_PGA_GEN7;
501 } else if (IS_GEN6(ring->dev)) {
502 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
504 /* XXX: gen8 returns to sanity */
505 mmio = RING_HWS_PGA(ring->mmio_base);
508 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
512 * Flush the TLB for this page
514 * FIXME: These two bits have disappeared on gen8, so a question
515 * arises: do we still need this and if so how should we go about
516 * invalidating the TLB?
518 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
519 u32 reg = RING_INSTPM(ring->mmio_base);
521 /* ring should be idle before issuing a sync flush*/
522 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
525 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
527 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
529 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
534 static bool stop_ring(struct intel_engine_cs *ring)
536 struct drm_i915_private *dev_priv = to_i915(ring->dev);
538 if (!IS_GEN2(ring->dev)) {
539 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
540 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
541 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
542 /* Sometimes we observe that the idle flag is not
543 * set even though the ring is empty. So double
544 * check before giving up.
546 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
551 I915_WRITE_CTL(ring, 0);
552 I915_WRITE_HEAD(ring, 0);
553 ring->write_tail(ring, 0);
555 if (!IS_GEN2(ring->dev)) {
556 (void)I915_READ_CTL(ring);
557 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
560 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
563 static int init_ring_common(struct intel_engine_cs *ring)
565 struct drm_device *dev = ring->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
567 struct intel_ringbuffer *ringbuf = ring->buffer;
568 struct drm_i915_gem_object *obj = ringbuf->obj;
571 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
573 if (!stop_ring(ring)) {
574 /* G45 ring initialization often fails to reset head to zero */
575 DRM_DEBUG_KMS("%s head not reset to zero "
576 "ctl %08x head %08x tail %08x start %08x\n",
579 I915_READ_HEAD(ring),
580 I915_READ_TAIL(ring),
581 I915_READ_START(ring));
583 if (!stop_ring(ring)) {
584 DRM_ERROR("failed to set %s head to zero "
585 "ctl %08x head %08x tail %08x start %08x\n",
588 I915_READ_HEAD(ring),
589 I915_READ_TAIL(ring),
590 I915_READ_START(ring));
596 if (I915_NEED_GFX_HWS(dev))
597 intel_ring_setup_status_page(ring);
599 ring_setup_phys_status_page(ring);
601 /* Enforce ordering by reading HEAD register back */
602 I915_READ_HEAD(ring);
604 /* Initialize the ring. This must happen _after_ we've cleared the ring
605 * registers with the above sequence (the readback of the HEAD registers
606 * also enforces ordering), otherwise the hw might lose the new ring
607 * register values. */
608 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
610 /* WaClearRingBufHeadRegAtInit:ctg,elk */
611 if (I915_READ_HEAD(ring))
612 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
613 ring->name, I915_READ_HEAD(ring));
614 I915_WRITE_HEAD(ring, 0);
615 (void)I915_READ_HEAD(ring);
618 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
621 /* If the head is still not zero, the ring is dead */
622 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
623 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
624 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
625 DRM_ERROR("%s initialization failed "
626 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
628 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
629 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
630 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
635 ringbuf->last_retired_head = -1;
636 ringbuf->head = I915_READ_HEAD(ring);
637 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
638 intel_ring_update_space(ringbuf);
640 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
643 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
649 intel_fini_pipe_control(struct intel_engine_cs *ring)
651 struct drm_device *dev = ring->dev;
653 if (ring->scratch.obj == NULL)
656 if (INTEL_INFO(dev)->gen >= 5) {
657 kunmap(sg_page(ring->scratch.obj->pages->sgl));
658 i915_gem_object_ggtt_unpin(ring->scratch.obj);
661 drm_gem_object_unreference(&ring->scratch.obj->base);
662 ring->scratch.obj = NULL;
666 intel_init_pipe_control(struct intel_engine_cs *ring)
670 WARN_ON(ring->scratch.obj);
672 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
673 if (ring->scratch.obj == NULL) {
674 DRM_ERROR("Failed to allocate seqno page\n");
679 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
683 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
687 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
688 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
689 if (ring->scratch.cpu_page == NULL) {
694 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
695 ring->name, ring->scratch.gtt_offset);
699 i915_gem_object_ggtt_unpin(ring->scratch.obj);
701 drm_gem_object_unreference(&ring->scratch.obj->base);
706 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
707 struct intel_context *ctx)
710 struct drm_device *dev = ring->dev;
711 struct drm_i915_private *dev_priv = dev->dev_private;
712 struct i915_workarounds *w = &dev_priv->workarounds;
714 if (WARN_ON_ONCE(w->count == 0))
717 ring->gpu_caches_dirty = true;
718 ret = intel_ring_flush_all_caches(ring);
722 ret = intel_ring_begin(ring, (w->count * 2 + 2));
726 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
727 for (i = 0; i < w->count; i++) {
728 intel_ring_emit(ring, w->reg[i].addr);
729 intel_ring_emit(ring, w->reg[i].value);
731 intel_ring_emit(ring, MI_NOOP);
733 intel_ring_advance(ring);
735 ring->gpu_caches_dirty = true;
736 ret = intel_ring_flush_all_caches(ring);
740 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
745 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
746 struct intel_context *ctx)
750 ret = intel_ring_workarounds_emit(ring, ctx);
754 ret = i915_gem_render_state_init(ring);
756 DRM_ERROR("init render state: %d\n", ret);
761 static int wa_add(struct drm_i915_private *dev_priv,
762 const u32 addr, const u32 mask, const u32 val)
764 const u32 idx = dev_priv->workarounds.count;
766 if (WARN_ON(idx >= I915_MAX_WA_REGS))
769 dev_priv->workarounds.reg[idx].addr = addr;
770 dev_priv->workarounds.reg[idx].value = val;
771 dev_priv->workarounds.reg[idx].mask = mask;
773 dev_priv->workarounds.count++;
778 #define WA_REG(addr, mask, val) { \
779 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
784 #define WA_SET_BIT_MASKED(addr, mask) \
785 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
787 #define WA_CLR_BIT_MASKED(addr, mask) \
788 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
790 #define WA_SET_FIELD_MASKED(addr, mask, value) \
791 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
793 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
794 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
796 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
798 static int bdw_init_workarounds(struct intel_engine_cs *ring)
800 struct drm_device *dev = ring->dev;
801 struct drm_i915_private *dev_priv = dev->dev_private;
803 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
805 /* WaDisableAsyncFlipPerfMode:bdw */
806 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
808 /* WaDisablePartialInstShootdown:bdw */
809 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
810 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
811 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
812 STALL_DOP_GATING_DISABLE);
814 /* WaDisableDopClockGating:bdw */
815 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
816 DOP_CLOCK_GATING_DISABLE);
818 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
819 GEN8_SAMPLER_POWER_BYPASS_DIS);
821 /* Use Force Non-Coherent whenever executing a 3D context. This is a
822 * workaround for for a possible hang in the unlikely event a TLB
823 * invalidation occurs during a PSD flush.
825 WA_SET_BIT_MASKED(HDC_CHICKEN0,
826 /* WaForceEnableNonCoherent:bdw */
827 HDC_FORCE_NON_COHERENT |
828 /* WaForceContextSaveRestoreNonCoherent:bdw */
829 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
830 /* WaHdcDisableFetchWhenMasked:bdw */
831 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
832 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
833 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
835 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
836 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
837 * polygons in the same 8x4 pixel/sample area to be processed without
838 * stalling waiting for the earlier ones to write to Hierarchical Z
841 * This optimization is off by default for Broadwell; turn it on.
843 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
845 /* Wa4x4STCOptimizationDisable:bdw */
846 WA_SET_BIT_MASKED(CACHE_MODE_1,
847 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
850 * BSpec recommends 8x4 when MSAA is used,
851 * however in practice 16x4 seems fastest.
853 * Note that PS/WM thread counts depend on the WIZ hashing
854 * disable bit, which we don't touch here, but it's good
855 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
857 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
858 GEN6_WIZ_HASHING_MASK,
859 GEN6_WIZ_HASHING_16x4);
864 static int chv_init_workarounds(struct intel_engine_cs *ring)
866 struct drm_device *dev = ring->dev;
867 struct drm_i915_private *dev_priv = dev->dev_private;
869 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
871 /* WaDisableAsyncFlipPerfMode:chv */
872 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
874 /* WaDisablePartialInstShootdown:chv */
875 /* WaDisableThreadStallDopClockGating:chv */
876 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
877 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
878 STALL_DOP_GATING_DISABLE);
880 /* Use Force Non-Coherent whenever executing a 3D context. This is a
881 * workaround for a possible hang in the unlikely event a TLB
882 * invalidation occurs during a PSD flush.
884 /* WaForceEnableNonCoherent:chv */
885 /* WaHdcDisableFetchWhenMasked:chv */
886 WA_SET_BIT_MASKED(HDC_CHICKEN0,
887 HDC_FORCE_NON_COHERENT |
888 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
890 /* According to the CACHE_MODE_0 default value documentation, some
891 * CHV platforms disable this optimization by default. Turn it on.
893 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
895 /* Wa4x4STCOptimizationDisable:chv */
896 WA_SET_BIT_MASKED(CACHE_MODE_1,
897 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
899 /* Improve HiZ throughput on CHV. */
900 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
903 * BSpec recommends 8x4 when MSAA is used,
904 * however in practice 16x4 seems fastest.
906 * Note that PS/WM thread counts depend on the WIZ hashing
907 * disable bit, which we don't touch here, but it's good
908 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
910 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
911 GEN6_WIZ_HASHING_MASK,
912 GEN6_WIZ_HASHING_16x4);
917 static int gen9_init_workarounds(struct intel_engine_cs *ring)
919 struct drm_device *dev = ring->dev;
920 struct drm_i915_private *dev_priv = dev->dev_private;
923 /* WaDisablePartialInstShootdown:skl,bxt */
924 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
925 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
927 /* Syncing dependencies between camera and graphics:skl,bxt */
928 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
929 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
931 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
932 INTEL_REVID(dev) == SKL_REVID_B0)) ||
933 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
934 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
935 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
936 GEN9_DG_MIRROR_FIX_ENABLE);
939 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
940 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
941 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
942 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
943 GEN9_RHWO_OPTIMIZATION_DISABLE);
944 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
945 DISABLE_PIXEL_MASK_CAMMING);
948 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
950 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
951 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
952 GEN9_ENABLE_YV12_BUGFIX);
955 /* Wa4x4STCOptimizationDisable:skl,bxt */
956 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
958 /* WaDisablePartialResolveInVc:skl,bxt */
959 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
961 /* WaCcsTlbPrefetchDisable:skl,bxt */
962 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
963 GEN9_CCS_TLB_PREFETCH_ENABLE);
965 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
966 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
967 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
968 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
969 PIXEL_MASK_CAMMING_DISABLE);
971 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
972 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
973 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
974 (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
975 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
976 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
981 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
983 struct drm_device *dev = ring->dev;
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 u8 vals[3] = { 0, 0, 0 };
988 for (i = 0; i < 3; i++) {
992 * Only consider slices where one, and only one, subslice has 7
995 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
999 * subslice_7eu[i] != 0 (because of the check above) and
1000 * ss_max == 4 (maximum number of subslices possible per slice)
1004 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1008 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1011 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1012 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1013 GEN9_IZ_HASHING_MASK(2) |
1014 GEN9_IZ_HASHING_MASK(1) |
1015 GEN9_IZ_HASHING_MASK(0),
1016 GEN9_IZ_HASHING(2, vals[2]) |
1017 GEN9_IZ_HASHING(1, vals[1]) |
1018 GEN9_IZ_HASHING(0, vals[0]));
1024 static int skl_init_workarounds(struct intel_engine_cs *ring)
1026 struct drm_device *dev = ring->dev;
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1029 gen9_init_workarounds(ring);
1031 /* WaDisablePowerCompilerClockGating:skl */
1032 if (INTEL_REVID(dev) == SKL_REVID_B0)
1033 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1034 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1036 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1038 *Use Force Non-Coherent whenever executing a 3D context. This
1039 * is a workaround for a possible hang in the unlikely event
1040 * a TLB invalidation occurs during a PSD flush.
1042 /* WaForceEnableNonCoherent:skl */
1043 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1044 HDC_FORCE_NON_COHERENT);
1047 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1048 INTEL_REVID(dev) == SKL_REVID_D0)
1049 /* WaBarrierPerformanceFixDisable:skl */
1050 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1051 HDC_FENCE_DEST_SLM_DISABLE |
1052 HDC_BARRIER_PERFORMANCE_DISABLE);
1054 return skl_tune_iz_hashing(ring);
1057 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1059 struct drm_device *dev = ring->dev;
1060 struct drm_i915_private *dev_priv = dev->dev_private;
1062 gen9_init_workarounds(ring);
1064 /* WaDisableThreadStallDopClockGating:bxt */
1065 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1066 STALL_DOP_GATING_DISABLE);
1068 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1069 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1071 GEN7_HALF_SLICE_CHICKEN1,
1072 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1078 int init_workarounds_ring(struct intel_engine_cs *ring)
1080 struct drm_device *dev = ring->dev;
1081 struct drm_i915_private *dev_priv = dev->dev_private;
1083 WARN_ON(ring->id != RCS);
1085 dev_priv->workarounds.count = 0;
1087 if (IS_BROADWELL(dev))
1088 return bdw_init_workarounds(ring);
1090 if (IS_CHERRYVIEW(dev))
1091 return chv_init_workarounds(ring);
1093 if (IS_SKYLAKE(dev))
1094 return skl_init_workarounds(ring);
1096 if (IS_BROXTON(dev))
1097 return bxt_init_workarounds(ring);
1102 static int init_render_ring(struct intel_engine_cs *ring)
1104 struct drm_device *dev = ring->dev;
1105 struct drm_i915_private *dev_priv = dev->dev_private;
1106 int ret = init_ring_common(ring);
1110 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1111 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1112 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1114 /* We need to disable the AsyncFlip performance optimisations in order
1115 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1116 * programmed to '1' on all products.
1118 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1120 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1121 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1123 /* Required for the hardware to program scanline values for waiting */
1124 /* WaEnableFlushTlbInvalidationMode:snb */
1125 if (INTEL_INFO(dev)->gen == 6)
1126 I915_WRITE(GFX_MODE,
1127 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1129 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1131 I915_WRITE(GFX_MODE_GEN7,
1132 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1133 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1136 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1137 * "If this bit is set, STCunit will have LRA as replacement
1138 * policy. [...] This bit must be reset. LRA replacement
1139 * policy is not supported."
1141 I915_WRITE(CACHE_MODE_0,
1142 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1145 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1146 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1148 if (HAS_L3_DPF(dev))
1149 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1151 return init_workarounds_ring(ring);
1154 static void render_ring_cleanup(struct intel_engine_cs *ring)
1156 struct drm_device *dev = ring->dev;
1157 struct drm_i915_private *dev_priv = dev->dev_private;
1159 if (dev_priv->semaphore_obj) {
1160 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1161 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1162 dev_priv->semaphore_obj = NULL;
1165 intel_fini_pipe_control(ring);
1168 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1169 unsigned int num_dwords)
1171 #define MBOX_UPDATE_DWORDS 8
1172 struct drm_device *dev = signaller->dev;
1173 struct drm_i915_private *dev_priv = dev->dev_private;
1174 struct intel_engine_cs *waiter;
1175 int i, ret, num_rings;
1177 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1178 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1179 #undef MBOX_UPDATE_DWORDS
1181 ret = intel_ring_begin(signaller, num_dwords);
1185 for_each_ring(waiter, dev_priv, i) {
1187 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1188 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1191 seqno = i915_gem_request_get_seqno(
1192 signaller->outstanding_lazy_request);
1193 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1194 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1195 PIPE_CONTROL_QW_WRITE |
1196 PIPE_CONTROL_FLUSH_ENABLE);
1197 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1198 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1199 intel_ring_emit(signaller, seqno);
1200 intel_ring_emit(signaller, 0);
1201 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1202 MI_SEMAPHORE_TARGET(waiter->id));
1203 intel_ring_emit(signaller, 0);
1209 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1210 unsigned int num_dwords)
1212 #define MBOX_UPDATE_DWORDS 6
1213 struct drm_device *dev = signaller->dev;
1214 struct drm_i915_private *dev_priv = dev->dev_private;
1215 struct intel_engine_cs *waiter;
1216 int i, ret, num_rings;
1218 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1219 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1220 #undef MBOX_UPDATE_DWORDS
1222 ret = intel_ring_begin(signaller, num_dwords);
1226 for_each_ring(waiter, dev_priv, i) {
1228 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1229 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1232 seqno = i915_gem_request_get_seqno(
1233 signaller->outstanding_lazy_request);
1234 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1235 MI_FLUSH_DW_OP_STOREDW);
1236 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1237 MI_FLUSH_DW_USE_GTT);
1238 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1239 intel_ring_emit(signaller, seqno);
1240 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1241 MI_SEMAPHORE_TARGET(waiter->id));
1242 intel_ring_emit(signaller, 0);
1248 static int gen6_signal(struct intel_engine_cs *signaller,
1249 unsigned int num_dwords)
1251 struct drm_device *dev = signaller->dev;
1252 struct drm_i915_private *dev_priv = dev->dev_private;
1253 struct intel_engine_cs *useless;
1254 int i, ret, num_rings;
1256 #define MBOX_UPDATE_DWORDS 3
1257 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1258 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1259 #undef MBOX_UPDATE_DWORDS
1261 ret = intel_ring_begin(signaller, num_dwords);
1265 for_each_ring(useless, dev_priv, i) {
1266 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1267 if (mbox_reg != GEN6_NOSYNC) {
1268 u32 seqno = i915_gem_request_get_seqno(
1269 signaller->outstanding_lazy_request);
1270 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1271 intel_ring_emit(signaller, mbox_reg);
1272 intel_ring_emit(signaller, seqno);
1276 /* If num_dwords was rounded, make sure the tail pointer is correct */
1277 if (num_rings % 2 == 0)
1278 intel_ring_emit(signaller, MI_NOOP);
1284 * gen6_add_request - Update the semaphore mailbox registers
1286 * @ring - ring that is adding a request
1287 * @seqno - return seqno stuck into the ring
1289 * Update the mailbox registers in the *other* rings with the current seqno.
1290 * This acts like a signal in the canonical semaphore.
1293 gen6_add_request(struct intel_engine_cs *ring)
1297 if (ring->semaphore.signal)
1298 ret = ring->semaphore.signal(ring, 4);
1300 ret = intel_ring_begin(ring, 4);
1305 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1306 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1307 intel_ring_emit(ring,
1308 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1309 intel_ring_emit(ring, MI_USER_INTERRUPT);
1310 __intel_ring_advance(ring);
1315 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1318 struct drm_i915_private *dev_priv = dev->dev_private;
1319 return dev_priv->last_seqno < seqno;
1323 * intel_ring_sync - sync the waiter to the signaller on seqno
1325 * @waiter - ring that is waiting
1326 * @signaller - ring which has, or will signal
1327 * @seqno - seqno which the waiter will block on
1331 gen8_ring_sync(struct intel_engine_cs *waiter,
1332 struct intel_engine_cs *signaller,
1335 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1338 ret = intel_ring_begin(waiter, 4);
1342 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1343 MI_SEMAPHORE_GLOBAL_GTT |
1345 MI_SEMAPHORE_SAD_GTE_SDD);
1346 intel_ring_emit(waiter, seqno);
1347 intel_ring_emit(waiter,
1348 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1349 intel_ring_emit(waiter,
1350 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1351 intel_ring_advance(waiter);
1356 gen6_ring_sync(struct intel_engine_cs *waiter,
1357 struct intel_engine_cs *signaller,
1360 u32 dw1 = MI_SEMAPHORE_MBOX |
1361 MI_SEMAPHORE_COMPARE |
1362 MI_SEMAPHORE_REGISTER;
1363 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1366 /* Throughout all of the GEM code, seqno passed implies our current
1367 * seqno is >= the last seqno executed. However for hardware the
1368 * comparison is strictly greater than.
1372 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1374 ret = intel_ring_begin(waiter, 4);
1378 /* If seqno wrap happened, omit the wait with no-ops */
1379 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1380 intel_ring_emit(waiter, dw1 | wait_mbox);
1381 intel_ring_emit(waiter, seqno);
1382 intel_ring_emit(waiter, 0);
1383 intel_ring_emit(waiter, MI_NOOP);
1385 intel_ring_emit(waiter, MI_NOOP);
1386 intel_ring_emit(waiter, MI_NOOP);
1387 intel_ring_emit(waiter, MI_NOOP);
1388 intel_ring_emit(waiter, MI_NOOP);
1390 intel_ring_advance(waiter);
1395 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1397 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1398 PIPE_CONTROL_DEPTH_STALL); \
1399 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1400 intel_ring_emit(ring__, 0); \
1401 intel_ring_emit(ring__, 0); \
1405 pc_render_add_request(struct intel_engine_cs *ring)
1407 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1410 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1411 * incoherent with writes to memory, i.e. completely fubar,
1412 * so we need to use PIPE_NOTIFY instead.
1414 * However, we also need to workaround the qword write
1415 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1416 * memory before requesting an interrupt.
1418 ret = intel_ring_begin(ring, 32);
1422 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1423 PIPE_CONTROL_WRITE_FLUSH |
1424 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1425 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1426 intel_ring_emit(ring,
1427 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1428 intel_ring_emit(ring, 0);
1429 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1430 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1431 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1432 scratch_addr += 2 * CACHELINE_BYTES;
1433 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1434 scratch_addr += 2 * CACHELINE_BYTES;
1435 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1436 scratch_addr += 2 * CACHELINE_BYTES;
1437 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1438 scratch_addr += 2 * CACHELINE_BYTES;
1439 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1441 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1442 PIPE_CONTROL_WRITE_FLUSH |
1443 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1444 PIPE_CONTROL_NOTIFY);
1445 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1446 intel_ring_emit(ring,
1447 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1448 intel_ring_emit(ring, 0);
1449 __intel_ring_advance(ring);
1455 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1457 /* Workaround to force correct ordering between irq and seqno writes on
1458 * ivb (and maybe also on snb) by reading from a CS register (like
1459 * ACTHD) before reading the status page. */
1460 if (!lazy_coherency) {
1461 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1462 POSTING_READ(RING_ACTHD(ring->mmio_base));
1465 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1469 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1471 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1475 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1477 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1481 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1483 return ring->scratch.cpu_page[0];
1487 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1489 ring->scratch.cpu_page[0] = seqno;
1493 gen5_ring_get_irq(struct intel_engine_cs *ring)
1495 struct drm_device *dev = ring->dev;
1496 struct drm_i915_private *dev_priv = dev->dev_private;
1497 unsigned long flags;
1499 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1502 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1503 if (ring->irq_refcount++ == 0)
1504 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1505 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1511 gen5_ring_put_irq(struct intel_engine_cs *ring)
1513 struct drm_device *dev = ring->dev;
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 unsigned long flags;
1517 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1518 if (--ring->irq_refcount == 0)
1519 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1520 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1524 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1526 struct drm_device *dev = ring->dev;
1527 struct drm_i915_private *dev_priv = dev->dev_private;
1528 unsigned long flags;
1530 if (!intel_irqs_enabled(dev_priv))
1533 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1534 if (ring->irq_refcount++ == 0) {
1535 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1536 I915_WRITE(IMR, dev_priv->irq_mask);
1539 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1545 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1547 struct drm_device *dev = ring->dev;
1548 struct drm_i915_private *dev_priv = dev->dev_private;
1549 unsigned long flags;
1551 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1552 if (--ring->irq_refcount == 0) {
1553 dev_priv->irq_mask |= ring->irq_enable_mask;
1554 I915_WRITE(IMR, dev_priv->irq_mask);
1557 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1561 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1563 struct drm_device *dev = ring->dev;
1564 struct drm_i915_private *dev_priv = dev->dev_private;
1565 unsigned long flags;
1567 if (!intel_irqs_enabled(dev_priv))
1570 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1571 if (ring->irq_refcount++ == 0) {
1572 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1573 I915_WRITE16(IMR, dev_priv->irq_mask);
1574 POSTING_READ16(IMR);
1576 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1582 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1584 struct drm_device *dev = ring->dev;
1585 struct drm_i915_private *dev_priv = dev->dev_private;
1586 unsigned long flags;
1588 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1589 if (--ring->irq_refcount == 0) {
1590 dev_priv->irq_mask |= ring->irq_enable_mask;
1591 I915_WRITE16(IMR, dev_priv->irq_mask);
1592 POSTING_READ16(IMR);
1594 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1598 bsd_ring_flush(struct intel_engine_cs *ring,
1599 u32 invalidate_domains,
1604 ret = intel_ring_begin(ring, 2);
1608 intel_ring_emit(ring, MI_FLUSH);
1609 intel_ring_emit(ring, MI_NOOP);
1610 intel_ring_advance(ring);
1615 i9xx_add_request(struct intel_engine_cs *ring)
1619 ret = intel_ring_begin(ring, 4);
1623 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1624 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1625 intel_ring_emit(ring,
1626 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1627 intel_ring_emit(ring, MI_USER_INTERRUPT);
1628 __intel_ring_advance(ring);
1634 gen6_ring_get_irq(struct intel_engine_cs *ring)
1636 struct drm_device *dev = ring->dev;
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638 unsigned long flags;
1640 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1643 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1644 if (ring->irq_refcount++ == 0) {
1645 if (HAS_L3_DPF(dev) && ring->id == RCS)
1646 I915_WRITE_IMR(ring,
1647 ~(ring->irq_enable_mask |
1648 GT_PARITY_ERROR(dev)));
1650 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1651 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1653 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1659 gen6_ring_put_irq(struct intel_engine_cs *ring)
1661 struct drm_device *dev = ring->dev;
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663 unsigned long flags;
1665 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1666 if (--ring->irq_refcount == 0) {
1667 if (HAS_L3_DPF(dev) && ring->id == RCS)
1668 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1670 I915_WRITE_IMR(ring, ~0);
1671 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1673 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1677 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1679 struct drm_device *dev = ring->dev;
1680 struct drm_i915_private *dev_priv = dev->dev_private;
1681 unsigned long flags;
1683 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1686 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1687 if (ring->irq_refcount++ == 0) {
1688 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1689 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1691 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1697 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1699 struct drm_device *dev = ring->dev;
1700 struct drm_i915_private *dev_priv = dev->dev_private;
1701 unsigned long flags;
1703 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1704 if (--ring->irq_refcount == 0) {
1705 I915_WRITE_IMR(ring, ~0);
1706 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1708 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1712 gen8_ring_get_irq(struct intel_engine_cs *ring)
1714 struct drm_device *dev = ring->dev;
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716 unsigned long flags;
1718 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1721 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1722 if (ring->irq_refcount++ == 0) {
1723 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1724 I915_WRITE_IMR(ring,
1725 ~(ring->irq_enable_mask |
1726 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1728 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1730 POSTING_READ(RING_IMR(ring->mmio_base));
1732 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1738 gen8_ring_put_irq(struct intel_engine_cs *ring)
1740 struct drm_device *dev = ring->dev;
1741 struct drm_i915_private *dev_priv = dev->dev_private;
1742 unsigned long flags;
1744 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1745 if (--ring->irq_refcount == 0) {
1746 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1747 I915_WRITE_IMR(ring,
1748 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1750 I915_WRITE_IMR(ring, ~0);
1752 POSTING_READ(RING_IMR(ring->mmio_base));
1754 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1758 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1759 u64 offset, u32 length,
1760 unsigned dispatch_flags)
1764 ret = intel_ring_begin(ring, 2);
1768 intel_ring_emit(ring,
1769 MI_BATCH_BUFFER_START |
1771 (dispatch_flags & I915_DISPATCH_SECURE ?
1772 0 : MI_BATCH_NON_SECURE_I965));
1773 intel_ring_emit(ring, offset);
1774 intel_ring_advance(ring);
1779 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1780 #define I830_BATCH_LIMIT (256*1024)
1781 #define I830_TLB_ENTRIES (2)
1782 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1784 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1785 u64 offset, u32 len,
1786 unsigned dispatch_flags)
1788 u32 cs_offset = ring->scratch.gtt_offset;
1791 ret = intel_ring_begin(ring, 6);
1795 /* Evict the invalid PTE TLBs */
1796 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1797 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1798 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1799 intel_ring_emit(ring, cs_offset);
1800 intel_ring_emit(ring, 0xdeadbeef);
1801 intel_ring_emit(ring, MI_NOOP);
1802 intel_ring_advance(ring);
1804 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1805 if (len > I830_BATCH_LIMIT)
1808 ret = intel_ring_begin(ring, 6 + 2);
1812 /* Blit the batch (which has now all relocs applied) to the
1813 * stable batch scratch bo area (so that the CS never
1814 * stumbles over its tlb invalidation bug) ...
1816 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1817 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1818 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1819 intel_ring_emit(ring, cs_offset);
1820 intel_ring_emit(ring, 4096);
1821 intel_ring_emit(ring, offset);
1823 intel_ring_emit(ring, MI_FLUSH);
1824 intel_ring_emit(ring, MI_NOOP);
1825 intel_ring_advance(ring);
1827 /* ... and execute it. */
1831 ret = intel_ring_begin(ring, 4);
1835 intel_ring_emit(ring, MI_BATCH_BUFFER);
1836 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1837 0 : MI_BATCH_NON_SECURE));
1838 intel_ring_emit(ring, offset + len - 8);
1839 intel_ring_emit(ring, MI_NOOP);
1840 intel_ring_advance(ring);
1846 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1847 u64 offset, u32 len,
1848 unsigned dispatch_flags)
1852 ret = intel_ring_begin(ring, 2);
1856 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1857 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1858 0 : MI_BATCH_NON_SECURE));
1859 intel_ring_advance(ring);
1864 static void cleanup_status_page(struct intel_engine_cs *ring)
1866 struct drm_i915_gem_object *obj;
1868 obj = ring->status_page.obj;
1872 kunmap(sg_page(obj->pages->sgl));
1873 i915_gem_object_ggtt_unpin(obj);
1874 drm_gem_object_unreference(&obj->base);
1875 ring->status_page.obj = NULL;
1878 static int init_status_page(struct intel_engine_cs *ring)
1880 struct drm_i915_gem_object *obj;
1882 if ((obj = ring->status_page.obj) == NULL) {
1886 obj = i915_gem_alloc_object(ring->dev, 4096);
1888 DRM_ERROR("Failed to allocate status page\n");
1892 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1897 if (!HAS_LLC(ring->dev))
1898 /* On g33, we cannot place HWS above 256MiB, so
1899 * restrict its pinning to the low mappable arena.
1900 * Though this restriction is not documented for
1901 * gen4, gen5, or byt, they also behave similarly
1902 * and hang if the HWS is placed at the top of the
1903 * GTT. To generalise, it appears that all !llc
1904 * platforms have issues with us placing the HWS
1905 * above the mappable region (even though we never
1908 flags |= PIN_MAPPABLE;
1909 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1912 drm_gem_object_unreference(&obj->base);
1916 ring->status_page.obj = obj;
1919 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1920 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1921 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1923 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1924 ring->name, ring->status_page.gfx_addr);
1929 static int init_phys_status_page(struct intel_engine_cs *ring)
1931 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1933 if (!dev_priv->status_page_dmah) {
1934 dev_priv->status_page_dmah =
1935 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1936 if (!dev_priv->status_page_dmah)
1940 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1941 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1946 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1948 iounmap(ringbuf->virtual_start);
1949 ringbuf->virtual_start = NULL;
1950 i915_gem_object_ggtt_unpin(ringbuf->obj);
1953 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1954 struct intel_ringbuffer *ringbuf)
1956 struct drm_i915_private *dev_priv = to_i915(dev);
1957 struct drm_i915_gem_object *obj = ringbuf->obj;
1960 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1964 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1966 i915_gem_object_ggtt_unpin(obj);
1970 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1971 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1972 if (ringbuf->virtual_start == NULL) {
1973 i915_gem_object_ggtt_unpin(obj);
1980 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1982 drm_gem_object_unreference(&ringbuf->obj->base);
1983 ringbuf->obj = NULL;
1986 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1987 struct intel_ringbuffer *ringbuf)
1989 struct drm_i915_gem_object *obj;
1993 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1995 obj = i915_gem_alloc_object(dev, ringbuf->size);
1999 /* mark ring buffers as read-only from GPU side by default */
2007 static int intel_init_ring_buffer(struct drm_device *dev,
2008 struct intel_engine_cs *ring)
2010 struct intel_ringbuffer *ringbuf;
2013 WARN_ON(ring->buffer);
2015 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2018 ring->buffer = ringbuf;
2021 INIT_LIST_HEAD(&ring->active_list);
2022 INIT_LIST_HEAD(&ring->request_list);
2023 INIT_LIST_HEAD(&ring->execlist_queue);
2024 i915_gem_batch_pool_init(dev, &ring->batch_pool);
2025 ringbuf->size = 32 * PAGE_SIZE;
2026 ringbuf->ring = ring;
2027 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2029 init_waitqueue_head(&ring->irq_queue);
2031 if (I915_NEED_GFX_HWS(dev)) {
2032 ret = init_status_page(ring);
2036 BUG_ON(ring->id != RCS);
2037 ret = init_phys_status_page(ring);
2042 WARN_ON(ringbuf->obj);
2044 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2046 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2051 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2053 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2055 intel_destroy_ringbuffer_obj(ringbuf);
2059 /* Workaround an erratum on the i830 which causes a hang if
2060 * the TAIL pointer points to within the last 2 cachelines
2063 ringbuf->effective_size = ringbuf->size;
2064 if (IS_I830(dev) || IS_845G(dev))
2065 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2067 ret = i915_cmd_parser_init_ring(ring);
2075 ring->buffer = NULL;
2079 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2081 struct drm_i915_private *dev_priv;
2082 struct intel_ringbuffer *ringbuf;
2084 if (!intel_ring_initialized(ring))
2087 dev_priv = to_i915(ring->dev);
2088 ringbuf = ring->buffer;
2090 intel_stop_ring_buffer(ring);
2091 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2093 intel_unpin_ringbuffer_obj(ringbuf);
2094 intel_destroy_ringbuffer_obj(ringbuf);
2095 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2098 ring->cleanup(ring);
2100 cleanup_status_page(ring);
2102 i915_cmd_parser_fini_ring(ring);
2103 i915_gem_batch_pool_fini(&ring->batch_pool);
2106 ring->buffer = NULL;
2109 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2111 struct intel_ringbuffer *ringbuf = ring->buffer;
2112 struct drm_i915_gem_request *request;
2116 if (intel_ring_space(ringbuf) >= n)
2119 list_for_each_entry(request, &ring->request_list, list) {
2120 space = __intel_ring_space(request->postfix, ringbuf->tail,
2126 if (WARN_ON(&request->list == &ring->request_list))
2129 ret = i915_wait_request(request);
2133 ringbuf->space = space;
2137 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2139 uint32_t __iomem *virt;
2140 struct intel_ringbuffer *ringbuf = ring->buffer;
2141 int rem = ringbuf->size - ringbuf->tail;
2143 if (ringbuf->space < rem) {
2144 int ret = ring_wait_for_space(ring, rem);
2149 virt = ringbuf->virtual_start + ringbuf->tail;
2152 iowrite32(MI_NOOP, virt++);
2155 intel_ring_update_space(ringbuf);
2160 int intel_ring_idle(struct intel_engine_cs *ring)
2162 struct drm_i915_gem_request *req;
2165 /* We need to add any requests required to flush the objects and ring */
2166 if (ring->outstanding_lazy_request) {
2167 ret = i915_add_request(ring);
2172 /* Wait upon the last request to be completed */
2173 if (list_empty(&ring->request_list))
2176 req = list_entry(ring->request_list.prev,
2177 struct drm_i915_gem_request,
2180 /* Make sure we do not trigger any retires */
2181 return __i915_wait_request(req,
2182 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2183 to_i915(ring->dev)->mm.interruptible,
2187 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2189 request->ringbuf = request->ring->buffer;
2193 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2196 struct intel_ringbuffer *ringbuf = ring->buffer;
2199 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2200 ret = intel_wrap_ring_buffer(ring);
2205 if (unlikely(ringbuf->space < bytes)) {
2206 ret = ring_wait_for_space(ring, bytes);
2214 int intel_ring_begin(struct intel_engine_cs *ring,
2217 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2220 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2221 dev_priv->mm.interruptible);
2225 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2229 /* Preallocate the olr before touching the ring */
2230 ret = i915_gem_request_alloc(ring, ring->default_context);
2234 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2238 /* Align the ring tail to a cacheline boundary */
2239 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2241 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2244 if (num_dwords == 0)
2247 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2248 ret = intel_ring_begin(ring, num_dwords);
2252 while (num_dwords--)
2253 intel_ring_emit(ring, MI_NOOP);
2255 intel_ring_advance(ring);
2260 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2262 struct drm_device *dev = ring->dev;
2263 struct drm_i915_private *dev_priv = dev->dev_private;
2265 BUG_ON(ring->outstanding_lazy_request);
2267 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2268 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2269 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2271 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2274 ring->set_seqno(ring, seqno);
2275 ring->hangcheck.seqno = seqno;
2278 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2281 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2283 /* Every tail move must follow the sequence below */
2285 /* Disable notification that the ring is IDLE. The GT
2286 * will then assume that it is busy and bring it out of rc6.
2288 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2289 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2291 /* Clear the context id. Here be magic! */
2292 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2294 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2295 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2296 GEN6_BSD_SLEEP_INDICATOR) == 0,
2298 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2300 /* Now that the ring is fully powered up, update the tail */
2301 I915_WRITE_TAIL(ring, value);
2302 POSTING_READ(RING_TAIL(ring->mmio_base));
2304 /* Let the ring send IDLE messages to the GT again,
2305 * and so let it sleep to conserve power when idle.
2307 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2308 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2311 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2312 u32 invalidate, u32 flush)
2317 ret = intel_ring_begin(ring, 4);
2322 if (INTEL_INFO(ring->dev)->gen >= 8)
2325 /* We always require a command barrier so that subsequent
2326 * commands, such as breadcrumb interrupts, are strictly ordered
2327 * wrt the contents of the write cache being flushed to memory
2328 * (and thus being coherent from the CPU).
2330 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2333 * Bspec vol 1c.5 - video engine command streamer:
2334 * "If ENABLED, all TLBs will be invalidated once the flush
2335 * operation is complete. This bit is only valid when the
2336 * Post-Sync Operation field is a value of 1h or 3h."
2338 if (invalidate & I915_GEM_GPU_DOMAINS)
2339 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2341 intel_ring_emit(ring, cmd);
2342 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2343 if (INTEL_INFO(ring->dev)->gen >= 8) {
2344 intel_ring_emit(ring, 0); /* upper addr */
2345 intel_ring_emit(ring, 0); /* value */
2347 intel_ring_emit(ring, 0);
2348 intel_ring_emit(ring, MI_NOOP);
2350 intel_ring_advance(ring);
2355 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2356 u64 offset, u32 len,
2357 unsigned dispatch_flags)
2359 bool ppgtt = USES_PPGTT(ring->dev) &&
2360 !(dispatch_flags & I915_DISPATCH_SECURE);
2363 ret = intel_ring_begin(ring, 4);
2367 /* FIXME(BDW): Address space and security selectors. */
2368 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2369 intel_ring_emit(ring, lower_32_bits(offset));
2370 intel_ring_emit(ring, upper_32_bits(offset));
2371 intel_ring_emit(ring, MI_NOOP);
2372 intel_ring_advance(ring);
2378 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2379 u64 offset, u32 len,
2380 unsigned dispatch_flags)
2384 ret = intel_ring_begin(ring, 2);
2388 intel_ring_emit(ring,
2389 MI_BATCH_BUFFER_START |
2390 (dispatch_flags & I915_DISPATCH_SECURE ?
2391 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2392 /* bit0-7 is the length on GEN6+ */
2393 intel_ring_emit(ring, offset);
2394 intel_ring_advance(ring);
2400 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2401 u64 offset, u32 len,
2402 unsigned dispatch_flags)
2406 ret = intel_ring_begin(ring, 2);
2410 intel_ring_emit(ring,
2411 MI_BATCH_BUFFER_START |
2412 (dispatch_flags & I915_DISPATCH_SECURE ?
2413 0 : MI_BATCH_NON_SECURE_I965));
2414 /* bit0-7 is the length on GEN6+ */
2415 intel_ring_emit(ring, offset);
2416 intel_ring_advance(ring);
2421 /* Blitter support (SandyBridge+) */
2423 static int gen6_ring_flush(struct intel_engine_cs *ring,
2424 u32 invalidate, u32 flush)
2426 struct drm_device *dev = ring->dev;
2430 ret = intel_ring_begin(ring, 4);
2435 if (INTEL_INFO(dev)->gen >= 8)
2438 /* We always require a command barrier so that subsequent
2439 * commands, such as breadcrumb interrupts, are strictly ordered
2440 * wrt the contents of the write cache being flushed to memory
2441 * (and thus being coherent from the CPU).
2443 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2446 * Bspec vol 1c.3 - blitter engine command streamer:
2447 * "If ENABLED, all TLBs will be invalidated once the flush
2448 * operation is complete. This bit is only valid when the
2449 * Post-Sync Operation field is a value of 1h or 3h."
2451 if (invalidate & I915_GEM_DOMAIN_RENDER)
2452 cmd |= MI_INVALIDATE_TLB;
2453 intel_ring_emit(ring, cmd);
2454 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2455 if (INTEL_INFO(dev)->gen >= 8) {
2456 intel_ring_emit(ring, 0); /* upper addr */
2457 intel_ring_emit(ring, 0); /* value */
2459 intel_ring_emit(ring, 0);
2460 intel_ring_emit(ring, MI_NOOP);
2462 intel_ring_advance(ring);
2467 int intel_init_render_ring_buffer(struct drm_device *dev)
2469 struct drm_i915_private *dev_priv = dev->dev_private;
2470 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2471 struct drm_i915_gem_object *obj;
2474 ring->name = "render ring";
2476 ring->mmio_base = RENDER_RING_BASE;
2478 if (INTEL_INFO(dev)->gen >= 8) {
2479 if (i915_semaphore_is_enabled(dev)) {
2480 obj = i915_gem_alloc_object(dev, 4096);
2482 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2483 i915.semaphores = 0;
2485 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2486 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2488 drm_gem_object_unreference(&obj->base);
2489 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2490 i915.semaphores = 0;
2492 dev_priv->semaphore_obj = obj;
2496 ring->init_context = intel_rcs_ctx_init;
2497 ring->add_request = gen6_add_request;
2498 ring->flush = gen8_render_ring_flush;
2499 ring->irq_get = gen8_ring_get_irq;
2500 ring->irq_put = gen8_ring_put_irq;
2501 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2502 ring->get_seqno = gen6_ring_get_seqno;
2503 ring->set_seqno = ring_set_seqno;
2504 if (i915_semaphore_is_enabled(dev)) {
2505 WARN_ON(!dev_priv->semaphore_obj);
2506 ring->semaphore.sync_to = gen8_ring_sync;
2507 ring->semaphore.signal = gen8_rcs_signal;
2508 GEN8_RING_SEMAPHORE_INIT;
2510 } else if (INTEL_INFO(dev)->gen >= 6) {
2511 ring->add_request = gen6_add_request;
2512 ring->flush = gen7_render_ring_flush;
2513 if (INTEL_INFO(dev)->gen == 6)
2514 ring->flush = gen6_render_ring_flush;
2515 ring->irq_get = gen6_ring_get_irq;
2516 ring->irq_put = gen6_ring_put_irq;
2517 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2518 ring->get_seqno = gen6_ring_get_seqno;
2519 ring->set_seqno = ring_set_seqno;
2520 if (i915_semaphore_is_enabled(dev)) {
2521 ring->semaphore.sync_to = gen6_ring_sync;
2522 ring->semaphore.signal = gen6_signal;
2524 * The current semaphore is only applied on pre-gen8
2525 * platform. And there is no VCS2 ring on the pre-gen8
2526 * platform. So the semaphore between RCS and VCS2 is
2527 * initialized as INVALID. Gen8 will initialize the
2528 * sema between VCS2 and RCS later.
2530 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2531 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2532 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2533 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2534 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2535 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2536 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2537 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2538 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2539 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2541 } else if (IS_GEN5(dev)) {
2542 ring->add_request = pc_render_add_request;
2543 ring->flush = gen4_render_ring_flush;
2544 ring->get_seqno = pc_render_get_seqno;
2545 ring->set_seqno = pc_render_set_seqno;
2546 ring->irq_get = gen5_ring_get_irq;
2547 ring->irq_put = gen5_ring_put_irq;
2548 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2549 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2551 ring->add_request = i9xx_add_request;
2552 if (INTEL_INFO(dev)->gen < 4)
2553 ring->flush = gen2_render_ring_flush;
2555 ring->flush = gen4_render_ring_flush;
2556 ring->get_seqno = ring_get_seqno;
2557 ring->set_seqno = ring_set_seqno;
2559 ring->irq_get = i8xx_ring_get_irq;
2560 ring->irq_put = i8xx_ring_put_irq;
2562 ring->irq_get = i9xx_ring_get_irq;
2563 ring->irq_put = i9xx_ring_put_irq;
2565 ring->irq_enable_mask = I915_USER_INTERRUPT;
2567 ring->write_tail = ring_write_tail;
2569 if (IS_HASWELL(dev))
2570 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2571 else if (IS_GEN8(dev))
2572 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2573 else if (INTEL_INFO(dev)->gen >= 6)
2574 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2575 else if (INTEL_INFO(dev)->gen >= 4)
2576 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2577 else if (IS_I830(dev) || IS_845G(dev))
2578 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2580 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2581 ring->init_hw = init_render_ring;
2582 ring->cleanup = render_ring_cleanup;
2584 /* Workaround batchbuffer to combat CS tlb bug. */
2585 if (HAS_BROKEN_CS_TLB(dev)) {
2586 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2588 DRM_ERROR("Failed to allocate batch bo\n");
2592 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2594 drm_gem_object_unreference(&obj->base);
2595 DRM_ERROR("Failed to ping batch bo\n");
2599 ring->scratch.obj = obj;
2600 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2603 ret = intel_init_ring_buffer(dev, ring);
2607 if (INTEL_INFO(dev)->gen >= 5) {
2608 ret = intel_init_pipe_control(ring);
2616 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2618 struct drm_i915_private *dev_priv = dev->dev_private;
2619 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2621 ring->name = "bsd ring";
2624 ring->write_tail = ring_write_tail;
2625 if (INTEL_INFO(dev)->gen >= 6) {
2626 ring->mmio_base = GEN6_BSD_RING_BASE;
2627 /* gen6 bsd needs a special wa for tail updates */
2629 ring->write_tail = gen6_bsd_ring_write_tail;
2630 ring->flush = gen6_bsd_ring_flush;
2631 ring->add_request = gen6_add_request;
2632 ring->get_seqno = gen6_ring_get_seqno;
2633 ring->set_seqno = ring_set_seqno;
2634 if (INTEL_INFO(dev)->gen >= 8) {
2635 ring->irq_enable_mask =
2636 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2637 ring->irq_get = gen8_ring_get_irq;
2638 ring->irq_put = gen8_ring_put_irq;
2639 ring->dispatch_execbuffer =
2640 gen8_ring_dispatch_execbuffer;
2641 if (i915_semaphore_is_enabled(dev)) {
2642 ring->semaphore.sync_to = gen8_ring_sync;
2643 ring->semaphore.signal = gen8_xcs_signal;
2644 GEN8_RING_SEMAPHORE_INIT;
2647 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2648 ring->irq_get = gen6_ring_get_irq;
2649 ring->irq_put = gen6_ring_put_irq;
2650 ring->dispatch_execbuffer =
2651 gen6_ring_dispatch_execbuffer;
2652 if (i915_semaphore_is_enabled(dev)) {
2653 ring->semaphore.sync_to = gen6_ring_sync;
2654 ring->semaphore.signal = gen6_signal;
2655 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2656 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2657 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2658 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2659 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2660 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2661 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2662 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2663 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2664 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2668 ring->mmio_base = BSD_RING_BASE;
2669 ring->flush = bsd_ring_flush;
2670 ring->add_request = i9xx_add_request;
2671 ring->get_seqno = ring_get_seqno;
2672 ring->set_seqno = ring_set_seqno;
2674 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2675 ring->irq_get = gen5_ring_get_irq;
2676 ring->irq_put = gen5_ring_put_irq;
2678 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2679 ring->irq_get = i9xx_ring_get_irq;
2680 ring->irq_put = i9xx_ring_put_irq;
2682 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2684 ring->init_hw = init_ring_common;
2686 return intel_init_ring_buffer(dev, ring);
2690 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2692 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2697 ring->name = "bsd2 ring";
2700 ring->write_tail = ring_write_tail;
2701 ring->mmio_base = GEN8_BSD2_RING_BASE;
2702 ring->flush = gen6_bsd_ring_flush;
2703 ring->add_request = gen6_add_request;
2704 ring->get_seqno = gen6_ring_get_seqno;
2705 ring->set_seqno = ring_set_seqno;
2706 ring->irq_enable_mask =
2707 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2708 ring->irq_get = gen8_ring_get_irq;
2709 ring->irq_put = gen8_ring_put_irq;
2710 ring->dispatch_execbuffer =
2711 gen8_ring_dispatch_execbuffer;
2712 if (i915_semaphore_is_enabled(dev)) {
2713 ring->semaphore.sync_to = gen8_ring_sync;
2714 ring->semaphore.signal = gen8_xcs_signal;
2715 GEN8_RING_SEMAPHORE_INIT;
2717 ring->init_hw = init_ring_common;
2719 return intel_init_ring_buffer(dev, ring);
2722 int intel_init_blt_ring_buffer(struct drm_device *dev)
2724 struct drm_i915_private *dev_priv = dev->dev_private;
2725 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2727 ring->name = "blitter ring";
2730 ring->mmio_base = BLT_RING_BASE;
2731 ring->write_tail = ring_write_tail;
2732 ring->flush = gen6_ring_flush;
2733 ring->add_request = gen6_add_request;
2734 ring->get_seqno = gen6_ring_get_seqno;
2735 ring->set_seqno = ring_set_seqno;
2736 if (INTEL_INFO(dev)->gen >= 8) {
2737 ring->irq_enable_mask =
2738 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2739 ring->irq_get = gen8_ring_get_irq;
2740 ring->irq_put = gen8_ring_put_irq;
2741 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2742 if (i915_semaphore_is_enabled(dev)) {
2743 ring->semaphore.sync_to = gen8_ring_sync;
2744 ring->semaphore.signal = gen8_xcs_signal;
2745 GEN8_RING_SEMAPHORE_INIT;
2748 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2749 ring->irq_get = gen6_ring_get_irq;
2750 ring->irq_put = gen6_ring_put_irq;
2751 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2752 if (i915_semaphore_is_enabled(dev)) {
2753 ring->semaphore.signal = gen6_signal;
2754 ring->semaphore.sync_to = gen6_ring_sync;
2756 * The current semaphore is only applied on pre-gen8
2757 * platform. And there is no VCS2 ring on the pre-gen8
2758 * platform. So the semaphore between BCS and VCS2 is
2759 * initialized as INVALID. Gen8 will initialize the
2760 * sema between BCS and VCS2 later.
2762 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2763 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2764 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2765 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2766 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2767 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2768 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2769 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2770 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2771 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2774 ring->init_hw = init_ring_common;
2776 return intel_init_ring_buffer(dev, ring);
2779 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2784 ring->name = "video enhancement ring";
2787 ring->mmio_base = VEBOX_RING_BASE;
2788 ring->write_tail = ring_write_tail;
2789 ring->flush = gen6_ring_flush;
2790 ring->add_request = gen6_add_request;
2791 ring->get_seqno = gen6_ring_get_seqno;
2792 ring->set_seqno = ring_set_seqno;
2794 if (INTEL_INFO(dev)->gen >= 8) {
2795 ring->irq_enable_mask =
2796 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2797 ring->irq_get = gen8_ring_get_irq;
2798 ring->irq_put = gen8_ring_put_irq;
2799 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2800 if (i915_semaphore_is_enabled(dev)) {
2801 ring->semaphore.sync_to = gen8_ring_sync;
2802 ring->semaphore.signal = gen8_xcs_signal;
2803 GEN8_RING_SEMAPHORE_INIT;
2806 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2807 ring->irq_get = hsw_vebox_get_irq;
2808 ring->irq_put = hsw_vebox_put_irq;
2809 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2810 if (i915_semaphore_is_enabled(dev)) {
2811 ring->semaphore.sync_to = gen6_ring_sync;
2812 ring->semaphore.signal = gen6_signal;
2813 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2814 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2815 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2816 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2817 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2818 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2819 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2820 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2821 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2822 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2825 ring->init_hw = init_ring_common;
2827 return intel_init_ring_buffer(dev, ring);
2831 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2835 if (!ring->gpu_caches_dirty)
2838 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2842 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2844 ring->gpu_caches_dirty = false;
2849 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2851 uint32_t flush_domains;
2855 if (ring->gpu_caches_dirty)
2856 flush_domains = I915_GEM_GPU_DOMAINS;
2858 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2862 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2864 ring->gpu_caches_dirty = false;
2869 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2873 if (!intel_ring_initialized(ring))
2876 ret = intel_ring_idle(ring);
2877 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2878 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",