drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct intel_engine_cs *ring,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         u32 cmd;
  99         int ret;
 100
 101         cmd = MI_FLUSH;
 102         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 103                 cmd |= MI_NO_WRITE_FLUSH;
 104
 105         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 106                 cmd |= MI_READ_FLUSH;
 107
 108         ret = intel_ring_begin(ring, 2);
 109         if (ret)
 110                 return ret;
 111
 112         intel_ring_emit(ring, cmd);
 113         intel_ring_emit(ring, MI_NOOP);
 114         intel_ring_advance(ring);
 115
 116         return 0;
 117 }
 118
 119 static int
 120 gen4_render_ring_flush(struct intel_engine_cs *ring,
 121                        u32      invalidate_domains,
 122                        u32      flush_domains)
 123 {
 124         struct drm_device *dev = ring->dev;
 125         u32 cmd;
 126         int ret;
 127
 128         /*
 129          * read/write caches:
 130          *
 131          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 132          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 133          * also flushed at 2d versus 3d pipeline switches.
 134          *
 135          * read-only caches:
 136          *
 137          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 138          * MI_READ_FLUSH is set, and is always flushed on 965.
 139          *
 140          * I915_GEM_DOMAIN_COMMAND may not exist?
 141          *
 142          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 143          * invalidated when MI_EXE_FLUSH is set.
 144          *
 145          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 146          * invalidated with every MI_FLUSH.
 147          *
 148          * TLBs:
 149          *
 150          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 151          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 152          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 153          * are flushed at any MI_FLUSH.
 154          */
 155
 156         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 157         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 158                 cmd &= ~MI_NO_WRITE_FLUSH;
 159         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 160                 cmd |= MI_EXE_FLUSH;
 161
 162         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 163             (IS_G4X(dev) || IS_GEN5(dev)))
 164                 cmd |= MI_INVALIDATE_ISP;
 165
 166         ret = intel_ring_begin(ring, 2);
 167         if (ret)
 168                 return ret;
 169
 170         intel_ring_emit(ring, cmd);
 171         intel_ring_emit(ring, MI_NOOP);
 172         intel_ring_advance(ring);
 173
 174         return 0;
 175 }
 176
 177 /**
 178  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 179  * implementing two workarounds on gen6.  From section 1.4.7.1
 180  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 181  *
 182  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 183  * produced by non-pipelined state commands), software needs to first
 184  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 185  * 0.
 186  *
 187  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 188  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 189  *
 190  * And the workaround for these two requires this workaround first:
 191  *
 192  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 193  * BEFORE the pipe-control with a post-sync op and no write-cache
 194  * flushes.
 195  *
 196  * And this last workaround is tricky because of the requirements on
 197  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 198  * volume 2 part 1:
 199  *
 200  *     "1 of the following must also be set:
 201  *      - Render Target Cache Flush Enable ([12] of DW1)
 202  *      - Depth Cache Flush Enable ([0] of DW1)
 203  *      - Stall at Pixel Scoreboard ([1] of DW1)
 204  *      - Depth Stall ([13] of DW1)
 205  *      - Post-Sync Operation ([13] of DW1)
 206  *      - Notify Enable ([8] of DW1)"
 207  *
 208  * The cache flushes require the workaround flush that triggered this
 209  * one, so we can't use it.  Depth stall would trigger the same.
 210  * Post-sync nonzero is what triggered this second workaround, so we
 211  * can't use that one either.  Notify enable is IRQs, which aren't
 212  * really our business.  That leaves only stall at scoreboard.
 213  */
 214 static int
 215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
 216 {
 217         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 218         int ret;
 219
 220
 221         ret = intel_ring_begin(ring, 6);
 222         if (ret)
 223                 return ret;
 224
 225         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 226         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 227                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 228         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 229         intel_ring_emit(ring, 0); /* low dword */
 230         intel_ring_emit(ring, 0); /* high dword */
 231         intel_ring_emit(ring, MI_NOOP);
 232         intel_ring_advance(ring);
 233
 234         ret = intel_ring_begin(ring, 6);
 235         if (ret)
 236                 return ret;
 237
 238         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 239         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 240         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 241         intel_ring_emit(ring, 0);
 242         intel_ring_emit(ring, 0);
 243         intel_ring_emit(ring, MI_NOOP);
 244         intel_ring_advance(ring);
 245
 246         return 0;
 247 }
 248
 249 static int
 250 gen6_render_ring_flush(struct intel_engine_cs *ring,
 251                          u32 invalidate_domains, u32 flush_domains)
 252 {
 253         u32 flags = 0;
 254         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 255         int ret;
 256
 257         /* Force SNB workarounds for PIPE_CONTROL flushes */
 258         ret = intel_emit_post_sync_nonzero_flush(ring);
 259         if (ret)
 260                 return ret;
 261
 262         /* Just flush everything.  Experiments have shown that reducing the
 263          * number of bits based on the write domains has little performance
 264          * impact.
 265          */
 266         if (flush_domains) {
 267                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 268                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 269                 /*
 270                  * Ensure that any following seqno writes only happen
 271                  * when the render cache is indeed flushed.
 272                  */
 273                 flags |= PIPE_CONTROL_CS_STALL;
 274         }
 275         if (invalidate_domains) {
 276                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 277                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 278                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 279                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 280                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 281                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 282                 /*
 283                  * TLB invalidate requires a post-sync write.
 284                  */
 285                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 286         }
 287
 288         ret = intel_ring_begin(ring, 4);
 289         if (ret)
 290                 return ret;
 291
 292         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 293         intel_ring_emit(ring, flags);
 294         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 295         intel_ring_emit(ring, 0);
 296         intel_ring_advance(ring);
 297
 298         return 0;
 299 }
 300
 301 static int
 302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
 303 {
 304         int ret;
 305
 306         ret = intel_ring_begin(ring, 4);
 307         if (ret)
 308                 return ret;
 309
 310         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 311         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 312                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 313         intel_ring_emit(ring, 0);
 314         intel_ring_emit(ring, 0);
 315         intel_ring_advance(ring);
 316
 317         return 0;
 318 }
 319
 320 static int
 321 gen7_render_ring_flush(struct intel_engine_cs *ring,
 322                        u32 invalidate_domains, u32 flush_domains)
 323 {
 324         u32 flags = 0;
 325         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 326         int ret;
 327
 328         /*
 329          * Ensure that any following seqno writes only happen when the render
 330          * cache is indeed flushed.
 331          *
 332          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 333          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 334          * don't try to be clever and just set it unconditionally.
 335          */
 336         flags |= PIPE_CONTROL_CS_STALL;
 337
 338         /* Just flush everything.  Experiments have shown that reducing the
 339          * number of bits based on the write domains has little performance
 340          * impact.
 341          */
 342         if (flush_domains) {
 343                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 344                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 345         }
 346         if (invalidate_domains) {
 347                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 348                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 349                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 350                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 351                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 352                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 353                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 354                 /*
 355                  * TLB invalidate requires a post-sync write.
 356                  */
 357                 flags |= PIPE_CONTROL_QW_WRITE;
 358                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 359
 360                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 361
 362                 /* Workaround: we must issue a pipe_control with CS-stall bit
 363                  * set before a pipe_control command that has the state cache
 364                  * invalidate bit set. */
 365                 gen7_render_ring_cs_stall_wa(ring);
 366         }
 367
 368         ret = intel_ring_begin(ring, 4);
 369         if (ret)
 370                 return ret;
 371
 372         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 373         intel_ring_emit(ring, flags);
 374         intel_ring_emit(ring, scratch_addr);
 375         intel_ring_emit(ring, 0);
 376         intel_ring_advance(ring);
 377
 378         return 0;
 379 }
 380
 381 static int
 382 gen8_emit_pipe_control(struct intel_engine_cs *ring,
 383                        u32 flags, u32 scratch_addr)
 384 {
 385         int ret;
 386
 387         ret = intel_ring_begin(ring, 6);
 388         if (ret)
 389                 return ret;
 390
 391         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 392         intel_ring_emit(ring, flags);
 393         intel_ring_emit(ring, scratch_addr);
 394         intel_ring_emit(ring, 0);
 395         intel_ring_emit(ring, 0);
 396         intel_ring_emit(ring, 0);
 397         intel_ring_advance(ring);
 398
 399         return 0;
 400 }
 401
 402 static int
 403 gen8_render_ring_flush(struct intel_engine_cs *ring,
 404                        u32 invalidate_domains, u32 flush_domains)
 405 {
 406         u32 flags = 0;
 407         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 408         int ret;
 409
 410         flags |= PIPE_CONTROL_CS_STALL;
 411
 412         if (flush_domains) {
 413                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 414                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 415         }
 416         if (invalidate_domains) {
 417                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 418                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 419                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 420                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 421                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 422                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 423                 flags |= PIPE_CONTROL_QW_WRITE;
 424                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 425
 426                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 427                 ret = gen8_emit_pipe_control(ring,
 428                                              PIPE_CONTROL_CS_STALL |
 429                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 430                                              0);
 431                 if (ret)
 432                         return ret;
 433         }
 434
 435         return gen8_emit_pipe_control(ring, flags, scratch_addr);
 436 }
 437
 438 static void ring_write_tail(struct intel_engine_cs *ring,
 439                             u32 value)
 440 {
 441         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 442         I915_WRITE_TAIL(ring, value);
 443 }
 444
 445 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 446 {
 447         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 448         u64 acthd;
 449
 450         if (INTEL_INFO(ring->dev)->gen >= 8)
 451                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 452                                          RING_ACTHD_UDW(ring->mmio_base));
 453         else if (INTEL_INFO(ring->dev)->gen >= 4)
 454                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 455         else
 456                 acthd = I915_READ(ACTHD);
 457
 458         return acthd;
 459 }
 460
 461 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 462 {
 463         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 464         u32 addr;
 465
 466         addr = dev_priv->status_page_dmah->busaddr;
 467         if (INTEL_INFO(ring->dev)->gen >= 4)
 468                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 469         I915_WRITE(HWS_PGA, addr);
 470 }
 471
 472 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 473 {
 474         struct drm_device *dev = ring->dev;
 475         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 476         u32 mmio = 0;
 477
 478         /* The ring status page addresses are no longer next to the rest of
 479          * the ring registers as of gen7.
 480          */
 481         if (IS_GEN7(dev)) {
 482                 switch (ring->id) {
 483                 case RCS:
 484                         mmio = RENDER_HWS_PGA_GEN7;
 485                         break;
 486                 case BCS:
 487                         mmio = BLT_HWS_PGA_GEN7;
 488                         break;
 489                 /*
 490                  * VCS2 actually doesn't exist on Gen7. Only shut up
 491                  * gcc switch check warning
 492                  */
 493                 case VCS2:
 494                 case VCS:
 495                         mmio = BSD_HWS_PGA_GEN7;
 496                         break;
 497                 case VECS:
 498                         mmio = VEBOX_HWS_PGA_GEN7;
 499                         break;
 500                 }
 501         } else if (IS_GEN6(ring->dev)) {
 502                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 503         } else {
 504                 /* XXX: gen8 returns to sanity */
 505                 mmio = RING_HWS_PGA(ring->mmio_base);
 506         }
 507
 508         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 509         POSTING_READ(mmio);
 510
 511         /*
 512          * Flush the TLB for this page
 513          *
 514          * FIXME: These two bits have disappeared on gen8, so a question
 515          * arises: do we still need this and if so how should we go about
 516          * invalidating the TLB?
 517          */
 518         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 519                 u32 reg = RING_INSTPM(ring->mmio_base);
 520
 521                 /* ring should be idle before issuing a sync flush*/
 522                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
 523
 524                 I915_WRITE(reg,
 525                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 526                                               INSTPM_SYNC_FLUSH));
 527                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 528                              1000))
 529                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 530                                   ring->name);
 531         }
 532 }
 533
 534 static bool stop_ring(struct intel_engine_cs *ring)
 535 {
 536         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 537
 538         if (!IS_GEN2(ring->dev)) {
 539                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 540                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 541                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 542                         /* Sometimes we observe that the idle flag is not
 543                          * set even though the ring is empty. So double
 544                          * check before giving up.
 545                          */
 546                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 547                                 return false;
 548                 }
 549         }
 550
 551         I915_WRITE_CTL(ring, 0);
 552         I915_WRITE_HEAD(ring, 0);
 553         ring->write_tail(ring, 0);
 554
 555         if (!IS_GEN2(ring->dev)) {
 556                 (void)I915_READ_CTL(ring);
 557                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 558         }
 559
 560         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 561 }
 562
 563 static int init_ring_common(struct intel_engine_cs *ring)
 564 {
 565         struct drm_device *dev = ring->dev;
 566         struct drm_i915_private *dev_priv = dev->dev_private;
 567         struct intel_ringbuffer *ringbuf = ring->buffer;
 568         struct drm_i915_gem_object *obj = ringbuf->obj;
 569         int ret = 0;
 570
 571         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 572
 573         if (!stop_ring(ring)) {
 574                 /* G45 ring initialization often fails to reset head to zero */
 575                 DRM_DEBUG_KMS("%s head not reset to zero "
 576                               "ctl %08x head %08x tail %08x start %08x\n",
 577                               ring->name,
 578                               I915_READ_CTL(ring),
 579                               I915_READ_HEAD(ring),
 580                               I915_READ_TAIL(ring),
 581                               I915_READ_START(ring));
 582
 583                 if (!stop_ring(ring)) {
 584                         DRM_ERROR("failed to set %s head to zero "
 585                                   "ctl %08x head %08x tail %08x start %08x\n",
 586                                   ring->name,
 587                                   I915_READ_CTL(ring),
 588                                   I915_READ_HEAD(ring),
 589                                   I915_READ_TAIL(ring),
 590                                   I915_READ_START(ring));
 591                         ret = -EIO;
 592                         goto out;
 593                 }
 594         }
 595
 596         if (I915_NEED_GFX_HWS(dev))
 597                 intel_ring_setup_status_page(ring);
 598         else
 599                 ring_setup_phys_status_page(ring);
 600
 601         /* Enforce ordering by reading HEAD register back */
 602         I915_READ_HEAD(ring);
 603
 604         /* Initialize the ring. This must happen _after_ we've cleared the ring
 605          * registers with the above sequence (the readback of the HEAD registers
 606          * also enforces ordering), otherwise the hw might lose the new ring
 607          * register values. */
 608         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 609
 610         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 611         if (I915_READ_HEAD(ring))
 612                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 613                           ring->name, I915_READ_HEAD(ring));
 614         I915_WRITE_HEAD(ring, 0);
 615         (void)I915_READ_HEAD(ring);
 616
 617         I915_WRITE_CTL(ring,
 618                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 619                         | RING_VALID);
 620
 621         /* If the head is still not zero, the ring is dead */
 622         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 623                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 624                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 625                 DRM_ERROR("%s initialization failed "
 626                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 627                           ring->name,
 628                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 629                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 630                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 631                 ret = -EIO;
 632                 goto out;
 633         }
 634
 635         ringbuf->last_retired_head = -1;
 636         ringbuf->head = I915_READ_HEAD(ring);
 637         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 638         intel_ring_update_space(ringbuf);
 639
 640         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 641
 642 out:
 643         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 644
 645         return ret;
 646 }
 647
 648 void
 649 intel_fini_pipe_control(struct intel_engine_cs *ring)
 650 {
 651         struct drm_device *dev = ring->dev;
 652
 653         if (ring->scratch.obj == NULL)
 654                 return;
 655
 656         if (INTEL_INFO(dev)->gen >= 5) {
 657                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 658                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 659         }
 660
 661         drm_gem_object_unreference(&ring->scratch.obj->base);
 662         ring->scratch.obj = NULL;
 663 }
 664
 665 int
 666 intel_init_pipe_control(struct intel_engine_cs *ring)
 667 {
 668         int ret;
 669
 670         WARN_ON(ring->scratch.obj);
 671
 672         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 673         if (ring->scratch.obj == NULL) {
 674                 DRM_ERROR("Failed to allocate seqno page\n");
 675                 ret = -ENOMEM;
 676                 goto err;
 677         }
 678
 679         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 680         if (ret)
 681                 goto err_unref;
 682
 683         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 684         if (ret)
 685                 goto err_unref;
 686
 687         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 688         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 689         if (ring->scratch.cpu_page == NULL) {
 690                 ret = -ENOMEM;
 691                 goto err_unpin;
 692         }
 693
 694         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 695                          ring->name, ring->scratch.gtt_offset);
 696         return 0;
 697
 698 err_unpin:
 699         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 700 err_unref:
 701         drm_gem_object_unreference(&ring->scratch.obj->base);
 702 err:
 703         return ret;
 704 }
 705
 706 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
 707                                        struct intel_context *ctx)
 708 {
 709         int ret, i;
 710         struct drm_device *dev = ring->dev;
 711         struct drm_i915_private *dev_priv = dev->dev_private;
 712         struct i915_workarounds *w = &dev_priv->workarounds;
 713
 714         if (WARN_ON_ONCE(w->count == 0))
 715                 return 0;
 716
 717         ring->gpu_caches_dirty = true;
 718         ret = intel_ring_flush_all_caches(ring);
 719         if (ret)
 720                 return ret;
 721
 722         ret = intel_ring_begin(ring, (w->count * 2 + 2));
 723         if (ret)
 724                 return ret;
 725
 726         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 727         for (i = 0; i < w->count; i++) {
 728                 intel_ring_emit(ring, w->reg[i].addr);
 729                 intel_ring_emit(ring, w->reg[i].value);
 730         }
 731         intel_ring_emit(ring, MI_NOOP);
 732
 733         intel_ring_advance(ring);
 734
 735         ring->gpu_caches_dirty = true;
 736         ret = intel_ring_flush_all_caches(ring);
 737         if (ret)
 738                 return ret;
 739
 740         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 741
 742         return 0;
 743 }
 744
 745 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
 746                               struct intel_context *ctx)
 747 {
 748         int ret;
 749
 750         ret = intel_ring_workarounds_emit(ring, ctx);
 751         if (ret != 0)
 752                 return ret;
 753
 754         ret = i915_gem_render_state_init(ring);
 755         if (ret)
 756                 DRM_ERROR("init render state: %d\n", ret);
 757
 758         return ret;
 759 }
 760
 761 static int wa_add(struct drm_i915_private *dev_priv,
 762                   const u32 addr, const u32 mask, const u32 val)
 763 {
 764         const u32 idx = dev_priv->workarounds.count;
 765
 766         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 767                 return -ENOSPC;
 768
 769         dev_priv->workarounds.reg[idx].addr = addr;
 770         dev_priv->workarounds.reg[idx].value = val;
 771         dev_priv->workarounds.reg[idx].mask = mask;
 772
 773         dev_priv->workarounds.count++;
 774
 775         return 0;
 776 }
 777
 778 #define WA_REG(addr, mask, val) { \
 779                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 780                 if (r) \
 781                         return r; \
 782         }
 783
 784 #define WA_SET_BIT_MASKED(addr, mask) \
 785         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 786
 787 #define WA_CLR_BIT_MASKED(addr, mask) \
 788         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 789
 790 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 791         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 792
 793 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 794 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 795
 796 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 797
 798 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 799 {
 800         struct drm_device *dev = ring->dev;
 801         struct drm_i915_private *dev_priv = dev->dev_private;
 802
 803         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 804
 805         /* WaDisableAsyncFlipPerfMode:bdw */
 806         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 807
 808         /* WaDisablePartialInstShootdown:bdw */
 809         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 810         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 811                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 812                           STALL_DOP_GATING_DISABLE);
 813
 814         /* WaDisableDopClockGating:bdw */
 815         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 816                           DOP_CLOCK_GATING_DISABLE);
 817
 818         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 819                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 820
 821         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 822          * workaround for for a possible hang in the unlikely event a TLB
 823          * invalidation occurs during a PSD flush.
 824          */
 825         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 826                           /* WaForceEnableNonCoherent:bdw */
 827                           HDC_FORCE_NON_COHERENT |
 828                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 829                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 830                           /* WaHdcDisableFetchWhenMasked:bdw */
 831                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 832                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 833                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 834
 835         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 836          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 837          *  polygons in the same 8x4 pixel/sample area to be processed without
 838          *  stalling waiting for the earlier ones to write to Hierarchical Z
 839          *  buffer."
 840          *
 841          * This optimization is off by default for Broadwell; turn it on.
 842          */
 843         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 844
 845         /* Wa4x4STCOptimizationDisable:bdw */
 846         WA_SET_BIT_MASKED(CACHE_MODE_1,
 847                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 848
 849         /*
 850          * BSpec recommends 8x4 when MSAA is used,
 851          * however in practice 16x4 seems fastest.
 852          *
 853          * Note that PS/WM thread counts depend on the WIZ hashing
 854          * disable bit, which we don't touch here, but it's good
 855          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 856          */
 857         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 858                             GEN6_WIZ_HASHING_MASK,
 859                             GEN6_WIZ_HASHING_16x4);
 860
 861         return 0;
 862 }
 863
 864 static int chv_init_workarounds(struct intel_engine_cs *ring)
 865 {
 866         struct drm_device *dev = ring->dev;
 867         struct drm_i915_private *dev_priv = dev->dev_private;
 868
 869         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 870
 871         /* WaDisableAsyncFlipPerfMode:chv */
 872         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 873
 874         /* WaDisablePartialInstShootdown:chv */
 875         /* WaDisableThreadStallDopClockGating:chv */
 876         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 877                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 878                           STALL_DOP_GATING_DISABLE);
 879
 880         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 881          * workaround for a possible hang in the unlikely event a TLB
 882          * invalidation occurs during a PSD flush.
 883          */
 884         /* WaForceEnableNonCoherent:chv */
 885         /* WaHdcDisableFetchWhenMasked:chv */
 886         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 887                           HDC_FORCE_NON_COHERENT |
 888                           HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 889
 890         /* According to the CACHE_MODE_0 default value documentation, some
 891          * CHV platforms disable this optimization by default.  Turn it on.
 892          */
 893         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 894
 895         /* Wa4x4STCOptimizationDisable:chv */
 896         WA_SET_BIT_MASKED(CACHE_MODE_1,
 897                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 898
 899         /* Improve HiZ throughput on CHV. */
 900         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 901
 902         /*
 903          * BSpec recommends 8x4 when MSAA is used,
 904          * however in practice 16x4 seems fastest.
 905          *
 906          * Note that PS/WM thread counts depend on the WIZ hashing
 907          * disable bit, which we don't touch here, but it's good
 908          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 909          */
 910         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 911                             GEN6_WIZ_HASHING_MASK,
 912                             GEN6_WIZ_HASHING_16x4);
 913
 914         return 0;
 915 }
 916
 917 static int gen9_init_workarounds(struct intel_engine_cs *ring)
 918 {
 919         struct drm_device *dev = ring->dev;
 920         struct drm_i915_private *dev_priv = dev->dev_private;
 921         uint32_t tmp;
 922
 923         /* WaDisablePartialInstShootdown:skl,bxt */
 924         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 925                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 926
 927         /* Syncing dependencies between camera and graphics:skl,bxt */
 928         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 929                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 930
 931         if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
 932             INTEL_REVID(dev) == SKL_REVID_B0)) ||
 933             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
 934                 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 935                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 936                                   GEN9_DG_MIRROR_FIX_ENABLE);
 937         }
 938
 939         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
 940             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
 941                 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 942                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 943                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 944                 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
 945                                   DISABLE_PIXEL_MASK_CAMMING);
 946         }
 947
 948         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
 949             IS_BROXTON(dev)) {
 950                 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 951                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 952                                   GEN9_ENABLE_YV12_BUGFIX);
 953         }
 954
 955         /* Wa4x4STCOptimizationDisable:skl,bxt */
 956         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 957
 958         /* WaDisablePartialResolveInVc:skl,bxt */
 959         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 960
 961         /* WaCcsTlbPrefetchDisable:skl,bxt */
 962         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 963                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 964
 965         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 966         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
 967             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
 968                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 969                                   PIXEL_MASK_CAMMING_DISABLE);
 970
 971         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 972         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 973         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
 974             (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
 975                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 976         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 977
 978         return 0;
 979 }
 980
 981 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
 982 {
 983         struct drm_device *dev = ring->dev;
 984         struct drm_i915_private *dev_priv = dev->dev_private;
 985         u8 vals[3] = { 0, 0, 0 };
 986         unsigned int i;
 987
 988         for (i = 0; i < 3; i++) {
 989                 u8 ss;
 990
 991                 /*
 992                  * Only consider slices where one, and only one, subslice has 7
 993                  * EUs
 994                  */
 995                 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
 996                         continue;
 997
 998                 /*
 999                  * subslice_7eu[i] != 0 (because of the check above) and
1000                  * ss_max == 4 (maximum number of subslices possible per slice)
1001                  *
1002                  * ->    0 <= ss <= 3;
1003                  */
1004                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1005                 vals[i] = 3 - ss;
1006         }
1007
1008         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1009                 return 0;
1010
1011         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1012         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1013                             GEN9_IZ_HASHING_MASK(2) |
1014                             GEN9_IZ_HASHING_MASK(1) |
1015                             GEN9_IZ_HASHING_MASK(0),
1016                             GEN9_IZ_HASHING(2, vals[2]) |
1017                             GEN9_IZ_HASHING(1, vals[1]) |
1018                             GEN9_IZ_HASHING(0, vals[0]));
1019
1020         return 0;
1021 }
1022
1023
1024 static int skl_init_workarounds(struct intel_engine_cs *ring)
1025 {
1026         struct drm_device *dev = ring->dev;
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028
1029         gen9_init_workarounds(ring);
1030
1031         /* WaDisablePowerCompilerClockGating:skl */
1032         if (INTEL_REVID(dev) == SKL_REVID_B0)
1033                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1034                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1035
1036         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1037                 /*
1038                  *Use Force Non-Coherent whenever executing a 3D context. This
1039                  * is a workaround for a possible hang in the unlikely event
1040                  * a TLB invalidation occurs during a PSD flush.
1041                  */
1042                 /* WaForceEnableNonCoherent:skl */
1043                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1044                                   HDC_FORCE_NON_COHERENT);
1045         }
1046
1047         if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1048             INTEL_REVID(dev) == SKL_REVID_D0)
1049                 /* WaBarrierPerformanceFixDisable:skl */
1050                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1051                                   HDC_FENCE_DEST_SLM_DISABLE |
1052                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1053
1054         return skl_tune_iz_hashing(ring);
1055 }
1056
1057 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1058 {
1059         struct drm_device *dev = ring->dev;
1060         struct drm_i915_private *dev_priv = dev->dev_private;
1061
1062         gen9_init_workarounds(ring);
1063
1064         /* WaDisableThreadStallDopClockGating:bxt */
1065         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1066                           STALL_DOP_GATING_DISABLE);
1067
1068         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1069         if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1070                 WA_SET_BIT_MASKED(
1071                         GEN7_HALF_SLICE_CHICKEN1,
1072                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1073         }
1074
1075         return 0;
1076 }
1077
1078 int init_workarounds_ring(struct intel_engine_cs *ring)
1079 {
1080         struct drm_device *dev = ring->dev;
1081         struct drm_i915_private *dev_priv = dev->dev_private;
1082
1083         WARN_ON(ring->id != RCS);
1084
1085         dev_priv->workarounds.count = 0;
1086
1087         if (IS_BROADWELL(dev))
1088                 return bdw_init_workarounds(ring);
1089
1090         if (IS_CHERRYVIEW(dev))
1091                 return chv_init_workarounds(ring);
1092
1093         if (IS_SKYLAKE(dev))
1094                 return skl_init_workarounds(ring);
1095
1096         if (IS_BROXTON(dev))
1097                 return bxt_init_workarounds(ring);
1098
1099         return 0;
1100 }
1101
1102 static int init_render_ring(struct intel_engine_cs *ring)
1103 {
1104         struct drm_device *dev = ring->dev;
1105         struct drm_i915_private *dev_priv = dev->dev_private;
1106         int ret = init_ring_common(ring);
1107         if (ret)
1108                 return ret;
1109
1110         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1111         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1112                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1113
1114         /* We need to disable the AsyncFlip performance optimisations in order
1115          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1116          * programmed to '1' on all products.
1117          *
1118          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1119          */
1120         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1121                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1122
1123         /* Required for the hardware to program scanline values for waiting */
1124         /* WaEnableFlushTlbInvalidationMode:snb */
1125         if (INTEL_INFO(dev)->gen == 6)
1126                 I915_WRITE(GFX_MODE,
1127                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1128
1129         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1130         if (IS_GEN7(dev))
1131                 I915_WRITE(GFX_MODE_GEN7,
1132                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1133                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1134
1135         if (IS_GEN6(dev)) {
1136                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1137                  * "If this bit is set, STCunit will have LRA as replacement
1138                  *  policy. [...] This bit must be reset.  LRA replacement
1139                  *  policy is not supported."
1140                  */
1141                 I915_WRITE(CACHE_MODE_0,
1142                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1143         }
1144
1145         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1146                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1147
1148         if (HAS_L3_DPF(dev))
1149                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1150
1151         return init_workarounds_ring(ring);
1152 }
1153
1154 static void render_ring_cleanup(struct intel_engine_cs *ring)
1155 {
1156         struct drm_device *dev = ring->dev;
1157         struct drm_i915_private *dev_priv = dev->dev_private;
1158
1159         if (dev_priv->semaphore_obj) {
1160                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1161                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1162                 dev_priv->semaphore_obj = NULL;
1163         }
1164
1165         intel_fini_pipe_control(ring);
1166 }
1167
1168 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1169                            unsigned int num_dwords)
1170 {
1171 #define MBOX_UPDATE_DWORDS 8
1172         struct drm_device *dev = signaller->dev;
1173         struct drm_i915_private *dev_priv = dev->dev_private;
1174         struct intel_engine_cs *waiter;
1175         int i, ret, num_rings;
1176
1177         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1178         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1179 #undef MBOX_UPDATE_DWORDS
1180
1181         ret = intel_ring_begin(signaller, num_dwords);
1182         if (ret)
1183                 return ret;
1184
1185         for_each_ring(waiter, dev_priv, i) {
1186                 u32 seqno;
1187                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1188                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1189                         continue;
1190
1191                 seqno = i915_gem_request_get_seqno(
1192                                            signaller->outstanding_lazy_request);
1193                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1194                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1195                                            PIPE_CONTROL_QW_WRITE |
1196                                            PIPE_CONTROL_FLUSH_ENABLE);
1197                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1198                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1199                 intel_ring_emit(signaller, seqno);
1200                 intel_ring_emit(signaller, 0);
1201                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1202                                            MI_SEMAPHORE_TARGET(waiter->id));
1203                 intel_ring_emit(signaller, 0);
1204         }
1205
1206         return 0;
1207 }
1208
1209 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1210                            unsigned int num_dwords)
1211 {
1212 #define MBOX_UPDATE_DWORDS 6
1213         struct drm_device *dev = signaller->dev;
1214         struct drm_i915_private *dev_priv = dev->dev_private;
1215         struct intel_engine_cs *waiter;
1216         int i, ret, num_rings;
1217
1218         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1219         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1220 #undef MBOX_UPDATE_DWORDS
1221
1222         ret = intel_ring_begin(signaller, num_dwords);
1223         if (ret)
1224                 return ret;
1225
1226         for_each_ring(waiter, dev_priv, i) {
1227                 u32 seqno;
1228                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1229                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1230                         continue;
1231
1232                 seqno = i915_gem_request_get_seqno(
1233                                            signaller->outstanding_lazy_request);
1234                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1235                                            MI_FLUSH_DW_OP_STOREDW);
1236                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1237                                            MI_FLUSH_DW_USE_GTT);
1238                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1239                 intel_ring_emit(signaller, seqno);
1240                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1241                                            MI_SEMAPHORE_TARGET(waiter->id));
1242                 intel_ring_emit(signaller, 0);
1243         }
1244
1245         return 0;
1246 }
1247
1248 static int gen6_signal(struct intel_engine_cs *signaller,
1249                        unsigned int num_dwords)
1250 {
1251         struct drm_device *dev = signaller->dev;
1252         struct drm_i915_private *dev_priv = dev->dev_private;
1253         struct intel_engine_cs *useless;
1254         int i, ret, num_rings;
1255
1256 #define MBOX_UPDATE_DWORDS 3
1257         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1258         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1259 #undef MBOX_UPDATE_DWORDS
1260
1261         ret = intel_ring_begin(signaller, num_dwords);
1262         if (ret)
1263                 return ret;
1264
1265         for_each_ring(useless, dev_priv, i) {
1266                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1267                 if (mbox_reg != GEN6_NOSYNC) {
1268                         u32 seqno = i915_gem_request_get_seqno(
1269                                            signaller->outstanding_lazy_request);
1270                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1271                         intel_ring_emit(signaller, mbox_reg);
1272                         intel_ring_emit(signaller, seqno);
1273                 }
1274         }
1275
1276         /* If num_dwords was rounded, make sure the tail pointer is correct */
1277         if (num_rings % 2 == 0)
1278                 intel_ring_emit(signaller, MI_NOOP);
1279
1280         return 0;
1281 }
1282
1283 /**
1284  * gen6_add_request - Update the semaphore mailbox registers
1285  *
1286  * @ring - ring that is adding a request
1287  * @seqno - return seqno stuck into the ring
1288  *
1289  * Update the mailbox registers in the *other* rings with the current seqno.
1290  * This acts like a signal in the canonical semaphore.
1291  */
1292 static int
1293 gen6_add_request(struct intel_engine_cs *ring)
1294 {
1295         int ret;
1296
1297         if (ring->semaphore.signal)
1298                 ret = ring->semaphore.signal(ring, 4);
1299         else
1300                 ret = intel_ring_begin(ring, 4);
1301
1302         if (ret)
1303                 return ret;
1304
1305         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1306         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1307         intel_ring_emit(ring,
1308                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1309         intel_ring_emit(ring, MI_USER_INTERRUPT);
1310         __intel_ring_advance(ring);
1311
1312         return 0;
1313 }
1314
1315 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1316                                               u32 seqno)
1317 {
1318         struct drm_i915_private *dev_priv = dev->dev_private;
1319         return dev_priv->last_seqno < seqno;
1320 }
1321
1322 /**
1323  * intel_ring_sync - sync the waiter to the signaller on seqno
1324  *
1325  * @waiter - ring that is waiting
1326  * @signaller - ring which has, or will signal
1327  * @seqno - seqno which the waiter will block on
1328  */
1329
1330 static int
1331 gen8_ring_sync(struct intel_engine_cs *waiter,
1332                struct intel_engine_cs *signaller,
1333                u32 seqno)
1334 {
1335         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1336         int ret;
1337
1338         ret = intel_ring_begin(waiter, 4);
1339         if (ret)
1340                 return ret;
1341
1342         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1343                                 MI_SEMAPHORE_GLOBAL_GTT |
1344                                 MI_SEMAPHORE_POLL |
1345                                 MI_SEMAPHORE_SAD_GTE_SDD);
1346         intel_ring_emit(waiter, seqno);
1347         intel_ring_emit(waiter,
1348                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1349         intel_ring_emit(waiter,
1350                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1351         intel_ring_advance(waiter);
1352         return 0;
1353 }
1354
1355 static int
1356 gen6_ring_sync(struct intel_engine_cs *waiter,
1357                struct intel_engine_cs *signaller,
1358                u32 seqno)
1359 {
1360         u32 dw1 = MI_SEMAPHORE_MBOX |
1361                   MI_SEMAPHORE_COMPARE |
1362                   MI_SEMAPHORE_REGISTER;
1363         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1364         int ret;
1365
1366         /* Throughout all of the GEM code, seqno passed implies our current
1367          * seqno is >= the last seqno executed. However for hardware the
1368          * comparison is strictly greater than.
1369          */
1370         seqno -= 1;
1371
1372         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1373
1374         ret = intel_ring_begin(waiter, 4);
1375         if (ret)
1376                 return ret;
1377
1378         /* If seqno wrap happened, omit the wait with no-ops */
1379         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1380                 intel_ring_emit(waiter, dw1 | wait_mbox);
1381                 intel_ring_emit(waiter, seqno);
1382                 intel_ring_emit(waiter, 0);
1383                 intel_ring_emit(waiter, MI_NOOP);
1384         } else {
1385                 intel_ring_emit(waiter, MI_NOOP);
1386                 intel_ring_emit(waiter, MI_NOOP);
1387                 intel_ring_emit(waiter, MI_NOOP);
1388                 intel_ring_emit(waiter, MI_NOOP);
1389         }
1390         intel_ring_advance(waiter);
1391
1392         return 0;
1393 }
1394
1395 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1396 do {                                                                    \
1397         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1398                  PIPE_CONTROL_DEPTH_STALL);                             \
1399         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1400         intel_ring_emit(ring__, 0);                                                     \
1401         intel_ring_emit(ring__, 0);                                                     \
1402 } while (0)
1403
1404 static int
1405 pc_render_add_request(struct intel_engine_cs *ring)
1406 {
1407         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1408         int ret;
1409
1410         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1411          * incoherent with writes to memory, i.e. completely fubar,
1412          * so we need to use PIPE_NOTIFY instead.
1413          *
1414          * However, we also need to workaround the qword write
1415          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1416          * memory before requesting an interrupt.
1417          */
1418         ret = intel_ring_begin(ring, 32);
1419         if (ret)
1420                 return ret;
1421
1422         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1423                         PIPE_CONTROL_WRITE_FLUSH |
1424                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1425         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1426         intel_ring_emit(ring,
1427                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1428         intel_ring_emit(ring, 0);
1429         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1430         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1431         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1432         scratch_addr += 2 * CACHELINE_BYTES;
1433         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1434         scratch_addr += 2 * CACHELINE_BYTES;
1435         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1436         scratch_addr += 2 * CACHELINE_BYTES;
1437         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1438         scratch_addr += 2 * CACHELINE_BYTES;
1439         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1440
1441         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1442                         PIPE_CONTROL_WRITE_FLUSH |
1443                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1444                         PIPE_CONTROL_NOTIFY);
1445         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1446         intel_ring_emit(ring,
1447                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1448         intel_ring_emit(ring, 0);
1449         __intel_ring_advance(ring);
1450
1451         return 0;
1452 }
1453
1454 static u32
1455 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1456 {
1457         /* Workaround to force correct ordering between irq and seqno writes on
1458          * ivb (and maybe also on snb) by reading from a CS register (like
1459          * ACTHD) before reading the status page. */
1460         if (!lazy_coherency) {
1461                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1462                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1463         }
1464
1465         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1466 }
1467
1468 static u32
1469 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1470 {
1471         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1472 }
1473
1474 static void
1475 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1476 {
1477         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1478 }
1479
1480 static u32
1481 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1482 {
1483         return ring->scratch.cpu_page[0];
1484 }
1485
1486 static void
1487 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1488 {
1489         ring->scratch.cpu_page[0] = seqno;
1490 }
1491
1492 static bool
1493 gen5_ring_get_irq(struct intel_engine_cs *ring)
1494 {
1495         struct drm_device *dev = ring->dev;
1496         struct drm_i915_private *dev_priv = dev->dev_private;
1497         unsigned long flags;
1498
1499         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1500                 return false;
1501
1502         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1503         if (ring->irq_refcount++ == 0)
1504                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1505         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1506
1507         return true;
1508 }
1509
1510 static void
1511 gen5_ring_put_irq(struct intel_engine_cs *ring)
1512 {
1513         struct drm_device *dev = ring->dev;
1514         struct drm_i915_private *dev_priv = dev->dev_private;
1515         unsigned long flags;
1516
1517         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1518         if (--ring->irq_refcount == 0)
1519                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1520         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1521 }
1522
1523 static bool
1524 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1525 {
1526         struct drm_device *dev = ring->dev;
1527         struct drm_i915_private *dev_priv = dev->dev_private;
1528         unsigned long flags;
1529
1530         if (!intel_irqs_enabled(dev_priv))
1531                 return false;
1532
1533         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1534         if (ring->irq_refcount++ == 0) {
1535                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1536                 I915_WRITE(IMR, dev_priv->irq_mask);
1537                 POSTING_READ(IMR);
1538         }
1539         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1540
1541         return true;
1542 }
1543
1544 static void
1545 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1546 {
1547         struct drm_device *dev = ring->dev;
1548         struct drm_i915_private *dev_priv = dev->dev_private;
1549         unsigned long flags;
1550
1551         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1552         if (--ring->irq_refcount == 0) {
1553                 dev_priv->irq_mask |= ring->irq_enable_mask;
1554                 I915_WRITE(IMR, dev_priv->irq_mask);
1555                 POSTING_READ(IMR);
1556         }
1557         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1558 }
1559
1560 static bool
1561 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1562 {
1563         struct drm_device *dev = ring->dev;
1564         struct drm_i915_private *dev_priv = dev->dev_private;
1565         unsigned long flags;
1566
1567         if (!intel_irqs_enabled(dev_priv))
1568                 return false;
1569
1570         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1571         if (ring->irq_refcount++ == 0) {
1572                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1573                 I915_WRITE16(IMR, dev_priv->irq_mask);
1574                 POSTING_READ16(IMR);
1575         }
1576         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1577
1578         return true;
1579 }
1580
1581 static void
1582 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1583 {
1584         struct drm_device *dev = ring->dev;
1585         struct drm_i915_private *dev_priv = dev->dev_private;
1586         unsigned long flags;
1587
1588         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1589         if (--ring->irq_refcount == 0) {
1590                 dev_priv->irq_mask |= ring->irq_enable_mask;
1591                 I915_WRITE16(IMR, dev_priv->irq_mask);
1592                 POSTING_READ16(IMR);
1593         }
1594         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1595 }
1596
1597 static int
1598 bsd_ring_flush(struct intel_engine_cs *ring,
1599                u32     invalidate_domains,
1600                u32     flush_domains)
1601 {
1602         int ret;
1603
1604         ret = intel_ring_begin(ring, 2);
1605         if (ret)
1606                 return ret;
1607
1608         intel_ring_emit(ring, MI_FLUSH);
1609         intel_ring_emit(ring, MI_NOOP);
1610         intel_ring_advance(ring);
1611         return 0;
1612 }
1613
1614 static int
1615 i9xx_add_request(struct intel_engine_cs *ring)
1616 {
1617         int ret;
1618
1619         ret = intel_ring_begin(ring, 4);
1620         if (ret)
1621                 return ret;
1622
1623         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1624         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1625         intel_ring_emit(ring,
1626                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1627         intel_ring_emit(ring, MI_USER_INTERRUPT);
1628         __intel_ring_advance(ring);
1629
1630         return 0;
1631 }
1632
1633 static bool
1634 gen6_ring_get_irq(struct intel_engine_cs *ring)
1635 {
1636         struct drm_device *dev = ring->dev;
1637         struct drm_i915_private *dev_priv = dev->dev_private;
1638         unsigned long flags;
1639
1640         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1641                 return false;
1642
1643         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1644         if (ring->irq_refcount++ == 0) {
1645                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1646                         I915_WRITE_IMR(ring,
1647                                        ~(ring->irq_enable_mask |
1648                                          GT_PARITY_ERROR(dev)));
1649                 else
1650                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1651                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1652         }
1653         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1654
1655         return true;
1656 }
1657
1658 static void
1659 gen6_ring_put_irq(struct intel_engine_cs *ring)
1660 {
1661         struct drm_device *dev = ring->dev;
1662         struct drm_i915_private *dev_priv = dev->dev_private;
1663         unsigned long flags;
1664
1665         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1666         if (--ring->irq_refcount == 0) {
1667                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1668                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1669                 else
1670                         I915_WRITE_IMR(ring, ~0);
1671                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1672         }
1673         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1674 }
1675
1676 static bool
1677 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1678 {
1679         struct drm_device *dev = ring->dev;
1680         struct drm_i915_private *dev_priv = dev->dev_private;
1681         unsigned long flags;
1682
1683         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1684                 return false;
1685
1686         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1687         if (ring->irq_refcount++ == 0) {
1688                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1689                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1690         }
1691         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1692
1693         return true;
1694 }
1695
1696 static void
1697 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1698 {
1699         struct drm_device *dev = ring->dev;
1700         struct drm_i915_private *dev_priv = dev->dev_private;
1701         unsigned long flags;
1702
1703         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1704         if (--ring->irq_refcount == 0) {
1705                 I915_WRITE_IMR(ring, ~0);
1706                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1707         }
1708         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1709 }
1710
1711 static bool
1712 gen8_ring_get_irq(struct intel_engine_cs *ring)
1713 {
1714         struct drm_device *dev = ring->dev;
1715         struct drm_i915_private *dev_priv = dev->dev_private;
1716         unsigned long flags;
1717
1718         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1719                 return false;
1720
1721         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1722         if (ring->irq_refcount++ == 0) {
1723                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1724                         I915_WRITE_IMR(ring,
1725                                        ~(ring->irq_enable_mask |
1726                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1727                 } else {
1728                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1729                 }
1730                 POSTING_READ(RING_IMR(ring->mmio_base));
1731         }
1732         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1733
1734         return true;
1735 }
1736
1737 static void
1738 gen8_ring_put_irq(struct intel_engine_cs *ring)
1739 {
1740         struct drm_device *dev = ring->dev;
1741         struct drm_i915_private *dev_priv = dev->dev_private;
1742         unsigned long flags;
1743
1744         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1745         if (--ring->irq_refcount == 0) {
1746                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1747                         I915_WRITE_IMR(ring,
1748                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1749                 } else {
1750                         I915_WRITE_IMR(ring, ~0);
1751                 }
1752                 POSTING_READ(RING_IMR(ring->mmio_base));
1753         }
1754         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1755 }
1756
1757 static int
1758 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1759                          u64 offset, u32 length,
1760                          unsigned dispatch_flags)
1761 {
1762         int ret;
1763
1764         ret = intel_ring_begin(ring, 2);
1765         if (ret)
1766                 return ret;
1767
1768         intel_ring_emit(ring,
1769                         MI_BATCH_BUFFER_START |
1770                         MI_BATCH_GTT |
1771                         (dispatch_flags & I915_DISPATCH_SECURE ?
1772                          0 : MI_BATCH_NON_SECURE_I965));
1773         intel_ring_emit(ring, offset);
1774         intel_ring_advance(ring);
1775
1776         return 0;
1777 }
1778
1779 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1780 #define I830_BATCH_LIMIT (256*1024)
1781 #define I830_TLB_ENTRIES (2)
1782 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1783 static int
1784 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1785                          u64 offset, u32 len,
1786                          unsigned dispatch_flags)
1787 {
1788         u32 cs_offset = ring->scratch.gtt_offset;
1789         int ret;
1790
1791         ret = intel_ring_begin(ring, 6);
1792         if (ret)
1793                 return ret;
1794
1795         /* Evict the invalid PTE TLBs */
1796         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1797         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1798         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1799         intel_ring_emit(ring, cs_offset);
1800         intel_ring_emit(ring, 0xdeadbeef);
1801         intel_ring_emit(ring, MI_NOOP);
1802         intel_ring_advance(ring);
1803
1804         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1805                 if (len > I830_BATCH_LIMIT)
1806                         return -ENOSPC;
1807
1808                 ret = intel_ring_begin(ring, 6 + 2);
1809                 if (ret)
1810                         return ret;
1811
1812                 /* Blit the batch (which has now all relocs applied) to the
1813                  * stable batch scratch bo area (so that the CS never
1814                  * stumbles over its tlb invalidation bug) ...
1815                  */
1816                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1817                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1818                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1819                 intel_ring_emit(ring, cs_offset);
1820                 intel_ring_emit(ring, 4096);
1821                 intel_ring_emit(ring, offset);
1822
1823                 intel_ring_emit(ring, MI_FLUSH);
1824                 intel_ring_emit(ring, MI_NOOP);
1825                 intel_ring_advance(ring);
1826
1827                 /* ... and execute it. */
1828                 offset = cs_offset;
1829         }
1830
1831         ret = intel_ring_begin(ring, 4);
1832         if (ret)
1833                 return ret;
1834
1835         intel_ring_emit(ring, MI_BATCH_BUFFER);
1836         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1837                                         0 : MI_BATCH_NON_SECURE));
1838         intel_ring_emit(ring, offset + len - 8);
1839         intel_ring_emit(ring, MI_NOOP);
1840         intel_ring_advance(ring);
1841
1842         return 0;
1843 }
1844
1845 static int
1846 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1847                          u64 offset, u32 len,
1848                          unsigned dispatch_flags)
1849 {
1850         int ret;
1851
1852         ret = intel_ring_begin(ring, 2);
1853         if (ret)
1854                 return ret;
1855
1856         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1857         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1858                                         0 : MI_BATCH_NON_SECURE));
1859         intel_ring_advance(ring);
1860
1861         return 0;
1862 }
1863
1864 static void cleanup_status_page(struct intel_engine_cs *ring)
1865 {
1866         struct drm_i915_gem_object *obj;
1867
1868         obj = ring->status_page.obj;
1869         if (obj == NULL)
1870                 return;
1871
1872         kunmap(sg_page(obj->pages->sgl));
1873         i915_gem_object_ggtt_unpin(obj);
1874         drm_gem_object_unreference(&obj->base);
1875         ring->status_page.obj = NULL;
1876 }
1877
1878 static int init_status_page(struct intel_engine_cs *ring)
1879 {
1880         struct drm_i915_gem_object *obj;
1881
1882         if ((obj = ring->status_page.obj) == NULL) {
1883                 unsigned flags;
1884                 int ret;
1885
1886                 obj = i915_gem_alloc_object(ring->dev, 4096);
1887                 if (obj == NULL) {
1888                         DRM_ERROR("Failed to allocate status page\n");
1889                         return -ENOMEM;
1890                 }
1891
1892                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1893                 if (ret)
1894                         goto err_unref;
1895
1896                 flags = 0;
1897                 if (!HAS_LLC(ring->dev))
1898                         /* On g33, we cannot place HWS above 256MiB, so
1899                          * restrict its pinning to the low mappable arena.
1900                          * Though this restriction is not documented for
1901                          * gen4, gen5, or byt, they also behave similarly
1902                          * and hang if the HWS is placed at the top of the
1903                          * GTT. To generalise, it appears that all !llc
1904                          * platforms have issues with us placing the HWS
1905                          * above the mappable region (even though we never
1906                          * actualy map it).
1907                          */
1908                         flags |= PIN_MAPPABLE;
1909                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1910                 if (ret) {
1911 err_unref:
1912                         drm_gem_object_unreference(&obj->base);
1913                         return ret;
1914                 }
1915
1916                 ring->status_page.obj = obj;
1917         }
1918
1919         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1920         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1921         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1922
1923         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1924                         ring->name, ring->status_page.gfx_addr);
1925
1926         return 0;
1927 }
1928
1929 static int init_phys_status_page(struct intel_engine_cs *ring)
1930 {
1931         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1932
1933         if (!dev_priv->status_page_dmah) {
1934                 dev_priv->status_page_dmah =
1935                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1936                 if (!dev_priv->status_page_dmah)
1937                         return -ENOMEM;
1938         }
1939
1940         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1941         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1942
1943         return 0;
1944 }
1945
1946 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1947 {
1948         iounmap(ringbuf->virtual_start);
1949         ringbuf->virtual_start = NULL;
1950         i915_gem_object_ggtt_unpin(ringbuf->obj);
1951 }
1952
1953 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1954                                      struct intel_ringbuffer *ringbuf)
1955 {
1956         struct drm_i915_private *dev_priv = to_i915(dev);
1957         struct drm_i915_gem_object *obj = ringbuf->obj;
1958         int ret;
1959
1960         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1961         if (ret)
1962                 return ret;
1963
1964         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1965         if (ret) {
1966                 i915_gem_object_ggtt_unpin(obj);
1967                 return ret;
1968         }
1969
1970         ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1971                         i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1972         if (ringbuf->virtual_start == NULL) {
1973                 i915_gem_object_ggtt_unpin(obj);
1974                 return -EINVAL;
1975         }
1976
1977         return 0;
1978 }
1979
1980 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1981 {
1982         drm_gem_object_unreference(&ringbuf->obj->base);
1983         ringbuf->obj = NULL;
1984 }
1985
1986 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1987                                struct intel_ringbuffer *ringbuf)
1988 {
1989         struct drm_i915_gem_object *obj;
1990
1991         obj = NULL;
1992         if (!HAS_LLC(dev))
1993                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1994         if (obj == NULL)
1995                 obj = i915_gem_alloc_object(dev, ringbuf->size);
1996         if (obj == NULL)
1997                 return -ENOMEM;
1998
1999         /* mark ring buffers as read-only from GPU side by default */
2000         obj->gt_ro = 1;
2001
2002         ringbuf->obj = obj;
2003
2004         return 0;
2005 }
2006
2007 static int intel_init_ring_buffer(struct drm_device *dev,
2008                                   struct intel_engine_cs *ring)
2009 {
2010         struct intel_ringbuffer *ringbuf;
2011         int ret;
2012
2013         WARN_ON(ring->buffer);
2014
2015         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2016         if (!ringbuf)
2017                 return -ENOMEM;
2018         ring->buffer = ringbuf;
2019
2020         ring->dev = dev;
2021         INIT_LIST_HEAD(&ring->active_list);
2022         INIT_LIST_HEAD(&ring->request_list);
2023         INIT_LIST_HEAD(&ring->execlist_queue);
2024         i915_gem_batch_pool_init(dev, &ring->batch_pool);
2025         ringbuf->size = 32 * PAGE_SIZE;
2026         ringbuf->ring = ring;
2027         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2028
2029         init_waitqueue_head(&ring->irq_queue);
2030
2031         if (I915_NEED_GFX_HWS(dev)) {
2032                 ret = init_status_page(ring);
2033                 if (ret)
2034                         goto error;
2035         } else {
2036                 BUG_ON(ring->id != RCS);
2037                 ret = init_phys_status_page(ring);
2038                 if (ret)
2039                         goto error;
2040         }
2041
2042         WARN_ON(ringbuf->obj);
2043
2044         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2045         if (ret) {
2046                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2047                                 ring->name, ret);
2048                 goto error;
2049         }
2050
2051         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2052         if (ret) {
2053                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2054                                 ring->name, ret);
2055                 intel_destroy_ringbuffer_obj(ringbuf);
2056                 goto error;
2057         }
2058
2059         /* Workaround an erratum on the i830 which causes a hang if
2060          * the TAIL pointer points to within the last 2 cachelines
2061          * of the buffer.
2062          */
2063         ringbuf->effective_size = ringbuf->size;
2064         if (IS_I830(dev) || IS_845G(dev))
2065                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2066
2067         ret = i915_cmd_parser_init_ring(ring);
2068         if (ret)
2069                 goto error;
2070
2071         return 0;
2072
2073 error:
2074         kfree(ringbuf);
2075         ring->buffer = NULL;
2076         return ret;
2077 }
2078
2079 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2080 {
2081         struct drm_i915_private *dev_priv;
2082         struct intel_ringbuffer *ringbuf;
2083
2084         if (!intel_ring_initialized(ring))
2085                 return;
2086
2087         dev_priv = to_i915(ring->dev);
2088         ringbuf = ring->buffer;
2089
2090         intel_stop_ring_buffer(ring);
2091         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2092
2093         intel_unpin_ringbuffer_obj(ringbuf);
2094         intel_destroy_ringbuffer_obj(ringbuf);
2095         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2096
2097         if (ring->cleanup)
2098                 ring->cleanup(ring);
2099
2100         cleanup_status_page(ring);
2101
2102         i915_cmd_parser_fini_ring(ring);
2103         i915_gem_batch_pool_fini(&ring->batch_pool);
2104
2105         kfree(ringbuf);
2106         ring->buffer = NULL;
2107 }
2108
2109 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2110 {
2111         struct intel_ringbuffer *ringbuf = ring->buffer;
2112         struct drm_i915_gem_request *request;
2113         unsigned space;
2114         int ret;
2115
2116         /* The whole point of reserving space is to not wait! */
2117         WARN_ON(ringbuf->reserved_in_use);
2118
2119         if (intel_ring_space(ringbuf) >= n)
2120                 return 0;
2121
2122         list_for_each_entry(request, &ring->request_list, list) {
2123                 space = __intel_ring_space(request->postfix, ringbuf->tail,
2124                                            ringbuf->size);
2125                 if (space >= n)
2126                         break;
2127         }
2128
2129         if (WARN_ON(&request->list == &ring->request_list))
2130                 return -ENOSPC;
2131
2132         ret = i915_wait_request(request);
2133         if (ret)
2134                 return ret;
2135
2136         ringbuf->space = space;
2137         return 0;
2138 }
2139
2140 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2141 {
2142         uint32_t __iomem *virt;
2143         struct intel_ringbuffer *ringbuf = ring->buffer;
2144         int rem = ringbuf->size - ringbuf->tail;
2145
2146         /* Can't wrap if space has already been reserved! */
2147         WARN_ON(ringbuf->reserved_in_use);
2148
2149         if (ringbuf->space < rem) {
2150                 int ret = ring_wait_for_space(ring, rem);
2151                 if (ret)
2152                         return ret;
2153         }
2154
2155         virt = ringbuf->virtual_start + ringbuf->tail;
2156         rem /= 4;
2157         while (rem--)
2158                 iowrite32(MI_NOOP, virt++);
2159
2160         ringbuf->tail = 0;
2161         intel_ring_update_space(ringbuf);
2162
2163         return 0;
2164 }
2165
2166 int intel_ring_idle(struct intel_engine_cs *ring)
2167 {
2168         struct drm_i915_gem_request *req;
2169         int ret;
2170
2171         /* We need to add any requests required to flush the objects and ring */
2172         if (ring->outstanding_lazy_request) {
2173                 ret = i915_add_request(ring);
2174                 if (ret)
2175                         return ret;
2176         }
2177
2178         /* Wait upon the last request to be completed */
2179         if (list_empty(&ring->request_list))
2180                 return 0;
2181
2182         req = list_entry(ring->request_list.prev,
2183                         struct drm_i915_gem_request,
2184                         list);
2185
2186         /* Make sure we do not trigger any retires */
2187         return __i915_wait_request(req,
2188                                    atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2189                                    to_i915(ring->dev)->mm.interruptible,
2190                                    NULL, NULL);
2191 }
2192
2193 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2194 {
2195         request->ringbuf = request->ring->buffer;
2196         return 0;
2197 }
2198
2199 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2200 {
2201         /* NB: Until request management is fully tidied up and the OLR is
2202          * removed, there are too many ways for get false hits on this
2203          * anti-recursion check! */
2204         /*WARN_ON(ringbuf->reserved_size);*/
2205         WARN_ON(ringbuf->reserved_in_use);
2206
2207         ringbuf->reserved_size = size;
2208
2209         /*
2210          * Really need to call _begin() here but that currently leads to
2211          * recursion problems! This will be fixed later but for now just
2212          * return and hope for the best. Note that there is only a real
2213          * problem if the create of the request never actually calls _begin()
2214          * but if they are not submitting any work then why did they create
2215          * the request in the first place?
2216          */
2217 }
2218
2219 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2220 {
2221         WARN_ON(ringbuf->reserved_in_use);
2222
2223         ringbuf->reserved_size   = 0;
2224         ringbuf->reserved_in_use = false;
2225 }
2226
2227 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2228 {
2229         WARN_ON(ringbuf->reserved_in_use);
2230
2231         ringbuf->reserved_in_use = true;
2232         ringbuf->reserved_tail   = ringbuf->tail;
2233 }
2234
2235 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2236 {
2237         WARN_ON(!ringbuf->reserved_in_use);
2238         WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2239              "request reserved size too small: %d vs %d!\n",
2240              ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2241
2242         ringbuf->reserved_size   = 0;
2243         ringbuf->reserved_in_use = false;
2244 }
2245
2246 static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2247 {
2248         struct intel_ringbuffer *ringbuf = ring->buffer;
2249         int ret;
2250
2251         /*
2252          * Add on the reserved size to the request to make sure that after
2253          * the intended commands have been emitted, there is guaranteed to
2254          * still be enough free space to send them to the hardware.
2255          */
2256         if (!ringbuf->reserved_in_use)
2257                 bytes += ringbuf->reserved_size;
2258
2259         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2260                 ret = intel_wrap_ring_buffer(ring);
2261                 if (unlikely(ret))
2262                         return ret;
2263
2264                 if(ringbuf->reserved_size) {
2265                         uint32_t size = ringbuf->reserved_size;
2266
2267                         intel_ring_reserved_space_cancel(ringbuf);
2268                         intel_ring_reserved_space_reserve(ringbuf, size);
2269                 }
2270         }
2271
2272         if (unlikely(ringbuf->space < bytes)) {
2273                 ret = ring_wait_for_space(ring, bytes);
2274                 if (unlikely(ret))
2275                         return ret;
2276         }
2277
2278         return 0;
2279 }
2280
2281 int intel_ring_begin(struct intel_engine_cs *ring,
2282                      int num_dwords)
2283 {
2284         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2285         int ret;
2286
2287         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2288                                    dev_priv->mm.interruptible);
2289         if (ret)
2290                 return ret;
2291
2292         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2293         if (ret)
2294                 return ret;
2295
2296         /* Preallocate the olr before touching the ring */
2297         ret = i915_gem_request_alloc(ring, ring->default_context);
2298         if (ret)
2299                 return ret;
2300
2301         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2302         return 0;
2303 }
2304
2305 /* Align the ring tail to a cacheline boundary */
2306 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2307 {
2308         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2309         int ret;
2310
2311         if (num_dwords == 0)
2312                 return 0;
2313
2314         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2315         ret = intel_ring_begin(ring, num_dwords);
2316         if (ret)
2317                 return ret;
2318
2319         while (num_dwords--)
2320                 intel_ring_emit(ring, MI_NOOP);
2321
2322         intel_ring_advance(ring);
2323
2324         return 0;
2325 }
2326
2327 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2328 {
2329         struct drm_device *dev = ring->dev;
2330         struct drm_i915_private *dev_priv = dev->dev_private;
2331
2332         BUG_ON(ring->outstanding_lazy_request);
2333
2334         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2335                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2336                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2337                 if (HAS_VEBOX(dev))
2338                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2339         }
2340
2341         ring->set_seqno(ring, seqno);
2342         ring->hangcheck.seqno = seqno;
2343 }
2344
2345 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2346                                      u32 value)
2347 {
2348         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2349
2350        /* Every tail move must follow the sequence below */
2351
2352         /* Disable notification that the ring is IDLE. The GT
2353          * will then assume that it is busy and bring it out of rc6.
2354          */
2355         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2356                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2357
2358         /* Clear the context id. Here be magic! */
2359         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2360
2361         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2362         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2363                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2364                      50))
2365                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2366
2367         /* Now that the ring is fully powered up, update the tail */
2368         I915_WRITE_TAIL(ring, value);
2369         POSTING_READ(RING_TAIL(ring->mmio_base));
2370
2371         /* Let the ring send IDLE messages to the GT again,
2372          * and so let it sleep to conserve power when idle.
2373          */
2374         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2375                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2376 }
2377
2378 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2379                                u32 invalidate, u32 flush)
2380 {
2381         uint32_t cmd;
2382         int ret;
2383
2384         ret = intel_ring_begin(ring, 4);
2385         if (ret)
2386                 return ret;
2387
2388         cmd = MI_FLUSH_DW;
2389         if (INTEL_INFO(ring->dev)->gen >= 8)
2390                 cmd += 1;
2391
2392         /* We always require a command barrier so that subsequent
2393          * commands, such as breadcrumb interrupts, are strictly ordered
2394          * wrt the contents of the write cache being flushed to memory
2395          * (and thus being coherent from the CPU).
2396          */
2397         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2398
2399         /*
2400          * Bspec vol 1c.5 - video engine command streamer:
2401          * "If ENABLED, all TLBs will be invalidated once the flush
2402          * operation is complete. This bit is only valid when the
2403          * Post-Sync Operation field is a value of 1h or 3h."
2404          */
2405         if (invalidate & I915_GEM_GPU_DOMAINS)
2406                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2407
2408         intel_ring_emit(ring, cmd);
2409         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2410         if (INTEL_INFO(ring->dev)->gen >= 8) {
2411                 intel_ring_emit(ring, 0); /* upper addr */
2412                 intel_ring_emit(ring, 0); /* value */
2413         } else  {
2414                 intel_ring_emit(ring, 0);
2415                 intel_ring_emit(ring, MI_NOOP);
2416         }
2417         intel_ring_advance(ring);
2418         return 0;
2419 }
2420
2421 static int
2422 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2423                               u64 offset, u32 len,
2424                               unsigned dispatch_flags)
2425 {
2426         bool ppgtt = USES_PPGTT(ring->dev) &&
2427                         !(dispatch_flags & I915_DISPATCH_SECURE);
2428         int ret;
2429
2430         ret = intel_ring_begin(ring, 4);
2431         if (ret)
2432                 return ret;
2433
2434         /* FIXME(BDW): Address space and security selectors. */
2435         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2436         intel_ring_emit(ring, lower_32_bits(offset));
2437         intel_ring_emit(ring, upper_32_bits(offset));
2438         intel_ring_emit(ring, MI_NOOP);
2439         intel_ring_advance(ring);
2440
2441         return 0;
2442 }
2443
2444 static int
2445 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2446                              u64 offset, u32 len,
2447                              unsigned dispatch_flags)
2448 {
2449         int ret;
2450
2451         ret = intel_ring_begin(ring, 2);
2452         if (ret)
2453                 return ret;
2454
2455         intel_ring_emit(ring,
2456                         MI_BATCH_BUFFER_START |
2457                         (dispatch_flags & I915_DISPATCH_SECURE ?
2458                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2459         /* bit0-7 is the length on GEN6+ */
2460         intel_ring_emit(ring, offset);
2461         intel_ring_advance(ring);
2462
2463         return 0;
2464 }
2465
2466 static int
2467 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2468                               u64 offset, u32 len,
2469                               unsigned dispatch_flags)
2470 {
2471         int ret;
2472
2473         ret = intel_ring_begin(ring, 2);
2474         if (ret)
2475                 return ret;
2476
2477         intel_ring_emit(ring,
2478                         MI_BATCH_BUFFER_START |
2479                         (dispatch_flags & I915_DISPATCH_SECURE ?
2480                          0 : MI_BATCH_NON_SECURE_I965));
2481         /* bit0-7 is the length on GEN6+ */
2482         intel_ring_emit(ring, offset);
2483         intel_ring_advance(ring);
2484
2485         return 0;
2486 }
2487
2488 /* Blitter support (SandyBridge+) */
2489
2490 static int gen6_ring_flush(struct intel_engine_cs *ring,
2491                            u32 invalidate, u32 flush)
2492 {
2493         struct drm_device *dev = ring->dev;
2494         uint32_t cmd;
2495         int ret;
2496
2497         ret = intel_ring_begin(ring, 4);
2498         if (ret)
2499                 return ret;
2500
2501         cmd = MI_FLUSH_DW;
2502         if (INTEL_INFO(dev)->gen >= 8)
2503                 cmd += 1;
2504
2505         /* We always require a command barrier so that subsequent
2506          * commands, such as breadcrumb interrupts, are strictly ordered
2507          * wrt the contents of the write cache being flushed to memory
2508          * (and thus being coherent from the CPU).
2509          */
2510         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2511
2512         /*
2513          * Bspec vol 1c.3 - blitter engine command streamer:
2514          * "If ENABLED, all TLBs will be invalidated once the flush
2515          * operation is complete. This bit is only valid when the
2516          * Post-Sync Operation field is a value of 1h or 3h."
2517          */
2518         if (invalidate & I915_GEM_DOMAIN_RENDER)
2519                 cmd |= MI_INVALIDATE_TLB;
2520         intel_ring_emit(ring, cmd);
2521         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2522         if (INTEL_INFO(dev)->gen >= 8) {
2523                 intel_ring_emit(ring, 0); /* upper addr */
2524                 intel_ring_emit(ring, 0); /* value */
2525         } else  {
2526                 intel_ring_emit(ring, 0);
2527                 intel_ring_emit(ring, MI_NOOP);
2528         }
2529         intel_ring_advance(ring);
2530
2531         return 0;
2532 }
2533
2534 int intel_init_render_ring_buffer(struct drm_device *dev)
2535 {
2536         struct drm_i915_private *dev_priv = dev->dev_private;
2537         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2538         struct drm_i915_gem_object *obj;
2539         int ret;
2540
2541         ring->name = "render ring";
2542         ring->id = RCS;
2543         ring->mmio_base = RENDER_RING_BASE;
2544
2545         if (INTEL_INFO(dev)->gen >= 8) {
2546                 if (i915_semaphore_is_enabled(dev)) {
2547                         obj = i915_gem_alloc_object(dev, 4096);
2548                         if (obj == NULL) {
2549                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2550                                 i915.semaphores = 0;
2551                         } else {
2552                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2553                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2554                                 if (ret != 0) {
2555                                         drm_gem_object_unreference(&obj->base);
2556                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2557                                         i915.semaphores = 0;
2558                                 } else
2559                                         dev_priv->semaphore_obj = obj;
2560                         }
2561                 }
2562
2563                 ring->init_context = intel_rcs_ctx_init;
2564                 ring->add_request = gen6_add_request;
2565                 ring->flush = gen8_render_ring_flush;
2566                 ring->irq_get = gen8_ring_get_irq;
2567                 ring->irq_put = gen8_ring_put_irq;
2568                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2569                 ring->get_seqno = gen6_ring_get_seqno;
2570                 ring->set_seqno = ring_set_seqno;
2571                 if (i915_semaphore_is_enabled(dev)) {
2572                         WARN_ON(!dev_priv->semaphore_obj);
2573                         ring->semaphore.sync_to = gen8_ring_sync;
2574                         ring->semaphore.signal = gen8_rcs_signal;
2575                         GEN8_RING_SEMAPHORE_INIT;
2576                 }
2577         } else if (INTEL_INFO(dev)->gen >= 6) {
2578                 ring->add_request = gen6_add_request;
2579                 ring->flush = gen7_render_ring_flush;
2580                 if (INTEL_INFO(dev)->gen == 6)
2581                         ring->flush = gen6_render_ring_flush;
2582                 ring->irq_get = gen6_ring_get_irq;
2583                 ring->irq_put = gen6_ring_put_irq;
2584                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2585                 ring->get_seqno = gen6_ring_get_seqno;
2586                 ring->set_seqno = ring_set_seqno;
2587                 if (i915_semaphore_is_enabled(dev)) {
2588                         ring->semaphore.sync_to = gen6_ring_sync;
2589                         ring->semaphore.signal = gen6_signal;
2590                         /*
2591                          * The current semaphore is only applied on pre-gen8
2592                          * platform.  And there is no VCS2 ring on the pre-gen8
2593                          * platform. So the semaphore between RCS and VCS2 is
2594                          * initialized as INVALID.  Gen8 will initialize the
2595                          * sema between VCS2 and RCS later.
2596                          */
2597                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2598                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2599                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2600                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2601                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2602                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2603                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2604                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2605                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2606                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2607                 }
2608         } else if (IS_GEN5(dev)) {
2609                 ring->add_request = pc_render_add_request;
2610                 ring->flush = gen4_render_ring_flush;
2611                 ring->get_seqno = pc_render_get_seqno;
2612                 ring->set_seqno = pc_render_set_seqno;
2613                 ring->irq_get = gen5_ring_get_irq;
2614                 ring->irq_put = gen5_ring_put_irq;
2615                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2616                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2617         } else {
2618                 ring->add_request = i9xx_add_request;
2619                 if (INTEL_INFO(dev)->gen < 4)
2620                         ring->flush = gen2_render_ring_flush;
2621                 else
2622                         ring->flush = gen4_render_ring_flush;
2623                 ring->get_seqno = ring_get_seqno;
2624                 ring->set_seqno = ring_set_seqno;
2625                 if (IS_GEN2(dev)) {
2626                         ring->irq_get = i8xx_ring_get_irq;
2627                         ring->irq_put = i8xx_ring_put_irq;
2628                 } else {
2629                         ring->irq_get = i9xx_ring_get_irq;
2630                         ring->irq_put = i9xx_ring_put_irq;
2631                 }
2632                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2633         }
2634         ring->write_tail = ring_write_tail;
2635
2636         if (IS_HASWELL(dev))
2637                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2638         else if (IS_GEN8(dev))
2639                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2640         else if (INTEL_INFO(dev)->gen >= 6)
2641                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2642         else if (INTEL_INFO(dev)->gen >= 4)
2643                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2644         else if (IS_I830(dev) || IS_845G(dev))
2645                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2646         else
2647                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2648         ring->init_hw = init_render_ring;
2649         ring->cleanup = render_ring_cleanup;
2650
2651         /* Workaround batchbuffer to combat CS tlb bug. */
2652         if (HAS_BROKEN_CS_TLB(dev)) {
2653                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2654                 if (obj == NULL) {
2655                         DRM_ERROR("Failed to allocate batch bo\n");
2656                         return -ENOMEM;
2657                 }
2658
2659                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2660                 if (ret != 0) {
2661                         drm_gem_object_unreference(&obj->base);
2662                         DRM_ERROR("Failed to ping batch bo\n");
2663                         return ret;
2664                 }
2665
2666                 ring->scratch.obj = obj;
2667                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2668         }
2669
2670         ret = intel_init_ring_buffer(dev, ring);
2671         if (ret)
2672                 return ret;
2673
2674         if (INTEL_INFO(dev)->gen >= 5) {
2675                 ret = intel_init_pipe_control(ring);
2676                 if (ret)
2677                         return ret;
2678         }
2679
2680         return 0;
2681 }
2682
2683 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2684 {
2685         struct drm_i915_private *dev_priv = dev->dev_private;
2686         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2687
2688         ring->name = "bsd ring";
2689         ring->id = VCS;
2690
2691         ring->write_tail = ring_write_tail;
2692         if (INTEL_INFO(dev)->gen >= 6) {
2693                 ring->mmio_base = GEN6_BSD_RING_BASE;
2694                 /* gen6 bsd needs a special wa for tail updates */
2695                 if (IS_GEN6(dev))
2696                         ring->write_tail = gen6_bsd_ring_write_tail;
2697                 ring->flush = gen6_bsd_ring_flush;
2698                 ring->add_request = gen6_add_request;
2699                 ring->get_seqno = gen6_ring_get_seqno;
2700                 ring->set_seqno = ring_set_seqno;
2701                 if (INTEL_INFO(dev)->gen >= 8) {
2702                         ring->irq_enable_mask =
2703                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2704                         ring->irq_get = gen8_ring_get_irq;
2705                         ring->irq_put = gen8_ring_put_irq;
2706                         ring->dispatch_execbuffer =
2707                                 gen8_ring_dispatch_execbuffer;
2708                         if (i915_semaphore_is_enabled(dev)) {
2709                                 ring->semaphore.sync_to = gen8_ring_sync;
2710                                 ring->semaphore.signal = gen8_xcs_signal;
2711                                 GEN8_RING_SEMAPHORE_INIT;
2712                         }
2713                 } else {
2714                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2715                         ring->irq_get = gen6_ring_get_irq;
2716                         ring->irq_put = gen6_ring_put_irq;
2717                         ring->dispatch_execbuffer =
2718                                 gen6_ring_dispatch_execbuffer;
2719                         if (i915_semaphore_is_enabled(dev)) {
2720                                 ring->semaphore.sync_to = gen6_ring_sync;
2721                                 ring->semaphore.signal = gen6_signal;
2722                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2723                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2724                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2725                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2726                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2727                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2728                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2729                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2730                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2731                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2732                         }
2733                 }
2734         } else {
2735                 ring->mmio_base = BSD_RING_BASE;
2736                 ring->flush = bsd_ring_flush;
2737                 ring->add_request = i9xx_add_request;
2738                 ring->get_seqno = ring_get_seqno;
2739                 ring->set_seqno = ring_set_seqno;
2740                 if (IS_GEN5(dev)) {
2741                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2742                         ring->irq_get = gen5_ring_get_irq;
2743                         ring->irq_put = gen5_ring_put_irq;
2744                 } else {
2745                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2746                         ring->irq_get = i9xx_ring_get_irq;
2747                         ring->irq_put = i9xx_ring_put_irq;
2748                 }
2749                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2750         }
2751         ring->init_hw = init_ring_common;
2752
2753         return intel_init_ring_buffer(dev, ring);
2754 }
2755
2756 /**
2757  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2758  */
2759 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2760 {
2761         struct drm_i915_private *dev_priv = dev->dev_private;
2762         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2763
2764         ring->name = "bsd2 ring";
2765         ring->id = VCS2;
2766
2767         ring->write_tail = ring_write_tail;
2768         ring->mmio_base = GEN8_BSD2_RING_BASE;
2769         ring->flush = gen6_bsd_ring_flush;
2770         ring->add_request = gen6_add_request;
2771         ring->get_seqno = gen6_ring_get_seqno;
2772         ring->set_seqno = ring_set_seqno;
2773         ring->irq_enable_mask =
2774                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2775         ring->irq_get = gen8_ring_get_irq;
2776         ring->irq_put = gen8_ring_put_irq;
2777         ring->dispatch_execbuffer =
2778                         gen8_ring_dispatch_execbuffer;
2779         if (i915_semaphore_is_enabled(dev)) {
2780                 ring->semaphore.sync_to = gen8_ring_sync;
2781                 ring->semaphore.signal = gen8_xcs_signal;
2782                 GEN8_RING_SEMAPHORE_INIT;
2783         }
2784         ring->init_hw = init_ring_common;
2785
2786         return intel_init_ring_buffer(dev, ring);
2787 }
2788
2789 int intel_init_blt_ring_buffer(struct drm_device *dev)
2790 {
2791         struct drm_i915_private *dev_priv = dev->dev_private;
2792         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2793
2794         ring->name = "blitter ring";
2795         ring->id = BCS;
2796
2797         ring->mmio_base = BLT_RING_BASE;
2798         ring->write_tail = ring_write_tail;
2799         ring->flush = gen6_ring_flush;
2800         ring->add_request = gen6_add_request;
2801         ring->get_seqno = gen6_ring_get_seqno;
2802         ring->set_seqno = ring_set_seqno;
2803         if (INTEL_INFO(dev)->gen >= 8) {
2804                 ring->irq_enable_mask =
2805                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2806                 ring->irq_get = gen8_ring_get_irq;
2807                 ring->irq_put = gen8_ring_put_irq;
2808                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2809                 if (i915_semaphore_is_enabled(dev)) {
2810                         ring->semaphore.sync_to = gen8_ring_sync;
2811                         ring->semaphore.signal = gen8_xcs_signal;
2812                         GEN8_RING_SEMAPHORE_INIT;
2813                 }
2814         } else {
2815                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2816                 ring->irq_get = gen6_ring_get_irq;
2817                 ring->irq_put = gen6_ring_put_irq;
2818                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2819                 if (i915_semaphore_is_enabled(dev)) {
2820                         ring->semaphore.signal = gen6_signal;
2821                         ring->semaphore.sync_to = gen6_ring_sync;
2822                         /*
2823                          * The current semaphore is only applied on pre-gen8
2824                          * platform.  And there is no VCS2 ring on the pre-gen8
2825                          * platform. So the semaphore between BCS and VCS2 is
2826                          * initialized as INVALID.  Gen8 will initialize the
2827                          * sema between BCS and VCS2 later.
2828                          */
2829                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2830                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2831                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2832                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2833                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2834                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2835                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2836                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2837                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2838                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2839                 }
2840         }
2841         ring->init_hw = init_ring_common;
2842
2843         return intel_init_ring_buffer(dev, ring);
2844 }
2845
2846 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2847 {
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2850
2851         ring->name = "video enhancement ring";
2852         ring->id = VECS;
2853
2854         ring->mmio_base = VEBOX_RING_BASE;
2855         ring->write_tail = ring_write_tail;
2856         ring->flush = gen6_ring_flush;
2857         ring->add_request = gen6_add_request;
2858         ring->get_seqno = gen6_ring_get_seqno;
2859         ring->set_seqno = ring_set_seqno;
2860
2861         if (INTEL_INFO(dev)->gen >= 8) {
2862                 ring->irq_enable_mask =
2863                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2864                 ring->irq_get = gen8_ring_get_irq;
2865                 ring->irq_put = gen8_ring_put_irq;
2866                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2867                 if (i915_semaphore_is_enabled(dev)) {
2868                         ring->semaphore.sync_to = gen8_ring_sync;
2869                         ring->semaphore.signal = gen8_xcs_signal;
2870                         GEN8_RING_SEMAPHORE_INIT;
2871                 }
2872         } else {
2873                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2874                 ring->irq_get = hsw_vebox_get_irq;
2875                 ring->irq_put = hsw_vebox_put_irq;
2876                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2877                 if (i915_semaphore_is_enabled(dev)) {
2878                         ring->semaphore.sync_to = gen6_ring_sync;
2879                         ring->semaphore.signal = gen6_signal;
2880                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2881                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2882                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2883                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2884                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2885                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2886                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2887                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2888                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2889                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2890                 }
2891         }
2892         ring->init_hw = init_ring_common;
2893
2894         return intel_init_ring_buffer(dev, ring);
2895 }
2896
2897 int
2898 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2899 {
2900         int ret;
2901
2902         if (!ring->gpu_caches_dirty)
2903                 return 0;
2904
2905         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2906         if (ret)
2907                 return ret;
2908
2909         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2910
2911         ring->gpu_caches_dirty = false;
2912         return 0;
2913 }
2914
2915 int
2916 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2917 {
2918         uint32_t flush_domains;
2919         int ret;
2920
2921         flush_domains = 0;
2922         if (ring->gpu_caches_dirty)
2923                 flush_domains = I915_GEM_GPU_DOMAINS;
2924
2925         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2926         if (ret)
2927                 return ret;
2928
2929         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2930
2931         ring->gpu_caches_dirty = false;
2932         return 0;
2933 }
2934
2935 void
2936 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2937 {
2938         int ret;
2939
2940         if (!intel_ring_initialized(ring))
2941                 return;
2942
2943         ret = intel_ring_idle(ring);
2944         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2945                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2946                           ring->name, ret);
2947
2948         stop_ring(ring);
2949 }