drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 static void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         struct intel_engine_cs *ring = req->ring;
  99         u32 cmd;
 100         int ret;
 101
 102         cmd = MI_FLUSH;
 103         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 104                 cmd |= MI_NO_WRITE_FLUSH;
 105
 106         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 107                 cmd |= MI_READ_FLUSH;
 108
 109         ret = intel_ring_begin(ring, 2);
 110         if (ret)
 111                 return ret;
 112
 113         intel_ring_emit(ring, cmd);
 114         intel_ring_emit(ring, MI_NOOP);
 115         intel_ring_advance(ring);
 116
 117         return 0;
 118 }
 119
 120 static int
 121 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 122                        u32      invalidate_domains,
 123                        u32      flush_domains)
 124 {
 125         struct intel_engine_cs *ring = req->ring;
 126         struct drm_device *dev = ring->dev;
 127         u32 cmd;
 128         int ret;
 129
 130         /*
 131          * read/write caches:
 132          *
 133          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 134          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 135          * also flushed at 2d versus 3d pipeline switches.
 136          *
 137          * read-only caches:
 138          *
 139          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 140          * MI_READ_FLUSH is set, and is always flushed on 965.
 141          *
 142          * I915_GEM_DOMAIN_COMMAND may not exist?
 143          *
 144          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 145          * invalidated when MI_EXE_FLUSH is set.
 146          *
 147          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 148          * invalidated with every MI_FLUSH.
 149          *
 150          * TLBs:
 151          *
 152          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 153          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 154          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 155          * are flushed at any MI_FLUSH.
 156          */
 157
 158         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 159         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 160                 cmd &= ~MI_NO_WRITE_FLUSH;
 161         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 162                 cmd |= MI_EXE_FLUSH;
 163
 164         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 165             (IS_G4X(dev) || IS_GEN5(dev)))
 166                 cmd |= MI_INVALIDATE_ISP;
 167
 168         ret = intel_ring_begin(ring, 2);
 169         if (ret)
 170                 return ret;
 171
 172         intel_ring_emit(ring, cmd);
 173         intel_ring_emit(ring, MI_NOOP);
 174         intel_ring_advance(ring);
 175
 176         return 0;
 177 }
 178
 179 /**
 180  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 181  * implementing two workarounds on gen6.  From section 1.4.7.1
 182  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 183  *
 184  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 185  * produced by non-pipelined state commands), software needs to first
 186  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 187  * 0.
 188  *
 189  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 190  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 191  *
 192  * And the workaround for these two requires this workaround first:
 193  *
 194  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 195  * BEFORE the pipe-control with a post-sync op and no write-cache
 196  * flushes.
 197  *
 198  * And this last workaround is tricky because of the requirements on
 199  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 200  * volume 2 part 1:
 201  *
 202  *     "1 of the following must also be set:
 203  *      - Render Target Cache Flush Enable ([12] of DW1)
 204  *      - Depth Cache Flush Enable ([0] of DW1)
 205  *      - Stall at Pixel Scoreboard ([1] of DW1)
 206  *      - Depth Stall ([13] of DW1)
 207  *      - Post-Sync Operation ([13] of DW1)
 208  *      - Notify Enable ([8] of DW1)"
 209  *
 210  * The cache flushes require the workaround flush that triggered this
 211  * one, so we can't use it.  Depth stall would trigger the same.
 212  * Post-sync nonzero is what triggered this second workaround, so we
 213  * can't use that one either.  Notify enable is IRQs, which aren't
 214  * really our business.  That leaves only stall at scoreboard.
 215  */
 216 static int
 217 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 218 {
 219         struct intel_engine_cs *ring = req->ring;
 220         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 221         int ret;
 222
 223
 224         ret = intel_ring_begin(ring, 6);
 225         if (ret)
 226                 return ret;
 227
 228         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 229         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 230                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 231         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 232         intel_ring_emit(ring, 0); /* low dword */
 233         intel_ring_emit(ring, 0); /* high dword */
 234         intel_ring_emit(ring, MI_NOOP);
 235         intel_ring_advance(ring);
 236
 237         ret = intel_ring_begin(ring, 6);
 238         if (ret)
 239                 return ret;
 240
 241         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 242         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 243         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 244         intel_ring_emit(ring, 0);
 245         intel_ring_emit(ring, 0);
 246         intel_ring_emit(ring, MI_NOOP);
 247         intel_ring_advance(ring);
 248
 249         return 0;
 250 }
 251
 252 static int
 253 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 254                        u32 invalidate_domains, u32 flush_domains)
 255 {
 256         struct intel_engine_cs *ring = req->ring;
 257         u32 flags = 0;
 258         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 259         int ret;
 260
 261         /* Force SNB workarounds for PIPE_CONTROL flushes */
 262         ret = intel_emit_post_sync_nonzero_flush(req);
 263         if (ret)
 264                 return ret;
 265
 266         /* Just flush everything.  Experiments have shown that reducing the
 267          * number of bits based on the write domains has little performance
 268          * impact.
 269          */
 270         if (flush_domains) {
 271                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 272                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 273                 /*
 274                  * Ensure that any following seqno writes only happen
 275                  * when the render cache is indeed flushed.
 276                  */
 277                 flags |= PIPE_CONTROL_CS_STALL;
 278         }
 279         if (invalidate_domains) {
 280                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 281                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 282                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 283                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 284                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 285                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 286                 /*
 287                  * TLB invalidate requires a post-sync write.
 288                  */
 289                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 290         }
 291
 292         ret = intel_ring_begin(ring, 4);
 293         if (ret)
 294                 return ret;
 295
 296         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 297         intel_ring_emit(ring, flags);
 298         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 299         intel_ring_emit(ring, 0);
 300         intel_ring_advance(ring);
 301
 302         return 0;
 303 }
 304
 305 static int
 306 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 307 {
 308         struct intel_engine_cs *ring = req->ring;
 309         int ret;
 310
 311         ret = intel_ring_begin(ring, 4);
 312         if (ret)
 313                 return ret;
 314
 315         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 316         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 317                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 318         intel_ring_emit(ring, 0);
 319         intel_ring_emit(ring, 0);
 320         intel_ring_advance(ring);
 321
 322         return 0;
 323 }
 324
 325 static int
 326 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 327                        u32 invalidate_domains, u32 flush_domains)
 328 {
 329         struct intel_engine_cs *ring = req->ring;
 330         u32 flags = 0;
 331         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 332         int ret;
 333
 334         /*
 335          * Ensure that any following seqno writes only happen when the render
 336          * cache is indeed flushed.
 337          *
 338          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 339          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 340          * don't try to be clever and just set it unconditionally.
 341          */
 342         flags |= PIPE_CONTROL_CS_STALL;
 343
 344         /* Just flush everything.  Experiments have shown that reducing the
 345          * number of bits based on the write domains has little performance
 346          * impact.
 347          */
 348         if (flush_domains) {
 349                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 350                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 351         }
 352         if (invalidate_domains) {
 353                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 354                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 355                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 356                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 357                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 358                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 359                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 360                 /*
 361                  * TLB invalidate requires a post-sync write.
 362                  */
 363                 flags |= PIPE_CONTROL_QW_WRITE;
 364                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 365
 366                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 367
 368                 /* Workaround: we must issue a pipe_control with CS-stall bit
 369                  * set before a pipe_control command that has the state cache
 370                  * invalidate bit set. */
 371                 gen7_render_ring_cs_stall_wa(req);
 372         }
 373
 374         ret = intel_ring_begin(ring, 4);
 375         if (ret)
 376                 return ret;
 377
 378         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 379         intel_ring_emit(ring, flags);
 380         intel_ring_emit(ring, scratch_addr);
 381         intel_ring_emit(ring, 0);
 382         intel_ring_advance(ring);
 383
 384         return 0;
 385 }
 386
 387 static int
 388 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 389                        u32 flags, u32 scratch_addr)
 390 {
 391         struct intel_engine_cs *ring = req->ring;
 392         int ret;
 393
 394         ret = intel_ring_begin(ring, 6);
 395         if (ret)
 396                 return ret;
 397
 398         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 399         intel_ring_emit(ring, flags);
 400         intel_ring_emit(ring, scratch_addr);
 401         intel_ring_emit(ring, 0);
 402         intel_ring_emit(ring, 0);
 403         intel_ring_emit(ring, 0);
 404         intel_ring_advance(ring);
 405
 406         return 0;
 407 }
 408
 409 static int
 410 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 411                        u32 invalidate_domains, u32 flush_domains)
 412 {
 413         u32 flags = 0;
 414         u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 415         int ret;
 416
 417         flags |= PIPE_CONTROL_CS_STALL;
 418
 419         if (flush_domains) {
 420                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 421                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 422         }
 423         if (invalidate_domains) {
 424                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 425                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 426                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 427                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 428                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 429                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 430                 flags |= PIPE_CONTROL_QW_WRITE;
 431                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 432
 433                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 434                 ret = gen8_emit_pipe_control(req,
 435                                              PIPE_CONTROL_CS_STALL |
 436                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 437                                              0);
 438                 if (ret)
 439                         return ret;
 440         }
 441
 442         return gen8_emit_pipe_control(req, flags, scratch_addr);
 443 }
 444
 445 static void ring_write_tail(struct intel_engine_cs *ring,
 446                             u32 value)
 447 {
 448         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 449         I915_WRITE_TAIL(ring, value);
 450 }
 451
 452 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 453 {
 454         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 455         u64 acthd;
 456
 457         if (INTEL_INFO(ring->dev)->gen >= 8)
 458                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 459                                          RING_ACTHD_UDW(ring->mmio_base));
 460         else if (INTEL_INFO(ring->dev)->gen >= 4)
 461                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 462         else
 463                 acthd = I915_READ(ACTHD);
 464
 465         return acthd;
 466 }
 467
 468 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 469 {
 470         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 471         u32 addr;
 472
 473         addr = dev_priv->status_page_dmah->busaddr;
 474         if (INTEL_INFO(ring->dev)->gen >= 4)
 475                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 476         I915_WRITE(HWS_PGA, addr);
 477 }
 478
 479 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 480 {
 481         struct drm_device *dev = ring->dev;
 482         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 483         u32 mmio = 0;
 484
 485         /* The ring status page addresses are no longer next to the rest of
 486          * the ring registers as of gen7.
 487          */
 488         if (IS_GEN7(dev)) {
 489                 switch (ring->id) {
 490                 case RCS:
 491                         mmio = RENDER_HWS_PGA_GEN7;
 492                         break;
 493                 case BCS:
 494                         mmio = BLT_HWS_PGA_GEN7;
 495                         break;
 496                 /*
 497                  * VCS2 actually doesn't exist on Gen7. Only shut up
 498                  * gcc switch check warning
 499                  */
 500                 case VCS2:
 501                 case VCS:
 502                         mmio = BSD_HWS_PGA_GEN7;
 503                         break;
 504                 case VECS:
 505                         mmio = VEBOX_HWS_PGA_GEN7;
 506                         break;
 507                 }
 508         } else if (IS_GEN6(ring->dev)) {
 509                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 510         } else {
 511                 /* XXX: gen8 returns to sanity */
 512                 mmio = RING_HWS_PGA(ring->mmio_base);
 513         }
 514
 515         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 516         POSTING_READ(mmio);
 517
 518         /*
 519          * Flush the TLB for this page
 520          *
 521          * FIXME: These two bits have disappeared on gen8, so a question
 522          * arises: do we still need this and if so how should we go about
 523          * invalidating the TLB?
 524          */
 525         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 526                 u32 reg = RING_INSTPM(ring->mmio_base);
 527
 528                 /* ring should be idle before issuing a sync flush*/
 529                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
 530
 531                 I915_WRITE(reg,
 532                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 533                                               INSTPM_SYNC_FLUSH));
 534                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 535                              1000))
 536                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 537                                   ring->name);
 538         }
 539 }
 540
 541 static bool stop_ring(struct intel_engine_cs *ring)
 542 {
 543         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 544
 545         if (!IS_GEN2(ring->dev)) {
 546                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 547                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 548                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 549                         /* Sometimes we observe that the idle flag is not
 550                          * set even though the ring is empty. So double
 551                          * check before giving up.
 552                          */
 553                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 554                                 return false;
 555                 }
 556         }
 557
 558         I915_WRITE_CTL(ring, 0);
 559         I915_WRITE_HEAD(ring, 0);
 560         ring->write_tail(ring, 0);
 561
 562         if (!IS_GEN2(ring->dev)) {
 563                 (void)I915_READ_CTL(ring);
 564                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 565         }
 566
 567         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 568 }
 569
 570 static int init_ring_common(struct intel_engine_cs *ring)
 571 {
 572         struct drm_device *dev = ring->dev;
 573         struct drm_i915_private *dev_priv = dev->dev_private;
 574         struct intel_ringbuffer *ringbuf = ring->buffer;
 575         struct drm_i915_gem_object *obj = ringbuf->obj;
 576         int ret = 0;
 577
 578         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 579
 580         if (!stop_ring(ring)) {
 581                 /* G45 ring initialization often fails to reset head to zero */
 582                 DRM_DEBUG_KMS("%s head not reset to zero "
 583                               "ctl %08x head %08x tail %08x start %08x\n",
 584                               ring->name,
 585                               I915_READ_CTL(ring),
 586                               I915_READ_HEAD(ring),
 587                               I915_READ_TAIL(ring),
 588                               I915_READ_START(ring));
 589
 590                 if (!stop_ring(ring)) {
 591                         DRM_ERROR("failed to set %s head to zero "
 592                                   "ctl %08x head %08x tail %08x start %08x\n",
 593                                   ring->name,
 594                                   I915_READ_CTL(ring),
 595                                   I915_READ_HEAD(ring),
 596                                   I915_READ_TAIL(ring),
 597                                   I915_READ_START(ring));
 598                         ret = -EIO;
 599                         goto out;
 600                 }
 601         }
 602
 603         if (I915_NEED_GFX_HWS(dev))
 604                 intel_ring_setup_status_page(ring);
 605         else
 606                 ring_setup_phys_status_page(ring);
 607
 608         /* Enforce ordering by reading HEAD register back */
 609         I915_READ_HEAD(ring);
 610
 611         /* Initialize the ring. This must happen _after_ we've cleared the ring
 612          * registers with the above sequence (the readback of the HEAD registers
 613          * also enforces ordering), otherwise the hw might lose the new ring
 614          * register values. */
 615         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 616
 617         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 618         if (I915_READ_HEAD(ring))
 619                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 620                           ring->name, I915_READ_HEAD(ring));
 621         I915_WRITE_HEAD(ring, 0);
 622         (void)I915_READ_HEAD(ring);
 623
 624         I915_WRITE_CTL(ring,
 625                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 626                         | RING_VALID);
 627
 628         /* If the head is still not zero, the ring is dead */
 629         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 630                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 631                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 632                 DRM_ERROR("%s initialization failed "
 633                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 634                           ring->name,
 635                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 636                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 637                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 638                 ret = -EIO;
 639                 goto out;
 640         }
 641
 642         ringbuf->last_retired_head = -1;
 643         ringbuf->head = I915_READ_HEAD(ring);
 644         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 645         intel_ring_update_space(ringbuf);
 646
 647         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 648
 649 out:
 650         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 651
 652         return ret;
 653 }
 654
 655 void
 656 intel_fini_pipe_control(struct intel_engine_cs *ring)
 657 {
 658         struct drm_device *dev = ring->dev;
 659
 660         if (ring->scratch.obj == NULL)
 661                 return;
 662
 663         if (INTEL_INFO(dev)->gen >= 5) {
 664                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 665                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 666         }
 667
 668         drm_gem_object_unreference(&ring->scratch.obj->base);
 669         ring->scratch.obj = NULL;
 670 }
 671
 672 int
 673 intel_init_pipe_control(struct intel_engine_cs *ring)
 674 {
 675         int ret;
 676
 677         WARN_ON(ring->scratch.obj);
 678
 679         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 680         if (ring->scratch.obj == NULL) {
 681                 DRM_ERROR("Failed to allocate seqno page\n");
 682                 ret = -ENOMEM;
 683                 goto err;
 684         }
 685
 686         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 687         if (ret)
 688                 goto err_unref;
 689
 690         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 691         if (ret)
 692                 goto err_unref;
 693
 694         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 695         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 696         if (ring->scratch.cpu_page == NULL) {
 697                 ret = -ENOMEM;
 698                 goto err_unpin;
 699         }
 700
 701         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 702                          ring->name, ring->scratch.gtt_offset);
 703         return 0;
 704
 705 err_unpin:
 706         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 707 err_unref:
 708         drm_gem_object_unreference(&ring->scratch.obj->base);
 709 err:
 710         return ret;
 711 }
 712
 713 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 714 {
 715         int ret, i;
 716         struct intel_engine_cs *ring = req->ring;
 717         struct drm_device *dev = ring->dev;
 718         struct drm_i915_private *dev_priv = dev->dev_private;
 719         struct i915_workarounds *w = &dev_priv->workarounds;
 720
 721         if (WARN_ON_ONCE(w->count == 0))
 722                 return 0;
 723
 724         ring->gpu_caches_dirty = true;
 725         ret = intel_ring_flush_all_caches(req);
 726         if (ret)
 727                 return ret;
 728
 729         ret = intel_ring_begin(ring, (w->count * 2 + 2));
 730         if (ret)
 731                 return ret;
 732
 733         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 734         for (i = 0; i < w->count; i++) {
 735                 intel_ring_emit(ring, w->reg[i].addr);
 736                 intel_ring_emit(ring, w->reg[i].value);
 737         }
 738         intel_ring_emit(ring, MI_NOOP);
 739
 740         intel_ring_advance(ring);
 741
 742         ring->gpu_caches_dirty = true;
 743         ret = intel_ring_flush_all_caches(req);
 744         if (ret)
 745                 return ret;
 746
 747         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 748
 749         return 0;
 750 }
 751
 752 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 753 {
 754         int ret;
 755
 756         ret = intel_ring_workarounds_emit(req);
 757         if (ret != 0)
 758                 return ret;
 759
 760         ret = i915_gem_render_state_init(req);
 761         if (ret)
 762                 DRM_ERROR("init render state: %d\n", ret);
 763
 764         return ret;
 765 }
 766
 767 static int wa_add(struct drm_i915_private *dev_priv,
 768                   const u32 addr, const u32 mask, const u32 val)
 769 {
 770         const u32 idx = dev_priv->workarounds.count;
 771
 772         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 773                 return -ENOSPC;
 774
 775         dev_priv->workarounds.reg[idx].addr = addr;
 776         dev_priv->workarounds.reg[idx].value = val;
 777         dev_priv->workarounds.reg[idx].mask = mask;
 778
 779         dev_priv->workarounds.count++;
 780
 781         return 0;
 782 }
 783
 784 #define WA_REG(addr, mask, val) { \
 785                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 786                 if (r) \
 787                         return r; \
 788         }
 789
 790 #define WA_SET_BIT_MASKED(addr, mask) \
 791         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 792
 793 #define WA_CLR_BIT_MASKED(addr, mask) \
 794         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 795
 796 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 797         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 798
 799 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 800 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 801
 802 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 803
 804 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 805 {
 806         struct drm_device *dev = ring->dev;
 807         struct drm_i915_private *dev_priv = dev->dev_private;
 808
 809         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 810
 811         /* WaDisableAsyncFlipPerfMode:bdw */
 812         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 813
 814         /* WaDisablePartialInstShootdown:bdw */
 815         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 816         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 817                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 818                           STALL_DOP_GATING_DISABLE);
 819
 820         /* WaDisableDopClockGating:bdw */
 821         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 822                           DOP_CLOCK_GATING_DISABLE);
 823
 824         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 825                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 826
 827         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 828          * workaround for for a possible hang in the unlikely event a TLB
 829          * invalidation occurs during a PSD flush.
 830          */
 831         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 832                           /* WaForceEnableNonCoherent:bdw */
 833                           HDC_FORCE_NON_COHERENT |
 834                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 835                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 836                           /* WaHdcDisableFetchWhenMasked:bdw */
 837                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 838                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 839                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 840
 841         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 842          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 843          *  polygons in the same 8x4 pixel/sample area to be processed without
 844          *  stalling waiting for the earlier ones to write to Hierarchical Z
 845          *  buffer."
 846          *
 847          * This optimization is off by default for Broadwell; turn it on.
 848          */
 849         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 850
 851         /* Wa4x4STCOptimizationDisable:bdw */
 852         WA_SET_BIT_MASKED(CACHE_MODE_1,
 853                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 854
 855         /*
 856          * BSpec recommends 8x4 when MSAA is used,
 857          * however in practice 16x4 seems fastest.
 858          *
 859          * Note that PS/WM thread counts depend on the WIZ hashing
 860          * disable bit, which we don't touch here, but it's good
 861          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 862          */
 863         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 864                             GEN6_WIZ_HASHING_MASK,
 865                             GEN6_WIZ_HASHING_16x4);
 866
 867         return 0;
 868 }
 869
 870 static int chv_init_workarounds(struct intel_engine_cs *ring)
 871 {
 872         struct drm_device *dev = ring->dev;
 873         struct drm_i915_private *dev_priv = dev->dev_private;
 874
 875         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 876
 877         /* WaDisableAsyncFlipPerfMode:chv */
 878         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 879
 880         /* WaDisablePartialInstShootdown:chv */
 881         /* WaDisableThreadStallDopClockGating:chv */
 882         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 883                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 884                           STALL_DOP_GATING_DISABLE);
 885
 886         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 887          * workaround for a possible hang in the unlikely event a TLB
 888          * invalidation occurs during a PSD flush.
 889          */
 890         /* WaForceEnableNonCoherent:chv */
 891         /* WaHdcDisableFetchWhenMasked:chv */
 892         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 893                           HDC_FORCE_NON_COHERENT |
 894                           HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 895
 896         /* According to the CACHE_MODE_0 default value documentation, some
 897          * CHV platforms disable this optimization by default.  Turn it on.
 898          */
 899         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 900
 901         /* Wa4x4STCOptimizationDisable:chv */
 902         WA_SET_BIT_MASKED(CACHE_MODE_1,
 903                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 904
 905         /* Improve HiZ throughput on CHV. */
 906         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 907
 908         /*
 909          * BSpec recommends 8x4 when MSAA is used,
 910          * however in practice 16x4 seems fastest.
 911          *
 912          * Note that PS/WM thread counts depend on the WIZ hashing
 913          * disable bit, which we don't touch here, but it's good
 914          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 915          */
 916         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 917                             GEN6_WIZ_HASHING_MASK,
 918                             GEN6_WIZ_HASHING_16x4);
 919
 920         return 0;
 921 }
 922
 923 static int gen9_init_workarounds(struct intel_engine_cs *ring)
 924 {
 925         struct drm_device *dev = ring->dev;
 926         struct drm_i915_private *dev_priv = dev->dev_private;
 927         uint32_t tmp;
 928
 929         /* WaDisablePartialInstShootdown:skl,bxt */
 930         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 931                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 932
 933         /* Syncing dependencies between camera and graphics:skl,bxt */
 934         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 935                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 936
 937         if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
 938             INTEL_REVID(dev) == SKL_REVID_B0)) ||
 939             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
 940                 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 941                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 942                                   GEN9_DG_MIRROR_FIX_ENABLE);
 943         }
 944
 945         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
 946             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
 947                 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 948                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 949                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 950                 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
 951                                   DISABLE_PIXEL_MASK_CAMMING);
 952         }
 953
 954         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
 955             IS_BROXTON(dev)) {
 956                 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 957                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 958                                   GEN9_ENABLE_YV12_BUGFIX);
 959         }
 960
 961         /* Wa4x4STCOptimizationDisable:skl,bxt */
 962         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 963
 964         /* WaDisablePartialResolveInVc:skl,bxt */
 965         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 966
 967         /* WaCcsTlbPrefetchDisable:skl,bxt */
 968         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 969                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 970
 971         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 972         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
 973             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
 974                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 975                                   PIXEL_MASK_CAMMING_DISABLE);
 976
 977         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 978         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 979         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
 980             (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
 981                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 982         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 983
 984         return 0;
 985 }
 986
 987 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
 988 {
 989         struct drm_device *dev = ring->dev;
 990         struct drm_i915_private *dev_priv = dev->dev_private;
 991         u8 vals[3] = { 0, 0, 0 };
 992         unsigned int i;
 993
 994         for (i = 0; i < 3; i++) {
 995                 u8 ss;
 996
 997                 /*
 998                  * Only consider slices where one, and only one, subslice has 7
 999                  * EUs
1000                  */
1001                 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
1002                         continue;
1003
1004                 /*
1005                  * subslice_7eu[i] != 0 (because of the check above) and
1006                  * ss_max == 4 (maximum number of subslices possible per slice)
1007                  *
1008                  * ->    0 <= ss <= 3;
1009                  */
1010                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1011                 vals[i] = 3 - ss;
1012         }
1013
1014         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1015                 return 0;
1016
1017         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1018         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1019                             GEN9_IZ_HASHING_MASK(2) |
1020                             GEN9_IZ_HASHING_MASK(1) |
1021                             GEN9_IZ_HASHING_MASK(0),
1022                             GEN9_IZ_HASHING(2, vals[2]) |
1023                             GEN9_IZ_HASHING(1, vals[1]) |
1024                             GEN9_IZ_HASHING(0, vals[0]));
1025
1026         return 0;
1027 }
1028
1029
1030 static int skl_init_workarounds(struct intel_engine_cs *ring)
1031 {
1032         struct drm_device *dev = ring->dev;
1033         struct drm_i915_private *dev_priv = dev->dev_private;
1034
1035         gen9_init_workarounds(ring);
1036
1037         /* WaDisablePowerCompilerClockGating:skl */
1038         if (INTEL_REVID(dev) == SKL_REVID_B0)
1039                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1040                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1041
1042         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1043                 /*
1044                  *Use Force Non-Coherent whenever executing a 3D context. This
1045                  * is a workaround for a possible hang in the unlikely event
1046                  * a TLB invalidation occurs during a PSD flush.
1047                  */
1048                 /* WaForceEnableNonCoherent:skl */
1049                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1050                                   HDC_FORCE_NON_COHERENT);
1051         }
1052
1053         if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1054             INTEL_REVID(dev) == SKL_REVID_D0)
1055                 /* WaBarrierPerformanceFixDisable:skl */
1056                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1057                                   HDC_FENCE_DEST_SLM_DISABLE |
1058                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1059
1060         return skl_tune_iz_hashing(ring);
1061 }
1062
1063 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1064 {
1065         struct drm_device *dev = ring->dev;
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067
1068         gen9_init_workarounds(ring);
1069
1070         /* WaDisableThreadStallDopClockGating:bxt */
1071         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1072                           STALL_DOP_GATING_DISABLE);
1073
1074         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1075         if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1076                 WA_SET_BIT_MASKED(
1077                         GEN7_HALF_SLICE_CHICKEN1,
1078                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1079         }
1080
1081         return 0;
1082 }
1083
1084 int init_workarounds_ring(struct intel_engine_cs *ring)
1085 {
1086         struct drm_device *dev = ring->dev;
1087         struct drm_i915_private *dev_priv = dev->dev_private;
1088
1089         WARN_ON(ring->id != RCS);
1090
1091         dev_priv->workarounds.count = 0;
1092
1093         if (IS_BROADWELL(dev))
1094                 return bdw_init_workarounds(ring);
1095
1096         if (IS_CHERRYVIEW(dev))
1097                 return chv_init_workarounds(ring);
1098
1099         if (IS_SKYLAKE(dev))
1100                 return skl_init_workarounds(ring);
1101
1102         if (IS_BROXTON(dev))
1103                 return bxt_init_workarounds(ring);
1104
1105         return 0;
1106 }
1107
1108 static int init_render_ring(struct intel_engine_cs *ring)
1109 {
1110         struct drm_device *dev = ring->dev;
1111         struct drm_i915_private *dev_priv = dev->dev_private;
1112         int ret = init_ring_common(ring);
1113         if (ret)
1114                 return ret;
1115
1116         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1117         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1118                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1119
1120         /* We need to disable the AsyncFlip performance optimisations in order
1121          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1122          * programmed to '1' on all products.
1123          *
1124          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1125          */
1126         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1127                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1128
1129         /* Required for the hardware to program scanline values for waiting */
1130         /* WaEnableFlushTlbInvalidationMode:snb */
1131         if (INTEL_INFO(dev)->gen == 6)
1132                 I915_WRITE(GFX_MODE,
1133                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1134
1135         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1136         if (IS_GEN7(dev))
1137                 I915_WRITE(GFX_MODE_GEN7,
1138                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1139                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1140
1141         if (IS_GEN6(dev)) {
1142                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1143                  * "If this bit is set, STCunit will have LRA as replacement
1144                  *  policy. [...] This bit must be reset.  LRA replacement
1145                  *  policy is not supported."
1146                  */
1147                 I915_WRITE(CACHE_MODE_0,
1148                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1149         }
1150
1151         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1152                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1153
1154         if (HAS_L3_DPF(dev))
1155                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1156
1157         return init_workarounds_ring(ring);
1158 }
1159
1160 static void render_ring_cleanup(struct intel_engine_cs *ring)
1161 {
1162         struct drm_device *dev = ring->dev;
1163         struct drm_i915_private *dev_priv = dev->dev_private;
1164
1165         if (dev_priv->semaphore_obj) {
1166                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1167                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1168                 dev_priv->semaphore_obj = NULL;
1169         }
1170
1171         intel_fini_pipe_control(ring);
1172 }
1173
1174 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1175                            unsigned int num_dwords)
1176 {
1177 #define MBOX_UPDATE_DWORDS 8
1178         struct drm_device *dev = signaller->dev;
1179         struct drm_i915_private *dev_priv = dev->dev_private;
1180         struct intel_engine_cs *waiter;
1181         int i, ret, num_rings;
1182
1183         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1184         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1185 #undef MBOX_UPDATE_DWORDS
1186
1187         ret = intel_ring_begin(signaller, num_dwords);
1188         if (ret)
1189                 return ret;
1190
1191         for_each_ring(waiter, dev_priv, i) {
1192                 u32 seqno;
1193                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1194                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1195                         continue;
1196
1197                 seqno = i915_gem_request_get_seqno(
1198                                            signaller->outstanding_lazy_request);
1199                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1200                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1201                                            PIPE_CONTROL_QW_WRITE |
1202                                            PIPE_CONTROL_FLUSH_ENABLE);
1203                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1204                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1205                 intel_ring_emit(signaller, seqno);
1206                 intel_ring_emit(signaller, 0);
1207                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1208                                            MI_SEMAPHORE_TARGET(waiter->id));
1209                 intel_ring_emit(signaller, 0);
1210         }
1211
1212         return 0;
1213 }
1214
1215 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1216                            unsigned int num_dwords)
1217 {
1218 #define MBOX_UPDATE_DWORDS 6
1219         struct drm_device *dev = signaller->dev;
1220         struct drm_i915_private *dev_priv = dev->dev_private;
1221         struct intel_engine_cs *waiter;
1222         int i, ret, num_rings;
1223
1224         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1225         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1226 #undef MBOX_UPDATE_DWORDS
1227
1228         ret = intel_ring_begin(signaller, num_dwords);
1229         if (ret)
1230                 return ret;
1231
1232         for_each_ring(waiter, dev_priv, i) {
1233                 u32 seqno;
1234                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1235                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1236                         continue;
1237
1238                 seqno = i915_gem_request_get_seqno(
1239                                            signaller->outstanding_lazy_request);
1240                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1241                                            MI_FLUSH_DW_OP_STOREDW);
1242                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1243                                            MI_FLUSH_DW_USE_GTT);
1244                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1245                 intel_ring_emit(signaller, seqno);
1246                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1247                                            MI_SEMAPHORE_TARGET(waiter->id));
1248                 intel_ring_emit(signaller, 0);
1249         }
1250
1251         return 0;
1252 }
1253
1254 static int gen6_signal(struct intel_engine_cs *signaller,
1255                        unsigned int num_dwords)
1256 {
1257         struct drm_device *dev = signaller->dev;
1258         struct drm_i915_private *dev_priv = dev->dev_private;
1259         struct intel_engine_cs *useless;
1260         int i, ret, num_rings;
1261
1262 #define MBOX_UPDATE_DWORDS 3
1263         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1264         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1265 #undef MBOX_UPDATE_DWORDS
1266
1267         ret = intel_ring_begin(signaller, num_dwords);
1268         if (ret)
1269                 return ret;
1270
1271         for_each_ring(useless, dev_priv, i) {
1272                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1273                 if (mbox_reg != GEN6_NOSYNC) {
1274                         u32 seqno = i915_gem_request_get_seqno(
1275                                            signaller->outstanding_lazy_request);
1276                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1277                         intel_ring_emit(signaller, mbox_reg);
1278                         intel_ring_emit(signaller, seqno);
1279                 }
1280         }
1281
1282         /* If num_dwords was rounded, make sure the tail pointer is correct */
1283         if (num_rings % 2 == 0)
1284                 intel_ring_emit(signaller, MI_NOOP);
1285
1286         return 0;
1287 }
1288
1289 /**
1290  * gen6_add_request - Update the semaphore mailbox registers
1291  *
1292  * @request - request to write to the ring
1293  *
1294  * Update the mailbox registers in the *other* rings with the current seqno.
1295  * This acts like a signal in the canonical semaphore.
1296  */
1297 static int
1298 gen6_add_request(struct drm_i915_gem_request *req)
1299 {
1300         struct intel_engine_cs *ring = req->ring;
1301         int ret;
1302
1303         if (ring->semaphore.signal)
1304                 ret = ring->semaphore.signal(ring, 4);
1305         else
1306                 ret = intel_ring_begin(ring, 4);
1307
1308         if (ret)
1309                 return ret;
1310
1311         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1312         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1313         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1314         intel_ring_emit(ring, MI_USER_INTERRUPT);
1315         __intel_ring_advance(ring);
1316
1317         return 0;
1318 }
1319
1320 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1321                                               u32 seqno)
1322 {
1323         struct drm_i915_private *dev_priv = dev->dev_private;
1324         return dev_priv->last_seqno < seqno;
1325 }
1326
1327 /**
1328  * intel_ring_sync - sync the waiter to the signaller on seqno
1329  *
1330  * @waiter - ring that is waiting
1331  * @signaller - ring which has, or will signal
1332  * @seqno - seqno which the waiter will block on
1333  */
1334
1335 static int
1336 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1337                struct intel_engine_cs *signaller,
1338                u32 seqno)
1339 {
1340         struct intel_engine_cs *waiter = waiter_req->ring;
1341         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1342         int ret;
1343
1344         ret = intel_ring_begin(waiter, 4);
1345         if (ret)
1346                 return ret;
1347
1348         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1349                                 MI_SEMAPHORE_GLOBAL_GTT |
1350                                 MI_SEMAPHORE_POLL |
1351                                 MI_SEMAPHORE_SAD_GTE_SDD);
1352         intel_ring_emit(waiter, seqno);
1353         intel_ring_emit(waiter,
1354                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1355         intel_ring_emit(waiter,
1356                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1357         intel_ring_advance(waiter);
1358         return 0;
1359 }
1360
1361 static int
1362 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1363                struct intel_engine_cs *signaller,
1364                u32 seqno)
1365 {
1366         struct intel_engine_cs *waiter = waiter_req->ring;
1367         u32 dw1 = MI_SEMAPHORE_MBOX |
1368                   MI_SEMAPHORE_COMPARE |
1369                   MI_SEMAPHORE_REGISTER;
1370         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1371         int ret;
1372
1373         /* Throughout all of the GEM code, seqno passed implies our current
1374          * seqno is >= the last seqno executed. However for hardware the
1375          * comparison is strictly greater than.
1376          */
1377         seqno -= 1;
1378
1379         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1380
1381         ret = intel_ring_begin(waiter, 4);
1382         if (ret)
1383                 return ret;
1384
1385         /* If seqno wrap happened, omit the wait with no-ops */
1386         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1387                 intel_ring_emit(waiter, dw1 | wait_mbox);
1388                 intel_ring_emit(waiter, seqno);
1389                 intel_ring_emit(waiter, 0);
1390                 intel_ring_emit(waiter, MI_NOOP);
1391         } else {
1392                 intel_ring_emit(waiter, MI_NOOP);
1393                 intel_ring_emit(waiter, MI_NOOP);
1394                 intel_ring_emit(waiter, MI_NOOP);
1395                 intel_ring_emit(waiter, MI_NOOP);
1396         }
1397         intel_ring_advance(waiter);
1398
1399         return 0;
1400 }
1401
1402 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1403 do {                                                                    \
1404         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1405                  PIPE_CONTROL_DEPTH_STALL);                             \
1406         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1407         intel_ring_emit(ring__, 0);                                                     \
1408         intel_ring_emit(ring__, 0);                                                     \
1409 } while (0)
1410
1411 static int
1412 pc_render_add_request(struct drm_i915_gem_request *req)
1413 {
1414         struct intel_engine_cs *ring = req->ring;
1415         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1416         int ret;
1417
1418         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1419          * incoherent with writes to memory, i.e. completely fubar,
1420          * so we need to use PIPE_NOTIFY instead.
1421          *
1422          * However, we also need to workaround the qword write
1423          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1424          * memory before requesting an interrupt.
1425          */
1426         ret = intel_ring_begin(ring, 32);
1427         if (ret)
1428                 return ret;
1429
1430         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1431                         PIPE_CONTROL_WRITE_FLUSH |
1432                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1433         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1434         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1435         intel_ring_emit(ring, 0);
1436         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1437         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1438         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1439         scratch_addr += 2 * CACHELINE_BYTES;
1440         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1441         scratch_addr += 2 * CACHELINE_BYTES;
1442         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1443         scratch_addr += 2 * CACHELINE_BYTES;
1444         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1445         scratch_addr += 2 * CACHELINE_BYTES;
1446         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1447
1448         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1449                         PIPE_CONTROL_WRITE_FLUSH |
1450                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1451                         PIPE_CONTROL_NOTIFY);
1452         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1453         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1454         intel_ring_emit(ring, 0);
1455         __intel_ring_advance(ring);
1456
1457         return 0;
1458 }
1459
1460 static u32
1461 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1462 {
1463         /* Workaround to force correct ordering between irq and seqno writes on
1464          * ivb (and maybe also on snb) by reading from a CS register (like
1465          * ACTHD) before reading the status page. */
1466         if (!lazy_coherency) {
1467                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1468                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1469         }
1470
1471         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1472 }
1473
1474 static u32
1475 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1476 {
1477         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1478 }
1479
1480 static void
1481 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1482 {
1483         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1484 }
1485
1486 static u32
1487 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1488 {
1489         return ring->scratch.cpu_page[0];
1490 }
1491
1492 static void
1493 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1494 {
1495         ring->scratch.cpu_page[0] = seqno;
1496 }
1497
1498 static bool
1499 gen5_ring_get_irq(struct intel_engine_cs *ring)
1500 {
1501         struct drm_device *dev = ring->dev;
1502         struct drm_i915_private *dev_priv = dev->dev_private;
1503         unsigned long flags;
1504
1505         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1506                 return false;
1507
1508         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1509         if (ring->irq_refcount++ == 0)
1510                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1511         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1512
1513         return true;
1514 }
1515
1516 static void
1517 gen5_ring_put_irq(struct intel_engine_cs *ring)
1518 {
1519         struct drm_device *dev = ring->dev;
1520         struct drm_i915_private *dev_priv = dev->dev_private;
1521         unsigned long flags;
1522
1523         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1524         if (--ring->irq_refcount == 0)
1525                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1526         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1527 }
1528
1529 static bool
1530 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1531 {
1532         struct drm_device *dev = ring->dev;
1533         struct drm_i915_private *dev_priv = dev->dev_private;
1534         unsigned long flags;
1535
1536         if (!intel_irqs_enabled(dev_priv))
1537                 return false;
1538
1539         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1540         if (ring->irq_refcount++ == 0) {
1541                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1542                 I915_WRITE(IMR, dev_priv->irq_mask);
1543                 POSTING_READ(IMR);
1544         }
1545         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1546
1547         return true;
1548 }
1549
1550 static void
1551 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1552 {
1553         struct drm_device *dev = ring->dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         unsigned long flags;
1556
1557         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1558         if (--ring->irq_refcount == 0) {
1559                 dev_priv->irq_mask |= ring->irq_enable_mask;
1560                 I915_WRITE(IMR, dev_priv->irq_mask);
1561                 POSTING_READ(IMR);
1562         }
1563         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1564 }
1565
1566 static bool
1567 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1568 {
1569         struct drm_device *dev = ring->dev;
1570         struct drm_i915_private *dev_priv = dev->dev_private;
1571         unsigned long flags;
1572
1573         if (!intel_irqs_enabled(dev_priv))
1574                 return false;
1575
1576         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1577         if (ring->irq_refcount++ == 0) {
1578                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1579                 I915_WRITE16(IMR, dev_priv->irq_mask);
1580                 POSTING_READ16(IMR);
1581         }
1582         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1583
1584         return true;
1585 }
1586
1587 static void
1588 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1589 {
1590         struct drm_device *dev = ring->dev;
1591         struct drm_i915_private *dev_priv = dev->dev_private;
1592         unsigned long flags;
1593
1594         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1595         if (--ring->irq_refcount == 0) {
1596                 dev_priv->irq_mask |= ring->irq_enable_mask;
1597                 I915_WRITE16(IMR, dev_priv->irq_mask);
1598                 POSTING_READ16(IMR);
1599         }
1600         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1601 }
1602
1603 static int
1604 bsd_ring_flush(struct drm_i915_gem_request *req,
1605                u32     invalidate_domains,
1606                u32     flush_domains)
1607 {
1608         struct intel_engine_cs *ring = req->ring;
1609         int ret;
1610
1611         ret = intel_ring_begin(ring, 2);
1612         if (ret)
1613                 return ret;
1614
1615         intel_ring_emit(ring, MI_FLUSH);
1616         intel_ring_emit(ring, MI_NOOP);
1617         intel_ring_advance(ring);
1618         return 0;
1619 }
1620
1621 static int
1622 i9xx_add_request(struct drm_i915_gem_request *req)
1623 {
1624         struct intel_engine_cs *ring = req->ring;
1625         int ret;
1626
1627         ret = intel_ring_begin(ring, 4);
1628         if (ret)
1629                 return ret;
1630
1631         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1632         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1633         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1634         intel_ring_emit(ring, MI_USER_INTERRUPT);
1635         __intel_ring_advance(ring);
1636
1637         return 0;
1638 }
1639
1640 static bool
1641 gen6_ring_get_irq(struct intel_engine_cs *ring)
1642 {
1643         struct drm_device *dev = ring->dev;
1644         struct drm_i915_private *dev_priv = dev->dev_private;
1645         unsigned long flags;
1646
1647         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1648                 return false;
1649
1650         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1651         if (ring->irq_refcount++ == 0) {
1652                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1653                         I915_WRITE_IMR(ring,
1654                                        ~(ring->irq_enable_mask |
1655                                          GT_PARITY_ERROR(dev)));
1656                 else
1657                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1658                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1659         }
1660         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1661
1662         return true;
1663 }
1664
1665 static void
1666 gen6_ring_put_irq(struct intel_engine_cs *ring)
1667 {
1668         struct drm_device *dev = ring->dev;
1669         struct drm_i915_private *dev_priv = dev->dev_private;
1670         unsigned long flags;
1671
1672         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1673         if (--ring->irq_refcount == 0) {
1674                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1675                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1676                 else
1677                         I915_WRITE_IMR(ring, ~0);
1678                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1679         }
1680         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1681 }
1682
1683 static bool
1684 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1685 {
1686         struct drm_device *dev = ring->dev;
1687         struct drm_i915_private *dev_priv = dev->dev_private;
1688         unsigned long flags;
1689
1690         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1691                 return false;
1692
1693         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1694         if (ring->irq_refcount++ == 0) {
1695                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1696                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1697         }
1698         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1699
1700         return true;
1701 }
1702
1703 static void
1704 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1705 {
1706         struct drm_device *dev = ring->dev;
1707         struct drm_i915_private *dev_priv = dev->dev_private;
1708         unsigned long flags;
1709
1710         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1711         if (--ring->irq_refcount == 0) {
1712                 I915_WRITE_IMR(ring, ~0);
1713                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1714         }
1715         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1716 }
1717
1718 static bool
1719 gen8_ring_get_irq(struct intel_engine_cs *ring)
1720 {
1721         struct drm_device *dev = ring->dev;
1722         struct drm_i915_private *dev_priv = dev->dev_private;
1723         unsigned long flags;
1724
1725         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1726                 return false;
1727
1728         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1729         if (ring->irq_refcount++ == 0) {
1730                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1731                         I915_WRITE_IMR(ring,
1732                                        ~(ring->irq_enable_mask |
1733                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1734                 } else {
1735                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1736                 }
1737                 POSTING_READ(RING_IMR(ring->mmio_base));
1738         }
1739         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1740
1741         return true;
1742 }
1743
1744 static void
1745 gen8_ring_put_irq(struct intel_engine_cs *ring)
1746 {
1747         struct drm_device *dev = ring->dev;
1748         struct drm_i915_private *dev_priv = dev->dev_private;
1749         unsigned long flags;
1750
1751         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1752         if (--ring->irq_refcount == 0) {
1753                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1754                         I915_WRITE_IMR(ring,
1755                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1756                 } else {
1757                         I915_WRITE_IMR(ring, ~0);
1758                 }
1759                 POSTING_READ(RING_IMR(ring->mmio_base));
1760         }
1761         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1762 }
1763
1764 static int
1765 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1766                          u64 offset, u32 length,
1767                          unsigned dispatch_flags)
1768 {
1769         struct intel_engine_cs *ring = req->ring;
1770         int ret;
1771
1772         ret = intel_ring_begin(ring, 2);
1773         if (ret)
1774                 return ret;
1775
1776         intel_ring_emit(ring,
1777                         MI_BATCH_BUFFER_START |
1778                         MI_BATCH_GTT |
1779                         (dispatch_flags & I915_DISPATCH_SECURE ?
1780                          0 : MI_BATCH_NON_SECURE_I965));
1781         intel_ring_emit(ring, offset);
1782         intel_ring_advance(ring);
1783
1784         return 0;
1785 }
1786
1787 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1788 #define I830_BATCH_LIMIT (256*1024)
1789 #define I830_TLB_ENTRIES (2)
1790 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1791 static int
1792 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1793                          u64 offset, u32 len,
1794                          unsigned dispatch_flags)
1795 {
1796         struct intel_engine_cs *ring = req->ring;
1797         u32 cs_offset = ring->scratch.gtt_offset;
1798         int ret;
1799
1800         ret = intel_ring_begin(ring, 6);
1801         if (ret)
1802                 return ret;
1803
1804         /* Evict the invalid PTE TLBs */
1805         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1806         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1807         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1808         intel_ring_emit(ring, cs_offset);
1809         intel_ring_emit(ring, 0xdeadbeef);
1810         intel_ring_emit(ring, MI_NOOP);
1811         intel_ring_advance(ring);
1812
1813         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1814                 if (len > I830_BATCH_LIMIT)
1815                         return -ENOSPC;
1816
1817                 ret = intel_ring_begin(ring, 6 + 2);
1818                 if (ret)
1819                         return ret;
1820
1821                 /* Blit the batch (which has now all relocs applied) to the
1822                  * stable batch scratch bo area (so that the CS never
1823                  * stumbles over its tlb invalidation bug) ...
1824                  */
1825                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1826                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1827                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1828                 intel_ring_emit(ring, cs_offset);
1829                 intel_ring_emit(ring, 4096);
1830                 intel_ring_emit(ring, offset);
1831
1832                 intel_ring_emit(ring, MI_FLUSH);
1833                 intel_ring_emit(ring, MI_NOOP);
1834                 intel_ring_advance(ring);
1835
1836                 /* ... and execute it. */
1837                 offset = cs_offset;
1838         }
1839
1840         ret = intel_ring_begin(ring, 4);
1841         if (ret)
1842                 return ret;
1843
1844         intel_ring_emit(ring, MI_BATCH_BUFFER);
1845         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1846                                         0 : MI_BATCH_NON_SECURE));
1847         intel_ring_emit(ring, offset + len - 8);
1848         intel_ring_emit(ring, MI_NOOP);
1849         intel_ring_advance(ring);
1850
1851         return 0;
1852 }
1853
1854 static int
1855 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1856                          u64 offset, u32 len,
1857                          unsigned dispatch_flags)
1858 {
1859         struct intel_engine_cs *ring = req->ring;
1860         int ret;
1861
1862         ret = intel_ring_begin(ring, 2);
1863         if (ret)
1864                 return ret;
1865
1866         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1867         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1868                                         0 : MI_BATCH_NON_SECURE));
1869         intel_ring_advance(ring);
1870
1871         return 0;
1872 }
1873
1874 static void cleanup_status_page(struct intel_engine_cs *ring)
1875 {
1876         struct drm_i915_gem_object *obj;
1877
1878         obj = ring->status_page.obj;
1879         if (obj == NULL)
1880                 return;
1881
1882         kunmap(sg_page(obj->pages->sgl));
1883         i915_gem_object_ggtt_unpin(obj);
1884         drm_gem_object_unreference(&obj->base);
1885         ring->status_page.obj = NULL;
1886 }
1887
1888 static int init_status_page(struct intel_engine_cs *ring)
1889 {
1890         struct drm_i915_gem_object *obj;
1891
1892         if ((obj = ring->status_page.obj) == NULL) {
1893                 unsigned flags;
1894                 int ret;
1895
1896                 obj = i915_gem_alloc_object(ring->dev, 4096);
1897                 if (obj == NULL) {
1898                         DRM_ERROR("Failed to allocate status page\n");
1899                         return -ENOMEM;
1900                 }
1901
1902                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1903                 if (ret)
1904                         goto err_unref;
1905
1906                 flags = 0;
1907                 if (!HAS_LLC(ring->dev))
1908                         /* On g33, we cannot place HWS above 256MiB, so
1909                          * restrict its pinning to the low mappable arena.
1910                          * Though this restriction is not documented for
1911                          * gen4, gen5, or byt, they also behave similarly
1912                          * and hang if the HWS is placed at the top of the
1913                          * GTT. To generalise, it appears that all !llc
1914                          * platforms have issues with us placing the HWS
1915                          * above the mappable region (even though we never
1916                          * actualy map it).
1917                          */
1918                         flags |= PIN_MAPPABLE;
1919                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1920                 if (ret) {
1921 err_unref:
1922                         drm_gem_object_unreference(&obj->base);
1923                         return ret;
1924                 }
1925
1926                 ring->status_page.obj = obj;
1927         }
1928
1929         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1930         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1931         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1932
1933         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1934                         ring->name, ring->status_page.gfx_addr);
1935
1936         return 0;
1937 }
1938
1939 static int init_phys_status_page(struct intel_engine_cs *ring)
1940 {
1941         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1942
1943         if (!dev_priv->status_page_dmah) {
1944                 dev_priv->status_page_dmah =
1945                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1946                 if (!dev_priv->status_page_dmah)
1947                         return -ENOMEM;
1948         }
1949
1950         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1951         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1952
1953         return 0;
1954 }
1955
1956 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1957 {
1958         iounmap(ringbuf->virtual_start);
1959         ringbuf->virtual_start = NULL;
1960         i915_gem_object_ggtt_unpin(ringbuf->obj);
1961 }
1962
1963 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1964                                      struct intel_ringbuffer *ringbuf)
1965 {
1966         struct drm_i915_private *dev_priv = to_i915(dev);
1967         struct drm_i915_gem_object *obj = ringbuf->obj;
1968         int ret;
1969
1970         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1971         if (ret)
1972                 return ret;
1973
1974         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1975         if (ret) {
1976                 i915_gem_object_ggtt_unpin(obj);
1977                 return ret;
1978         }
1979
1980         ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1981                         i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1982         if (ringbuf->virtual_start == NULL) {
1983                 i915_gem_object_ggtt_unpin(obj);
1984                 return -EINVAL;
1985         }
1986
1987         return 0;
1988 }
1989
1990 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1991 {
1992         drm_gem_object_unreference(&ringbuf->obj->base);
1993         ringbuf->obj = NULL;
1994 }
1995
1996 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1997                                struct intel_ringbuffer *ringbuf)
1998 {
1999         struct drm_i915_gem_object *obj;
2000
2001         obj = NULL;
2002         if (!HAS_LLC(dev))
2003                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2004         if (obj == NULL)
2005                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2006         if (obj == NULL)
2007                 return -ENOMEM;
2008
2009         /* mark ring buffers as read-only from GPU side by default */
2010         obj->gt_ro = 1;
2011
2012         ringbuf->obj = obj;
2013
2014         return 0;
2015 }
2016
2017 static int intel_init_ring_buffer(struct drm_device *dev,
2018                                   struct intel_engine_cs *ring)
2019 {
2020         struct intel_ringbuffer *ringbuf;
2021         int ret;
2022
2023         WARN_ON(ring->buffer);
2024
2025         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2026         if (!ringbuf)
2027                 return -ENOMEM;
2028         ring->buffer = ringbuf;
2029
2030         ring->dev = dev;
2031         INIT_LIST_HEAD(&ring->active_list);
2032         INIT_LIST_HEAD(&ring->request_list);
2033         INIT_LIST_HEAD(&ring->execlist_queue);
2034         i915_gem_batch_pool_init(dev, &ring->batch_pool);
2035         ringbuf->size = 32 * PAGE_SIZE;
2036         ringbuf->ring = ring;
2037         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2038
2039         init_waitqueue_head(&ring->irq_queue);
2040
2041         if (I915_NEED_GFX_HWS(dev)) {
2042                 ret = init_status_page(ring);
2043                 if (ret)
2044                         goto error;
2045         } else {
2046                 BUG_ON(ring->id != RCS);
2047                 ret = init_phys_status_page(ring);
2048                 if (ret)
2049                         goto error;
2050         }
2051
2052         WARN_ON(ringbuf->obj);
2053
2054         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2055         if (ret) {
2056                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2057                                 ring->name, ret);
2058                 goto error;
2059         }
2060
2061         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2062         if (ret) {
2063                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2064                                 ring->name, ret);
2065                 intel_destroy_ringbuffer_obj(ringbuf);
2066                 goto error;
2067         }
2068
2069         /* Workaround an erratum on the i830 which causes a hang if
2070          * the TAIL pointer points to within the last 2 cachelines
2071          * of the buffer.
2072          */
2073         ringbuf->effective_size = ringbuf->size;
2074         if (IS_I830(dev) || IS_845G(dev))
2075                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2076
2077         ret = i915_cmd_parser_init_ring(ring);
2078         if (ret)
2079                 goto error;
2080
2081         return 0;
2082
2083 error:
2084         kfree(ringbuf);
2085         ring->buffer = NULL;
2086         return ret;
2087 }
2088
2089 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2090 {
2091         struct drm_i915_private *dev_priv;
2092         struct intel_ringbuffer *ringbuf;
2093
2094         if (!intel_ring_initialized(ring))
2095                 return;
2096
2097         dev_priv = to_i915(ring->dev);
2098         ringbuf = ring->buffer;
2099
2100         intel_stop_ring_buffer(ring);
2101         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2102
2103         intel_unpin_ringbuffer_obj(ringbuf);
2104         intel_destroy_ringbuffer_obj(ringbuf);
2105         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2106
2107         if (ring->cleanup)
2108                 ring->cleanup(ring);
2109
2110         cleanup_status_page(ring);
2111
2112         i915_cmd_parser_fini_ring(ring);
2113         i915_gem_batch_pool_fini(&ring->batch_pool);
2114
2115         kfree(ringbuf);
2116         ring->buffer = NULL;
2117 }
2118
2119 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2120 {
2121         struct intel_ringbuffer *ringbuf = ring->buffer;
2122         struct drm_i915_gem_request *request;
2123         unsigned space;
2124         int ret;
2125
2126         /* The whole point of reserving space is to not wait! */
2127         WARN_ON(ringbuf->reserved_in_use);
2128
2129         if (intel_ring_space(ringbuf) >= n)
2130                 return 0;
2131
2132         list_for_each_entry(request, &ring->request_list, list) {
2133                 space = __intel_ring_space(request->postfix, ringbuf->tail,
2134                                            ringbuf->size);
2135                 if (space >= n)
2136                         break;
2137         }
2138
2139         if (WARN_ON(&request->list == &ring->request_list))
2140                 return -ENOSPC;
2141
2142         ret = i915_wait_request(request);
2143         if (ret)
2144                 return ret;
2145
2146         ringbuf->space = space;
2147         return 0;
2148 }
2149
2150 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2151 {
2152         uint32_t __iomem *virt;
2153         struct intel_ringbuffer *ringbuf = ring->buffer;
2154         int rem = ringbuf->size - ringbuf->tail;
2155
2156         /* Can't wrap if space has already been reserved! */
2157         WARN_ON(ringbuf->reserved_in_use);
2158
2159         if (ringbuf->space < rem) {
2160                 int ret = ring_wait_for_space(ring, rem);
2161                 if (ret)
2162                         return ret;
2163         }
2164
2165         virt = ringbuf->virtual_start + ringbuf->tail;
2166         rem /= 4;
2167         while (rem--)
2168                 iowrite32(MI_NOOP, virt++);
2169
2170         ringbuf->tail = 0;
2171         intel_ring_update_space(ringbuf);
2172
2173         return 0;
2174 }
2175
2176 int intel_ring_idle(struct intel_engine_cs *ring)
2177 {
2178         struct drm_i915_gem_request *req;
2179
2180         /* We need to add any requests required to flush the objects and ring */
2181         WARN_ON(ring->outstanding_lazy_request);
2182         if (ring->outstanding_lazy_request)
2183                 i915_add_request(ring->outstanding_lazy_request);
2184
2185         /* Wait upon the last request to be completed */
2186         if (list_empty(&ring->request_list))
2187                 return 0;
2188
2189         req = list_entry(ring->request_list.prev,
2190                         struct drm_i915_gem_request,
2191                         list);
2192
2193         /* Make sure we do not trigger any retires */
2194         return __i915_wait_request(req,
2195                                    atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2196                                    to_i915(ring->dev)->mm.interruptible,
2197                                    NULL, NULL);
2198 }
2199
2200 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2201 {
2202         request->ringbuf = request->ring->buffer;
2203         return 0;
2204 }
2205
2206 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2207 {
2208         /* NB: Until request management is fully tidied up and the OLR is
2209          * removed, there are too many ways for get false hits on this
2210          * anti-recursion check! */
2211         /*WARN_ON(ringbuf->reserved_size);*/
2212         WARN_ON(ringbuf->reserved_in_use);
2213
2214         ringbuf->reserved_size = size;
2215
2216         /*
2217          * Really need to call _begin() here but that currently leads to
2218          * recursion problems! This will be fixed later but for now just
2219          * return and hope for the best. Note that there is only a real
2220          * problem if the create of the request never actually calls _begin()
2221          * but if they are not submitting any work then why did they create
2222          * the request in the first place?
2223          */
2224 }
2225
2226 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2227 {
2228         WARN_ON(ringbuf->reserved_in_use);
2229
2230         ringbuf->reserved_size   = 0;
2231         ringbuf->reserved_in_use = false;
2232 }
2233
2234 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2235 {
2236         WARN_ON(ringbuf->reserved_in_use);
2237
2238         ringbuf->reserved_in_use = true;
2239         ringbuf->reserved_tail   = ringbuf->tail;
2240 }
2241
2242 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2243 {
2244         WARN_ON(!ringbuf->reserved_in_use);
2245         WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2246              "request reserved size too small: %d vs %d!\n",
2247              ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2248
2249         ringbuf->reserved_size   = 0;
2250         ringbuf->reserved_in_use = false;
2251 }
2252
2253 static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2254 {
2255         struct intel_ringbuffer *ringbuf = ring->buffer;
2256         int ret;
2257
2258         /*
2259          * Add on the reserved size to the request to make sure that after
2260          * the intended commands have been emitted, there is guaranteed to
2261          * still be enough free space to send them to the hardware.
2262          */
2263         if (!ringbuf->reserved_in_use)
2264                 bytes += ringbuf->reserved_size;
2265
2266         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2267                 ret = intel_wrap_ring_buffer(ring);
2268                 if (unlikely(ret))
2269                         return ret;
2270
2271                 if(ringbuf->reserved_size) {
2272                         uint32_t size = ringbuf->reserved_size;
2273
2274                         intel_ring_reserved_space_cancel(ringbuf);
2275                         intel_ring_reserved_space_reserve(ringbuf, size);
2276                 }
2277         }
2278
2279         if (unlikely(ringbuf->space < bytes)) {
2280                 ret = ring_wait_for_space(ring, bytes);
2281                 if (unlikely(ret))
2282                         return ret;
2283         }
2284
2285         return 0;
2286 }
2287
2288 int intel_ring_begin(struct intel_engine_cs *ring,
2289                      int num_dwords)
2290 {
2291         struct drm_i915_gem_request *req;
2292         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2293         int ret;
2294
2295         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2296                                    dev_priv->mm.interruptible);
2297         if (ret)
2298                 return ret;
2299
2300         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2301         if (ret)
2302                 return ret;
2303
2304         /* Preallocate the olr before touching the ring */
2305         ret = i915_gem_request_alloc(ring, ring->default_context, &req);
2306         if (ret)
2307                 return ret;
2308
2309         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2310         return 0;
2311 }
2312
2313 /* Align the ring tail to a cacheline boundary */
2314 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2315 {
2316         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2317         int ret;
2318
2319         if (num_dwords == 0)
2320                 return 0;
2321
2322         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2323         ret = intel_ring_begin(ring, num_dwords);
2324         if (ret)
2325                 return ret;
2326
2327         while (num_dwords--)
2328                 intel_ring_emit(ring, MI_NOOP);
2329
2330         intel_ring_advance(ring);
2331
2332         return 0;
2333 }
2334
2335 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2336 {
2337         struct drm_device *dev = ring->dev;
2338         struct drm_i915_private *dev_priv = dev->dev_private;
2339
2340         BUG_ON(ring->outstanding_lazy_request);
2341
2342         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2343                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2344                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2345                 if (HAS_VEBOX(dev))
2346                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2347         }
2348
2349         ring->set_seqno(ring, seqno);
2350         ring->hangcheck.seqno = seqno;
2351 }
2352
2353 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2354                                      u32 value)
2355 {
2356         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2357
2358        /* Every tail move must follow the sequence below */
2359
2360         /* Disable notification that the ring is IDLE. The GT
2361          * will then assume that it is busy and bring it out of rc6.
2362          */
2363         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2364                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2365
2366         /* Clear the context id. Here be magic! */
2367         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2368
2369         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2370         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2371                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2372                      50))
2373                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2374
2375         /* Now that the ring is fully powered up, update the tail */
2376         I915_WRITE_TAIL(ring, value);
2377         POSTING_READ(RING_TAIL(ring->mmio_base));
2378
2379         /* Let the ring send IDLE messages to the GT again,
2380          * and so let it sleep to conserve power when idle.
2381          */
2382         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2383                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2384 }
2385
2386 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2387                                u32 invalidate, u32 flush)
2388 {
2389         struct intel_engine_cs *ring = req->ring;
2390         uint32_t cmd;
2391         int ret;
2392
2393         ret = intel_ring_begin(ring, 4);
2394         if (ret)
2395                 return ret;
2396
2397         cmd = MI_FLUSH_DW;
2398         if (INTEL_INFO(ring->dev)->gen >= 8)
2399                 cmd += 1;
2400
2401         /* We always require a command barrier so that subsequent
2402          * commands, such as breadcrumb interrupts, are strictly ordered
2403          * wrt the contents of the write cache being flushed to memory
2404          * (and thus being coherent from the CPU).
2405          */
2406         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2407
2408         /*
2409          * Bspec vol 1c.5 - video engine command streamer:
2410          * "If ENABLED, all TLBs will be invalidated once the flush
2411          * operation is complete. This bit is only valid when the
2412          * Post-Sync Operation field is a value of 1h or 3h."
2413          */
2414         if (invalidate & I915_GEM_GPU_DOMAINS)
2415                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2416
2417         intel_ring_emit(ring, cmd);
2418         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2419         if (INTEL_INFO(ring->dev)->gen >= 8) {
2420                 intel_ring_emit(ring, 0); /* upper addr */
2421                 intel_ring_emit(ring, 0); /* value */
2422         } else  {
2423                 intel_ring_emit(ring, 0);
2424                 intel_ring_emit(ring, MI_NOOP);
2425         }
2426         intel_ring_advance(ring);
2427         return 0;
2428 }
2429
2430 static int
2431 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2432                               u64 offset, u32 len,
2433                               unsigned dispatch_flags)
2434 {
2435         struct intel_engine_cs *ring = req->ring;
2436         bool ppgtt = USES_PPGTT(ring->dev) &&
2437                         !(dispatch_flags & I915_DISPATCH_SECURE);
2438         int ret;
2439
2440         ret = intel_ring_begin(ring, 4);
2441         if (ret)
2442                 return ret;
2443
2444         /* FIXME(BDW): Address space and security selectors. */
2445         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2446         intel_ring_emit(ring, lower_32_bits(offset));
2447         intel_ring_emit(ring, upper_32_bits(offset));
2448         intel_ring_emit(ring, MI_NOOP);
2449         intel_ring_advance(ring);
2450
2451         return 0;
2452 }
2453
2454 static int
2455 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2456                              u64 offset, u32 len,
2457                              unsigned dispatch_flags)
2458 {
2459         struct intel_engine_cs *ring = req->ring;
2460         int ret;
2461
2462         ret = intel_ring_begin(ring, 2);
2463         if (ret)
2464                 return ret;
2465
2466         intel_ring_emit(ring,
2467                         MI_BATCH_BUFFER_START |
2468                         (dispatch_flags & I915_DISPATCH_SECURE ?
2469                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2470         /* bit0-7 is the length on GEN6+ */
2471         intel_ring_emit(ring, offset);
2472         intel_ring_advance(ring);
2473
2474         return 0;
2475 }
2476
2477 static int
2478 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2479                               u64 offset, u32 len,
2480                               unsigned dispatch_flags)
2481 {
2482         struct intel_engine_cs *ring = req->ring;
2483         int ret;
2484
2485         ret = intel_ring_begin(ring, 2);
2486         if (ret)
2487                 return ret;
2488
2489         intel_ring_emit(ring,
2490                         MI_BATCH_BUFFER_START |
2491                         (dispatch_flags & I915_DISPATCH_SECURE ?
2492                          0 : MI_BATCH_NON_SECURE_I965));
2493         /* bit0-7 is the length on GEN6+ */
2494         intel_ring_emit(ring, offset);
2495         intel_ring_advance(ring);
2496
2497         return 0;
2498 }
2499
2500 /* Blitter support (SandyBridge+) */
2501
2502 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2503                            u32 invalidate, u32 flush)
2504 {
2505         struct intel_engine_cs *ring = req->ring;
2506         struct drm_device *dev = ring->dev;
2507         uint32_t cmd;
2508         int ret;
2509
2510         ret = intel_ring_begin(ring, 4);
2511         if (ret)
2512                 return ret;
2513
2514         cmd = MI_FLUSH_DW;
2515         if (INTEL_INFO(dev)->gen >= 8)
2516                 cmd += 1;
2517
2518         /* We always require a command barrier so that subsequent
2519          * commands, such as breadcrumb interrupts, are strictly ordered
2520          * wrt the contents of the write cache being flushed to memory
2521          * (and thus being coherent from the CPU).
2522          */
2523         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2524
2525         /*
2526          * Bspec vol 1c.3 - blitter engine command streamer:
2527          * "If ENABLED, all TLBs will be invalidated once the flush
2528          * operation is complete. This bit is only valid when the
2529          * Post-Sync Operation field is a value of 1h or 3h."
2530          */
2531         if (invalidate & I915_GEM_DOMAIN_RENDER)
2532                 cmd |= MI_INVALIDATE_TLB;
2533         intel_ring_emit(ring, cmd);
2534         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2535         if (INTEL_INFO(dev)->gen >= 8) {
2536                 intel_ring_emit(ring, 0); /* upper addr */
2537                 intel_ring_emit(ring, 0); /* value */
2538         } else  {
2539                 intel_ring_emit(ring, 0);
2540                 intel_ring_emit(ring, MI_NOOP);
2541         }
2542         intel_ring_advance(ring);
2543
2544         return 0;
2545 }
2546
2547 int intel_init_render_ring_buffer(struct drm_device *dev)
2548 {
2549         struct drm_i915_private *dev_priv = dev->dev_private;
2550         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2551         struct drm_i915_gem_object *obj;
2552         int ret;
2553
2554         ring->name = "render ring";
2555         ring->id = RCS;
2556         ring->mmio_base = RENDER_RING_BASE;
2557
2558         if (INTEL_INFO(dev)->gen >= 8) {
2559                 if (i915_semaphore_is_enabled(dev)) {
2560                         obj = i915_gem_alloc_object(dev, 4096);
2561                         if (obj == NULL) {
2562                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2563                                 i915.semaphores = 0;
2564                         } else {
2565                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2566                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2567                                 if (ret != 0) {
2568                                         drm_gem_object_unreference(&obj->base);
2569                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2570                                         i915.semaphores = 0;
2571                                 } else
2572                                         dev_priv->semaphore_obj = obj;
2573                         }
2574                 }
2575
2576                 ring->init_context = intel_rcs_ctx_init;
2577                 ring->add_request = gen6_add_request;
2578                 ring->flush = gen8_render_ring_flush;
2579                 ring->irq_get = gen8_ring_get_irq;
2580                 ring->irq_put = gen8_ring_put_irq;
2581                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2582                 ring->get_seqno = gen6_ring_get_seqno;
2583                 ring->set_seqno = ring_set_seqno;
2584                 if (i915_semaphore_is_enabled(dev)) {
2585                         WARN_ON(!dev_priv->semaphore_obj);
2586                         ring->semaphore.sync_to = gen8_ring_sync;
2587                         ring->semaphore.signal = gen8_rcs_signal;
2588                         GEN8_RING_SEMAPHORE_INIT;
2589                 }
2590         } else if (INTEL_INFO(dev)->gen >= 6) {
2591                 ring->add_request = gen6_add_request;
2592                 ring->flush = gen7_render_ring_flush;
2593                 if (INTEL_INFO(dev)->gen == 6)
2594                         ring->flush = gen6_render_ring_flush;
2595                 ring->irq_get = gen6_ring_get_irq;
2596                 ring->irq_put = gen6_ring_put_irq;
2597                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2598                 ring->get_seqno = gen6_ring_get_seqno;
2599                 ring->set_seqno = ring_set_seqno;
2600                 if (i915_semaphore_is_enabled(dev)) {
2601                         ring->semaphore.sync_to = gen6_ring_sync;
2602                         ring->semaphore.signal = gen6_signal;
2603                         /*
2604                          * The current semaphore is only applied on pre-gen8
2605                          * platform.  And there is no VCS2 ring on the pre-gen8
2606                          * platform. So the semaphore between RCS and VCS2 is
2607                          * initialized as INVALID.  Gen8 will initialize the
2608                          * sema between VCS2 and RCS later.
2609                          */
2610                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2611                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2612                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2613                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2614                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2615                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2616                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2617                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2618                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2619                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2620                 }
2621         } else if (IS_GEN5(dev)) {
2622                 ring->add_request = pc_render_add_request;
2623                 ring->flush = gen4_render_ring_flush;
2624                 ring->get_seqno = pc_render_get_seqno;
2625                 ring->set_seqno = pc_render_set_seqno;
2626                 ring->irq_get = gen5_ring_get_irq;
2627                 ring->irq_put = gen5_ring_put_irq;
2628                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2629                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2630         } else {
2631                 ring->add_request = i9xx_add_request;
2632                 if (INTEL_INFO(dev)->gen < 4)
2633                         ring->flush = gen2_render_ring_flush;
2634                 else
2635                         ring->flush = gen4_render_ring_flush;
2636                 ring->get_seqno = ring_get_seqno;
2637                 ring->set_seqno = ring_set_seqno;
2638                 if (IS_GEN2(dev)) {
2639                         ring->irq_get = i8xx_ring_get_irq;
2640                         ring->irq_put = i8xx_ring_put_irq;
2641                 } else {
2642                         ring->irq_get = i9xx_ring_get_irq;
2643                         ring->irq_put = i9xx_ring_put_irq;
2644                 }
2645                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2646         }
2647         ring->write_tail = ring_write_tail;
2648
2649         if (IS_HASWELL(dev))
2650                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2651         else if (IS_GEN8(dev))
2652                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2653         else if (INTEL_INFO(dev)->gen >= 6)
2654                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2655         else if (INTEL_INFO(dev)->gen >= 4)
2656                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2657         else if (IS_I830(dev) || IS_845G(dev))
2658                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2659         else
2660                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2661         ring->init_hw = init_render_ring;
2662         ring->cleanup = render_ring_cleanup;
2663
2664         /* Workaround batchbuffer to combat CS tlb bug. */
2665         if (HAS_BROKEN_CS_TLB(dev)) {
2666                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2667                 if (obj == NULL) {
2668                         DRM_ERROR("Failed to allocate batch bo\n");
2669                         return -ENOMEM;
2670                 }
2671
2672                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2673                 if (ret != 0) {
2674                         drm_gem_object_unreference(&obj->base);
2675                         DRM_ERROR("Failed to ping batch bo\n");
2676                         return ret;
2677                 }
2678
2679                 ring->scratch.obj = obj;
2680                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2681         }
2682
2683         ret = intel_init_ring_buffer(dev, ring);
2684         if (ret)
2685                 return ret;
2686
2687         if (INTEL_INFO(dev)->gen >= 5) {
2688                 ret = intel_init_pipe_control(ring);
2689                 if (ret)
2690                         return ret;
2691         }
2692
2693         return 0;
2694 }
2695
2696 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2697 {
2698         struct drm_i915_private *dev_priv = dev->dev_private;
2699         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2700
2701         ring->name = "bsd ring";
2702         ring->id = VCS;
2703
2704         ring->write_tail = ring_write_tail;
2705         if (INTEL_INFO(dev)->gen >= 6) {
2706                 ring->mmio_base = GEN6_BSD_RING_BASE;
2707                 /* gen6 bsd needs a special wa for tail updates */
2708                 if (IS_GEN6(dev))
2709                         ring->write_tail = gen6_bsd_ring_write_tail;
2710                 ring->flush = gen6_bsd_ring_flush;
2711                 ring->add_request = gen6_add_request;
2712                 ring->get_seqno = gen6_ring_get_seqno;
2713                 ring->set_seqno = ring_set_seqno;
2714                 if (INTEL_INFO(dev)->gen >= 8) {
2715                         ring->irq_enable_mask =
2716                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2717                         ring->irq_get = gen8_ring_get_irq;
2718                         ring->irq_put = gen8_ring_put_irq;
2719                         ring->dispatch_execbuffer =
2720                                 gen8_ring_dispatch_execbuffer;
2721                         if (i915_semaphore_is_enabled(dev)) {
2722                                 ring->semaphore.sync_to = gen8_ring_sync;
2723                                 ring->semaphore.signal = gen8_xcs_signal;
2724                                 GEN8_RING_SEMAPHORE_INIT;
2725                         }
2726                 } else {
2727                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2728                         ring->irq_get = gen6_ring_get_irq;
2729                         ring->irq_put = gen6_ring_put_irq;
2730                         ring->dispatch_execbuffer =
2731                                 gen6_ring_dispatch_execbuffer;
2732                         if (i915_semaphore_is_enabled(dev)) {
2733                                 ring->semaphore.sync_to = gen6_ring_sync;
2734                                 ring->semaphore.signal = gen6_signal;
2735                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2736                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2737                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2738                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2739                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2740                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2741                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2742                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2743                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2744                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2745                         }
2746                 }
2747         } else {
2748                 ring->mmio_base = BSD_RING_BASE;
2749                 ring->flush = bsd_ring_flush;
2750                 ring->add_request = i9xx_add_request;
2751                 ring->get_seqno = ring_get_seqno;
2752                 ring->set_seqno = ring_set_seqno;
2753                 if (IS_GEN5(dev)) {
2754                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2755                         ring->irq_get = gen5_ring_get_irq;
2756                         ring->irq_put = gen5_ring_put_irq;
2757                 } else {
2758                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2759                         ring->irq_get = i9xx_ring_get_irq;
2760                         ring->irq_put = i9xx_ring_put_irq;
2761                 }
2762                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2763         }
2764         ring->init_hw = init_ring_common;
2765
2766         return intel_init_ring_buffer(dev, ring);
2767 }
2768
2769 /**
2770  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2771  */
2772 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2773 {
2774         struct drm_i915_private *dev_priv = dev->dev_private;
2775         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2776
2777         ring->name = "bsd2 ring";
2778         ring->id = VCS2;
2779
2780         ring->write_tail = ring_write_tail;
2781         ring->mmio_base = GEN8_BSD2_RING_BASE;
2782         ring->flush = gen6_bsd_ring_flush;
2783         ring->add_request = gen6_add_request;
2784         ring->get_seqno = gen6_ring_get_seqno;
2785         ring->set_seqno = ring_set_seqno;
2786         ring->irq_enable_mask =
2787                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2788         ring->irq_get = gen8_ring_get_irq;
2789         ring->irq_put = gen8_ring_put_irq;
2790         ring->dispatch_execbuffer =
2791                         gen8_ring_dispatch_execbuffer;
2792         if (i915_semaphore_is_enabled(dev)) {
2793                 ring->semaphore.sync_to = gen8_ring_sync;
2794                 ring->semaphore.signal = gen8_xcs_signal;
2795                 GEN8_RING_SEMAPHORE_INIT;
2796         }
2797         ring->init_hw = init_ring_common;
2798
2799         return intel_init_ring_buffer(dev, ring);
2800 }
2801
2802 int intel_init_blt_ring_buffer(struct drm_device *dev)
2803 {
2804         struct drm_i915_private *dev_priv = dev->dev_private;
2805         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2806
2807         ring->name = "blitter ring";
2808         ring->id = BCS;
2809
2810         ring->mmio_base = BLT_RING_BASE;
2811         ring->write_tail = ring_write_tail;
2812         ring->flush = gen6_ring_flush;
2813         ring->add_request = gen6_add_request;
2814         ring->get_seqno = gen6_ring_get_seqno;
2815         ring->set_seqno = ring_set_seqno;
2816         if (INTEL_INFO(dev)->gen >= 8) {
2817                 ring->irq_enable_mask =
2818                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2819                 ring->irq_get = gen8_ring_get_irq;
2820                 ring->irq_put = gen8_ring_put_irq;
2821                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2822                 if (i915_semaphore_is_enabled(dev)) {
2823                         ring->semaphore.sync_to = gen8_ring_sync;
2824                         ring->semaphore.signal = gen8_xcs_signal;
2825                         GEN8_RING_SEMAPHORE_INIT;
2826                 }
2827         } else {
2828                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2829                 ring->irq_get = gen6_ring_get_irq;
2830                 ring->irq_put = gen6_ring_put_irq;
2831                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2832                 if (i915_semaphore_is_enabled(dev)) {
2833                         ring->semaphore.signal = gen6_signal;
2834                         ring->semaphore.sync_to = gen6_ring_sync;
2835                         /*
2836                          * The current semaphore is only applied on pre-gen8
2837                          * platform.  And there is no VCS2 ring on the pre-gen8
2838                          * platform. So the semaphore between BCS and VCS2 is
2839                          * initialized as INVALID.  Gen8 will initialize the
2840                          * sema between BCS and VCS2 later.
2841                          */
2842                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2843                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2844                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2845                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2846                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2847                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2848                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2849                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2850                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2851                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2852                 }
2853         }
2854         ring->init_hw = init_ring_common;
2855
2856         return intel_init_ring_buffer(dev, ring);
2857 }
2858
2859 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2860 {
2861         struct drm_i915_private *dev_priv = dev->dev_private;
2862         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2863
2864         ring->name = "video enhancement ring";
2865         ring->id = VECS;
2866
2867         ring->mmio_base = VEBOX_RING_BASE;
2868         ring->write_tail = ring_write_tail;
2869         ring->flush = gen6_ring_flush;
2870         ring->add_request = gen6_add_request;
2871         ring->get_seqno = gen6_ring_get_seqno;
2872         ring->set_seqno = ring_set_seqno;
2873
2874         if (INTEL_INFO(dev)->gen >= 8) {
2875                 ring->irq_enable_mask =
2876                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2877                 ring->irq_get = gen8_ring_get_irq;
2878                 ring->irq_put = gen8_ring_put_irq;
2879                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2880                 if (i915_semaphore_is_enabled(dev)) {
2881                         ring->semaphore.sync_to = gen8_ring_sync;
2882                         ring->semaphore.signal = gen8_xcs_signal;
2883                         GEN8_RING_SEMAPHORE_INIT;
2884                 }
2885         } else {
2886                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2887                 ring->irq_get = hsw_vebox_get_irq;
2888                 ring->irq_put = hsw_vebox_put_irq;
2889                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2890                 if (i915_semaphore_is_enabled(dev)) {
2891                         ring->semaphore.sync_to = gen6_ring_sync;
2892                         ring->semaphore.signal = gen6_signal;
2893                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2894                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2895                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2896                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2897                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2898                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2899                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2900                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2901                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2902                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2903                 }
2904         }
2905         ring->init_hw = init_ring_common;
2906
2907         return intel_init_ring_buffer(dev, ring);
2908 }
2909
2910 int
2911 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
2912 {
2913         struct intel_engine_cs *ring = req->ring;
2914         int ret;
2915
2916         if (!ring->gpu_caches_dirty)
2917                 return 0;
2918
2919         ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
2920         if (ret)
2921                 return ret;
2922
2923         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
2924
2925         ring->gpu_caches_dirty = false;
2926         return 0;
2927 }
2928
2929 int
2930 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
2931 {
2932         struct intel_engine_cs *ring = req->ring;
2933         uint32_t flush_domains;
2934         int ret;
2935
2936         flush_domains = 0;
2937         if (ring->gpu_caches_dirty)
2938                 flush_domains = I915_GEM_GPU_DOMAINS;
2939
2940         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
2941         if (ret)
2942                 return ret;
2943
2944         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
2945
2946         ring->gpu_caches_dirty = false;
2947         return 0;
2948 }
2949
2950 void
2951 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2952 {
2953         int ret;
2954
2955         if (!intel_ring_initialized(ring))
2956                 return;
2957
2958         ret = intel_ring_idle(ring);
2959         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2960                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2961                           ring->name, ret);
2962
2963         stop_ring(ring);
2964 }