drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 /*
  37  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  38  * over cache flushing.
  39  */
  40 struct pipe_control {
  41         struct drm_i915_gem_object *obj;
  42         volatile u32 *cpu_page;
  43         u32 gtt_offset;
  44 };
  45
  46 static inline int ring_space(struct intel_ring_buffer *ring)
  47 {
  48         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  49         if (space < 0)
  50                 space += ring->size;
  51         return space;
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         struct pipe_control *pc = ring->private;
 179         u32 scratch_addr = pc->gtt_offset + 128;
 180         int ret;
 181
 182
 183         ret = intel_ring_begin(ring, 6);
 184         if (ret)
 185                 return ret;
 186
 187         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 188         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 189                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 190         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 191         intel_ring_emit(ring, 0); /* low dword */
 192         intel_ring_emit(ring, 0); /* high dword */
 193         intel_ring_emit(ring, MI_NOOP);
 194         intel_ring_advance(ring);
 195
 196         ret = intel_ring_begin(ring, 6);
 197         if (ret)
 198                 return ret;
 199
 200         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 201         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 202         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, 0);
 205         intel_ring_emit(ring, MI_NOOP);
 206         intel_ring_advance(ring);
 207
 208         return 0;
 209 }
 210
 211 static int
 212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 213                          u32 invalidate_domains, u32 flush_domains)
 214 {
 215         u32 flags = 0;
 216         struct pipe_control *pc = ring->private;
 217         u32 scratch_addr = pc->gtt_offset + 128;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(ring);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (flush_domains) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (invalidate_domains) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         ret = intel_ring_begin(ring, 4);
 252         if (ret)
 253                 return ret;
 254
 255         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 256         intel_ring_emit(ring, flags);
 257         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 258         intel_ring_emit(ring, 0);
 259         intel_ring_advance(ring);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 266 {
 267         int ret;
 268
 269         ret = intel_ring_begin(ring, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 275                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 276         intel_ring_emit(ring, 0);
 277         intel_ring_emit(ring, 0);
 278         intel_ring_advance(ring);
 279
 280         return 0;
 281 }
 282
 283 static int
 284 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 285                        u32 invalidate_domains, u32 flush_domains)
 286 {
 287         u32 flags = 0;
 288         struct pipe_control *pc = ring->private;
 289         u32 scratch_addr = pc->gtt_offset + 128;
 290         int ret;
 291
 292         /*
 293          * Ensure that any following seqno writes only happen when the render
 294          * cache is indeed flushed.
 295          *
 296          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 297          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 298          * don't try to be clever and just set it unconditionally.
 299          */
 300         flags |= PIPE_CONTROL_CS_STALL;
 301
 302         /* Just flush everything.  Experiments have shown that reducing the
 303          * number of bits based on the write domains has little performance
 304          * impact.
 305          */
 306         if (flush_domains) {
 307                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 308                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 309         }
 310         if (invalidate_domains) {
 311                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 312                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 313                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 314                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 315                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 316                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 317                 /*
 318                  * TLB invalidate requires a post-sync write.
 319                  */
 320                 flags |= PIPE_CONTROL_QW_WRITE;
 321                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 322
 323                 /* Workaround: we must issue a pipe_control with CS-stall bit
 324                  * set before a pipe_control command that has the state cache
 325                  * invalidate bit set. */
 326                 gen7_render_ring_cs_stall_wa(ring);
 327         }
 328
 329         ret = intel_ring_begin(ring, 4);
 330         if (ret)
 331                 return ret;
 332
 333         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 334         intel_ring_emit(ring, flags);
 335         intel_ring_emit(ring, scratch_addr);
 336         intel_ring_emit(ring, 0);
 337         intel_ring_advance(ring);
 338
 339         return 0;
 340 }
 341
 342 static void ring_write_tail(struct intel_ring_buffer *ring,
 343                             u32 value)
 344 {
 345         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 346         I915_WRITE_TAIL(ring, value);
 347 }
 348
 349 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 350 {
 351         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 352         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 353                         RING_ACTHD(ring->mmio_base) : ACTHD;
 354
 355         return I915_READ(acthd_reg);
 356 }
 357
 358 static int init_ring_common(struct intel_ring_buffer *ring)
 359 {
 360         struct drm_device *dev = ring->dev;
 361         drm_i915_private_t *dev_priv = dev->dev_private;
 362         struct drm_i915_gem_object *obj = ring->obj;
 363         int ret = 0;
 364         u32 head;
 365
 366         if (HAS_FORCE_WAKE(dev))
 367                 gen6_gt_force_wake_get(dev_priv);
 368
 369         /* Stop the ring if it's running. */
 370         I915_WRITE_CTL(ring, 0);
 371         I915_WRITE_HEAD(ring, 0);
 372         ring->write_tail(ring, 0);
 373
 374         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 375
 376         /* G45 ring initialization fails to reset head to zero */
 377         if (head != 0) {
 378                 DRM_DEBUG_KMS("%s head not reset to zero "
 379                               "ctl %08x head %08x tail %08x start %08x\n",
 380                               ring->name,
 381                               I915_READ_CTL(ring),
 382                               I915_READ_HEAD(ring),
 383                               I915_READ_TAIL(ring),
 384                               I915_READ_START(ring));
 385
 386                 I915_WRITE_HEAD(ring, 0);
 387
 388                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 389                         DRM_ERROR("failed to set %s head to zero "
 390                                   "ctl %08x head %08x tail %08x start %08x\n",
 391                                   ring->name,
 392                                   I915_READ_CTL(ring),
 393                                   I915_READ_HEAD(ring),
 394                                   I915_READ_TAIL(ring),
 395                                   I915_READ_START(ring));
 396                 }
 397         }
 398
 399         /* Initialize the ring. This must happen _after_ we've cleared the ring
 400          * registers with the above sequence (the readback of the HEAD registers
 401          * also enforces ordering), otherwise the hw might lose the new ring
 402          * register values. */
 403         I915_WRITE_START(ring, obj->gtt_offset);
 404         I915_WRITE_CTL(ring,
 405                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 406                         | RING_VALID);
 407
 408         /* If the head is still not zero, the ring is dead */
 409         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 410                      I915_READ_START(ring) == obj->gtt_offset &&
 411                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 412                 DRM_ERROR("%s initialization failed "
 413                                 "ctl %08x head %08x tail %08x start %08x\n",
 414                                 ring->name,
 415                                 I915_READ_CTL(ring),
 416                                 I915_READ_HEAD(ring),
 417                                 I915_READ_TAIL(ring),
 418                                 I915_READ_START(ring));
 419                 ret = -EIO;
 420                 goto out;
 421         }
 422
 423         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 424                 i915_kernel_lost_context(ring->dev);
 425         else {
 426                 ring->head = I915_READ_HEAD(ring);
 427                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 428                 ring->space = ring_space(ring);
 429                 ring->last_retired_head = -1;
 430         }
 431
 432 out:
 433         if (HAS_FORCE_WAKE(dev))
 434                 gen6_gt_force_wake_put(dev_priv);
 435
 436         return ret;
 437 }
 438
 439 static int
 440 init_pipe_control(struct intel_ring_buffer *ring)
 441 {
 442         struct pipe_control *pc;
 443         struct drm_i915_gem_object *obj;
 444         int ret;
 445
 446         if (ring->private)
 447                 return 0;
 448
 449         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 450         if (!pc)
 451                 return -ENOMEM;
 452
 453         obj = i915_gem_alloc_object(ring->dev, 4096);
 454         if (obj == NULL) {
 455                 DRM_ERROR("Failed to allocate seqno page\n");
 456                 ret = -ENOMEM;
 457                 goto err;
 458         }
 459
 460         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 461
 462         ret = i915_gem_object_pin(obj, 4096, true, false);
 463         if (ret)
 464                 goto err_unref;
 465
 466         pc->gtt_offset = obj->gtt_offset;
 467         pc->cpu_page =  kmap(sg_page(obj->pages->sgl));
 468         if (pc->cpu_page == NULL)
 469                 goto err_unpin;
 470
 471         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 472                          ring->name, pc->gtt_offset);
 473
 474         pc->obj = obj;
 475         ring->private = pc;
 476         return 0;
 477
 478 err_unpin:
 479         i915_gem_object_unpin(obj);
 480 err_unref:
 481         drm_gem_object_unreference(&obj->base);
 482 err:
 483         kfree(pc);
 484         return ret;
 485 }
 486
 487 static void
 488 cleanup_pipe_control(struct intel_ring_buffer *ring)
 489 {
 490         struct pipe_control *pc = ring->private;
 491         struct drm_i915_gem_object *obj;
 492
 493         obj = pc->obj;
 494
 495         kunmap(sg_page(obj->pages->sgl));
 496         i915_gem_object_unpin(obj);
 497         drm_gem_object_unreference(&obj->base);
 498
 499         kfree(pc);
 500 }
 501
 502 static int init_render_ring(struct intel_ring_buffer *ring)
 503 {
 504         struct drm_device *dev = ring->dev;
 505         struct drm_i915_private *dev_priv = dev->dev_private;
 506         int ret = init_ring_common(ring);
 507
 508         if (INTEL_INFO(dev)->gen > 3)
 509                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 510
 511         /* We need to disable the AsyncFlip performance optimisations in order
 512          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 513          * programmed to '1' on all products.
 514          */
 515         if (INTEL_INFO(dev)->gen >= 6)
 516                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 517
 518         /* Required for the hardware to program scanline values for waiting */
 519         if (INTEL_INFO(dev)->gen == 6)
 520                 I915_WRITE(GFX_MODE,
 521                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 522
 523         if (IS_GEN7(dev))
 524                 I915_WRITE(GFX_MODE_GEN7,
 525                            _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 526                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 527
 528         if (INTEL_INFO(dev)->gen >= 5) {
 529                 ret = init_pipe_control(ring);
 530                 if (ret)
 531                         return ret;
 532         }
 533
 534         if (IS_GEN6(dev)) {
 535                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 536                  * "If this bit is set, STCunit will have LRA as replacement
 537                  *  policy. [...] This bit must be reset.  LRA replacement
 538                  *  policy is not supported."
 539                  */
 540                 I915_WRITE(CACHE_MODE_0,
 541                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 542
 543                 /* This is not explicitly set for GEN6, so read the register.
 544                  * see intel_ring_mi_set_context() for why we care.
 545                  * TODO: consider explicitly setting the bit for GEN5
 546                  */
 547                 ring->itlb_before_ctx_switch =
 548                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 549         }
 550
 551         if (INTEL_INFO(dev)->gen >= 6)
 552                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 553
 554         if (HAS_L3_GPU_CACHE(dev))
 555                 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
 556
 557         return ret;
 558 }
 559
 560 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 561 {
 562         struct drm_device *dev = ring->dev;
 563
 564         if (!ring->private)
 565                 return;
 566
 567         if (HAS_BROKEN_CS_TLB(dev))
 568                 drm_gem_object_unreference(to_gem_object(ring->private));
 569
 570         if (INTEL_INFO(dev)->gen >= 5)
 571                 cleanup_pipe_control(ring);
 572
 573         ring->private = NULL;
 574 }
 575
 576 static void
 577 update_mboxes(struct intel_ring_buffer *ring,
 578               u32 mmio_offset)
 579 {
 580         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 581         intel_ring_emit(ring, mmio_offset);
 582         intel_ring_emit(ring, ring->outstanding_lazy_request);
 583 }
 584
 585 /**
 586  * gen6_add_request - Update the semaphore mailbox registers
 587  *
 588  * @ring - ring that is adding a request
 589  * @seqno - return seqno stuck into the ring
 590  *
 591  * Update the mailbox registers in the *other* rings with the current seqno.
 592  * This acts like a signal in the canonical semaphore.
 593  */
 594 static int
 595 gen6_add_request(struct intel_ring_buffer *ring)
 596 {
 597         u32 mbox1_reg;
 598         u32 mbox2_reg;
 599         int ret;
 600
 601         ret = intel_ring_begin(ring, 10);
 602         if (ret)
 603                 return ret;
 604
 605         mbox1_reg = ring->signal_mbox[0];
 606         mbox2_reg = ring->signal_mbox[1];
 607
 608         update_mboxes(ring, mbox1_reg);
 609         update_mboxes(ring, mbox2_reg);
 610         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 611         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 612         intel_ring_emit(ring, ring->outstanding_lazy_request);
 613         intel_ring_emit(ring, MI_USER_INTERRUPT);
 614         intel_ring_advance(ring);
 615
 616         return 0;
 617 }
 618
 619 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 620                                               u32 seqno)
 621 {
 622         struct drm_i915_private *dev_priv = dev->dev_private;
 623         return dev_priv->last_seqno < seqno;
 624 }
 625
 626 /**
 627  * intel_ring_sync - sync the waiter to the signaller on seqno
 628  *
 629  * @waiter - ring that is waiting
 630  * @signaller - ring which has, or will signal
 631  * @seqno - seqno which the waiter will block on
 632  */
 633 static int
 634 gen6_ring_sync(struct intel_ring_buffer *waiter,
 635                struct intel_ring_buffer *signaller,
 636                u32 seqno)
 637 {
 638         int ret;
 639         u32 dw1 = MI_SEMAPHORE_MBOX |
 640                   MI_SEMAPHORE_COMPARE |
 641                   MI_SEMAPHORE_REGISTER;
 642
 643         /* Throughout all of the GEM code, seqno passed implies our current
 644          * seqno is >= the last seqno executed. However for hardware the
 645          * comparison is strictly greater than.
 646          */
 647         seqno -= 1;
 648
 649         WARN_ON(signaller->semaphore_register[waiter->id] ==
 650                 MI_SEMAPHORE_SYNC_INVALID);
 651
 652         ret = intel_ring_begin(waiter, 4);
 653         if (ret)
 654                 return ret;
 655
 656         /* If seqno wrap happened, omit the wait with no-ops */
 657         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 658                 intel_ring_emit(waiter,
 659                                 dw1 |
 660                                 signaller->semaphore_register[waiter->id]);
 661                 intel_ring_emit(waiter, seqno);
 662                 intel_ring_emit(waiter, 0);
 663                 intel_ring_emit(waiter, MI_NOOP);
 664         } else {
 665                 intel_ring_emit(waiter, MI_NOOP);
 666                 intel_ring_emit(waiter, MI_NOOP);
 667                 intel_ring_emit(waiter, MI_NOOP);
 668                 intel_ring_emit(waiter, MI_NOOP);
 669         }
 670         intel_ring_advance(waiter);
 671
 672         return 0;
 673 }
 674
 675 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 676 do {                                                                    \
 677         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 678                  PIPE_CONTROL_DEPTH_STALL);                             \
 679         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 680         intel_ring_emit(ring__, 0);                                                     \
 681         intel_ring_emit(ring__, 0);                                                     \
 682 } while (0)
 683
 684 static int
 685 pc_render_add_request(struct intel_ring_buffer *ring)
 686 {
 687         struct pipe_control *pc = ring->private;
 688         u32 scratch_addr = pc->gtt_offset + 128;
 689         int ret;
 690
 691         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 692          * incoherent with writes to memory, i.e. completely fubar,
 693          * so we need to use PIPE_NOTIFY instead.
 694          *
 695          * However, we also need to workaround the qword write
 696          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 697          * memory before requesting an interrupt.
 698          */
 699         ret = intel_ring_begin(ring, 32);
 700         if (ret)
 701                 return ret;
 702
 703         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 704                         PIPE_CONTROL_WRITE_FLUSH |
 705                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 706         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 707         intel_ring_emit(ring, ring->outstanding_lazy_request);
 708         intel_ring_emit(ring, 0);
 709         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 710         scratch_addr += 128; /* write to separate cachelines */
 711         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 712         scratch_addr += 128;
 713         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 714         scratch_addr += 128;
 715         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 716         scratch_addr += 128;
 717         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 718         scratch_addr += 128;
 719         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 720
 721         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 722                         PIPE_CONTROL_WRITE_FLUSH |
 723                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 724                         PIPE_CONTROL_NOTIFY);
 725         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 726         intel_ring_emit(ring, ring->outstanding_lazy_request);
 727         intel_ring_emit(ring, 0);
 728         intel_ring_advance(ring);
 729
 730         return 0;
 731 }
 732
 733 static u32
 734 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 735 {
 736         /* Workaround to force correct ordering between irq and seqno writes on
 737          * ivb (and maybe also on snb) by reading from a CS register (like
 738          * ACTHD) before reading the status page. */
 739         if (!lazy_coherency)
 740                 intel_ring_get_active_head(ring);
 741         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 742 }
 743
 744 static u32
 745 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 746 {
 747         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 748 }
 749
 750 static void
 751 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 752 {
 753         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 754 }
 755
 756 static u32
 757 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 758 {
 759         struct pipe_control *pc = ring->private;
 760         return pc->cpu_page[0];
 761 }
 762
 763 static void
 764 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 765 {
 766         struct pipe_control *pc = ring->private;
 767         pc->cpu_page[0] = seqno;
 768 }
 769
 770 static bool
 771 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 772 {
 773         struct drm_device *dev = ring->dev;
 774         drm_i915_private_t *dev_priv = dev->dev_private;
 775         unsigned long flags;
 776
 777         if (!dev->irq_enabled)
 778                 return false;
 779
 780         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 781         if (ring->irq_refcount++ == 0) {
 782                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 783                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 784                 POSTING_READ(GTIMR);
 785         }
 786         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 787
 788         return true;
 789 }
 790
 791 static void
 792 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 793 {
 794         struct drm_device *dev = ring->dev;
 795         drm_i915_private_t *dev_priv = dev->dev_private;
 796         unsigned long flags;
 797
 798         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 799         if (--ring->irq_refcount == 0) {
 800                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 801                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 802                 POSTING_READ(GTIMR);
 803         }
 804         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 805 }
 806
 807 static bool
 808 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 809 {
 810         struct drm_device *dev = ring->dev;
 811         drm_i915_private_t *dev_priv = dev->dev_private;
 812         unsigned long flags;
 813
 814         if (!dev->irq_enabled)
 815                 return false;
 816
 817         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 818         if (ring->irq_refcount++ == 0) {
 819                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 820                 I915_WRITE(IMR, dev_priv->irq_mask);
 821                 POSTING_READ(IMR);
 822         }
 823         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 824
 825         return true;
 826 }
 827
 828 static void
 829 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 830 {
 831         struct drm_device *dev = ring->dev;
 832         drm_i915_private_t *dev_priv = dev->dev_private;
 833         unsigned long flags;
 834
 835         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 836         if (--ring->irq_refcount == 0) {
 837                 dev_priv->irq_mask |= ring->irq_enable_mask;
 838                 I915_WRITE(IMR, dev_priv->irq_mask);
 839                 POSTING_READ(IMR);
 840         }
 841         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 842 }
 843
 844 static bool
 845 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 846 {
 847         struct drm_device *dev = ring->dev;
 848         drm_i915_private_t *dev_priv = dev->dev_private;
 849         unsigned long flags;
 850
 851         if (!dev->irq_enabled)
 852                 return false;
 853
 854         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 855         if (ring->irq_refcount++ == 0) {
 856                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 857                 I915_WRITE16(IMR, dev_priv->irq_mask);
 858                 POSTING_READ16(IMR);
 859         }
 860         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 861
 862         return true;
 863 }
 864
 865 static void
 866 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 867 {
 868         struct drm_device *dev = ring->dev;
 869         drm_i915_private_t *dev_priv = dev->dev_private;
 870         unsigned long flags;
 871
 872         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 873         if (--ring->irq_refcount == 0) {
 874                 dev_priv->irq_mask |= ring->irq_enable_mask;
 875                 I915_WRITE16(IMR, dev_priv->irq_mask);
 876                 POSTING_READ16(IMR);
 877         }
 878         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 879 }
 880
 881 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 882 {
 883         struct drm_device *dev = ring->dev;
 884         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 885         u32 mmio = 0;
 886
 887         /* The ring status page addresses are no longer next to the rest of
 888          * the ring registers as of gen7.
 889          */
 890         if (IS_GEN7(dev)) {
 891                 switch (ring->id) {
 892                 case RCS:
 893                         mmio = RENDER_HWS_PGA_GEN7;
 894                         break;
 895                 case BCS:
 896                         mmio = BLT_HWS_PGA_GEN7;
 897                         break;
 898                 case VCS:
 899                         mmio = BSD_HWS_PGA_GEN7;
 900                         break;
 901                 }
 902         } else if (IS_GEN6(ring->dev)) {
 903                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 904         } else {
 905                 mmio = RING_HWS_PGA(ring->mmio_base);
 906         }
 907
 908         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 909         POSTING_READ(mmio);
 910 }
 911
 912 static int
 913 bsd_ring_flush(struct intel_ring_buffer *ring,
 914                u32     invalidate_domains,
 915                u32     flush_domains)
 916 {
 917         int ret;
 918
 919         ret = intel_ring_begin(ring, 2);
 920         if (ret)
 921                 return ret;
 922
 923         intel_ring_emit(ring, MI_FLUSH);
 924         intel_ring_emit(ring, MI_NOOP);
 925         intel_ring_advance(ring);
 926         return 0;
 927 }
 928
 929 static int
 930 i9xx_add_request(struct intel_ring_buffer *ring)
 931 {
 932         int ret;
 933
 934         ret = intel_ring_begin(ring, 4);
 935         if (ret)
 936                 return ret;
 937
 938         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 939         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 940         intel_ring_emit(ring, ring->outstanding_lazy_request);
 941         intel_ring_emit(ring, MI_USER_INTERRUPT);
 942         intel_ring_advance(ring);
 943
 944         return 0;
 945 }
 946
 947 static bool
 948 gen6_ring_get_irq(struct intel_ring_buffer *ring)
 949 {
 950         struct drm_device *dev = ring->dev;
 951         drm_i915_private_t *dev_priv = dev->dev_private;
 952         unsigned long flags;
 953
 954         if (!dev->irq_enabled)
 955                return false;
 956
 957         /* It looks like we need to prevent the gt from suspending while waiting
 958          * for an notifiy irq, otherwise irqs seem to get lost on at least the
 959          * blt/bsd rings on ivb. */
 960         gen6_gt_force_wake_get(dev_priv);
 961
 962         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 963         if (ring->irq_refcount++ == 0) {
 964                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
 965                         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
 966                                                 GEN6_RENDER_L3_PARITY_ERROR));
 967                 else
 968                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
 969                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 970                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 971                 POSTING_READ(GTIMR);
 972         }
 973         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 974
 975         return true;
 976 }
 977
 978 static void
 979 gen6_ring_put_irq(struct intel_ring_buffer *ring)
 980 {
 981         struct drm_device *dev = ring->dev;
 982         drm_i915_private_t *dev_priv = dev->dev_private;
 983         unsigned long flags;
 984
 985         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 986         if (--ring->irq_refcount == 0) {
 987                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
 988                         I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
 989                 else
 990                         I915_WRITE_IMR(ring, ~0);
 991                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 992                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 993                 POSTING_READ(GTIMR);
 994         }
 995         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 996
 997         gen6_gt_force_wake_put(dev_priv);
 998 }
 999
1000 static int
1001 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1002                          u32 offset, u32 length,
1003                          unsigned flags)
1004 {
1005         int ret;
1006
1007         ret = intel_ring_begin(ring, 2);
1008         if (ret)
1009                 return ret;
1010
1011         intel_ring_emit(ring,
1012                         MI_BATCH_BUFFER_START |
1013                         MI_BATCH_GTT |
1014                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1015         intel_ring_emit(ring, offset);
1016         intel_ring_advance(ring);
1017
1018         return 0;
1019 }
1020
1021 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1022 #define I830_BATCH_LIMIT (256*1024)
1023 static int
1024 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1025                                 u32 offset, u32 len,
1026                                 unsigned flags)
1027 {
1028         int ret;
1029
1030         if (flags & I915_DISPATCH_PINNED) {
1031                 ret = intel_ring_begin(ring, 4);
1032                 if (ret)
1033                         return ret;
1034
1035                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1036                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1037                 intel_ring_emit(ring, offset + len - 8);
1038                 intel_ring_emit(ring, MI_NOOP);
1039                 intel_ring_advance(ring);
1040         } else {
1041                 struct drm_i915_gem_object *obj = ring->private;
1042                 u32 cs_offset = obj->gtt_offset;
1043
1044                 if (len > I830_BATCH_LIMIT)
1045                         return -ENOSPC;
1046
1047                 ret = intel_ring_begin(ring, 9+3);
1048                 if (ret)
1049                         return ret;
1050                 /* Blit the batch (which has now all relocs applied) to the stable batch
1051                  * scratch bo area (so that the CS never stumbles over its tlb
1052                  * invalidation bug) ... */
1053                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1054                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1055                                 XY_SRC_COPY_BLT_WRITE_RGB);
1056                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1057                 intel_ring_emit(ring, 0);
1058                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1059                 intel_ring_emit(ring, cs_offset);
1060                 intel_ring_emit(ring, 0);
1061                 intel_ring_emit(ring, 4096);
1062                 intel_ring_emit(ring, offset);
1063                 intel_ring_emit(ring, MI_FLUSH);
1064
1065                 /* ... and execute it. */
1066                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1067                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1068                 intel_ring_emit(ring, cs_offset + len - 8);
1069                 intel_ring_advance(ring);
1070         }
1071
1072         return 0;
1073 }
1074
1075 static int
1076 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1077                          u32 offset, u32 len,
1078                          unsigned flags)
1079 {
1080         int ret;
1081
1082         ret = intel_ring_begin(ring, 2);
1083         if (ret)
1084                 return ret;
1085
1086         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1087         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1088         intel_ring_advance(ring);
1089
1090         return 0;
1091 }
1092
1093 static void cleanup_status_page(struct intel_ring_buffer *ring)
1094 {
1095         struct drm_i915_gem_object *obj;
1096
1097         obj = ring->status_page.obj;
1098         if (obj == NULL)
1099                 return;
1100
1101         kunmap(sg_page(obj->pages->sgl));
1102         i915_gem_object_unpin(obj);
1103         drm_gem_object_unreference(&obj->base);
1104         ring->status_page.obj = NULL;
1105 }
1106
1107 static int init_status_page(struct intel_ring_buffer *ring)
1108 {
1109         struct drm_device *dev = ring->dev;
1110         struct drm_i915_gem_object *obj;
1111         int ret;
1112
1113         obj = i915_gem_alloc_object(dev, 4096);
1114         if (obj == NULL) {
1115                 DRM_ERROR("Failed to allocate status page\n");
1116                 ret = -ENOMEM;
1117                 goto err;
1118         }
1119
1120         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1121
1122         ret = i915_gem_object_pin(obj, 4096, true, false);
1123         if (ret != 0) {
1124                 goto err_unref;
1125         }
1126
1127         ring->status_page.gfx_addr = obj->gtt_offset;
1128         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1129         if (ring->status_page.page_addr == NULL) {
1130                 ret = -ENOMEM;
1131                 goto err_unpin;
1132         }
1133         ring->status_page.obj = obj;
1134         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1135
1136         intel_ring_setup_status_page(ring);
1137         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1138                         ring->name, ring->status_page.gfx_addr);
1139
1140         return 0;
1141
1142 err_unpin:
1143         i915_gem_object_unpin(obj);
1144 err_unref:
1145         drm_gem_object_unreference(&obj->base);
1146 err:
1147         return ret;
1148 }
1149
1150 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
1151 {
1152         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1153         u32 addr;
1154
1155         if (!dev_priv->status_page_dmah) {
1156                 dev_priv->status_page_dmah =
1157                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1158                 if (!dev_priv->status_page_dmah)
1159                         return -ENOMEM;
1160         }
1161
1162         addr = dev_priv->status_page_dmah->busaddr;
1163         if (INTEL_INFO(ring->dev)->gen >= 4)
1164                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
1165         I915_WRITE(HWS_PGA, addr);
1166
1167         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1168         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1169
1170         return 0;
1171 }
1172
1173 static int intel_init_ring_buffer(struct drm_device *dev,
1174                                   struct intel_ring_buffer *ring)
1175 {
1176         struct drm_i915_gem_object *obj;
1177         struct drm_i915_private *dev_priv = dev->dev_private;
1178         int ret;
1179
1180         ring->dev = dev;
1181         INIT_LIST_HEAD(&ring->active_list);
1182         INIT_LIST_HEAD(&ring->request_list);
1183         ring->size = 32 * PAGE_SIZE;
1184         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1185
1186         init_waitqueue_head(&ring->irq_queue);
1187
1188         if (I915_NEED_GFX_HWS(dev)) {
1189                 ret = init_status_page(ring);
1190                 if (ret)
1191                         return ret;
1192         } else {
1193                 BUG_ON(ring->id != RCS);
1194                 ret = init_phys_hws_pga(ring);
1195                 if (ret)
1196                         return ret;
1197         }
1198
1199         obj = NULL;
1200         if (!HAS_LLC(dev))
1201                 obj = i915_gem_object_create_stolen(dev, ring->size);
1202         if (obj == NULL)
1203                 obj = i915_gem_alloc_object(dev, ring->size);
1204         if (obj == NULL) {
1205                 DRM_ERROR("Failed to allocate ringbuffer\n");
1206                 ret = -ENOMEM;
1207                 goto err_hws;
1208         }
1209
1210         ring->obj = obj;
1211
1212         ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1213         if (ret)
1214                 goto err_unref;
1215
1216         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1217         if (ret)
1218                 goto err_unpin;
1219
1220         ring->virtual_start =
1221                 ioremap_wc(dev_priv->gtt.mappable_base + obj->gtt_offset,
1222                            ring->size);
1223         if (ring->virtual_start == NULL) {
1224                 DRM_ERROR("Failed to map ringbuffer.\n");
1225                 ret = -EINVAL;
1226                 goto err_unpin;
1227         }
1228
1229         ret = ring->init(ring);
1230         if (ret)
1231                 goto err_unmap;
1232
1233         /* Workaround an erratum on the i830 which causes a hang if
1234          * the TAIL pointer points to within the last 2 cachelines
1235          * of the buffer.
1236          */
1237         ring->effective_size = ring->size;
1238         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1239                 ring->effective_size -= 128;
1240
1241         return 0;
1242
1243 err_unmap:
1244         iounmap(ring->virtual_start);
1245 err_unpin:
1246         i915_gem_object_unpin(obj);
1247 err_unref:
1248         drm_gem_object_unreference(&obj->base);
1249         ring->obj = NULL;
1250 err_hws:
1251         cleanup_status_page(ring);
1252         return ret;
1253 }
1254
1255 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1256 {
1257         struct drm_i915_private *dev_priv;
1258         int ret;
1259
1260         if (ring->obj == NULL)
1261                 return;
1262
1263         /* Disable the ring buffer. The ring must be idle at this point */
1264         dev_priv = ring->dev->dev_private;
1265         ret = intel_ring_idle(ring);
1266         if (ret)
1267                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1268                           ring->name, ret);
1269
1270         I915_WRITE_CTL(ring, 0);
1271
1272         iounmap(ring->virtual_start);
1273
1274         i915_gem_object_unpin(ring->obj);
1275         drm_gem_object_unreference(&ring->obj->base);
1276         ring->obj = NULL;
1277
1278         if (ring->cleanup)
1279                 ring->cleanup(ring);
1280
1281         cleanup_status_page(ring);
1282 }
1283
1284 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1285 {
1286         int ret;
1287
1288         ret = i915_wait_seqno(ring, seqno);
1289         if (!ret)
1290                 i915_gem_retire_requests_ring(ring);
1291
1292         return ret;
1293 }
1294
1295 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1296 {
1297         struct drm_i915_gem_request *request;
1298         u32 seqno = 0;
1299         int ret;
1300
1301         i915_gem_retire_requests_ring(ring);
1302
1303         if (ring->last_retired_head != -1) {
1304                 ring->head = ring->last_retired_head;
1305                 ring->last_retired_head = -1;
1306                 ring->space = ring_space(ring);
1307                 if (ring->space >= n)
1308                         return 0;
1309         }
1310
1311         list_for_each_entry(request, &ring->request_list, list) {
1312                 int space;
1313
1314                 if (request->tail == -1)
1315                         continue;
1316
1317                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1318                 if (space < 0)
1319                         space += ring->size;
1320                 if (space >= n) {
1321                         seqno = request->seqno;
1322                         break;
1323                 }
1324
1325                 /* Consume this request in case we need more space than
1326                  * is available and so need to prevent a race between
1327                  * updating last_retired_head and direct reads of
1328                  * I915_RING_HEAD. It also provides a nice sanity check.
1329                  */
1330                 request->tail = -1;
1331         }
1332
1333         if (seqno == 0)
1334                 return -ENOSPC;
1335
1336         ret = intel_ring_wait_seqno(ring, seqno);
1337         if (ret)
1338                 return ret;
1339
1340         if (WARN_ON(ring->last_retired_head == -1))
1341                 return -ENOSPC;
1342
1343         ring->head = ring->last_retired_head;
1344         ring->last_retired_head = -1;
1345         ring->space = ring_space(ring);
1346         if (WARN_ON(ring->space < n))
1347                 return -ENOSPC;
1348
1349         return 0;
1350 }
1351
1352 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1353 {
1354         struct drm_device *dev = ring->dev;
1355         struct drm_i915_private *dev_priv = dev->dev_private;
1356         unsigned long end;
1357         int ret;
1358
1359         ret = intel_ring_wait_request(ring, n);
1360         if (ret != -ENOSPC)
1361                 return ret;
1362
1363         trace_i915_ring_wait_begin(ring);
1364         /* With GEM the hangcheck timer should kick us out of the loop,
1365          * leaving it early runs the risk of corrupting GEM state (due
1366          * to running on almost untested codepaths). But on resume
1367          * timers don't work yet, so prevent a complete hang in that
1368          * case by choosing an insanely large timeout. */
1369         end = jiffies + 60 * HZ;
1370
1371         do {
1372                 ring->head = I915_READ_HEAD(ring);
1373                 ring->space = ring_space(ring);
1374                 if (ring->space >= n) {
1375                         trace_i915_ring_wait_end(ring);
1376                         return 0;
1377                 }
1378
1379                 if (dev->primary->master) {
1380                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1381                         if (master_priv->sarea_priv)
1382                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1383                 }
1384
1385                 msleep(1);
1386
1387                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1388                                            dev_priv->mm.interruptible);
1389                 if (ret)
1390                         return ret;
1391         } while (!time_after(jiffies, end));
1392         trace_i915_ring_wait_end(ring);
1393         return -EBUSY;
1394 }
1395
1396 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1397 {
1398         uint32_t __iomem *virt;
1399         int rem = ring->size - ring->tail;
1400
1401         if (ring->space < rem) {
1402                 int ret = ring_wait_for_space(ring, rem);
1403                 if (ret)
1404                         return ret;
1405         }
1406
1407         virt = ring->virtual_start + ring->tail;
1408         rem /= 4;
1409         while (rem--)
1410                 iowrite32(MI_NOOP, virt++);
1411
1412         ring->tail = 0;
1413         ring->space = ring_space(ring);
1414
1415         return 0;
1416 }
1417
1418 int intel_ring_idle(struct intel_ring_buffer *ring)
1419 {
1420         u32 seqno;
1421         int ret;
1422
1423         /* We need to add any requests required to flush the objects and ring */
1424         if (ring->outstanding_lazy_request) {
1425                 ret = i915_add_request(ring, NULL, NULL);
1426                 if (ret)
1427                         return ret;
1428         }
1429
1430         /* Wait upon the last request to be completed */
1431         if (list_empty(&ring->request_list))
1432                 return 0;
1433
1434         seqno = list_entry(ring->request_list.prev,
1435                            struct drm_i915_gem_request,
1436                            list)->seqno;
1437
1438         return i915_wait_seqno(ring, seqno);
1439 }
1440
1441 static int
1442 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1443 {
1444         if (ring->outstanding_lazy_request)
1445                 return 0;
1446
1447         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1448 }
1449
1450 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1451                               int bytes)
1452 {
1453         int ret;
1454
1455         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1456                 ret = intel_wrap_ring_buffer(ring);
1457                 if (unlikely(ret))
1458                         return ret;
1459         }
1460
1461         if (unlikely(ring->space < bytes)) {
1462                 ret = ring_wait_for_space(ring, bytes);
1463                 if (unlikely(ret))
1464                         return ret;
1465         }
1466
1467         ring->space -= bytes;
1468         return 0;
1469 }
1470
1471 int intel_ring_begin(struct intel_ring_buffer *ring,
1472                      int num_dwords)
1473 {
1474         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1475         int ret;
1476
1477         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1478                                    dev_priv->mm.interruptible);
1479         if (ret)
1480                 return ret;
1481
1482         /* Preallocate the olr before touching the ring */
1483         ret = intel_ring_alloc_seqno(ring);
1484         if (ret)
1485                 return ret;
1486
1487         return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1488 }
1489
1490 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1491 {
1492         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1493
1494         BUG_ON(ring->outstanding_lazy_request);
1495
1496         if (INTEL_INFO(ring->dev)->gen >= 6) {
1497                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1498                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1499         }
1500
1501         ring->set_seqno(ring, seqno);
1502 }
1503
1504 void intel_ring_advance(struct intel_ring_buffer *ring)
1505 {
1506         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1507
1508         ring->tail &= ring->size - 1;
1509         if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
1510                 return;
1511         ring->write_tail(ring, ring->tail);
1512 }
1513
1514
1515 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1516                                      u32 value)
1517 {
1518         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1519
1520        /* Every tail move must follow the sequence below */
1521
1522         /* Disable notification that the ring is IDLE. The GT
1523          * will then assume that it is busy and bring it out of rc6.
1524          */
1525         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1526                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1527
1528         /* Clear the context id. Here be magic! */
1529         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1530
1531         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1532         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1533                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1534                      50))
1535                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1536
1537         /* Now that the ring is fully powered up, update the tail */
1538         I915_WRITE_TAIL(ring, value);
1539         POSTING_READ(RING_TAIL(ring->mmio_base));
1540
1541         /* Let the ring send IDLE messages to the GT again,
1542          * and so let it sleep to conserve power when idle.
1543          */
1544         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1545                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1546 }
1547
1548 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1549                            u32 invalidate, u32 flush)
1550 {
1551         uint32_t cmd;
1552         int ret;
1553
1554         ret = intel_ring_begin(ring, 4);
1555         if (ret)
1556                 return ret;
1557
1558         cmd = MI_FLUSH_DW;
1559         /*
1560          * Bspec vol 1c.5 - video engine command streamer:
1561          * "If ENABLED, all TLBs will be invalidated once the flush
1562          * operation is complete. This bit is only valid when the
1563          * Post-Sync Operation field is a value of 1h or 3h."
1564          */
1565         if (invalidate & I915_GEM_GPU_DOMAINS)
1566                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1567                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1568         intel_ring_emit(ring, cmd);
1569         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1570         intel_ring_emit(ring, 0);
1571         intel_ring_emit(ring, MI_NOOP);
1572         intel_ring_advance(ring);
1573         return 0;
1574 }
1575
1576 static int
1577 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1578                               u32 offset, u32 len,
1579                               unsigned flags)
1580 {
1581         int ret;
1582
1583         ret = intel_ring_begin(ring, 2);
1584         if (ret)
1585                 return ret;
1586
1587         intel_ring_emit(ring,
1588                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1589                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1590         /* bit0-7 is the length on GEN6+ */
1591         intel_ring_emit(ring, offset);
1592         intel_ring_advance(ring);
1593
1594         return 0;
1595 }
1596
1597 static int
1598 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1599                               u32 offset, u32 len,
1600                               unsigned flags)
1601 {
1602         int ret;
1603
1604         ret = intel_ring_begin(ring, 2);
1605         if (ret)
1606                 return ret;
1607
1608         intel_ring_emit(ring,
1609                         MI_BATCH_BUFFER_START |
1610                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1611         /* bit0-7 is the length on GEN6+ */
1612         intel_ring_emit(ring, offset);
1613         intel_ring_advance(ring);
1614
1615         return 0;
1616 }
1617
1618 /* Blitter support (SandyBridge+) */
1619
1620 static int blt_ring_flush(struct intel_ring_buffer *ring,
1621                           u32 invalidate, u32 flush)
1622 {
1623         uint32_t cmd;
1624         int ret;
1625
1626         ret = intel_ring_begin(ring, 4);
1627         if (ret)
1628                 return ret;
1629
1630         cmd = MI_FLUSH_DW;
1631         /*
1632          * Bspec vol 1c.3 - blitter engine command streamer:
1633          * "If ENABLED, all TLBs will be invalidated once the flush
1634          * operation is complete. This bit is only valid when the
1635          * Post-Sync Operation field is a value of 1h or 3h."
1636          */
1637         if (invalidate & I915_GEM_DOMAIN_RENDER)
1638                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1639                         MI_FLUSH_DW_OP_STOREDW;
1640         intel_ring_emit(ring, cmd);
1641         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1642         intel_ring_emit(ring, 0);
1643         intel_ring_emit(ring, MI_NOOP);
1644         intel_ring_advance(ring);
1645         return 0;
1646 }
1647
1648 int intel_init_render_ring_buffer(struct drm_device *dev)
1649 {
1650         drm_i915_private_t *dev_priv = dev->dev_private;
1651         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1652
1653         ring->name = "render ring";
1654         ring->id = RCS;
1655         ring->mmio_base = RENDER_RING_BASE;
1656
1657         if (INTEL_INFO(dev)->gen >= 6) {
1658                 ring->add_request = gen6_add_request;
1659                 ring->flush = gen7_render_ring_flush;
1660                 if (INTEL_INFO(dev)->gen == 6)
1661                         ring->flush = gen6_render_ring_flush;
1662                 ring->irq_get = gen6_ring_get_irq;
1663                 ring->irq_put = gen6_ring_put_irq;
1664                 ring->irq_enable_mask = GT_USER_INTERRUPT;
1665                 ring->get_seqno = gen6_ring_get_seqno;
1666                 ring->set_seqno = ring_set_seqno;
1667                 ring->sync_to = gen6_ring_sync;
1668                 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1669                 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1670                 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1671                 ring->signal_mbox[0] = GEN6_VRSYNC;
1672                 ring->signal_mbox[1] = GEN6_BRSYNC;
1673         } else if (IS_GEN5(dev)) {
1674                 ring->add_request = pc_render_add_request;
1675                 ring->flush = gen4_render_ring_flush;
1676                 ring->get_seqno = pc_render_get_seqno;
1677                 ring->set_seqno = pc_render_set_seqno;
1678                 ring->irq_get = gen5_ring_get_irq;
1679                 ring->irq_put = gen5_ring_put_irq;
1680                 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1681         } else {
1682                 ring->add_request = i9xx_add_request;
1683                 if (INTEL_INFO(dev)->gen < 4)
1684                         ring->flush = gen2_render_ring_flush;
1685                 else
1686                         ring->flush = gen4_render_ring_flush;
1687                 ring->get_seqno = ring_get_seqno;
1688                 ring->set_seqno = ring_set_seqno;
1689                 if (IS_GEN2(dev)) {
1690                         ring->irq_get = i8xx_ring_get_irq;
1691                         ring->irq_put = i8xx_ring_put_irq;
1692                 } else {
1693                         ring->irq_get = i9xx_ring_get_irq;
1694                         ring->irq_put = i9xx_ring_put_irq;
1695                 }
1696                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1697         }
1698         ring->write_tail = ring_write_tail;
1699         if (IS_HASWELL(dev))
1700                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1701         else if (INTEL_INFO(dev)->gen >= 6)
1702                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1703         else if (INTEL_INFO(dev)->gen >= 4)
1704                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1705         else if (IS_I830(dev) || IS_845G(dev))
1706                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1707         else
1708                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1709         ring->init = init_render_ring;
1710         ring->cleanup = render_ring_cleanup;
1711
1712         /* Workaround batchbuffer to combat CS tlb bug. */
1713         if (HAS_BROKEN_CS_TLB(dev)) {
1714                 struct drm_i915_gem_object *obj;
1715                 int ret;
1716
1717                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1718                 if (obj == NULL) {
1719                         DRM_ERROR("Failed to allocate batch bo\n");
1720                         return -ENOMEM;
1721                 }
1722
1723                 ret = i915_gem_object_pin(obj, 0, true, false);
1724                 if (ret != 0) {
1725                         drm_gem_object_unreference(&obj->base);
1726                         DRM_ERROR("Failed to ping batch bo\n");
1727                         return ret;
1728                 }
1729
1730                 ring->private = obj;
1731         }
1732
1733         return intel_init_ring_buffer(dev, ring);
1734 }
1735
1736 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1737 {
1738         drm_i915_private_t *dev_priv = dev->dev_private;
1739         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1740         int ret;
1741
1742         ring->name = "render ring";
1743         ring->id = RCS;
1744         ring->mmio_base = RENDER_RING_BASE;
1745
1746         if (INTEL_INFO(dev)->gen >= 6) {
1747                 /* non-kms not supported on gen6+ */
1748                 return -ENODEV;
1749         }
1750
1751         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1752          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1753          * the special gen5 functions. */
1754         ring->add_request = i9xx_add_request;
1755         if (INTEL_INFO(dev)->gen < 4)
1756                 ring->flush = gen2_render_ring_flush;
1757         else
1758                 ring->flush = gen4_render_ring_flush;
1759         ring->get_seqno = ring_get_seqno;
1760         ring->set_seqno = ring_set_seqno;
1761         if (IS_GEN2(dev)) {
1762                 ring->irq_get = i8xx_ring_get_irq;
1763                 ring->irq_put = i8xx_ring_put_irq;
1764         } else {
1765                 ring->irq_get = i9xx_ring_get_irq;
1766                 ring->irq_put = i9xx_ring_put_irq;
1767         }
1768         ring->irq_enable_mask = I915_USER_INTERRUPT;
1769         ring->write_tail = ring_write_tail;
1770         if (INTEL_INFO(dev)->gen >= 4)
1771                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1772         else if (IS_I830(dev) || IS_845G(dev))
1773                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1774         else
1775                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1776         ring->init = init_render_ring;
1777         ring->cleanup = render_ring_cleanup;
1778
1779         ring->dev = dev;
1780         INIT_LIST_HEAD(&ring->active_list);
1781         INIT_LIST_HEAD(&ring->request_list);
1782
1783         ring->size = size;
1784         ring->effective_size = ring->size;
1785         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1786                 ring->effective_size -= 128;
1787
1788         ring->virtual_start = ioremap_wc(start, size);
1789         if (ring->virtual_start == NULL) {
1790                 DRM_ERROR("can not ioremap virtual address for"
1791                           " ring buffer\n");
1792                 return -ENOMEM;
1793         }
1794
1795         if (!I915_NEED_GFX_HWS(dev)) {
1796                 ret = init_phys_hws_pga(ring);
1797                 if (ret)
1798                         return ret;
1799         }
1800
1801         return 0;
1802 }
1803
1804 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1805 {
1806         drm_i915_private_t *dev_priv = dev->dev_private;
1807         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1808
1809         ring->name = "bsd ring";
1810         ring->id = VCS;
1811
1812         ring->write_tail = ring_write_tail;
1813         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1814                 ring->mmio_base = GEN6_BSD_RING_BASE;
1815                 /* gen6 bsd needs a special wa for tail updates */
1816                 if (IS_GEN6(dev))
1817                         ring->write_tail = gen6_bsd_ring_write_tail;
1818                 ring->flush = gen6_ring_flush;
1819                 ring->add_request = gen6_add_request;
1820                 ring->get_seqno = gen6_ring_get_seqno;
1821                 ring->set_seqno = ring_set_seqno;
1822                 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1823                 ring->irq_get = gen6_ring_get_irq;
1824                 ring->irq_put = gen6_ring_put_irq;
1825                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1826                 ring->sync_to = gen6_ring_sync;
1827                 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1828                 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1829                 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1830                 ring->signal_mbox[0] = GEN6_RVSYNC;
1831                 ring->signal_mbox[1] = GEN6_BVSYNC;
1832         } else {
1833                 ring->mmio_base = BSD_RING_BASE;
1834                 ring->flush = bsd_ring_flush;
1835                 ring->add_request = i9xx_add_request;
1836                 ring->get_seqno = ring_get_seqno;
1837                 ring->set_seqno = ring_set_seqno;
1838                 if (IS_GEN5(dev)) {
1839                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1840                         ring->irq_get = gen5_ring_get_irq;
1841                         ring->irq_put = gen5_ring_put_irq;
1842                 } else {
1843                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1844                         ring->irq_get = i9xx_ring_get_irq;
1845                         ring->irq_put = i9xx_ring_put_irq;
1846                 }
1847                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1848         }
1849         ring->init = init_ring_common;
1850
1851         return intel_init_ring_buffer(dev, ring);
1852 }
1853
1854 int intel_init_blt_ring_buffer(struct drm_device *dev)
1855 {
1856         drm_i915_private_t *dev_priv = dev->dev_private;
1857         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1858
1859         ring->name = "blitter ring";
1860         ring->id = BCS;
1861
1862         ring->mmio_base = BLT_RING_BASE;
1863         ring->write_tail = ring_write_tail;
1864         ring->flush = blt_ring_flush;
1865         ring->add_request = gen6_add_request;
1866         ring->get_seqno = gen6_ring_get_seqno;
1867         ring->set_seqno = ring_set_seqno;
1868         ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1869         ring->irq_get = gen6_ring_get_irq;
1870         ring->irq_put = gen6_ring_put_irq;
1871         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1872         ring->sync_to = gen6_ring_sync;
1873         ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1874         ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1875         ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1876         ring->signal_mbox[0] = GEN6_RBSYNC;
1877         ring->signal_mbox[1] = GEN6_VBSYNC;
1878         ring->init = init_ring_common;
1879
1880         return intel_init_ring_buffer(dev, ring);
1881 }
1882
1883 int
1884 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1885 {
1886         int ret;
1887
1888         if (!ring->gpu_caches_dirty)
1889                 return 0;
1890
1891         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1892         if (ret)
1893                 return ret;
1894
1895         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1896
1897         ring->gpu_caches_dirty = false;
1898         return 0;
1899 }
1900
1901 int
1902 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1903 {
1904         uint32_t flush_domains;
1905         int ret;
1906
1907         flush_domains = 0;
1908         if (ring->gpu_caches_dirty)
1909                 flush_domains = I915_GEM_GPU_DOMAINS;
1910
1911         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1912         if (ret)
1913                 return ret;
1914
1915         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1916
1917         ring->gpu_caches_dirty = false;
1918         return 0;
1919 }