drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 static void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         struct intel_engine_cs *ring = req->ring;
  99         u32 cmd;
 100         int ret;
 101
 102         cmd = MI_FLUSH;
 103         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 104                 cmd |= MI_NO_WRITE_FLUSH;
 105
 106         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 107                 cmd |= MI_READ_FLUSH;
 108
 109         ret = intel_ring_begin(ring, 2);
 110         if (ret)
 111                 return ret;
 112
 113         intel_ring_emit(ring, cmd);
 114         intel_ring_emit(ring, MI_NOOP);
 115         intel_ring_advance(ring);
 116
 117         return 0;
 118 }
 119
 120 static int
 121 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 122                        u32      invalidate_domains,
 123                        u32      flush_domains)
 124 {
 125         struct intel_engine_cs *ring = req->ring;
 126         struct drm_device *dev = ring->dev;
 127         u32 cmd;
 128         int ret;
 129
 130         /*
 131          * read/write caches:
 132          *
 133          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 134          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 135          * also flushed at 2d versus 3d pipeline switches.
 136          *
 137          * read-only caches:
 138          *
 139          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 140          * MI_READ_FLUSH is set, and is always flushed on 965.
 141          *
 142          * I915_GEM_DOMAIN_COMMAND may not exist?
 143          *
 144          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 145          * invalidated when MI_EXE_FLUSH is set.
 146          *
 147          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 148          * invalidated with every MI_FLUSH.
 149          *
 150          * TLBs:
 151          *
 152          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 153          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 154          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 155          * are flushed at any MI_FLUSH.
 156          */
 157
 158         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 159         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 160                 cmd &= ~MI_NO_WRITE_FLUSH;
 161         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 162                 cmd |= MI_EXE_FLUSH;
 163
 164         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 165             (IS_G4X(dev) || IS_GEN5(dev)))
 166                 cmd |= MI_INVALIDATE_ISP;
 167
 168         ret = intel_ring_begin(ring, 2);
 169         if (ret)
 170                 return ret;
 171
 172         intel_ring_emit(ring, cmd);
 173         intel_ring_emit(ring, MI_NOOP);
 174         intel_ring_advance(ring);
 175
 176         return 0;
 177 }
 178
 179 /**
 180  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 181  * implementing two workarounds on gen6.  From section 1.4.7.1
 182  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 183  *
 184  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 185  * produced by non-pipelined state commands), software needs to first
 186  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 187  * 0.
 188  *
 189  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 190  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 191  *
 192  * And the workaround for these two requires this workaround first:
 193  *
 194  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 195  * BEFORE the pipe-control with a post-sync op and no write-cache
 196  * flushes.
 197  *
 198  * And this last workaround is tricky because of the requirements on
 199  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 200  * volume 2 part 1:
 201  *
 202  *     "1 of the following must also be set:
 203  *      - Render Target Cache Flush Enable ([12] of DW1)
 204  *      - Depth Cache Flush Enable ([0] of DW1)
 205  *      - Stall at Pixel Scoreboard ([1] of DW1)
 206  *      - Depth Stall ([13] of DW1)
 207  *      - Post-Sync Operation ([13] of DW1)
 208  *      - Notify Enable ([8] of DW1)"
 209  *
 210  * The cache flushes require the workaround flush that triggered this
 211  * one, so we can't use it.  Depth stall would trigger the same.
 212  * Post-sync nonzero is what triggered this second workaround, so we
 213  * can't use that one either.  Notify enable is IRQs, which aren't
 214  * really our business.  That leaves only stall at scoreboard.
 215  */
 216 static int
 217 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
 218 {
 219         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 220         int ret;
 221
 222
 223         ret = intel_ring_begin(ring, 6);
 224         if (ret)
 225                 return ret;
 226
 227         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 228         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 229                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 230         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 231         intel_ring_emit(ring, 0); /* low dword */
 232         intel_ring_emit(ring, 0); /* high dword */
 233         intel_ring_emit(ring, MI_NOOP);
 234         intel_ring_advance(ring);
 235
 236         ret = intel_ring_begin(ring, 6);
 237         if (ret)
 238                 return ret;
 239
 240         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 241         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 242         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 243         intel_ring_emit(ring, 0);
 244         intel_ring_emit(ring, 0);
 245         intel_ring_emit(ring, MI_NOOP);
 246         intel_ring_advance(ring);
 247
 248         return 0;
 249 }
 250
 251 static int
 252 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 253                        u32 invalidate_domains, u32 flush_domains)
 254 {
 255         struct intel_engine_cs *ring = req->ring;
 256         u32 flags = 0;
 257         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 258         int ret;
 259
 260         /* Force SNB workarounds for PIPE_CONTROL flushes */
 261         ret = intel_emit_post_sync_nonzero_flush(ring);
 262         if (ret)
 263                 return ret;
 264
 265         /* Just flush everything.  Experiments have shown that reducing the
 266          * number of bits based on the write domains has little performance
 267          * impact.
 268          */
 269         if (flush_domains) {
 270                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 271                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 272                 /*
 273                  * Ensure that any following seqno writes only happen
 274                  * when the render cache is indeed flushed.
 275                  */
 276                 flags |= PIPE_CONTROL_CS_STALL;
 277         }
 278         if (invalidate_domains) {
 279                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 280                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 281                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 282                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 283                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 284                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 285                 /*
 286                  * TLB invalidate requires a post-sync write.
 287                  */
 288                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 289         }
 290
 291         ret = intel_ring_begin(ring, 4);
 292         if (ret)
 293                 return ret;
 294
 295         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 296         intel_ring_emit(ring, flags);
 297         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 298         intel_ring_emit(ring, 0);
 299         intel_ring_advance(ring);
 300
 301         return 0;
 302 }
 303
 304 static int
 305 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
 306 {
 307         int ret;
 308
 309         ret = intel_ring_begin(ring, 4);
 310         if (ret)
 311                 return ret;
 312
 313         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 314         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 315                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 316         intel_ring_emit(ring, 0);
 317         intel_ring_emit(ring, 0);
 318         intel_ring_advance(ring);
 319
 320         return 0;
 321 }
 322
 323 static int
 324 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 325                        u32 invalidate_domains, u32 flush_domains)
 326 {
 327         struct intel_engine_cs *ring = req->ring;
 328         u32 flags = 0;
 329         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 330         int ret;
 331
 332         /*
 333          * Ensure that any following seqno writes only happen when the render
 334          * cache is indeed flushed.
 335          *
 336          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 337          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 338          * don't try to be clever and just set it unconditionally.
 339          */
 340         flags |= PIPE_CONTROL_CS_STALL;
 341
 342         /* Just flush everything.  Experiments have shown that reducing the
 343          * number of bits based on the write domains has little performance
 344          * impact.
 345          */
 346         if (flush_domains) {
 347                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 348                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 349         }
 350         if (invalidate_domains) {
 351                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 352                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 353                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 354                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 355                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 356                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 357                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 358                 /*
 359                  * TLB invalidate requires a post-sync write.
 360                  */
 361                 flags |= PIPE_CONTROL_QW_WRITE;
 362                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 363
 364                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 365
 366                 /* Workaround: we must issue a pipe_control with CS-stall bit
 367                  * set before a pipe_control command that has the state cache
 368                  * invalidate bit set. */
 369                 gen7_render_ring_cs_stall_wa(ring);
 370         }
 371
 372         ret = intel_ring_begin(ring, 4);
 373         if (ret)
 374                 return ret;
 375
 376         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 377         intel_ring_emit(ring, flags);
 378         intel_ring_emit(ring, scratch_addr);
 379         intel_ring_emit(ring, 0);
 380         intel_ring_advance(ring);
 381
 382         return 0;
 383 }
 384
 385 static int
 386 gen8_emit_pipe_control(struct intel_engine_cs *ring,
 387                        u32 flags, u32 scratch_addr)
 388 {
 389         int ret;
 390
 391         ret = intel_ring_begin(ring, 6);
 392         if (ret)
 393                 return ret;
 394
 395         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 396         intel_ring_emit(ring, flags);
 397         intel_ring_emit(ring, scratch_addr);
 398         intel_ring_emit(ring, 0);
 399         intel_ring_emit(ring, 0);
 400         intel_ring_emit(ring, 0);
 401         intel_ring_advance(ring);
 402
 403         return 0;
 404 }
 405
 406 static int
 407 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 408                        u32 invalidate_domains, u32 flush_domains)
 409 {
 410         struct intel_engine_cs *ring = req->ring;
 411         u32 flags = 0;
 412         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 413         int ret;
 414
 415         flags |= PIPE_CONTROL_CS_STALL;
 416
 417         if (flush_domains) {
 418                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 419                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 420         }
 421         if (invalidate_domains) {
 422                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 423                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 424                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 425                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 426                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 427                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 428                 flags |= PIPE_CONTROL_QW_WRITE;
 429                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 430
 431                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 432                 ret = gen8_emit_pipe_control(ring,
 433                                              PIPE_CONTROL_CS_STALL |
 434                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 435                                              0);
 436                 if (ret)
 437                         return ret;
 438         }
 439
 440         return gen8_emit_pipe_control(ring, flags, scratch_addr);
 441 }
 442
 443 static void ring_write_tail(struct intel_engine_cs *ring,
 444                             u32 value)
 445 {
 446         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 447         I915_WRITE_TAIL(ring, value);
 448 }
 449
 450 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 451 {
 452         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 453         u64 acthd;
 454
 455         if (INTEL_INFO(ring->dev)->gen >= 8)
 456                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 457                                          RING_ACTHD_UDW(ring->mmio_base));
 458         else if (INTEL_INFO(ring->dev)->gen >= 4)
 459                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 460         else
 461                 acthd = I915_READ(ACTHD);
 462
 463         return acthd;
 464 }
 465
 466 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 467 {
 468         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 469         u32 addr;
 470
 471         addr = dev_priv->status_page_dmah->busaddr;
 472         if (INTEL_INFO(ring->dev)->gen >= 4)
 473                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 474         I915_WRITE(HWS_PGA, addr);
 475 }
 476
 477 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 478 {
 479         struct drm_device *dev = ring->dev;
 480         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 481         u32 mmio = 0;
 482
 483         /* The ring status page addresses are no longer next to the rest of
 484          * the ring registers as of gen7.
 485          */
 486         if (IS_GEN7(dev)) {
 487                 switch (ring->id) {
 488                 case RCS:
 489                         mmio = RENDER_HWS_PGA_GEN7;
 490                         break;
 491                 case BCS:
 492                         mmio = BLT_HWS_PGA_GEN7;
 493                         break;
 494                 /*
 495                  * VCS2 actually doesn't exist on Gen7. Only shut up
 496                  * gcc switch check warning
 497                  */
 498                 case VCS2:
 499                 case VCS:
 500                         mmio = BSD_HWS_PGA_GEN7;
 501                         break;
 502                 case VECS:
 503                         mmio = VEBOX_HWS_PGA_GEN7;
 504                         break;
 505                 }
 506         } else if (IS_GEN6(ring->dev)) {
 507                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 508         } else {
 509                 /* XXX: gen8 returns to sanity */
 510                 mmio = RING_HWS_PGA(ring->mmio_base);
 511         }
 512
 513         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 514         POSTING_READ(mmio);
 515
 516         /*
 517          * Flush the TLB for this page
 518          *
 519          * FIXME: These two bits have disappeared on gen8, so a question
 520          * arises: do we still need this and if so how should we go about
 521          * invalidating the TLB?
 522          */
 523         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 524                 u32 reg = RING_INSTPM(ring->mmio_base);
 525
 526                 /* ring should be idle before issuing a sync flush*/
 527                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
 528
 529                 I915_WRITE(reg,
 530                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 531                                               INSTPM_SYNC_FLUSH));
 532                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 533                              1000))
 534                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 535                                   ring->name);
 536         }
 537 }
 538
 539 static bool stop_ring(struct intel_engine_cs *ring)
 540 {
 541         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 542
 543         if (!IS_GEN2(ring->dev)) {
 544                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 545                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 546                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 547                         /* Sometimes we observe that the idle flag is not
 548                          * set even though the ring is empty. So double
 549                          * check before giving up.
 550                          */
 551                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 552                                 return false;
 553                 }
 554         }
 555
 556         I915_WRITE_CTL(ring, 0);
 557         I915_WRITE_HEAD(ring, 0);
 558         ring->write_tail(ring, 0);
 559
 560         if (!IS_GEN2(ring->dev)) {
 561                 (void)I915_READ_CTL(ring);
 562                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 563         }
 564
 565         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 566 }
 567
 568 static int init_ring_common(struct intel_engine_cs *ring)
 569 {
 570         struct drm_device *dev = ring->dev;
 571         struct drm_i915_private *dev_priv = dev->dev_private;
 572         struct intel_ringbuffer *ringbuf = ring->buffer;
 573         struct drm_i915_gem_object *obj = ringbuf->obj;
 574         int ret = 0;
 575
 576         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 577
 578         if (!stop_ring(ring)) {
 579                 /* G45 ring initialization often fails to reset head to zero */
 580                 DRM_DEBUG_KMS("%s head not reset to zero "
 581                               "ctl %08x head %08x tail %08x start %08x\n",
 582                               ring->name,
 583                               I915_READ_CTL(ring),
 584                               I915_READ_HEAD(ring),
 585                               I915_READ_TAIL(ring),
 586                               I915_READ_START(ring));
 587
 588                 if (!stop_ring(ring)) {
 589                         DRM_ERROR("failed to set %s head to zero "
 590                                   "ctl %08x head %08x tail %08x start %08x\n",
 591                                   ring->name,
 592                                   I915_READ_CTL(ring),
 593                                   I915_READ_HEAD(ring),
 594                                   I915_READ_TAIL(ring),
 595                                   I915_READ_START(ring));
 596                         ret = -EIO;
 597                         goto out;
 598                 }
 599         }
 600
 601         if (I915_NEED_GFX_HWS(dev))
 602                 intel_ring_setup_status_page(ring);
 603         else
 604                 ring_setup_phys_status_page(ring);
 605
 606         /* Enforce ordering by reading HEAD register back */
 607         I915_READ_HEAD(ring);
 608
 609         /* Initialize the ring. This must happen _after_ we've cleared the ring
 610          * registers with the above sequence (the readback of the HEAD registers
 611          * also enforces ordering), otherwise the hw might lose the new ring
 612          * register values. */
 613         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 614
 615         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 616         if (I915_READ_HEAD(ring))
 617                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 618                           ring->name, I915_READ_HEAD(ring));
 619         I915_WRITE_HEAD(ring, 0);
 620         (void)I915_READ_HEAD(ring);
 621
 622         I915_WRITE_CTL(ring,
 623                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 624                         | RING_VALID);
 625
 626         /* If the head is still not zero, the ring is dead */
 627         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 628                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 629                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 630                 DRM_ERROR("%s initialization failed "
 631                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 632                           ring->name,
 633                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 634                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 635                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 636                 ret = -EIO;
 637                 goto out;
 638         }
 639
 640         ringbuf->last_retired_head = -1;
 641         ringbuf->head = I915_READ_HEAD(ring);
 642         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 643         intel_ring_update_space(ringbuf);
 644
 645         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 646
 647 out:
 648         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 649
 650         return ret;
 651 }
 652
 653 void
 654 intel_fini_pipe_control(struct intel_engine_cs *ring)
 655 {
 656         struct drm_device *dev = ring->dev;
 657
 658         if (ring->scratch.obj == NULL)
 659                 return;
 660
 661         if (INTEL_INFO(dev)->gen >= 5) {
 662                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 663                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 664         }
 665
 666         drm_gem_object_unreference(&ring->scratch.obj->base);
 667         ring->scratch.obj = NULL;
 668 }
 669
 670 int
 671 intel_init_pipe_control(struct intel_engine_cs *ring)
 672 {
 673         int ret;
 674
 675         WARN_ON(ring->scratch.obj);
 676
 677         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 678         if (ring->scratch.obj == NULL) {
 679                 DRM_ERROR("Failed to allocate seqno page\n");
 680                 ret = -ENOMEM;
 681                 goto err;
 682         }
 683
 684         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 685         if (ret)
 686                 goto err_unref;
 687
 688         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 689         if (ret)
 690                 goto err_unref;
 691
 692         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 693         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 694         if (ring->scratch.cpu_page == NULL) {
 695                 ret = -ENOMEM;
 696                 goto err_unpin;
 697         }
 698
 699         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 700                          ring->name, ring->scratch.gtt_offset);
 701         return 0;
 702
 703 err_unpin:
 704         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 705 err_unref:
 706         drm_gem_object_unreference(&ring->scratch.obj->base);
 707 err:
 708         return ret;
 709 }
 710
 711 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 712 {
 713         int ret, i;
 714         struct intel_engine_cs *ring = req->ring;
 715         struct drm_device *dev = ring->dev;
 716         struct drm_i915_private *dev_priv = dev->dev_private;
 717         struct i915_workarounds *w = &dev_priv->workarounds;
 718
 719         if (WARN_ON_ONCE(w->count == 0))
 720                 return 0;
 721
 722         ring->gpu_caches_dirty = true;
 723         ret = intel_ring_flush_all_caches(req);
 724         if (ret)
 725                 return ret;
 726
 727         ret = intel_ring_begin(ring, (w->count * 2 + 2));
 728         if (ret)
 729                 return ret;
 730
 731         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 732         for (i = 0; i < w->count; i++) {
 733                 intel_ring_emit(ring, w->reg[i].addr);
 734                 intel_ring_emit(ring, w->reg[i].value);
 735         }
 736         intel_ring_emit(ring, MI_NOOP);
 737
 738         intel_ring_advance(ring);
 739
 740         ring->gpu_caches_dirty = true;
 741         ret = intel_ring_flush_all_caches(req);
 742         if (ret)
 743                 return ret;
 744
 745         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 746
 747         return 0;
 748 }
 749
 750 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 751 {
 752         int ret;
 753
 754         ret = intel_ring_workarounds_emit(req);
 755         if (ret != 0)
 756                 return ret;
 757
 758         ret = i915_gem_render_state_init(req);
 759         if (ret)
 760                 DRM_ERROR("init render state: %d\n", ret);
 761
 762         return ret;
 763 }
 764
 765 static int wa_add(struct drm_i915_private *dev_priv,
 766                   const u32 addr, const u32 mask, const u32 val)
 767 {
 768         const u32 idx = dev_priv->workarounds.count;
 769
 770         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 771                 return -ENOSPC;
 772
 773         dev_priv->workarounds.reg[idx].addr = addr;
 774         dev_priv->workarounds.reg[idx].value = val;
 775         dev_priv->workarounds.reg[idx].mask = mask;
 776
 777         dev_priv->workarounds.count++;
 778
 779         return 0;
 780 }
 781
 782 #define WA_REG(addr, mask, val) { \
 783                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 784                 if (r) \
 785                         return r; \
 786         }
 787
 788 #define WA_SET_BIT_MASKED(addr, mask) \
 789         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 790
 791 #define WA_CLR_BIT_MASKED(addr, mask) \
 792         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 793
 794 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 795         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 796
 797 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 798 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 799
 800 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 801
 802 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 803 {
 804         struct drm_device *dev = ring->dev;
 805         struct drm_i915_private *dev_priv = dev->dev_private;
 806
 807         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 808
 809         /* WaDisableAsyncFlipPerfMode:bdw */
 810         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 811
 812         /* WaDisablePartialInstShootdown:bdw */
 813         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 814         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 815                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 816                           STALL_DOP_GATING_DISABLE);
 817
 818         /* WaDisableDopClockGating:bdw */
 819         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 820                           DOP_CLOCK_GATING_DISABLE);
 821
 822         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 823                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 824
 825         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 826          * workaround for for a possible hang in the unlikely event a TLB
 827          * invalidation occurs during a PSD flush.
 828          */
 829         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 830                           /* WaForceEnableNonCoherent:bdw */
 831                           HDC_FORCE_NON_COHERENT |
 832                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 833                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 834                           /* WaHdcDisableFetchWhenMasked:bdw */
 835                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 836                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 837                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 838
 839         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 840          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 841          *  polygons in the same 8x4 pixel/sample area to be processed without
 842          *  stalling waiting for the earlier ones to write to Hierarchical Z
 843          *  buffer."
 844          *
 845          * This optimization is off by default for Broadwell; turn it on.
 846          */
 847         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 848
 849         /* Wa4x4STCOptimizationDisable:bdw */
 850         WA_SET_BIT_MASKED(CACHE_MODE_1,
 851                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 852
 853         /*
 854          * BSpec recommends 8x4 when MSAA is used,
 855          * however in practice 16x4 seems fastest.
 856          *
 857          * Note that PS/WM thread counts depend on the WIZ hashing
 858          * disable bit, which we don't touch here, but it's good
 859          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 860          */
 861         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 862                             GEN6_WIZ_HASHING_MASK,
 863                             GEN6_WIZ_HASHING_16x4);
 864
 865         return 0;
 866 }
 867
 868 static int chv_init_workarounds(struct intel_engine_cs *ring)
 869 {
 870         struct drm_device *dev = ring->dev;
 871         struct drm_i915_private *dev_priv = dev->dev_private;
 872
 873         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 874
 875         /* WaDisableAsyncFlipPerfMode:chv */
 876         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 877
 878         /* WaDisablePartialInstShootdown:chv */
 879         /* WaDisableThreadStallDopClockGating:chv */
 880         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 881                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 882                           STALL_DOP_GATING_DISABLE);
 883
 884         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 885          * workaround for a possible hang in the unlikely event a TLB
 886          * invalidation occurs during a PSD flush.
 887          */
 888         /* WaForceEnableNonCoherent:chv */
 889         /* WaHdcDisableFetchWhenMasked:chv */
 890         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 891                           HDC_FORCE_NON_COHERENT |
 892                           HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 893
 894         /* According to the CACHE_MODE_0 default value documentation, some
 895          * CHV platforms disable this optimization by default.  Turn it on.
 896          */
 897         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 898
 899         /* Wa4x4STCOptimizationDisable:chv */
 900         WA_SET_BIT_MASKED(CACHE_MODE_1,
 901                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 902
 903         /* Improve HiZ throughput on CHV. */
 904         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 905
 906         /*
 907          * BSpec recommends 8x4 when MSAA is used,
 908          * however in practice 16x4 seems fastest.
 909          *
 910          * Note that PS/WM thread counts depend on the WIZ hashing
 911          * disable bit, which we don't touch here, but it's good
 912          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 913          */
 914         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 915                             GEN6_WIZ_HASHING_MASK,
 916                             GEN6_WIZ_HASHING_16x4);
 917
 918         return 0;
 919 }
 920
 921 static int gen9_init_workarounds(struct intel_engine_cs *ring)
 922 {
 923         struct drm_device *dev = ring->dev;
 924         struct drm_i915_private *dev_priv = dev->dev_private;
 925         uint32_t tmp;
 926
 927         /* WaDisablePartialInstShootdown:skl,bxt */
 928         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 929                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 930
 931         /* Syncing dependencies between camera and graphics:skl,bxt */
 932         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 933                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 934
 935         if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
 936             INTEL_REVID(dev) == SKL_REVID_B0)) ||
 937             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
 938                 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 939                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 940                                   GEN9_DG_MIRROR_FIX_ENABLE);
 941         }
 942
 943         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
 944             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
 945                 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 946                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 947                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 948                 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
 949                                   DISABLE_PIXEL_MASK_CAMMING);
 950         }
 951
 952         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
 953             IS_BROXTON(dev)) {
 954                 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 955                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 956                                   GEN9_ENABLE_YV12_BUGFIX);
 957         }
 958
 959         /* Wa4x4STCOptimizationDisable:skl,bxt */
 960         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 961
 962         /* WaDisablePartialResolveInVc:skl,bxt */
 963         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 964
 965         /* WaCcsTlbPrefetchDisable:skl,bxt */
 966         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 967                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 968
 969         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 970         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
 971             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
 972                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 973                                   PIXEL_MASK_CAMMING_DISABLE);
 974
 975         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 976         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 977         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
 978             (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
 979                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 980         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 981
 982         return 0;
 983 }
 984
 985 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
 986 {
 987         struct drm_device *dev = ring->dev;
 988         struct drm_i915_private *dev_priv = dev->dev_private;
 989         u8 vals[3] = { 0, 0, 0 };
 990         unsigned int i;
 991
 992         for (i = 0; i < 3; i++) {
 993                 u8 ss;
 994
 995                 /*
 996                  * Only consider slices where one, and only one, subslice has 7
 997                  * EUs
 998                  */
 999                 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
1000                         continue;
1001
1002                 /*
1003                  * subslice_7eu[i] != 0 (because of the check above) and
1004                  * ss_max == 4 (maximum number of subslices possible per slice)
1005                  *
1006                  * ->    0 <= ss <= 3;
1007                  */
1008                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1009                 vals[i] = 3 - ss;
1010         }
1011
1012         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1013                 return 0;
1014
1015         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1016         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1017                             GEN9_IZ_HASHING_MASK(2) |
1018                             GEN9_IZ_HASHING_MASK(1) |
1019                             GEN9_IZ_HASHING_MASK(0),
1020                             GEN9_IZ_HASHING(2, vals[2]) |
1021                             GEN9_IZ_HASHING(1, vals[1]) |
1022                             GEN9_IZ_HASHING(0, vals[0]));
1023
1024         return 0;
1025 }
1026
1027
1028 static int skl_init_workarounds(struct intel_engine_cs *ring)
1029 {
1030         struct drm_device *dev = ring->dev;
1031         struct drm_i915_private *dev_priv = dev->dev_private;
1032
1033         gen9_init_workarounds(ring);
1034
1035         /* WaDisablePowerCompilerClockGating:skl */
1036         if (INTEL_REVID(dev) == SKL_REVID_B0)
1037                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1038                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1039
1040         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1041                 /*
1042                  *Use Force Non-Coherent whenever executing a 3D context. This
1043                  * is a workaround for a possible hang in the unlikely event
1044                  * a TLB invalidation occurs during a PSD flush.
1045                  */
1046                 /* WaForceEnableNonCoherent:skl */
1047                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1048                                   HDC_FORCE_NON_COHERENT);
1049         }
1050
1051         if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1052             INTEL_REVID(dev) == SKL_REVID_D0)
1053                 /* WaBarrierPerformanceFixDisable:skl */
1054                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1055                                   HDC_FENCE_DEST_SLM_DISABLE |
1056                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1057
1058         return skl_tune_iz_hashing(ring);
1059 }
1060
1061 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1062 {
1063         struct drm_device *dev = ring->dev;
1064         struct drm_i915_private *dev_priv = dev->dev_private;
1065
1066         gen9_init_workarounds(ring);
1067
1068         /* WaDisableThreadStallDopClockGating:bxt */
1069         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1070                           STALL_DOP_GATING_DISABLE);
1071
1072         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1073         if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1074                 WA_SET_BIT_MASKED(
1075                         GEN7_HALF_SLICE_CHICKEN1,
1076                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1077         }
1078
1079         return 0;
1080 }
1081
1082 int init_workarounds_ring(struct intel_engine_cs *ring)
1083 {
1084         struct drm_device *dev = ring->dev;
1085         struct drm_i915_private *dev_priv = dev->dev_private;
1086
1087         WARN_ON(ring->id != RCS);
1088
1089         dev_priv->workarounds.count = 0;
1090
1091         if (IS_BROADWELL(dev))
1092                 return bdw_init_workarounds(ring);
1093
1094         if (IS_CHERRYVIEW(dev))
1095                 return chv_init_workarounds(ring);
1096
1097         if (IS_SKYLAKE(dev))
1098                 return skl_init_workarounds(ring);
1099
1100         if (IS_BROXTON(dev))
1101                 return bxt_init_workarounds(ring);
1102
1103         return 0;
1104 }
1105
1106 static int init_render_ring(struct intel_engine_cs *ring)
1107 {
1108         struct drm_device *dev = ring->dev;
1109         struct drm_i915_private *dev_priv = dev->dev_private;
1110         int ret = init_ring_common(ring);
1111         if (ret)
1112                 return ret;
1113
1114         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1115         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1116                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1117
1118         /* We need to disable the AsyncFlip performance optimisations in order
1119          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1120          * programmed to '1' on all products.
1121          *
1122          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1123          */
1124         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1125                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1126
1127         /* Required for the hardware to program scanline values for waiting */
1128         /* WaEnableFlushTlbInvalidationMode:snb */
1129         if (INTEL_INFO(dev)->gen == 6)
1130                 I915_WRITE(GFX_MODE,
1131                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1132
1133         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1134         if (IS_GEN7(dev))
1135                 I915_WRITE(GFX_MODE_GEN7,
1136                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1137                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1138
1139         if (IS_GEN6(dev)) {
1140                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1141                  * "If this bit is set, STCunit will have LRA as replacement
1142                  *  policy. [...] This bit must be reset.  LRA replacement
1143                  *  policy is not supported."
1144                  */
1145                 I915_WRITE(CACHE_MODE_0,
1146                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1147         }
1148
1149         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1150                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1151
1152         if (HAS_L3_DPF(dev))
1153                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1154
1155         return init_workarounds_ring(ring);
1156 }
1157
1158 static void render_ring_cleanup(struct intel_engine_cs *ring)
1159 {
1160         struct drm_device *dev = ring->dev;
1161         struct drm_i915_private *dev_priv = dev->dev_private;
1162
1163         if (dev_priv->semaphore_obj) {
1164                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1165                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1166                 dev_priv->semaphore_obj = NULL;
1167         }
1168
1169         intel_fini_pipe_control(ring);
1170 }
1171
1172 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1173                            unsigned int num_dwords)
1174 {
1175 #define MBOX_UPDATE_DWORDS 8
1176         struct drm_device *dev = signaller->dev;
1177         struct drm_i915_private *dev_priv = dev->dev_private;
1178         struct intel_engine_cs *waiter;
1179         int i, ret, num_rings;
1180
1181         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1182         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1183 #undef MBOX_UPDATE_DWORDS
1184
1185         ret = intel_ring_begin(signaller, num_dwords);
1186         if (ret)
1187                 return ret;
1188
1189         for_each_ring(waiter, dev_priv, i) {
1190                 u32 seqno;
1191                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1192                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1193                         continue;
1194
1195                 seqno = i915_gem_request_get_seqno(
1196                                            signaller->outstanding_lazy_request);
1197                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1198                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1199                                            PIPE_CONTROL_QW_WRITE |
1200                                            PIPE_CONTROL_FLUSH_ENABLE);
1201                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1202                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1203                 intel_ring_emit(signaller, seqno);
1204                 intel_ring_emit(signaller, 0);
1205                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1206                                            MI_SEMAPHORE_TARGET(waiter->id));
1207                 intel_ring_emit(signaller, 0);
1208         }
1209
1210         return 0;
1211 }
1212
1213 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1214                            unsigned int num_dwords)
1215 {
1216 #define MBOX_UPDATE_DWORDS 6
1217         struct drm_device *dev = signaller->dev;
1218         struct drm_i915_private *dev_priv = dev->dev_private;
1219         struct intel_engine_cs *waiter;
1220         int i, ret, num_rings;
1221
1222         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1223         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1224 #undef MBOX_UPDATE_DWORDS
1225
1226         ret = intel_ring_begin(signaller, num_dwords);
1227         if (ret)
1228                 return ret;
1229
1230         for_each_ring(waiter, dev_priv, i) {
1231                 u32 seqno;
1232                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1233                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1234                         continue;
1235
1236                 seqno = i915_gem_request_get_seqno(
1237                                            signaller->outstanding_lazy_request);
1238                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1239                                            MI_FLUSH_DW_OP_STOREDW);
1240                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1241                                            MI_FLUSH_DW_USE_GTT);
1242                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1243                 intel_ring_emit(signaller, seqno);
1244                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1245                                            MI_SEMAPHORE_TARGET(waiter->id));
1246                 intel_ring_emit(signaller, 0);
1247         }
1248
1249         return 0;
1250 }
1251
1252 static int gen6_signal(struct intel_engine_cs *signaller,
1253                        unsigned int num_dwords)
1254 {
1255         struct drm_device *dev = signaller->dev;
1256         struct drm_i915_private *dev_priv = dev->dev_private;
1257         struct intel_engine_cs *useless;
1258         int i, ret, num_rings;
1259
1260 #define MBOX_UPDATE_DWORDS 3
1261         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1262         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1263 #undef MBOX_UPDATE_DWORDS
1264
1265         ret = intel_ring_begin(signaller, num_dwords);
1266         if (ret)
1267                 return ret;
1268
1269         for_each_ring(useless, dev_priv, i) {
1270                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1271                 if (mbox_reg != GEN6_NOSYNC) {
1272                         u32 seqno = i915_gem_request_get_seqno(
1273                                            signaller->outstanding_lazy_request);
1274                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1275                         intel_ring_emit(signaller, mbox_reg);
1276                         intel_ring_emit(signaller, seqno);
1277                 }
1278         }
1279
1280         /* If num_dwords was rounded, make sure the tail pointer is correct */
1281         if (num_rings % 2 == 0)
1282                 intel_ring_emit(signaller, MI_NOOP);
1283
1284         return 0;
1285 }
1286
1287 /**
1288  * gen6_add_request - Update the semaphore mailbox registers
1289  *
1290  * @ring - ring that is adding a request
1291  * @seqno - return seqno stuck into the ring
1292  *
1293  * Update the mailbox registers in the *other* rings with the current seqno.
1294  * This acts like a signal in the canonical semaphore.
1295  */
1296 static int
1297 gen6_add_request(struct intel_engine_cs *ring)
1298 {
1299         int ret;
1300
1301         if (ring->semaphore.signal)
1302                 ret = ring->semaphore.signal(ring, 4);
1303         else
1304                 ret = intel_ring_begin(ring, 4);
1305
1306         if (ret)
1307                 return ret;
1308
1309         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1310         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1311         intel_ring_emit(ring,
1312                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1313         intel_ring_emit(ring, MI_USER_INTERRUPT);
1314         __intel_ring_advance(ring);
1315
1316         return 0;
1317 }
1318
1319 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1320                                               u32 seqno)
1321 {
1322         struct drm_i915_private *dev_priv = dev->dev_private;
1323         return dev_priv->last_seqno < seqno;
1324 }
1325
1326 /**
1327  * intel_ring_sync - sync the waiter to the signaller on seqno
1328  *
1329  * @waiter - ring that is waiting
1330  * @signaller - ring which has, or will signal
1331  * @seqno - seqno which the waiter will block on
1332  */
1333
1334 static int
1335 gen8_ring_sync(struct intel_engine_cs *waiter,
1336                struct intel_engine_cs *signaller,
1337                u32 seqno)
1338 {
1339         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1340         int ret;
1341
1342         ret = intel_ring_begin(waiter, 4);
1343         if (ret)
1344                 return ret;
1345
1346         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1347                                 MI_SEMAPHORE_GLOBAL_GTT |
1348                                 MI_SEMAPHORE_POLL |
1349                                 MI_SEMAPHORE_SAD_GTE_SDD);
1350         intel_ring_emit(waiter, seqno);
1351         intel_ring_emit(waiter,
1352                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1353         intel_ring_emit(waiter,
1354                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1355         intel_ring_advance(waiter);
1356         return 0;
1357 }
1358
1359 static int
1360 gen6_ring_sync(struct intel_engine_cs *waiter,
1361                struct intel_engine_cs *signaller,
1362                u32 seqno)
1363 {
1364         u32 dw1 = MI_SEMAPHORE_MBOX |
1365                   MI_SEMAPHORE_COMPARE |
1366                   MI_SEMAPHORE_REGISTER;
1367         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1368         int ret;
1369
1370         /* Throughout all of the GEM code, seqno passed implies our current
1371          * seqno is >= the last seqno executed. However for hardware the
1372          * comparison is strictly greater than.
1373          */
1374         seqno -= 1;
1375
1376         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1377
1378         ret = intel_ring_begin(waiter, 4);
1379         if (ret)
1380                 return ret;
1381
1382         /* If seqno wrap happened, omit the wait with no-ops */
1383         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1384                 intel_ring_emit(waiter, dw1 | wait_mbox);
1385                 intel_ring_emit(waiter, seqno);
1386                 intel_ring_emit(waiter, 0);
1387                 intel_ring_emit(waiter, MI_NOOP);
1388         } else {
1389                 intel_ring_emit(waiter, MI_NOOP);
1390                 intel_ring_emit(waiter, MI_NOOP);
1391                 intel_ring_emit(waiter, MI_NOOP);
1392                 intel_ring_emit(waiter, MI_NOOP);
1393         }
1394         intel_ring_advance(waiter);
1395
1396         return 0;
1397 }
1398
1399 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1400 do {                                                                    \
1401         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1402                  PIPE_CONTROL_DEPTH_STALL);                             \
1403         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1404         intel_ring_emit(ring__, 0);                                                     \
1405         intel_ring_emit(ring__, 0);                                                     \
1406 } while (0)
1407
1408 static int
1409 pc_render_add_request(struct intel_engine_cs *ring)
1410 {
1411         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1412         int ret;
1413
1414         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1415          * incoherent with writes to memory, i.e. completely fubar,
1416          * so we need to use PIPE_NOTIFY instead.
1417          *
1418          * However, we also need to workaround the qword write
1419          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1420          * memory before requesting an interrupt.
1421          */
1422         ret = intel_ring_begin(ring, 32);
1423         if (ret)
1424                 return ret;
1425
1426         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1427                         PIPE_CONTROL_WRITE_FLUSH |
1428                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1429         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1430         intel_ring_emit(ring,
1431                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1432         intel_ring_emit(ring, 0);
1433         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1434         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1435         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1436         scratch_addr += 2 * CACHELINE_BYTES;
1437         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1438         scratch_addr += 2 * CACHELINE_BYTES;
1439         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1440         scratch_addr += 2 * CACHELINE_BYTES;
1441         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1442         scratch_addr += 2 * CACHELINE_BYTES;
1443         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1444
1445         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1446                         PIPE_CONTROL_WRITE_FLUSH |
1447                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1448                         PIPE_CONTROL_NOTIFY);
1449         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1450         intel_ring_emit(ring,
1451                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1452         intel_ring_emit(ring, 0);
1453         __intel_ring_advance(ring);
1454
1455         return 0;
1456 }
1457
1458 static u32
1459 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1460 {
1461         /* Workaround to force correct ordering between irq and seqno writes on
1462          * ivb (and maybe also on snb) by reading from a CS register (like
1463          * ACTHD) before reading the status page. */
1464         if (!lazy_coherency) {
1465                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1466                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1467         }
1468
1469         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1470 }
1471
1472 static u32
1473 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1474 {
1475         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1476 }
1477
1478 static void
1479 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1480 {
1481         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1482 }
1483
1484 static u32
1485 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1486 {
1487         return ring->scratch.cpu_page[0];
1488 }
1489
1490 static void
1491 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1492 {
1493         ring->scratch.cpu_page[0] = seqno;
1494 }
1495
1496 static bool
1497 gen5_ring_get_irq(struct intel_engine_cs *ring)
1498 {
1499         struct drm_device *dev = ring->dev;
1500         struct drm_i915_private *dev_priv = dev->dev_private;
1501         unsigned long flags;
1502
1503         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1504                 return false;
1505
1506         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1507         if (ring->irq_refcount++ == 0)
1508                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1509         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1510
1511         return true;
1512 }
1513
1514 static void
1515 gen5_ring_put_irq(struct intel_engine_cs *ring)
1516 {
1517         struct drm_device *dev = ring->dev;
1518         struct drm_i915_private *dev_priv = dev->dev_private;
1519         unsigned long flags;
1520
1521         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1522         if (--ring->irq_refcount == 0)
1523                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1524         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1525 }
1526
1527 static bool
1528 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1529 {
1530         struct drm_device *dev = ring->dev;
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         unsigned long flags;
1533
1534         if (!intel_irqs_enabled(dev_priv))
1535                 return false;
1536
1537         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1538         if (ring->irq_refcount++ == 0) {
1539                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1540                 I915_WRITE(IMR, dev_priv->irq_mask);
1541                 POSTING_READ(IMR);
1542         }
1543         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1544
1545         return true;
1546 }
1547
1548 static void
1549 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1550 {
1551         struct drm_device *dev = ring->dev;
1552         struct drm_i915_private *dev_priv = dev->dev_private;
1553         unsigned long flags;
1554
1555         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1556         if (--ring->irq_refcount == 0) {
1557                 dev_priv->irq_mask |= ring->irq_enable_mask;
1558                 I915_WRITE(IMR, dev_priv->irq_mask);
1559                 POSTING_READ(IMR);
1560         }
1561         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1562 }
1563
1564 static bool
1565 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1566 {
1567         struct drm_device *dev = ring->dev;
1568         struct drm_i915_private *dev_priv = dev->dev_private;
1569         unsigned long flags;
1570
1571         if (!intel_irqs_enabled(dev_priv))
1572                 return false;
1573
1574         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1575         if (ring->irq_refcount++ == 0) {
1576                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1577                 I915_WRITE16(IMR, dev_priv->irq_mask);
1578                 POSTING_READ16(IMR);
1579         }
1580         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1581
1582         return true;
1583 }
1584
1585 static void
1586 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1587 {
1588         struct drm_device *dev = ring->dev;
1589         struct drm_i915_private *dev_priv = dev->dev_private;
1590         unsigned long flags;
1591
1592         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1593         if (--ring->irq_refcount == 0) {
1594                 dev_priv->irq_mask |= ring->irq_enable_mask;
1595                 I915_WRITE16(IMR, dev_priv->irq_mask);
1596                 POSTING_READ16(IMR);
1597         }
1598         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1599 }
1600
1601 static int
1602 bsd_ring_flush(struct drm_i915_gem_request *req,
1603                u32     invalidate_domains,
1604                u32     flush_domains)
1605 {
1606         struct intel_engine_cs *ring = req->ring;
1607         int ret;
1608
1609         ret = intel_ring_begin(ring, 2);
1610         if (ret)
1611                 return ret;
1612
1613         intel_ring_emit(ring, MI_FLUSH);
1614         intel_ring_emit(ring, MI_NOOP);
1615         intel_ring_advance(ring);
1616         return 0;
1617 }
1618
1619 static int
1620 i9xx_add_request(struct intel_engine_cs *ring)
1621 {
1622         int ret;
1623
1624         ret = intel_ring_begin(ring, 4);
1625         if (ret)
1626                 return ret;
1627
1628         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1629         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1630         intel_ring_emit(ring,
1631                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1632         intel_ring_emit(ring, MI_USER_INTERRUPT);
1633         __intel_ring_advance(ring);
1634
1635         return 0;
1636 }
1637
1638 static bool
1639 gen6_ring_get_irq(struct intel_engine_cs *ring)
1640 {
1641         struct drm_device *dev = ring->dev;
1642         struct drm_i915_private *dev_priv = dev->dev_private;
1643         unsigned long flags;
1644
1645         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1646                 return false;
1647
1648         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1649         if (ring->irq_refcount++ == 0) {
1650                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1651                         I915_WRITE_IMR(ring,
1652                                        ~(ring->irq_enable_mask |
1653                                          GT_PARITY_ERROR(dev)));
1654                 else
1655                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1656                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1657         }
1658         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1659
1660         return true;
1661 }
1662
1663 static void
1664 gen6_ring_put_irq(struct intel_engine_cs *ring)
1665 {
1666         struct drm_device *dev = ring->dev;
1667         struct drm_i915_private *dev_priv = dev->dev_private;
1668         unsigned long flags;
1669
1670         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1671         if (--ring->irq_refcount == 0) {
1672                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1673                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1674                 else
1675                         I915_WRITE_IMR(ring, ~0);
1676                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1677         }
1678         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1679 }
1680
1681 static bool
1682 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1683 {
1684         struct drm_device *dev = ring->dev;
1685         struct drm_i915_private *dev_priv = dev->dev_private;
1686         unsigned long flags;
1687
1688         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1689                 return false;
1690
1691         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1692         if (ring->irq_refcount++ == 0) {
1693                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1694                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1695         }
1696         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1697
1698         return true;
1699 }
1700
1701 static void
1702 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1703 {
1704         struct drm_device *dev = ring->dev;
1705         struct drm_i915_private *dev_priv = dev->dev_private;
1706         unsigned long flags;
1707
1708         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1709         if (--ring->irq_refcount == 0) {
1710                 I915_WRITE_IMR(ring, ~0);
1711                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1712         }
1713         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1714 }
1715
1716 static bool
1717 gen8_ring_get_irq(struct intel_engine_cs *ring)
1718 {
1719         struct drm_device *dev = ring->dev;
1720         struct drm_i915_private *dev_priv = dev->dev_private;
1721         unsigned long flags;
1722
1723         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1724                 return false;
1725
1726         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1727         if (ring->irq_refcount++ == 0) {
1728                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1729                         I915_WRITE_IMR(ring,
1730                                        ~(ring->irq_enable_mask |
1731                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1732                 } else {
1733                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1734                 }
1735                 POSTING_READ(RING_IMR(ring->mmio_base));
1736         }
1737         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1738
1739         return true;
1740 }
1741
1742 static void
1743 gen8_ring_put_irq(struct intel_engine_cs *ring)
1744 {
1745         struct drm_device *dev = ring->dev;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747         unsigned long flags;
1748
1749         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1750         if (--ring->irq_refcount == 0) {
1751                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1752                         I915_WRITE_IMR(ring,
1753                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1754                 } else {
1755                         I915_WRITE_IMR(ring, ~0);
1756                 }
1757                 POSTING_READ(RING_IMR(ring->mmio_base));
1758         }
1759         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1760 }
1761
1762 static int
1763 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1764                          u64 offset, u32 length,
1765                          unsigned dispatch_flags)
1766 {
1767         int ret;
1768
1769         ret = intel_ring_begin(ring, 2);
1770         if (ret)
1771                 return ret;
1772
1773         intel_ring_emit(ring,
1774                         MI_BATCH_BUFFER_START |
1775                         MI_BATCH_GTT |
1776                         (dispatch_flags & I915_DISPATCH_SECURE ?
1777                          0 : MI_BATCH_NON_SECURE_I965));
1778         intel_ring_emit(ring, offset);
1779         intel_ring_advance(ring);
1780
1781         return 0;
1782 }
1783
1784 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1785 #define I830_BATCH_LIMIT (256*1024)
1786 #define I830_TLB_ENTRIES (2)
1787 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1788 static int
1789 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1790                          u64 offset, u32 len,
1791                          unsigned dispatch_flags)
1792 {
1793         u32 cs_offset = ring->scratch.gtt_offset;
1794         int ret;
1795
1796         ret = intel_ring_begin(ring, 6);
1797         if (ret)
1798                 return ret;
1799
1800         /* Evict the invalid PTE TLBs */
1801         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1802         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1803         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1804         intel_ring_emit(ring, cs_offset);
1805         intel_ring_emit(ring, 0xdeadbeef);
1806         intel_ring_emit(ring, MI_NOOP);
1807         intel_ring_advance(ring);
1808
1809         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1810                 if (len > I830_BATCH_LIMIT)
1811                         return -ENOSPC;
1812
1813                 ret = intel_ring_begin(ring, 6 + 2);
1814                 if (ret)
1815                         return ret;
1816
1817                 /* Blit the batch (which has now all relocs applied) to the
1818                  * stable batch scratch bo area (so that the CS never
1819                  * stumbles over its tlb invalidation bug) ...
1820                  */
1821                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1822                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1823                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1824                 intel_ring_emit(ring, cs_offset);
1825                 intel_ring_emit(ring, 4096);
1826                 intel_ring_emit(ring, offset);
1827
1828                 intel_ring_emit(ring, MI_FLUSH);
1829                 intel_ring_emit(ring, MI_NOOP);
1830                 intel_ring_advance(ring);
1831
1832                 /* ... and execute it. */
1833                 offset = cs_offset;
1834         }
1835
1836         ret = intel_ring_begin(ring, 4);
1837         if (ret)
1838                 return ret;
1839
1840         intel_ring_emit(ring, MI_BATCH_BUFFER);
1841         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1842                                         0 : MI_BATCH_NON_SECURE));
1843         intel_ring_emit(ring, offset + len - 8);
1844         intel_ring_emit(ring, MI_NOOP);
1845         intel_ring_advance(ring);
1846
1847         return 0;
1848 }
1849
1850 static int
1851 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1852                          u64 offset, u32 len,
1853                          unsigned dispatch_flags)
1854 {
1855         int ret;
1856
1857         ret = intel_ring_begin(ring, 2);
1858         if (ret)
1859                 return ret;
1860
1861         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1862         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1863                                         0 : MI_BATCH_NON_SECURE));
1864         intel_ring_advance(ring);
1865
1866         return 0;
1867 }
1868
1869 static void cleanup_status_page(struct intel_engine_cs *ring)
1870 {
1871         struct drm_i915_gem_object *obj;
1872
1873         obj = ring->status_page.obj;
1874         if (obj == NULL)
1875                 return;
1876
1877         kunmap(sg_page(obj->pages->sgl));
1878         i915_gem_object_ggtt_unpin(obj);
1879         drm_gem_object_unreference(&obj->base);
1880         ring->status_page.obj = NULL;
1881 }
1882
1883 static int init_status_page(struct intel_engine_cs *ring)
1884 {
1885         struct drm_i915_gem_object *obj;
1886
1887         if ((obj = ring->status_page.obj) == NULL) {
1888                 unsigned flags;
1889                 int ret;
1890
1891                 obj = i915_gem_alloc_object(ring->dev, 4096);
1892                 if (obj == NULL) {
1893                         DRM_ERROR("Failed to allocate status page\n");
1894                         return -ENOMEM;
1895                 }
1896
1897                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1898                 if (ret)
1899                         goto err_unref;
1900
1901                 flags = 0;
1902                 if (!HAS_LLC(ring->dev))
1903                         /* On g33, we cannot place HWS above 256MiB, so
1904                          * restrict its pinning to the low mappable arena.
1905                          * Though this restriction is not documented for
1906                          * gen4, gen5, or byt, they also behave similarly
1907                          * and hang if the HWS is placed at the top of the
1908                          * GTT. To generalise, it appears that all !llc
1909                          * platforms have issues with us placing the HWS
1910                          * above the mappable region (even though we never
1911                          * actualy map it).
1912                          */
1913                         flags |= PIN_MAPPABLE;
1914                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1915                 if (ret) {
1916 err_unref:
1917                         drm_gem_object_unreference(&obj->base);
1918                         return ret;
1919                 }
1920
1921                 ring->status_page.obj = obj;
1922         }
1923
1924         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1925         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1926         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1927
1928         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1929                         ring->name, ring->status_page.gfx_addr);
1930
1931         return 0;
1932 }
1933
1934 static int init_phys_status_page(struct intel_engine_cs *ring)
1935 {
1936         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1937
1938         if (!dev_priv->status_page_dmah) {
1939                 dev_priv->status_page_dmah =
1940                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1941                 if (!dev_priv->status_page_dmah)
1942                         return -ENOMEM;
1943         }
1944
1945         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1946         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1947
1948         return 0;
1949 }
1950
1951 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1952 {
1953         iounmap(ringbuf->virtual_start);
1954         ringbuf->virtual_start = NULL;
1955         i915_gem_object_ggtt_unpin(ringbuf->obj);
1956 }
1957
1958 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1959                                      struct intel_ringbuffer *ringbuf)
1960 {
1961         struct drm_i915_private *dev_priv = to_i915(dev);
1962         struct drm_i915_gem_object *obj = ringbuf->obj;
1963         int ret;
1964
1965         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1966         if (ret)
1967                 return ret;
1968
1969         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1970         if (ret) {
1971                 i915_gem_object_ggtt_unpin(obj);
1972                 return ret;
1973         }
1974
1975         ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1976                         i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1977         if (ringbuf->virtual_start == NULL) {
1978                 i915_gem_object_ggtt_unpin(obj);
1979                 return -EINVAL;
1980         }
1981
1982         return 0;
1983 }
1984
1985 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1986 {
1987         drm_gem_object_unreference(&ringbuf->obj->base);
1988         ringbuf->obj = NULL;
1989 }
1990
1991 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1992                                struct intel_ringbuffer *ringbuf)
1993 {
1994         struct drm_i915_gem_object *obj;
1995
1996         obj = NULL;
1997         if (!HAS_LLC(dev))
1998                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1999         if (obj == NULL)
2000                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2001         if (obj == NULL)
2002                 return -ENOMEM;
2003
2004         /* mark ring buffers as read-only from GPU side by default */
2005         obj->gt_ro = 1;
2006
2007         ringbuf->obj = obj;
2008
2009         return 0;
2010 }
2011
2012 static int intel_init_ring_buffer(struct drm_device *dev,
2013                                   struct intel_engine_cs *ring)
2014 {
2015         struct intel_ringbuffer *ringbuf;
2016         int ret;
2017
2018         WARN_ON(ring->buffer);
2019
2020         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2021         if (!ringbuf)
2022                 return -ENOMEM;
2023         ring->buffer = ringbuf;
2024
2025         ring->dev = dev;
2026         INIT_LIST_HEAD(&ring->active_list);
2027         INIT_LIST_HEAD(&ring->request_list);
2028         INIT_LIST_HEAD(&ring->execlist_queue);
2029         i915_gem_batch_pool_init(dev, &ring->batch_pool);
2030         ringbuf->size = 32 * PAGE_SIZE;
2031         ringbuf->ring = ring;
2032         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2033
2034         init_waitqueue_head(&ring->irq_queue);
2035
2036         if (I915_NEED_GFX_HWS(dev)) {
2037                 ret = init_status_page(ring);
2038                 if (ret)
2039                         goto error;
2040         } else {
2041                 BUG_ON(ring->id != RCS);
2042                 ret = init_phys_status_page(ring);
2043                 if (ret)
2044                         goto error;
2045         }
2046
2047         WARN_ON(ringbuf->obj);
2048
2049         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2050         if (ret) {
2051                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2052                                 ring->name, ret);
2053                 goto error;
2054         }
2055
2056         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2057         if (ret) {
2058                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2059                                 ring->name, ret);
2060                 intel_destroy_ringbuffer_obj(ringbuf);
2061                 goto error;
2062         }
2063
2064         /* Workaround an erratum on the i830 which causes a hang if
2065          * the TAIL pointer points to within the last 2 cachelines
2066          * of the buffer.
2067          */
2068         ringbuf->effective_size = ringbuf->size;
2069         if (IS_I830(dev) || IS_845G(dev))
2070                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2071
2072         ret = i915_cmd_parser_init_ring(ring);
2073         if (ret)
2074                 goto error;
2075
2076         return 0;
2077
2078 error:
2079         kfree(ringbuf);
2080         ring->buffer = NULL;
2081         return ret;
2082 }
2083
2084 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2085 {
2086         struct drm_i915_private *dev_priv;
2087         struct intel_ringbuffer *ringbuf;
2088
2089         if (!intel_ring_initialized(ring))
2090                 return;
2091
2092         dev_priv = to_i915(ring->dev);
2093         ringbuf = ring->buffer;
2094
2095         intel_stop_ring_buffer(ring);
2096         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2097
2098         intel_unpin_ringbuffer_obj(ringbuf);
2099         intel_destroy_ringbuffer_obj(ringbuf);
2100         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2101
2102         if (ring->cleanup)
2103                 ring->cleanup(ring);
2104
2105         cleanup_status_page(ring);
2106
2107         i915_cmd_parser_fini_ring(ring);
2108         i915_gem_batch_pool_fini(&ring->batch_pool);
2109
2110         kfree(ringbuf);
2111         ring->buffer = NULL;
2112 }
2113
2114 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2115 {
2116         struct intel_ringbuffer *ringbuf = ring->buffer;
2117         struct drm_i915_gem_request *request;
2118         unsigned space;
2119         int ret;
2120
2121         /* The whole point of reserving space is to not wait! */
2122         WARN_ON(ringbuf->reserved_in_use);
2123
2124         if (intel_ring_space(ringbuf) >= n)
2125                 return 0;
2126
2127         list_for_each_entry(request, &ring->request_list, list) {
2128                 space = __intel_ring_space(request->postfix, ringbuf->tail,
2129                                            ringbuf->size);
2130                 if (space >= n)
2131                         break;
2132         }
2133
2134         if (WARN_ON(&request->list == &ring->request_list))
2135                 return -ENOSPC;
2136
2137         ret = i915_wait_request(request);
2138         if (ret)
2139                 return ret;
2140
2141         ringbuf->space = space;
2142         return 0;
2143 }
2144
2145 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2146 {
2147         uint32_t __iomem *virt;
2148         struct intel_ringbuffer *ringbuf = ring->buffer;
2149         int rem = ringbuf->size - ringbuf->tail;
2150
2151         /* Can't wrap if space has already been reserved! */
2152         WARN_ON(ringbuf->reserved_in_use);
2153
2154         if (ringbuf->space < rem) {
2155                 int ret = ring_wait_for_space(ring, rem);
2156                 if (ret)
2157                         return ret;
2158         }
2159
2160         virt = ringbuf->virtual_start + ringbuf->tail;
2161         rem /= 4;
2162         while (rem--)
2163                 iowrite32(MI_NOOP, virt++);
2164
2165         ringbuf->tail = 0;
2166         intel_ring_update_space(ringbuf);
2167
2168         return 0;
2169 }
2170
2171 int intel_ring_idle(struct intel_engine_cs *ring)
2172 {
2173         struct drm_i915_gem_request *req;
2174
2175         /* We need to add any requests required to flush the objects and ring */
2176         WARN_ON(ring->outstanding_lazy_request);
2177         if (ring->outstanding_lazy_request)
2178                 i915_add_request(ring->outstanding_lazy_request);
2179
2180         /* Wait upon the last request to be completed */
2181         if (list_empty(&ring->request_list))
2182                 return 0;
2183
2184         req = list_entry(ring->request_list.prev,
2185                         struct drm_i915_gem_request,
2186                         list);
2187
2188         /* Make sure we do not trigger any retires */
2189         return __i915_wait_request(req,
2190                                    atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2191                                    to_i915(ring->dev)->mm.interruptible,
2192                                    NULL, NULL);
2193 }
2194
2195 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2196 {
2197         request->ringbuf = request->ring->buffer;
2198         return 0;
2199 }
2200
2201 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2202 {
2203         /* NB: Until request management is fully tidied up and the OLR is
2204          * removed, there are too many ways for get false hits on this
2205          * anti-recursion check! */
2206         /*WARN_ON(ringbuf->reserved_size);*/
2207         WARN_ON(ringbuf->reserved_in_use);
2208
2209         ringbuf->reserved_size = size;
2210
2211         /*
2212          * Really need to call _begin() here but that currently leads to
2213          * recursion problems! This will be fixed later but for now just
2214          * return and hope for the best. Note that there is only a real
2215          * problem if the create of the request never actually calls _begin()
2216          * but if they are not submitting any work then why did they create
2217          * the request in the first place?
2218          */
2219 }
2220
2221 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2222 {
2223         WARN_ON(ringbuf->reserved_in_use);
2224
2225         ringbuf->reserved_size   = 0;
2226         ringbuf->reserved_in_use = false;
2227 }
2228
2229 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2230 {
2231         WARN_ON(ringbuf->reserved_in_use);
2232
2233         ringbuf->reserved_in_use = true;
2234         ringbuf->reserved_tail   = ringbuf->tail;
2235 }
2236
2237 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2238 {
2239         WARN_ON(!ringbuf->reserved_in_use);
2240         WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2241              "request reserved size too small: %d vs %d!\n",
2242              ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2243
2244         ringbuf->reserved_size   = 0;
2245         ringbuf->reserved_in_use = false;
2246 }
2247
2248 static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2249 {
2250         struct intel_ringbuffer *ringbuf = ring->buffer;
2251         int ret;
2252
2253         /*
2254          * Add on the reserved size to the request to make sure that after
2255          * the intended commands have been emitted, there is guaranteed to
2256          * still be enough free space to send them to the hardware.
2257          */
2258         if (!ringbuf->reserved_in_use)
2259                 bytes += ringbuf->reserved_size;
2260
2261         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2262                 ret = intel_wrap_ring_buffer(ring);
2263                 if (unlikely(ret))
2264                         return ret;
2265
2266                 if(ringbuf->reserved_size) {
2267                         uint32_t size = ringbuf->reserved_size;
2268
2269                         intel_ring_reserved_space_cancel(ringbuf);
2270                         intel_ring_reserved_space_reserve(ringbuf, size);
2271                 }
2272         }
2273
2274         if (unlikely(ringbuf->space < bytes)) {
2275                 ret = ring_wait_for_space(ring, bytes);
2276                 if (unlikely(ret))
2277                         return ret;
2278         }
2279
2280         return 0;
2281 }
2282
2283 int intel_ring_begin(struct intel_engine_cs *ring,
2284                      int num_dwords)
2285 {
2286         struct drm_i915_gem_request *req;
2287         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2288         int ret;
2289
2290         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2291                                    dev_priv->mm.interruptible);
2292         if (ret)
2293                 return ret;
2294
2295         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2296         if (ret)
2297                 return ret;
2298
2299         /* Preallocate the olr before touching the ring */
2300         ret = i915_gem_request_alloc(ring, ring->default_context, &req);
2301         if (ret)
2302                 return ret;
2303
2304         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2305         return 0;
2306 }
2307
2308 /* Align the ring tail to a cacheline boundary */
2309 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2310 {
2311         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2312         int ret;
2313
2314         if (num_dwords == 0)
2315                 return 0;
2316
2317         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2318         ret = intel_ring_begin(ring, num_dwords);
2319         if (ret)
2320                 return ret;
2321
2322         while (num_dwords--)
2323                 intel_ring_emit(ring, MI_NOOP);
2324
2325         intel_ring_advance(ring);
2326
2327         return 0;
2328 }
2329
2330 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2331 {
2332         struct drm_device *dev = ring->dev;
2333         struct drm_i915_private *dev_priv = dev->dev_private;
2334
2335         BUG_ON(ring->outstanding_lazy_request);
2336
2337         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2338                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2339                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2340                 if (HAS_VEBOX(dev))
2341                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2342         }
2343
2344         ring->set_seqno(ring, seqno);
2345         ring->hangcheck.seqno = seqno;
2346 }
2347
2348 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2349                                      u32 value)
2350 {
2351         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2352
2353        /* Every tail move must follow the sequence below */
2354
2355         /* Disable notification that the ring is IDLE. The GT
2356          * will then assume that it is busy and bring it out of rc6.
2357          */
2358         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2359                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2360
2361         /* Clear the context id. Here be magic! */
2362         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2363
2364         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2365         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2366                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2367                      50))
2368                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2369
2370         /* Now that the ring is fully powered up, update the tail */
2371         I915_WRITE_TAIL(ring, value);
2372         POSTING_READ(RING_TAIL(ring->mmio_base));
2373
2374         /* Let the ring send IDLE messages to the GT again,
2375          * and so let it sleep to conserve power when idle.
2376          */
2377         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2378                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2379 }
2380
2381 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2382                                u32 invalidate, u32 flush)
2383 {
2384         struct intel_engine_cs *ring = req->ring;
2385         uint32_t cmd;
2386         int ret;
2387
2388         ret = intel_ring_begin(ring, 4);
2389         if (ret)
2390                 return ret;
2391
2392         cmd = MI_FLUSH_DW;
2393         if (INTEL_INFO(ring->dev)->gen >= 8)
2394                 cmd += 1;
2395
2396         /* We always require a command barrier so that subsequent
2397          * commands, such as breadcrumb interrupts, are strictly ordered
2398          * wrt the contents of the write cache being flushed to memory
2399          * (and thus being coherent from the CPU).
2400          */
2401         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2402
2403         /*
2404          * Bspec vol 1c.5 - video engine command streamer:
2405          * "If ENABLED, all TLBs will be invalidated once the flush
2406          * operation is complete. This bit is only valid when the
2407          * Post-Sync Operation field is a value of 1h or 3h."
2408          */
2409         if (invalidate & I915_GEM_GPU_DOMAINS)
2410                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2411
2412         intel_ring_emit(ring, cmd);
2413         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2414         if (INTEL_INFO(ring->dev)->gen >= 8) {
2415                 intel_ring_emit(ring, 0); /* upper addr */
2416                 intel_ring_emit(ring, 0); /* value */
2417         } else  {
2418                 intel_ring_emit(ring, 0);
2419                 intel_ring_emit(ring, MI_NOOP);
2420         }
2421         intel_ring_advance(ring);
2422         return 0;
2423 }
2424
2425 static int
2426 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2427                               u64 offset, u32 len,
2428                               unsigned dispatch_flags)
2429 {
2430         bool ppgtt = USES_PPGTT(ring->dev) &&
2431                         !(dispatch_flags & I915_DISPATCH_SECURE);
2432         int ret;
2433
2434         ret = intel_ring_begin(ring, 4);
2435         if (ret)
2436                 return ret;
2437
2438         /* FIXME(BDW): Address space and security selectors. */
2439         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2440         intel_ring_emit(ring, lower_32_bits(offset));
2441         intel_ring_emit(ring, upper_32_bits(offset));
2442         intel_ring_emit(ring, MI_NOOP);
2443         intel_ring_advance(ring);
2444
2445         return 0;
2446 }
2447
2448 static int
2449 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2450                              u64 offset, u32 len,
2451                              unsigned dispatch_flags)
2452 {
2453         int ret;
2454
2455         ret = intel_ring_begin(ring, 2);
2456         if (ret)
2457                 return ret;
2458
2459         intel_ring_emit(ring,
2460                         MI_BATCH_BUFFER_START |
2461                         (dispatch_flags & I915_DISPATCH_SECURE ?
2462                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2463         /* bit0-7 is the length on GEN6+ */
2464         intel_ring_emit(ring, offset);
2465         intel_ring_advance(ring);
2466
2467         return 0;
2468 }
2469
2470 static int
2471 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2472                               u64 offset, u32 len,
2473                               unsigned dispatch_flags)
2474 {
2475         int ret;
2476
2477         ret = intel_ring_begin(ring, 2);
2478         if (ret)
2479                 return ret;
2480
2481         intel_ring_emit(ring,
2482                         MI_BATCH_BUFFER_START |
2483                         (dispatch_flags & I915_DISPATCH_SECURE ?
2484                          0 : MI_BATCH_NON_SECURE_I965));
2485         /* bit0-7 is the length on GEN6+ */
2486         intel_ring_emit(ring, offset);
2487         intel_ring_advance(ring);
2488
2489         return 0;
2490 }
2491
2492 /* Blitter support (SandyBridge+) */
2493
2494 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2495                            u32 invalidate, u32 flush)
2496 {
2497         struct intel_engine_cs *ring = req->ring;
2498         struct drm_device *dev = ring->dev;
2499         uint32_t cmd;
2500         int ret;
2501
2502         ret = intel_ring_begin(ring, 4);
2503         if (ret)
2504                 return ret;
2505
2506         cmd = MI_FLUSH_DW;
2507         if (INTEL_INFO(dev)->gen >= 8)
2508                 cmd += 1;
2509
2510         /* We always require a command barrier so that subsequent
2511          * commands, such as breadcrumb interrupts, are strictly ordered
2512          * wrt the contents of the write cache being flushed to memory
2513          * (and thus being coherent from the CPU).
2514          */
2515         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2516
2517         /*
2518          * Bspec vol 1c.3 - blitter engine command streamer:
2519          * "If ENABLED, all TLBs will be invalidated once the flush
2520          * operation is complete. This bit is only valid when the
2521          * Post-Sync Operation field is a value of 1h or 3h."
2522          */
2523         if (invalidate & I915_GEM_DOMAIN_RENDER)
2524                 cmd |= MI_INVALIDATE_TLB;
2525         intel_ring_emit(ring, cmd);
2526         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2527         if (INTEL_INFO(dev)->gen >= 8) {
2528                 intel_ring_emit(ring, 0); /* upper addr */
2529                 intel_ring_emit(ring, 0); /* value */
2530         } else  {
2531                 intel_ring_emit(ring, 0);
2532                 intel_ring_emit(ring, MI_NOOP);
2533         }
2534         intel_ring_advance(ring);
2535
2536         return 0;
2537 }
2538
2539 int intel_init_render_ring_buffer(struct drm_device *dev)
2540 {
2541         struct drm_i915_private *dev_priv = dev->dev_private;
2542         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2543         struct drm_i915_gem_object *obj;
2544         int ret;
2545
2546         ring->name = "render ring";
2547         ring->id = RCS;
2548         ring->mmio_base = RENDER_RING_BASE;
2549
2550         if (INTEL_INFO(dev)->gen >= 8) {
2551                 if (i915_semaphore_is_enabled(dev)) {
2552                         obj = i915_gem_alloc_object(dev, 4096);
2553                         if (obj == NULL) {
2554                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2555                                 i915.semaphores = 0;
2556                         } else {
2557                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2558                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2559                                 if (ret != 0) {
2560                                         drm_gem_object_unreference(&obj->base);
2561                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2562                                         i915.semaphores = 0;
2563                                 } else
2564                                         dev_priv->semaphore_obj = obj;
2565                         }
2566                 }
2567
2568                 ring->init_context = intel_rcs_ctx_init;
2569                 ring->add_request = gen6_add_request;
2570                 ring->flush = gen8_render_ring_flush;
2571                 ring->irq_get = gen8_ring_get_irq;
2572                 ring->irq_put = gen8_ring_put_irq;
2573                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2574                 ring->get_seqno = gen6_ring_get_seqno;
2575                 ring->set_seqno = ring_set_seqno;
2576                 if (i915_semaphore_is_enabled(dev)) {
2577                         WARN_ON(!dev_priv->semaphore_obj);
2578                         ring->semaphore.sync_to = gen8_ring_sync;
2579                         ring->semaphore.signal = gen8_rcs_signal;
2580                         GEN8_RING_SEMAPHORE_INIT;
2581                 }
2582         } else if (INTEL_INFO(dev)->gen >= 6) {
2583                 ring->add_request = gen6_add_request;
2584                 ring->flush = gen7_render_ring_flush;
2585                 if (INTEL_INFO(dev)->gen == 6)
2586                         ring->flush = gen6_render_ring_flush;
2587                 ring->irq_get = gen6_ring_get_irq;
2588                 ring->irq_put = gen6_ring_put_irq;
2589                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2590                 ring->get_seqno = gen6_ring_get_seqno;
2591                 ring->set_seqno = ring_set_seqno;
2592                 if (i915_semaphore_is_enabled(dev)) {
2593                         ring->semaphore.sync_to = gen6_ring_sync;
2594                         ring->semaphore.signal = gen6_signal;
2595                         /*
2596                          * The current semaphore is only applied on pre-gen8
2597                          * platform.  And there is no VCS2 ring on the pre-gen8
2598                          * platform. So the semaphore between RCS and VCS2 is
2599                          * initialized as INVALID.  Gen8 will initialize the
2600                          * sema between VCS2 and RCS later.
2601                          */
2602                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2603                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2604                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2605                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2606                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2607                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2608                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2609                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2610                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2611                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2612                 }
2613         } else if (IS_GEN5(dev)) {
2614                 ring->add_request = pc_render_add_request;
2615                 ring->flush = gen4_render_ring_flush;
2616                 ring->get_seqno = pc_render_get_seqno;
2617                 ring->set_seqno = pc_render_set_seqno;
2618                 ring->irq_get = gen5_ring_get_irq;
2619                 ring->irq_put = gen5_ring_put_irq;
2620                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2621                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2622         } else {
2623                 ring->add_request = i9xx_add_request;
2624                 if (INTEL_INFO(dev)->gen < 4)
2625                         ring->flush = gen2_render_ring_flush;
2626                 else
2627                         ring->flush = gen4_render_ring_flush;
2628                 ring->get_seqno = ring_get_seqno;
2629                 ring->set_seqno = ring_set_seqno;
2630                 if (IS_GEN2(dev)) {
2631                         ring->irq_get = i8xx_ring_get_irq;
2632                         ring->irq_put = i8xx_ring_put_irq;
2633                 } else {
2634                         ring->irq_get = i9xx_ring_get_irq;
2635                         ring->irq_put = i9xx_ring_put_irq;
2636                 }
2637                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2638         }
2639         ring->write_tail = ring_write_tail;
2640
2641         if (IS_HASWELL(dev))
2642                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2643         else if (IS_GEN8(dev))
2644                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2645         else if (INTEL_INFO(dev)->gen >= 6)
2646                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2647         else if (INTEL_INFO(dev)->gen >= 4)
2648                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2649         else if (IS_I830(dev) || IS_845G(dev))
2650                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2651         else
2652                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2653         ring->init_hw = init_render_ring;
2654         ring->cleanup = render_ring_cleanup;
2655
2656         /* Workaround batchbuffer to combat CS tlb bug. */
2657         if (HAS_BROKEN_CS_TLB(dev)) {
2658                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2659                 if (obj == NULL) {
2660                         DRM_ERROR("Failed to allocate batch bo\n");
2661                         return -ENOMEM;
2662                 }
2663
2664                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2665                 if (ret != 0) {
2666                         drm_gem_object_unreference(&obj->base);
2667                         DRM_ERROR("Failed to ping batch bo\n");
2668                         return ret;
2669                 }
2670
2671                 ring->scratch.obj = obj;
2672                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2673         }
2674
2675         ret = intel_init_ring_buffer(dev, ring);
2676         if (ret)
2677                 return ret;
2678
2679         if (INTEL_INFO(dev)->gen >= 5) {
2680                 ret = intel_init_pipe_control(ring);
2681                 if (ret)
2682                         return ret;
2683         }
2684
2685         return 0;
2686 }
2687
2688 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2689 {
2690         struct drm_i915_private *dev_priv = dev->dev_private;
2691         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2692
2693         ring->name = "bsd ring";
2694         ring->id = VCS;
2695
2696         ring->write_tail = ring_write_tail;
2697         if (INTEL_INFO(dev)->gen >= 6) {
2698                 ring->mmio_base = GEN6_BSD_RING_BASE;
2699                 /* gen6 bsd needs a special wa for tail updates */
2700                 if (IS_GEN6(dev))
2701                         ring->write_tail = gen6_bsd_ring_write_tail;
2702                 ring->flush = gen6_bsd_ring_flush;
2703                 ring->add_request = gen6_add_request;
2704                 ring->get_seqno = gen6_ring_get_seqno;
2705                 ring->set_seqno = ring_set_seqno;
2706                 if (INTEL_INFO(dev)->gen >= 8) {
2707                         ring->irq_enable_mask =
2708                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2709                         ring->irq_get = gen8_ring_get_irq;
2710                         ring->irq_put = gen8_ring_put_irq;
2711                         ring->dispatch_execbuffer =
2712                                 gen8_ring_dispatch_execbuffer;
2713                         if (i915_semaphore_is_enabled(dev)) {
2714                                 ring->semaphore.sync_to = gen8_ring_sync;
2715                                 ring->semaphore.signal = gen8_xcs_signal;
2716                                 GEN8_RING_SEMAPHORE_INIT;
2717                         }
2718                 } else {
2719                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2720                         ring->irq_get = gen6_ring_get_irq;
2721                         ring->irq_put = gen6_ring_put_irq;
2722                         ring->dispatch_execbuffer =
2723                                 gen6_ring_dispatch_execbuffer;
2724                         if (i915_semaphore_is_enabled(dev)) {
2725                                 ring->semaphore.sync_to = gen6_ring_sync;
2726                                 ring->semaphore.signal = gen6_signal;
2727                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2728                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2729                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2730                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2731                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2732                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2733                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2734                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2735                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2736                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2737                         }
2738                 }
2739         } else {
2740                 ring->mmio_base = BSD_RING_BASE;
2741                 ring->flush = bsd_ring_flush;
2742                 ring->add_request = i9xx_add_request;
2743                 ring->get_seqno = ring_get_seqno;
2744                 ring->set_seqno = ring_set_seqno;
2745                 if (IS_GEN5(dev)) {
2746                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2747                         ring->irq_get = gen5_ring_get_irq;
2748                         ring->irq_put = gen5_ring_put_irq;
2749                 } else {
2750                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2751                         ring->irq_get = i9xx_ring_get_irq;
2752                         ring->irq_put = i9xx_ring_put_irq;
2753                 }
2754                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2755         }
2756         ring->init_hw = init_ring_common;
2757
2758         return intel_init_ring_buffer(dev, ring);
2759 }
2760
2761 /**
2762  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2763  */
2764 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2765 {
2766         struct drm_i915_private *dev_priv = dev->dev_private;
2767         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2768
2769         ring->name = "bsd2 ring";
2770         ring->id = VCS2;
2771
2772         ring->write_tail = ring_write_tail;
2773         ring->mmio_base = GEN8_BSD2_RING_BASE;
2774         ring->flush = gen6_bsd_ring_flush;
2775         ring->add_request = gen6_add_request;
2776         ring->get_seqno = gen6_ring_get_seqno;
2777         ring->set_seqno = ring_set_seqno;
2778         ring->irq_enable_mask =
2779                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2780         ring->irq_get = gen8_ring_get_irq;
2781         ring->irq_put = gen8_ring_put_irq;
2782         ring->dispatch_execbuffer =
2783                         gen8_ring_dispatch_execbuffer;
2784         if (i915_semaphore_is_enabled(dev)) {
2785                 ring->semaphore.sync_to = gen8_ring_sync;
2786                 ring->semaphore.signal = gen8_xcs_signal;
2787                 GEN8_RING_SEMAPHORE_INIT;
2788         }
2789         ring->init_hw = init_ring_common;
2790
2791         return intel_init_ring_buffer(dev, ring);
2792 }
2793
2794 int intel_init_blt_ring_buffer(struct drm_device *dev)
2795 {
2796         struct drm_i915_private *dev_priv = dev->dev_private;
2797         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2798
2799         ring->name = "blitter ring";
2800         ring->id = BCS;
2801
2802         ring->mmio_base = BLT_RING_BASE;
2803         ring->write_tail = ring_write_tail;
2804         ring->flush = gen6_ring_flush;
2805         ring->add_request = gen6_add_request;
2806         ring->get_seqno = gen6_ring_get_seqno;
2807         ring->set_seqno = ring_set_seqno;
2808         if (INTEL_INFO(dev)->gen >= 8) {
2809                 ring->irq_enable_mask =
2810                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2811                 ring->irq_get = gen8_ring_get_irq;
2812                 ring->irq_put = gen8_ring_put_irq;
2813                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2814                 if (i915_semaphore_is_enabled(dev)) {
2815                         ring->semaphore.sync_to = gen8_ring_sync;
2816                         ring->semaphore.signal = gen8_xcs_signal;
2817                         GEN8_RING_SEMAPHORE_INIT;
2818                 }
2819         } else {
2820                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2821                 ring->irq_get = gen6_ring_get_irq;
2822                 ring->irq_put = gen6_ring_put_irq;
2823                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2824                 if (i915_semaphore_is_enabled(dev)) {
2825                         ring->semaphore.signal = gen6_signal;
2826                         ring->semaphore.sync_to = gen6_ring_sync;
2827                         /*
2828                          * The current semaphore is only applied on pre-gen8
2829                          * platform.  And there is no VCS2 ring on the pre-gen8
2830                          * platform. So the semaphore between BCS and VCS2 is
2831                          * initialized as INVALID.  Gen8 will initialize the
2832                          * sema between BCS and VCS2 later.
2833                          */
2834                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2835                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2836                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2837                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2838                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2839                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2840                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2841                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2842                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2843                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2844                 }
2845         }
2846         ring->init_hw = init_ring_common;
2847
2848         return intel_init_ring_buffer(dev, ring);
2849 }
2850
2851 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2852 {
2853         struct drm_i915_private *dev_priv = dev->dev_private;
2854         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2855
2856         ring->name = "video enhancement ring";
2857         ring->id = VECS;
2858
2859         ring->mmio_base = VEBOX_RING_BASE;
2860         ring->write_tail = ring_write_tail;
2861         ring->flush = gen6_ring_flush;
2862         ring->add_request = gen6_add_request;
2863         ring->get_seqno = gen6_ring_get_seqno;
2864         ring->set_seqno = ring_set_seqno;
2865
2866         if (INTEL_INFO(dev)->gen >= 8) {
2867                 ring->irq_enable_mask =
2868                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2869                 ring->irq_get = gen8_ring_get_irq;
2870                 ring->irq_put = gen8_ring_put_irq;
2871                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2872                 if (i915_semaphore_is_enabled(dev)) {
2873                         ring->semaphore.sync_to = gen8_ring_sync;
2874                         ring->semaphore.signal = gen8_xcs_signal;
2875                         GEN8_RING_SEMAPHORE_INIT;
2876                 }
2877         } else {
2878                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2879                 ring->irq_get = hsw_vebox_get_irq;
2880                 ring->irq_put = hsw_vebox_put_irq;
2881                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2882                 if (i915_semaphore_is_enabled(dev)) {
2883                         ring->semaphore.sync_to = gen6_ring_sync;
2884                         ring->semaphore.signal = gen6_signal;
2885                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2886                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2887                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2888                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2889                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2890                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2891                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2892                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2893                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2894                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2895                 }
2896         }
2897         ring->init_hw = init_ring_common;
2898
2899         return intel_init_ring_buffer(dev, ring);
2900 }
2901
2902 int
2903 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
2904 {
2905         struct intel_engine_cs *ring = req->ring;
2906         int ret;
2907
2908         if (!ring->gpu_caches_dirty)
2909                 return 0;
2910
2911         ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
2912         if (ret)
2913                 return ret;
2914
2915         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
2916
2917         ring->gpu_caches_dirty = false;
2918         return 0;
2919 }
2920
2921 int
2922 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
2923 {
2924         struct intel_engine_cs *ring = req->ring;
2925         uint32_t flush_domains;
2926         int ret;
2927
2928         flush_domains = 0;
2929         if (ring->gpu_caches_dirty)
2930                 flush_domains = I915_GEM_GPU_DOMAINS;
2931
2932         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
2933         if (ret)
2934                 return ret;
2935
2936         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
2937
2938         ring->gpu_caches_dirty = false;
2939         return 0;
2940 }
2941
2942 void
2943 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2944 {
2945         int ret;
2946
2947         if (!intel_ring_initialized(ring))
2948                 return;
2949
2950         ret = intel_ring_idle(ring);
2951         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2952                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2953                           ring->name, ret);
2954
2955         stop_ring(ring);
2956 }