1 #ifndef _INTEL_RINGBUFFER_H_
2 #define _INTEL_RINGBUFFER_H_
4 #include <linux/hashtable.h>
5 #include "i915_gem_batch_pool.h"
7 #define I915_CMD_HASH_ORDER 9
9 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
10 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
11 * to give some inclination as to some of the magic values used in the various
14 #define CACHELINE_BYTES 64
15 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
18 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
19 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
20 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
22 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
23 * cacheline, the Head Pointer must not be greater than the Tail
26 #define I915_RING_FREE_SPACE 64
28 struct intel_hw_status_page {
30 unsigned int gfx_addr;
31 struct drm_i915_gem_object *obj;
34 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
35 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
37 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
38 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
40 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
41 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
43 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
44 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
46 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
47 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
49 #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
50 #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
52 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
53 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
55 #define i915_semaphore_seqno_size sizeof(uint64_t)
56 #define GEN8_SIGNAL_OFFSET(__ring, to) \
57 (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
58 ((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
59 (i915_semaphore_seqno_size * (to)))
61 #define GEN8_WAIT_OFFSET(__ring, from) \
62 (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
63 ((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
64 (i915_semaphore_seqno_size * (__ring)->id))
66 #define GEN8_RING_SEMAPHORE_INIT do { \
67 if (!dev_priv->semaphore_obj) { \
70 ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \
71 ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \
72 ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \
73 ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \
74 ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \
75 ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \
78 enum intel_ring_hangcheck_action {
82 HANGCHECK_ACTIVE_LOOP,
87 #define HANGCHECK_SCORE_RING_HUNG 31
89 struct intel_ring_hangcheck {
94 enum intel_ring_hangcheck_action action;
98 struct intel_ringbuffer {
99 struct drm_i915_gem_object *obj;
100 void __iomem *virtual_start;
102 struct intel_engine_cs *ring;
111 bool reserved_in_use;
113 /** We track the position of the requests in the ring buffer, and
114 * when each is retired we increment last_retired_head as the GPU
115 * must have finished processing the request and so we know we
116 * can advance the ringbuffer up to that position.
118 * last_retired_head is set to -1 after the value is consumed so
119 * we can detect new retirements.
121 u32 last_retired_head;
124 struct intel_context;
125 struct drm_i915_reg_descriptor;
128 * we use a single page to load ctx workarounds so all of these
129 * values are referred in terms of dwords
131 * struct i915_wa_ctx_bb:
132 * offset: specifies batch starting position, also helpful in case
133 * if we want to have multiple batches at different offsets based on
134 * some criteria. It is not a requirement at the moment but provides
135 * an option for future use.
136 * size: size of the batch in DWORDS
138 struct i915_ctx_workarounds {
139 struct i915_wa_ctx_bb {
142 } indirect_ctx, per_ctx;
143 struct drm_i915_gem_object *obj;
146 struct intel_engine_cs {
155 #define I915_NUM_RINGS 5
156 #define LAST_USER_RING (VECS + 1)
158 struct drm_device *dev;
159 struct intel_ringbuffer *buffer;
162 * A pool of objects to use as shadow copies of client batch buffers
163 * when the command parser is enabled. Prevents the client from
164 * modifying the batch contents after software parsing.
166 struct i915_gem_batch_pool batch_pool;
168 struct intel_hw_status_page status_page;
169 struct i915_ctx_workarounds wa_ctx;
171 unsigned irq_refcount; /* protected by dev_priv->irq_lock */
172 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
173 struct drm_i915_gem_request *trace_irq_req;
174 bool __must_check (*irq_get)(struct intel_engine_cs *ring);
175 void (*irq_put)(struct intel_engine_cs *ring);
177 int (*init_hw)(struct intel_engine_cs *ring);
179 int (*init_context)(struct drm_i915_gem_request *req);
181 void (*write_tail)(struct intel_engine_cs *ring,
183 int __must_check (*flush)(struct drm_i915_gem_request *req,
184 u32 invalidate_domains,
186 int (*add_request)(struct drm_i915_gem_request *req);
187 /* Some chipsets are not quite as coherent as advertised and need
188 * an expensive kick to force a true read of the up-to-date seqno.
189 * However, the up-to-date seqno is not always required and the last
190 * seen value is good enough. Note that the seqno will always be
191 * monotonic, even if not coherent.
193 u32 (*get_seqno)(struct intel_engine_cs *ring,
194 bool lazy_coherency);
195 void (*set_seqno)(struct intel_engine_cs *ring,
197 int (*dispatch_execbuffer)(struct drm_i915_gem_request *req,
198 u64 offset, u32 length,
199 unsigned dispatch_flags);
200 #define I915_DISPATCH_SECURE 0x1
201 #define I915_DISPATCH_PINNED 0x2
202 void (*cleanup)(struct intel_engine_cs *ring);
204 /* GEN8 signal/wait table - never trust comments!
205 * signal to signal to signal to signal to signal to
206 * RCS VCS BCS VECS VCS2
207 * --------------------------------------------------------------------
208 * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
209 * |-------------------------------------------------------------------
210 * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
211 * |-------------------------------------------------------------------
212 * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
213 * |-------------------------------------------------------------------
214 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
215 * |-------------------------------------------------------------------
216 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
217 * |-------------------------------------------------------------------
220 * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
221 * ie. transpose of g(x, y)
223 * sync from sync from sync from sync from sync from
224 * RCS VCS BCS VECS VCS2
225 * --------------------------------------------------------------------
226 * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
227 * |-------------------------------------------------------------------
228 * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
229 * |-------------------------------------------------------------------
230 * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
231 * |-------------------------------------------------------------------
232 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
233 * |-------------------------------------------------------------------
234 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
235 * |-------------------------------------------------------------------
238 * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
239 * ie. transpose of f(x, y)
242 u32 sync_seqno[I915_NUM_RINGS-1];
246 /* our mbox written by others */
247 u32 wait[I915_NUM_RINGS];
248 /* mboxes this ring signals to */
249 u32 signal[I915_NUM_RINGS];
251 u64 signal_ggtt[I915_NUM_RINGS];
255 int (*sync_to)(struct drm_i915_gem_request *to_req,
256 struct intel_engine_cs *from,
258 int (*signal)(struct drm_i915_gem_request *signaller_req,
259 /* num_dwords needed by caller */
260 unsigned int num_dwords);
264 spinlock_t execlist_lock;
265 struct list_head execlist_queue;
266 struct list_head execlist_retired_req_list;
267 u8 next_context_status_buffer;
268 u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
269 int (*emit_request)(struct drm_i915_gem_request *request);
270 int (*emit_flush)(struct drm_i915_gem_request *request,
271 u32 invalidate_domains,
273 int (*emit_bb_start)(struct drm_i915_gem_request *req,
274 u64 offset, unsigned dispatch_flags);
277 * List of objects currently involved in rendering from the
280 * Includes buffers having the contents of their GPU caches
281 * flushed, not necessarily primitives. last_read_req
282 * represents when the rendering involved will be completed.
284 * A reference is held on the buffer while on this list.
286 struct list_head active_list;
289 * List of breadcrumbs associated with GPU requests currently
292 struct list_head request_list;
295 * Do we have some not yet emitted requests outstanding?
297 struct drm_i915_gem_request *outstanding_lazy_request;
298 bool gpu_caches_dirty;
300 wait_queue_head_t irq_queue;
302 struct intel_context *default_context;
303 struct intel_context *last_context;
305 struct intel_ring_hangcheck hangcheck;
308 struct drm_i915_gem_object *obj;
310 volatile u32 *cpu_page;
313 bool needs_cmd_parser;
316 * Table of commands the command parser needs to know about
319 DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
322 * Table of registers allowed in commands that read/write registers.
324 const struct drm_i915_reg_descriptor *reg_table;
328 * Table of registers allowed in commands that read/write registers, but
329 * only from the DRM master.
331 const struct drm_i915_reg_descriptor *master_reg_table;
332 int master_reg_count;
335 * Returns the bitmask for the length field of the specified command.
336 * Return 0 for an unrecognized/invalid command.
338 * If the command parser finds an entry for a command in the ring's
339 * cmd_tables, it gets the command's length based on the table entry.
340 * If not, it calls this function to determine the per-ring length field
341 * encoding for the command (i.e. certain opcode ranges use certain bits
342 * to encode the command length in the header).
344 u32 (*get_cmd_length_mask)(u32 cmd_header);
347 bool intel_ring_initialized(struct intel_engine_cs *ring);
349 static inline unsigned
350 intel_ring_flag(struct intel_engine_cs *ring)
352 return 1 << ring->id;
356 intel_ring_sync_index(struct intel_engine_cs *ring,
357 struct intel_engine_cs *other)
362 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
363 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
364 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
365 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
366 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
369 idx = (other - ring) - 1;
371 idx += I915_NUM_RINGS;
377 intel_read_status_page(struct intel_engine_cs *ring,
380 /* Ensure that the compiler doesn't optimize away the load. */
382 return ring->status_page.page_addr[reg];
386 intel_write_status_page(struct intel_engine_cs *ring,
389 ring->status_page.page_addr[reg] = value;
393 * Reads a dword out of the status page, which is written to from the command
394 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
397 * The following dwords have a reserved meaning:
398 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
399 * 0x04: ring 0 head pointer
400 * 0x05: ring 1 head pointer (915-class)
401 * 0x06: ring 2 head pointer (915-class)
402 * 0x10-0x1b: Context status DWords (GM45)
403 * 0x1f: Last written status offset. (GM45)
404 * 0x20-0x2f: Reserved (Gen6+)
406 * The area from dword 0x30 to 0x3ff is available for driver usage.
408 #define I915_GEM_HWS_INDEX 0x30
409 #define I915_GEM_HWS_SCRATCH_INDEX 0x40
410 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
412 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
413 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
414 struct intel_ringbuffer *ringbuf);
415 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
416 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
417 struct intel_ringbuffer *ringbuf);
419 void intel_stop_ring_buffer(struct intel_engine_cs *ring);
420 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);
422 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
424 int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n);
425 int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
426 static inline void intel_ring_emit(struct intel_engine_cs *ring,
429 struct intel_ringbuffer *ringbuf = ring->buffer;
430 iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
433 static inline void intel_ring_advance(struct intel_engine_cs *ring)
435 struct intel_ringbuffer *ringbuf = ring->buffer;
436 ringbuf->tail &= ringbuf->size - 1;
438 int __intel_ring_space(int head, int tail, int size);
439 void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
440 int intel_ring_space(struct intel_ringbuffer *ringbuf);
441 bool intel_ring_stopped(struct intel_engine_cs *ring);
443 int __must_check intel_ring_idle(struct intel_engine_cs *ring);
444 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
445 int intel_ring_flush_all_caches(struct drm_i915_gem_request *req);
446 int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req);
448 void intel_fini_pipe_control(struct intel_engine_cs *ring);
449 int intel_init_pipe_control(struct intel_engine_cs *ring);
451 int intel_init_render_ring_buffer(struct drm_device *dev);
452 int intel_init_bsd_ring_buffer(struct drm_device *dev);
453 int intel_init_bsd2_ring_buffer(struct drm_device *dev);
454 int intel_init_blt_ring_buffer(struct drm_device *dev);
455 int intel_init_vebox_ring_buffer(struct drm_device *dev);
457 u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
459 int init_workarounds_ring(struct intel_engine_cs *ring);
461 static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
463 return ringbuf->tail;
466 static inline struct drm_i915_gem_request *
467 intel_ring_get_request(struct intel_engine_cs *ring)
469 BUG_ON(ring->outstanding_lazy_request == NULL);
470 return ring->outstanding_lazy_request;
474 * Arbitrary size for largest possible 'add request' sequence. The code paths
475 * are complex and variable. Empirical measurement shows that the worst case
476 * is ILK at 136 words. Reserving too much is better than reserving too little
477 * as that allows for corner cases that might have been missed. So the figure
478 * has been rounded up to 160 words.
480 #define MIN_SPACE_FOR_ADD_REQUEST 160
483 * Reserve space in the ring to guarantee that the i915_add_request() call
484 * will always have sufficient room to do its stuff. The request creation
485 * code calls this automatically.
487 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size);
488 /* Cancel the reservation, e.g. because the request is being discarded. */
489 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf);
490 /* Use the reserved space - for use by i915_add_request() only. */
491 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf);
492 /* Finish with the reserved space - for use by i915_add_request() only. */
493 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf);
495 #endif /* _INTEL_RINGBUFFER_H_ */