drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define GEN9_ENABLE_DC5(dev) 0
  53 #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
  54
  55 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  56         for (i = 0;                                                     \
  57              i < (power_domains)->power_well_count &&                   \
  58                  ((power_well) = &(power_domains)->power_wells[i]);     \
  59              i++)                                                       \
  60                 if ((power_well)->domains & (domain_mask))
  61
  62 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  63         for (i = (power_domains)->power_well_count - 1;                  \
  64              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  65              i--)                                                        \
  66                 if ((power_well)->domains & (domain_mask))
  67
  68 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  69                                     int power_well_id);
  70
  71 /*
  72  * We should only use the power well if we explicitly asked the hardware to
  73  * enable it, so check if it's enabled and also check if we've requested it to
  74  * be enabled.
  75  */
  76 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
  77                                    struct i915_power_well *power_well)
  78 {
  79         return I915_READ(HSW_PWR_WELL_DRIVER) ==
  80                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
  81 }
  82
  83 /**
  84  * __intel_display_power_is_enabled - unlocked check for a power domain
  85  * @dev_priv: i915 device instance
  86  * @domain: power domain to check
  87  *
  88  * This is the unlocked version of intel_display_power_is_enabled() and should
  89  * only be used from error capture and recovery code where deadlocks are
  90  * possible.
  91  *
  92  * Returns:
  93  * True when the power domain is enabled, false otherwise.
  94  */
  95 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
  96                                       enum intel_display_power_domain domain)
  97 {
  98         struct i915_power_domains *power_domains;
  99         struct i915_power_well *power_well;
 100         bool is_enabled;
 101         int i;
 102
 103         if (dev_priv->pm.suspended)
 104                 return false;
 105
 106         power_domains = &dev_priv->power_domains;
 107
 108         is_enabled = true;
 109
 110         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 111                 if (power_well->always_on)
 112                         continue;
 113
 114                 if (!power_well->hw_enabled) {
 115                         is_enabled = false;
 116                         break;
 117                 }
 118         }
 119
 120         return is_enabled;
 121 }
 122
 123 /**
 124  * intel_display_power_is_enabled - check for a power domain
 125  * @dev_priv: i915 device instance
 126  * @domain: power domain to check
 127  *
 128  * This function can be used to check the hw power domain state. It is mostly
 129  * used in hardware state readout functions. Everywhere else code should rely
 130  * upon explicit power domain reference counting to ensure that the hardware
 131  * block is powered up before accessing it.
 132  *
 133  * Callers must hold the relevant modesetting locks to ensure that concurrent
 134  * threads can't disable the power well while the caller tries to read a few
 135  * registers.
 136  *
 137  * Returns:
 138  * True when the power domain is enabled, false otherwise.
 139  */
 140 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 141                                     enum intel_display_power_domain domain)
 142 {
 143         struct i915_power_domains *power_domains;
 144         bool ret;
 145
 146         power_domains = &dev_priv->power_domains;
 147
 148         mutex_lock(&power_domains->lock);
 149         ret = __intel_display_power_is_enabled(dev_priv, domain);
 150         mutex_unlock(&power_domains->lock);
 151
 152         return ret;
 153 }
 154
 155 /**
 156  * intel_display_set_init_power - set the initial power domain state
 157  * @dev_priv: i915 device instance
 158  * @enable: whether to enable or disable the initial power domain state
 159  *
 160  * For simplicity our driver load/unload and system suspend/resume code assumes
 161  * that all power domains are always enabled. This functions controls the state
 162  * of this little hack. While the initial power domain state is enabled runtime
 163  * pm is effectively disabled.
 164  */
 165 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 166                                   bool enable)
 167 {
 168         if (dev_priv->power_domains.init_power_on == enable)
 169                 return;
 170
 171         if (enable)
 172                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 173         else
 174                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 175
 176         dev_priv->power_domains.init_power_on = enable;
 177 }
 178
 179 /*
 180  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 181  * when not needed anymore. We have 4 registers that can request the power well
 182  * to be enabled, and it will only be disabled if none of the registers is
 183  * requesting it to be enabled.
 184  */
 185 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 186 {
 187         struct drm_device *dev = dev_priv->dev;
 188
 189         /*
 190          * After we re-enable the power well, if we touch VGA register 0x3d5
 191          * we'll get unclaimed register interrupts. This stops after we write
 192          * anything to the VGA MSR register. The vgacon module uses this
 193          * register all the time, so if we unbind our driver and, as a
 194          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 195          * console_unlock(). So make here we touch the VGA MSR register, making
 196          * sure vgacon can keep working normally without triggering interrupts
 197          * and error messages.
 198          */
 199         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 200         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 201         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 202
 203         if (IS_BROADWELL(dev))
 204                 gen8_irq_power_well_post_enable(dev_priv,
 205                                                 1 << PIPE_C | 1 << PIPE_B);
 206 }
 207
 208 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 209                                        struct i915_power_well *power_well)
 210 {
 211         struct drm_device *dev = dev_priv->dev;
 212
 213         /*
 214          * After we re-enable the power well, if we touch VGA register 0x3d5
 215          * we'll get unclaimed register interrupts. This stops after we write
 216          * anything to the VGA MSR register. The vgacon module uses this
 217          * register all the time, so if we unbind our driver and, as a
 218          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 219          * console_unlock(). So make here we touch the VGA MSR register, making
 220          * sure vgacon can keep working normally without triggering interrupts
 221          * and error messages.
 222          */
 223         if (power_well->data == SKL_DISP_PW_2) {
 224                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 225                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 226                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 227
 228                 gen8_irq_power_well_post_enable(dev_priv,
 229                                                 1 << PIPE_C | 1 << PIPE_B);
 230         }
 231
 232         if (power_well->data == SKL_DISP_PW_1) {
 233                 intel_prepare_ddi(dev);
 234                 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
 235         }
 236 }
 237
 238 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 239                                struct i915_power_well *power_well, bool enable)
 240 {
 241         bool is_enabled, enable_requested;
 242         uint32_t tmp;
 243
 244         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 245         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 246         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 247
 248         if (enable) {
 249                 if (!enable_requested)
 250                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 251                                    HSW_PWR_WELL_ENABLE_REQUEST);
 252
 253                 if (!is_enabled) {
 254                         DRM_DEBUG_KMS("Enabling power well\n");
 255                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 256                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 257                                 DRM_ERROR("Timeout enabling power well\n");
 258                         hsw_power_well_post_enable(dev_priv);
 259                 }
 260
 261         } else {
 262                 if (enable_requested) {
 263                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 264                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 265                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 266                 }
 267         }
 268 }
 269
 270 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 271         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 272         BIT(POWER_DOMAIN_PIPE_B) |                      \
 273         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 274         BIT(POWER_DOMAIN_PIPE_C) |                      \
 275         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 276         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 277         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 278         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 279         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 280         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 281         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 282         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
 283         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
 284         BIT(POWER_DOMAIN_AUX_B) |                       \
 285         BIT(POWER_DOMAIN_AUX_C) |                       \
 286         BIT(POWER_DOMAIN_AUX_D) |                       \
 287         BIT(POWER_DOMAIN_AUDIO) |                       \
 288         BIT(POWER_DOMAIN_VGA) |                         \
 289         BIT(POWER_DOMAIN_INIT))
 290 #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 291         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 292         BIT(POWER_DOMAIN_PLLS) |                        \
 293         BIT(POWER_DOMAIN_PIPE_A) |                      \
 294         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 295         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 296         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 297         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 298         BIT(POWER_DOMAIN_AUX_A) |                       \
 299         BIT(POWER_DOMAIN_INIT))
 300 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 301         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 302         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 303         BIT(POWER_DOMAIN_INIT))
 304 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 305         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 306         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 307         BIT(POWER_DOMAIN_INIT))
 308 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 309         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 310         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 311         BIT(POWER_DOMAIN_INIT))
 312 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 313         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
 314         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
 315         BIT(POWER_DOMAIN_INIT))
 316 #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS (             \
 317         SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS)
 318 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 319         (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 320         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 321         SKL_DISPLAY_DDI_A_E_POWER_DOMAINS |             \
 322         SKL_DISPLAY_DDI_B_POWER_DOMAINS |               \
 323         SKL_DISPLAY_DDI_C_POWER_DOMAINS |               \
 324         SKL_DISPLAY_DDI_D_POWER_DOMAINS |               \
 325         SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) |           \
 326         BIT(POWER_DOMAIN_INIT))
 327
 328 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 329         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 330         BIT(POWER_DOMAIN_PIPE_B) |                      \
 331         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 332         BIT(POWER_DOMAIN_PIPE_C) |                      \
 333         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 334         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 335         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 336         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 337         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 338         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 339         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 340         BIT(POWER_DOMAIN_AUX_B) |                       \
 341         BIT(POWER_DOMAIN_AUX_C) |                       \
 342         BIT(POWER_DOMAIN_AUDIO) |                       \
 343         BIT(POWER_DOMAIN_VGA) |                         \
 344         BIT(POWER_DOMAIN_INIT))
 345 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 346         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 347         BIT(POWER_DOMAIN_PIPE_A) |                      \
 348         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 349         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 350         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 351         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 352         BIT(POWER_DOMAIN_AUX_A) |                       \
 353         BIT(POWER_DOMAIN_PLLS) |                        \
 354         BIT(POWER_DOMAIN_INIT))
 355 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 356         (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 357         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |       \
 358         BIT(POWER_DOMAIN_INIT))
 359
 360 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 361 {
 362         struct drm_device *dev = dev_priv->dev;
 363
 364         WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
 365         WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 366                 "DC9 already programmed to be enabled.\n");
 367         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 368                 "DC5 still not disabled to enable DC9.\n");
 369         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 370         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 371
 372          /*
 373           * TODO: check for the following to verify the conditions to enter DC9
 374           * state are satisfied:
 375           * 1] Check relevant display engine registers to verify if mode set
 376           * disable sequence was followed.
 377           * 2] Check if display uninitialize sequence is initialized.
 378           */
 379 }
 380
 381 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 382 {
 383         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 384         WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 385                 "DC9 already programmed to be disabled.\n");
 386         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 387                 "DC5 still not disabled.\n");
 388
 389          /*
 390           * TODO: check for the following to verify DC9 state was indeed
 391           * entered before programming to disable it:
 392           * 1] Check relevant display engine registers to verify if mode
 393           *  set disable sequence was followed.
 394           * 2] Check if display uninitialize sequence is initialized.
 395           */
 396 }
 397
 398 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 399 {
 400         uint32_t val;
 401
 402         assert_can_enable_dc9(dev_priv);
 403
 404         DRM_DEBUG_KMS("Enabling DC9\n");
 405
 406         val = I915_READ(DC_STATE_EN);
 407         val |= DC_STATE_EN_DC9;
 408         I915_WRITE(DC_STATE_EN, val);
 409         POSTING_READ(DC_STATE_EN);
 410 }
 411
 412 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 413 {
 414         uint32_t val;
 415
 416         assert_can_disable_dc9(dev_priv);
 417
 418         DRM_DEBUG_KMS("Disabling DC9\n");
 419
 420         val = I915_READ(DC_STATE_EN);
 421         val &= ~DC_STATE_EN_DC9;
 422         I915_WRITE(DC_STATE_EN, val);
 423         POSTING_READ(DC_STATE_EN);
 424 }
 425
 426 static void gen9_set_dc_state_debugmask_memory_up(
 427                         struct drm_i915_private *dev_priv)
 428 {
 429         uint32_t val;
 430
 431         /* The below bit doesn't need to be cleared ever afterwards */
 432         val = I915_READ(DC_STATE_DEBUG);
 433         if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
 434                 val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
 435                 I915_WRITE(DC_STATE_DEBUG, val);
 436                 POSTING_READ(DC_STATE_DEBUG);
 437         }
 438 }
 439
 440 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 441 {
 442         struct drm_device *dev = dev_priv->dev;
 443         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 444                                         SKL_DISP_PW_2);
 445
 446         WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
 447         WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 448         WARN(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 449
 450         WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 451                                 "DC5 already programmed to be enabled.\n");
 452         WARN(dev_priv->pm.suspended,
 453                 "DC5 cannot be enabled, if platform is runtime-suspended.\n");
 454
 455         assert_csr_loaded(dev_priv);
 456 }
 457
 458 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
 459 {
 460         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 461                                         SKL_DISP_PW_2);
 462         /*
 463          * During initialization, the firmware may not be loaded yet.
 464          * We still want to make sure that the DC enabling flag is cleared.
 465          */
 466         if (dev_priv->power_domains.initializing)
 467                 return;
 468
 469         WARN(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
 470         WARN(dev_priv->pm.suspended,
 471                 "Disabling of DC5 while platform is runtime-suspended should never happen.\n");
 472 }
 473
 474 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 475 {
 476         uint32_t val;
 477
 478         assert_can_enable_dc5(dev_priv);
 479
 480         DRM_DEBUG_KMS("Enabling DC5\n");
 481
 482         gen9_set_dc_state_debugmask_memory_up(dev_priv);
 483
 484         val = I915_READ(DC_STATE_EN);
 485         val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
 486         val |= DC_STATE_EN_UPTO_DC5;
 487         I915_WRITE(DC_STATE_EN, val);
 488         POSTING_READ(DC_STATE_EN);
 489 }
 490
 491 static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
 492 {
 493         uint32_t val;
 494
 495         assert_can_disable_dc5(dev_priv);
 496
 497         DRM_DEBUG_KMS("Disabling DC5\n");
 498
 499         val = I915_READ(DC_STATE_EN);
 500         val &= ~DC_STATE_EN_UPTO_DC5;
 501         I915_WRITE(DC_STATE_EN, val);
 502         POSTING_READ(DC_STATE_EN);
 503 }
 504
 505 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 506 {
 507         struct drm_device *dev = dev_priv->dev;
 508
 509         WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n");
 510         WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 511         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 512                 "Backlight is not disabled.\n");
 513         WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 514                 "DC6 already programmed to be enabled.\n");
 515
 516         assert_csr_loaded(dev_priv);
 517 }
 518
 519 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
 520 {
 521         /*
 522          * During initialization, the firmware may not be loaded yet.
 523          * We still want to make sure that the DC enabling flag is cleared.
 524          */
 525         if (dev_priv->power_domains.initializing)
 526                 return;
 527
 528         assert_csr_loaded(dev_priv);
 529         WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 530                 "DC6 already programmed to be disabled.\n");
 531 }
 532
 533 static void skl_enable_dc6(struct drm_i915_private *dev_priv)
 534 {
 535         uint32_t val;
 536
 537         assert_can_enable_dc6(dev_priv);
 538
 539         DRM_DEBUG_KMS("Enabling DC6\n");
 540
 541         gen9_set_dc_state_debugmask_memory_up(dev_priv);
 542
 543         val = I915_READ(DC_STATE_EN);
 544         val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
 545         val |= DC_STATE_EN_UPTO_DC6;
 546         I915_WRITE(DC_STATE_EN, val);
 547         POSTING_READ(DC_STATE_EN);
 548 }
 549
 550 static void skl_disable_dc6(struct drm_i915_private *dev_priv)
 551 {
 552         uint32_t val;
 553
 554         assert_can_disable_dc6(dev_priv);
 555
 556         DRM_DEBUG_KMS("Disabling DC6\n");
 557
 558         val = I915_READ(DC_STATE_EN);
 559         val &= ~DC_STATE_EN_UPTO_DC6;
 560         I915_WRITE(DC_STATE_EN, val);
 561         POSTING_READ(DC_STATE_EN);
 562 }
 563
 564 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 565                         struct i915_power_well *power_well, bool enable)
 566 {
 567         struct drm_device *dev = dev_priv->dev;
 568         uint32_t tmp, fuse_status;
 569         uint32_t req_mask, state_mask;
 570         bool is_enabled, enable_requested, check_fuse_status = false;
 571
 572         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 573         fuse_status = I915_READ(SKL_FUSE_STATUS);
 574
 575         switch (power_well->data) {
 576         case SKL_DISP_PW_1:
 577                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 578                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 579                         DRM_ERROR("PG0 not enabled\n");
 580                         return;
 581                 }
 582                 break;
 583         case SKL_DISP_PW_2:
 584                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 585                         DRM_ERROR("PG1 in disabled state\n");
 586                         return;
 587                 }
 588                 break;
 589         case SKL_DISP_PW_DDI_A_E:
 590         case SKL_DISP_PW_DDI_B:
 591         case SKL_DISP_PW_DDI_C:
 592         case SKL_DISP_PW_DDI_D:
 593         case SKL_DISP_PW_MISC_IO:
 594                 break;
 595         default:
 596                 WARN(1, "Unknown power well %lu\n", power_well->data);
 597                 return;
 598         }
 599
 600         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 601         enable_requested = tmp & req_mask;
 602         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 603         is_enabled = tmp & state_mask;
 604
 605         if (enable) {
 606                 if (!enable_requested) {
 607                         WARN((tmp & state_mask) &&
 608                                 !I915_READ(HSW_PWR_WELL_BIOS),
 609                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 610                                 when request is to disable!\n");
 611                         if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
 612                                 power_well->data == SKL_DISP_PW_2) {
 613                                 if (SKL_ENABLE_DC6(dev)) {
 614                                         skl_disable_dc6(dev_priv);
 615                                         /*
 616                                          * DDI buffer programming unnecessary during driver-load/resume
 617                                          * as it's already done during modeset initialization then.
 618                                          * It's also invalid here as encoder list is still uninitialized.
 619                                          */
 620                                         if (!dev_priv->power_domains.initializing)
 621                                                 intel_prepare_ddi(dev);
 622                                 } else {
 623                                         gen9_disable_dc5(dev_priv);
 624                                 }
 625                         }
 626                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 627                 }
 628
 629                 if (!is_enabled) {
 630                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 631                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 632                                 state_mask), 1))
 633                                 DRM_ERROR("%s enable timeout\n",
 634                                         power_well->name);
 635                         check_fuse_status = true;
 636                 }
 637         } else {
 638                 if (enable_requested) {
 639                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 640                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 641                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 642
 643                         if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
 644                                 power_well->data == SKL_DISP_PW_2) {
 645                                 enum csr_state state;
 646                                 /* TODO: wait for a completion event or
 647                                  * similar here instead of busy
 648                                  * waiting using wait_for function.
 649                                  */
 650                                 wait_for((state = intel_csr_load_status_get(dev_priv)) !=
 651                                                 FW_UNINITIALIZED, 1000);
 652                                 if (state != FW_LOADED)
 653                                         DRM_ERROR("CSR firmware not ready (%d)\n",
 654                                                         state);
 655                                 else
 656                                         if (SKL_ENABLE_DC6(dev))
 657                                                 skl_enable_dc6(dev_priv);
 658                                         else
 659                                                 gen9_enable_dc5(dev_priv);
 660                         }
 661                 }
 662         }
 663
 664         if (check_fuse_status) {
 665                 if (power_well->data == SKL_DISP_PW_1) {
 666                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 667                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 668                                 DRM_ERROR("PG1 distributing status timeout\n");
 669                 } else if (power_well->data == SKL_DISP_PW_2) {
 670                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 671                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 672                                 DRM_ERROR("PG2 distributing status timeout\n");
 673                 }
 674         }
 675
 676         if (enable && !is_enabled)
 677                 skl_power_well_post_enable(dev_priv, power_well);
 678 }
 679
 680 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 681                                    struct i915_power_well *power_well)
 682 {
 683         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 684
 685         /*
 686          * We're taking over the BIOS, so clear any requests made by it since
 687          * the driver is in charge now.
 688          */
 689         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 690                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 691 }
 692
 693 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 694                                   struct i915_power_well *power_well)
 695 {
 696         hsw_set_power_well(dev_priv, power_well, true);
 697 }
 698
 699 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 700                                    struct i915_power_well *power_well)
 701 {
 702         hsw_set_power_well(dev_priv, power_well, false);
 703 }
 704
 705 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 706                                         struct i915_power_well *power_well)
 707 {
 708         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 709                 SKL_POWER_WELL_STATE(power_well->data);
 710
 711         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 712 }
 713
 714 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 715                                 struct i915_power_well *power_well)
 716 {
 717         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 718
 719         /* Clear any request made by BIOS as driver is taking over */
 720         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 721 }
 722
 723 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 724                                 struct i915_power_well *power_well)
 725 {
 726         skl_set_power_well(dev_priv, power_well, true);
 727 }
 728
 729 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 730                                 struct i915_power_well *power_well)
 731 {
 732         skl_set_power_well(dev_priv, power_well, false);
 733 }
 734
 735 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 736                                            struct i915_power_well *power_well)
 737 {
 738 }
 739
 740 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 741                                              struct i915_power_well *power_well)
 742 {
 743         return true;
 744 }
 745
 746 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 747                                struct i915_power_well *power_well, bool enable)
 748 {
 749         enum punit_power_well power_well_id = power_well->data;
 750         u32 mask;
 751         u32 state;
 752         u32 ctrl;
 753
 754         mask = PUNIT_PWRGT_MASK(power_well_id);
 755         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 756                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 757
 758         mutex_lock(&dev_priv->rps.hw_lock);
 759
 760 #define COND \
 761         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 762
 763         if (COND)
 764                 goto out;
 765
 766         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 767         ctrl &= ~mask;
 768         ctrl |= state;
 769         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 770
 771         if (wait_for(COND, 100))
 772                 DRM_ERROR("timout setting power well state %08x (%08x)\n",
 773                           state,
 774                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 775
 776 #undef COND
 777
 778 out:
 779         mutex_unlock(&dev_priv->rps.hw_lock);
 780 }
 781
 782 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 783                                    struct i915_power_well *power_well)
 784 {
 785         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 786 }
 787
 788 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 789                                   struct i915_power_well *power_well)
 790 {
 791         vlv_set_power_well(dev_priv, power_well, true);
 792 }
 793
 794 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 795                                    struct i915_power_well *power_well)
 796 {
 797         vlv_set_power_well(dev_priv, power_well, false);
 798 }
 799
 800 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 801                                    struct i915_power_well *power_well)
 802 {
 803         int power_well_id = power_well->data;
 804         bool enabled = false;
 805         u32 mask;
 806         u32 state;
 807         u32 ctrl;
 808
 809         mask = PUNIT_PWRGT_MASK(power_well_id);
 810         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 811
 812         mutex_lock(&dev_priv->rps.hw_lock);
 813
 814         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 815         /*
 816          * We only ever set the power-on and power-gate states, anything
 817          * else is unexpected.
 818          */
 819         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 820                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 821         if (state == ctrl)
 822                 enabled = true;
 823
 824         /*
 825          * A transient state at this point would mean some unexpected party
 826          * is poking at the power controls too.
 827          */
 828         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 829         WARN_ON(ctrl != state);
 830
 831         mutex_unlock(&dev_priv->rps.hw_lock);
 832
 833         return enabled;
 834 }
 835
 836 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
 837                                           struct i915_power_well *power_well)
 838 {
 839         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 840
 841         vlv_set_power_well(dev_priv, power_well, true);
 842
 843         spin_lock_irq(&dev_priv->irq_lock);
 844         valleyview_enable_display_irqs(dev_priv);
 845         spin_unlock_irq(&dev_priv->irq_lock);
 846
 847         /*
 848          * During driver initialization/resume we can avoid restoring the
 849          * part of the HW/SW state that will be inited anyway explicitly.
 850          */
 851         if (dev_priv->power_domains.initializing)
 852                 return;
 853
 854         intel_hpd_init(dev_priv);
 855
 856         i915_redisable_vga_power_on(dev_priv->dev);
 857 }
 858
 859 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
 860                                            struct i915_power_well *power_well)
 861 {
 862         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 863
 864         spin_lock_irq(&dev_priv->irq_lock);
 865         valleyview_disable_display_irqs(dev_priv);
 866         spin_unlock_irq(&dev_priv->irq_lock);
 867
 868         vlv_set_power_well(dev_priv, power_well, false);
 869
 870         vlv_power_sequencer_reset(dev_priv);
 871 }
 872
 873 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 874                                            struct i915_power_well *power_well)
 875 {
 876         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 877
 878         /*
 879          * Enable the CRI clock source so we can get at the
 880          * display and the reference clock for VGA
 881          * hotplug / manual detection.
 882          */
 883         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
 884                    DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
 885         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 886
 887         vlv_set_power_well(dev_priv, power_well, true);
 888
 889         /*
 890          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
 891          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
 892          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
 893          *   b. The other bits such as sfr settings / modesel may all
 894          *      be set to 0.
 895          *
 896          * This should only be done on init and resume from S3 with
 897          * both PLLs disabled, or we risk losing DPIO and PLL
 898          * synchronization.
 899          */
 900         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
 901 }
 902
 903 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 904                                             struct i915_power_well *power_well)
 905 {
 906         enum pipe pipe;
 907
 908         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 909
 910         for_each_pipe(dev_priv, pipe)
 911                 assert_pll_disabled(dev_priv, pipe);
 912
 913         /* Assert common reset */
 914         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
 915
 916         vlv_set_power_well(dev_priv, power_well, false);
 917 }
 918
 919 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 920                                            struct i915_power_well *power_well)
 921 {
 922         enum dpio_phy phy;
 923
 924         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
 925                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
 926
 927         /*
 928          * Enable the CRI clock source so we can get at the
 929          * display and the reference clock for VGA
 930          * hotplug / manual detection.
 931          */
 932         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
 933                 phy = DPIO_PHY0;
 934                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
 935                            DPLL_REFA_CLK_ENABLE_VLV);
 936                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
 937                            DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
 938         } else {
 939                 phy = DPIO_PHY1;
 940                 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
 941                            DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
 942         }
 943         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 944         vlv_set_power_well(dev_priv, power_well, true);
 945
 946         /* Poll for phypwrgood signal */
 947         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
 948                 DRM_ERROR("Display PHY %d is not power up\n", phy);
 949
 950         I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
 951                    PHY_COM_LANE_RESET_DEASSERT(phy));
 952 }
 953
 954 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 955                                             struct i915_power_well *power_well)
 956 {
 957         enum dpio_phy phy;
 958
 959         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
 960                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
 961
 962         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
 963                 phy = DPIO_PHY0;
 964                 assert_pll_disabled(dev_priv, PIPE_A);
 965                 assert_pll_disabled(dev_priv, PIPE_B);
 966         } else {
 967                 phy = DPIO_PHY1;
 968                 assert_pll_disabled(dev_priv, PIPE_C);
 969         }
 970
 971         I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
 972                    ~PHY_COM_LANE_RESET_DEASSERT(phy));
 973
 974         vlv_set_power_well(dev_priv, power_well, false);
 975 }
 976
 977 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
 978                                         struct i915_power_well *power_well)
 979 {
 980         enum pipe pipe = power_well->data;
 981         bool enabled;
 982         u32 state, ctrl;
 983
 984         mutex_lock(&dev_priv->rps.hw_lock);
 985
 986         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
 987         /*
 988          * We only ever set the power-on and power-gate states, anything
 989          * else is unexpected.
 990          */
 991         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
 992         enabled = state == DP_SSS_PWR_ON(pipe);
 993
 994         /*
 995          * A transient state at this point would mean some unexpected party
 996          * is poking at the power controls too.
 997          */
 998         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
 999         WARN_ON(ctrl << 16 != state);
1000
1001         mutex_unlock(&dev_priv->rps.hw_lock);
1002
1003         return enabled;
1004 }
1005
1006 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1007                                     struct i915_power_well *power_well,
1008                                     bool enable)
1009 {
1010         enum pipe pipe = power_well->data;
1011         u32 state;
1012         u32 ctrl;
1013
1014         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1015
1016         mutex_lock(&dev_priv->rps.hw_lock);
1017
1018 #define COND \
1019         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1020
1021         if (COND)
1022                 goto out;
1023
1024         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1025         ctrl &= ~DP_SSC_MASK(pipe);
1026         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1027         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1028
1029         if (wait_for(COND, 100))
1030                 DRM_ERROR("timout setting power well state %08x (%08x)\n",
1031                           state,
1032                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1033
1034 #undef COND
1035
1036 out:
1037         mutex_unlock(&dev_priv->rps.hw_lock);
1038 }
1039
1040 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1041                                         struct i915_power_well *power_well)
1042 {
1043         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1044 }
1045
1046 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1047                                        struct i915_power_well *power_well)
1048 {
1049         WARN_ON_ONCE(power_well->data != PIPE_A &&
1050                      power_well->data != PIPE_B &&
1051                      power_well->data != PIPE_C);
1052
1053         chv_set_pipe_power_well(dev_priv, power_well, true);
1054
1055         if (power_well->data == PIPE_A) {
1056                 spin_lock_irq(&dev_priv->irq_lock);
1057                 valleyview_enable_display_irqs(dev_priv);
1058                 spin_unlock_irq(&dev_priv->irq_lock);
1059
1060                 /*
1061                  * During driver initialization/resume we can avoid restoring the
1062                  * part of the HW/SW state that will be inited anyway explicitly.
1063                  */
1064                 if (dev_priv->power_domains.initializing)
1065                         return;
1066
1067                 intel_hpd_init(dev_priv);
1068
1069                 i915_redisable_vga_power_on(dev_priv->dev);
1070         }
1071 }
1072
1073 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1074                                         struct i915_power_well *power_well)
1075 {
1076         WARN_ON_ONCE(power_well->data != PIPE_A &&
1077                      power_well->data != PIPE_B &&
1078                      power_well->data != PIPE_C);
1079
1080         if (power_well->data == PIPE_A) {
1081                 spin_lock_irq(&dev_priv->irq_lock);
1082                 valleyview_disable_display_irqs(dev_priv);
1083                 spin_unlock_irq(&dev_priv->irq_lock);
1084         }
1085
1086         chv_set_pipe_power_well(dev_priv, power_well, false);
1087
1088         if (power_well->data == PIPE_A)
1089                 vlv_power_sequencer_reset(dev_priv);
1090 }
1091
1092 /**
1093  * intel_display_power_get - grab a power domain reference
1094  * @dev_priv: i915 device instance
1095  * @domain: power domain to reference
1096  *
1097  * This function grabs a power domain reference for @domain and ensures that the
1098  * power domain and all its parents are powered up. Therefore users should only
1099  * grab a reference to the innermost power domain they need.
1100  *
1101  * Any power domain reference obtained by this function must have a symmetric
1102  * call to intel_display_power_put() to release the reference again.
1103  */
1104 void intel_display_power_get(struct drm_i915_private *dev_priv,
1105                              enum intel_display_power_domain domain)
1106 {
1107         struct i915_power_domains *power_domains;
1108         struct i915_power_well *power_well;
1109         int i;
1110
1111         intel_runtime_pm_get(dev_priv);
1112
1113         power_domains = &dev_priv->power_domains;
1114
1115         mutex_lock(&power_domains->lock);
1116
1117         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1118                 if (!power_well->count++) {
1119                         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
1120                         power_well->ops->enable(dev_priv, power_well);
1121                         power_well->hw_enabled = true;
1122                 }
1123         }
1124
1125         power_domains->domain_use_count[domain]++;
1126
1127         mutex_unlock(&power_domains->lock);
1128 }
1129
1130 /**
1131  * intel_display_power_put - release a power domain reference
1132  * @dev_priv: i915 device instance
1133  * @domain: power domain to reference
1134  *
1135  * This function drops the power domain reference obtained by
1136  * intel_display_power_get() and might power down the corresponding hardware
1137  * block right away if this is the last reference.
1138  */
1139 void intel_display_power_put(struct drm_i915_private *dev_priv,
1140                              enum intel_display_power_domain domain)
1141 {
1142         struct i915_power_domains *power_domains;
1143         struct i915_power_well *power_well;
1144         int i;
1145
1146         power_domains = &dev_priv->power_domains;
1147
1148         mutex_lock(&power_domains->lock);
1149
1150         WARN_ON(!power_domains->domain_use_count[domain]);
1151         power_domains->domain_use_count[domain]--;
1152
1153         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1154                 WARN_ON(!power_well->count);
1155
1156                 if (!--power_well->count && i915.disable_power_well) {
1157                         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
1158                         power_well->hw_enabled = false;
1159                         power_well->ops->disable(dev_priv, power_well);
1160                 }
1161         }
1162
1163         mutex_unlock(&power_domains->lock);
1164
1165         intel_runtime_pm_put(dev_priv);
1166 }
1167
1168 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1169
1170 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
1171         BIT(POWER_DOMAIN_PIPE_A) |                      \
1172         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
1173         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
1174         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
1175         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
1176         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
1177         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
1178         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
1179         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
1180         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
1181         BIT(POWER_DOMAIN_PORT_CRT) |                    \
1182         BIT(POWER_DOMAIN_PLLS) |                        \
1183         BIT(POWER_DOMAIN_AUX_A) |                       \
1184         BIT(POWER_DOMAIN_AUX_B) |                       \
1185         BIT(POWER_DOMAIN_AUX_C) |                       \
1186         BIT(POWER_DOMAIN_AUX_D) |                       \
1187         BIT(POWER_DOMAIN_INIT))
1188 #define HSW_DISPLAY_POWER_DOMAINS (                             \
1189         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
1190         BIT(POWER_DOMAIN_INIT))
1191
1192 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
1193         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
1194         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1195 #define BDW_DISPLAY_POWER_DOMAINS (                             \
1196         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
1197         BIT(POWER_DOMAIN_INIT))
1198
1199 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
1200 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
1201
1202 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1203         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1204         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1205         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1206         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1207         BIT(POWER_DOMAIN_PORT_CRT) |            \
1208         BIT(POWER_DOMAIN_AUX_B) |               \
1209         BIT(POWER_DOMAIN_AUX_C) |               \
1210         BIT(POWER_DOMAIN_INIT))
1211
1212 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1213         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1214         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1215         BIT(POWER_DOMAIN_AUX_B) |               \
1216         BIT(POWER_DOMAIN_INIT))
1217
1218 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1219         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1220         BIT(POWER_DOMAIN_AUX_B) |               \
1221         BIT(POWER_DOMAIN_INIT))
1222
1223 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1224         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1225         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1226         BIT(POWER_DOMAIN_AUX_C) |               \
1227         BIT(POWER_DOMAIN_INIT))
1228
1229 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1230         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1231         BIT(POWER_DOMAIN_AUX_C) |               \
1232         BIT(POWER_DOMAIN_INIT))
1233
1234 #define CHV_PIPE_A_POWER_DOMAINS (      \
1235         BIT(POWER_DOMAIN_PIPE_A) |      \
1236         BIT(POWER_DOMAIN_INIT))
1237
1238 #define CHV_PIPE_B_POWER_DOMAINS (      \
1239         BIT(POWER_DOMAIN_PIPE_B) |      \
1240         BIT(POWER_DOMAIN_INIT))
1241
1242 #define CHV_PIPE_C_POWER_DOMAINS (      \
1243         BIT(POWER_DOMAIN_PIPE_C) |      \
1244         BIT(POWER_DOMAIN_INIT))
1245
1246 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1247         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1248         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1249         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1250         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1251         BIT(POWER_DOMAIN_AUX_B) |               \
1252         BIT(POWER_DOMAIN_AUX_C) |               \
1253         BIT(POWER_DOMAIN_INIT))
1254
1255 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1256         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |  \
1257         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |  \
1258         BIT(POWER_DOMAIN_AUX_D) |               \
1259         BIT(POWER_DOMAIN_INIT))
1260
1261 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS (  \
1262         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |  \
1263         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |  \
1264         BIT(POWER_DOMAIN_AUX_D) |               \
1265         BIT(POWER_DOMAIN_INIT))
1266
1267 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS (  \
1268         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |  \
1269         BIT(POWER_DOMAIN_AUX_D) |               \
1270         BIT(POWER_DOMAIN_INIT))
1271
1272 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1273         .sync_hw = i9xx_always_on_power_well_noop,
1274         .enable = i9xx_always_on_power_well_noop,
1275         .disable = i9xx_always_on_power_well_noop,
1276         .is_enabled = i9xx_always_on_power_well_enabled,
1277 };
1278
1279 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1280         .sync_hw = chv_pipe_power_well_sync_hw,
1281         .enable = chv_pipe_power_well_enable,
1282         .disable = chv_pipe_power_well_disable,
1283         .is_enabled = chv_pipe_power_well_enabled,
1284 };
1285
1286 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1287         .sync_hw = vlv_power_well_sync_hw,
1288         .enable = chv_dpio_cmn_power_well_enable,
1289         .disable = chv_dpio_cmn_power_well_disable,
1290         .is_enabled = vlv_power_well_enabled,
1291 };
1292
1293 static struct i915_power_well i9xx_always_on_power_well[] = {
1294         {
1295                 .name = "always-on",
1296                 .always_on = 1,
1297                 .domains = POWER_DOMAIN_MASK,
1298                 .ops = &i9xx_always_on_power_well_ops,
1299         },
1300 };
1301
1302 static const struct i915_power_well_ops hsw_power_well_ops = {
1303         .sync_hw = hsw_power_well_sync_hw,
1304         .enable = hsw_power_well_enable,
1305         .disable = hsw_power_well_disable,
1306         .is_enabled = hsw_power_well_enabled,
1307 };
1308
1309 static const struct i915_power_well_ops skl_power_well_ops = {
1310         .sync_hw = skl_power_well_sync_hw,
1311         .enable = skl_power_well_enable,
1312         .disable = skl_power_well_disable,
1313         .is_enabled = skl_power_well_enabled,
1314 };
1315
1316 static struct i915_power_well hsw_power_wells[] = {
1317         {
1318                 .name = "always-on",
1319                 .always_on = 1,
1320                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1321                 .ops = &i9xx_always_on_power_well_ops,
1322         },
1323         {
1324                 .name = "display",
1325                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1326                 .ops = &hsw_power_well_ops,
1327         },
1328 };
1329
1330 static struct i915_power_well bdw_power_wells[] = {
1331         {
1332                 .name = "always-on",
1333                 .always_on = 1,
1334                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1335                 .ops = &i9xx_always_on_power_well_ops,
1336         },
1337         {
1338                 .name = "display",
1339                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1340                 .ops = &hsw_power_well_ops,
1341         },
1342 };
1343
1344 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1345         .sync_hw = vlv_power_well_sync_hw,
1346         .enable = vlv_display_power_well_enable,
1347         .disable = vlv_display_power_well_disable,
1348         .is_enabled = vlv_power_well_enabled,
1349 };
1350
1351 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1352         .sync_hw = vlv_power_well_sync_hw,
1353         .enable = vlv_dpio_cmn_power_well_enable,
1354         .disable = vlv_dpio_cmn_power_well_disable,
1355         .is_enabled = vlv_power_well_enabled,
1356 };
1357
1358 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1359         .sync_hw = vlv_power_well_sync_hw,
1360         .enable = vlv_power_well_enable,
1361         .disable = vlv_power_well_disable,
1362         .is_enabled = vlv_power_well_enabled,
1363 };
1364
1365 static struct i915_power_well vlv_power_wells[] = {
1366         {
1367                 .name = "always-on",
1368                 .always_on = 1,
1369                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1370                 .ops = &i9xx_always_on_power_well_ops,
1371         },
1372         {
1373                 .name = "display",
1374                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1375                 .data = PUNIT_POWER_WELL_DISP2D,
1376                 .ops = &vlv_display_power_well_ops,
1377         },
1378         {
1379                 .name = "dpio-tx-b-01",
1380                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1381                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1382                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1383                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1384                 .ops = &vlv_dpio_power_well_ops,
1385                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1386         },
1387         {
1388                 .name = "dpio-tx-b-23",
1389                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1390                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1391                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1392                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1393                 .ops = &vlv_dpio_power_well_ops,
1394                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1395         },
1396         {
1397                 .name = "dpio-tx-c-01",
1398                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1399                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1400                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1401                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1402                 .ops = &vlv_dpio_power_well_ops,
1403                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1404         },
1405         {
1406                 .name = "dpio-tx-c-23",
1407                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1408                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1409                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1410                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1411                 .ops = &vlv_dpio_power_well_ops,
1412                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1413         },
1414         {
1415                 .name = "dpio-common",
1416                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1417                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1418                 .ops = &vlv_dpio_cmn_power_well_ops,
1419         },
1420 };
1421
1422 static struct i915_power_well chv_power_wells[] = {
1423         {
1424                 .name = "always-on",
1425                 .always_on = 1,
1426                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1427                 .ops = &i9xx_always_on_power_well_ops,
1428         },
1429 #if 0
1430         {
1431                 .name = "display",
1432                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1433                 .data = PUNIT_POWER_WELL_DISP2D,
1434                 .ops = &vlv_display_power_well_ops,
1435         },
1436 #endif
1437         {
1438                 .name = "pipe-a",
1439                 /*
1440                  * FIXME: pipe A power well seems to be the new disp2d well.
1441                  * At least all registers seem to be housed there. Figure
1442                  * out if this a a temporary situation in pre-production
1443                  * hardware or a permanent state of affairs.
1444                  */
1445                 .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS,
1446                 .data = PIPE_A,
1447                 .ops = &chv_pipe_power_well_ops,
1448         },
1449 #if 0
1450         {
1451                 .name = "pipe-b",
1452                 .domains = CHV_PIPE_B_POWER_DOMAINS,
1453                 .data = PIPE_B,
1454                 .ops = &chv_pipe_power_well_ops,
1455         },
1456         {
1457                 .name = "pipe-c",
1458                 .domains = CHV_PIPE_C_POWER_DOMAINS,
1459                 .data = PIPE_C,
1460                 .ops = &chv_pipe_power_well_ops,
1461         },
1462 #endif
1463         {
1464                 .name = "dpio-common-bc",
1465                 /*
1466                  * XXX: cmnreset for one PHY seems to disturb the other.
1467                  * As a workaround keep both powered on at the same
1468                  * time for now.
1469                  */
1470                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
1471                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1472                 .ops = &chv_dpio_cmn_power_well_ops,
1473         },
1474         {
1475                 .name = "dpio-common-d",
1476                 /*
1477                  * XXX: cmnreset for one PHY seems to disturb the other.
1478                  * As a workaround keep both powered on at the same
1479                  * time for now.
1480                  */
1481                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
1482                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1483                 .ops = &chv_dpio_cmn_power_well_ops,
1484         },
1485 #if 0
1486         {
1487                 .name = "dpio-tx-b-01",
1488                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1489                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
1490                 .ops = &vlv_dpio_power_well_ops,
1491                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1492         },
1493         {
1494                 .name = "dpio-tx-b-23",
1495                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1496                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
1497                 .ops = &vlv_dpio_power_well_ops,
1498                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1499         },
1500         {
1501                 .name = "dpio-tx-c-01",
1502                 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1503                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1504                 .ops = &vlv_dpio_power_well_ops,
1505                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1506         },
1507         {
1508                 .name = "dpio-tx-c-23",
1509                 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1510                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1511                 .ops = &vlv_dpio_power_well_ops,
1512                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1513         },
1514         {
1515                 .name = "dpio-tx-d-01",
1516                 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
1517                            CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
1518                 .ops = &vlv_dpio_power_well_ops,
1519                 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
1520         },
1521         {
1522                 .name = "dpio-tx-d-23",
1523                 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
1524                            CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
1525                 .ops = &vlv_dpio_power_well_ops,
1526                 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
1527         },
1528 #endif
1529 };
1530
1531 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1532                                                  int power_well_id)
1533 {
1534         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1535         struct i915_power_well *power_well;
1536         int i;
1537
1538         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1539                 if (power_well->data == power_well_id)
1540                         return power_well;
1541         }
1542
1543         return NULL;
1544 }
1545
1546 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1547                                     int power_well_id)
1548 {
1549         struct i915_power_well *power_well;
1550         bool ret;
1551
1552         power_well = lookup_power_well(dev_priv, power_well_id);
1553         ret = power_well->ops->is_enabled(dev_priv, power_well);
1554
1555         return ret;
1556 }
1557
1558 static struct i915_power_well skl_power_wells[] = {
1559         {
1560                 .name = "always-on",
1561                 .always_on = 1,
1562                 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1563                 .ops = &i9xx_always_on_power_well_ops,
1564         },
1565         {
1566                 .name = "power well 1",
1567                 .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1568                 .ops = &skl_power_well_ops,
1569                 .data = SKL_DISP_PW_1,
1570         },
1571         {
1572                 .name = "MISC IO power well",
1573                 .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,
1574                 .ops = &skl_power_well_ops,
1575                 .data = SKL_DISP_PW_MISC_IO,
1576         },
1577         {
1578                 .name = "power well 2",
1579                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1580                 .ops = &skl_power_well_ops,
1581                 .data = SKL_DISP_PW_2,
1582         },
1583         {
1584                 .name = "DDI A/E power well",
1585                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1586                 .ops = &skl_power_well_ops,
1587                 .data = SKL_DISP_PW_DDI_A_E,
1588         },
1589         {
1590                 .name = "DDI B power well",
1591                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1592                 .ops = &skl_power_well_ops,
1593                 .data = SKL_DISP_PW_DDI_B,
1594         },
1595         {
1596                 .name = "DDI C power well",
1597                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1598                 .ops = &skl_power_well_ops,
1599                 .data = SKL_DISP_PW_DDI_C,
1600         },
1601         {
1602                 .name = "DDI D power well",
1603                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1604                 .ops = &skl_power_well_ops,
1605                 .data = SKL_DISP_PW_DDI_D,
1606         },
1607 };
1608
1609 static struct i915_power_well bxt_power_wells[] = {
1610         {
1611                 .name = "always-on",
1612                 .always_on = 1,
1613                 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1614                 .ops = &i9xx_always_on_power_well_ops,
1615         },
1616         {
1617                 .name = "power well 1",
1618                 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1619                 .ops = &skl_power_well_ops,
1620                 .data = SKL_DISP_PW_1,
1621         },
1622         {
1623                 .name = "power well 2",
1624                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1625                 .ops = &skl_power_well_ops,
1626                 .data = SKL_DISP_PW_2,
1627         }
1628 };
1629
1630 #define set_power_wells(power_domains, __power_wells) ({                \
1631         (power_domains)->power_wells = (__power_wells);                 \
1632         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
1633 })
1634
1635 /**
1636  * intel_power_domains_init - initializes the power domain structures
1637  * @dev_priv: i915 device instance
1638  *
1639  * Initializes the power domain structures for @dev_priv depending upon the
1640  * supported platform.
1641  */
1642 int intel_power_domains_init(struct drm_i915_private *dev_priv)
1643 {
1644         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1645
1646         mutex_init(&power_domains->lock);
1647
1648         /*
1649          * The enabling order will be from lower to higher indexed wells,
1650          * the disabling order is reversed.
1651          */
1652         if (IS_HASWELL(dev_priv->dev)) {
1653                 set_power_wells(power_domains, hsw_power_wells);
1654         } else if (IS_BROADWELL(dev_priv->dev)) {
1655                 set_power_wells(power_domains, bdw_power_wells);
1656         } else if (IS_SKYLAKE(dev_priv->dev)) {
1657                 set_power_wells(power_domains, skl_power_wells);
1658         } else if (IS_BROXTON(dev_priv->dev)) {
1659                 set_power_wells(power_domains, bxt_power_wells);
1660         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1661                 set_power_wells(power_domains, chv_power_wells);
1662         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
1663                 set_power_wells(power_domains, vlv_power_wells);
1664         } else {
1665                 set_power_wells(power_domains, i9xx_always_on_power_well);
1666         }
1667
1668         return 0;
1669 }
1670
1671 static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
1672 {
1673         struct drm_device *dev = dev_priv->dev;
1674         struct device *device = &dev->pdev->dev;
1675
1676         if (!HAS_RUNTIME_PM(dev))
1677                 return;
1678
1679         if (!intel_enable_rc6(dev))
1680                 return;
1681
1682         /* Make sure we're not suspended first. */
1683         pm_runtime_get_sync(device);
1684         pm_runtime_disable(device);
1685 }
1686
1687 /**
1688  * intel_power_domains_fini - finalizes the power domain structures
1689  * @dev_priv: i915 device instance
1690  *
1691  * Finalizes the power domain structures for @dev_priv depending upon the
1692  * supported platform. This function also disables runtime pm and ensures that
1693  * the device stays powered up so that the driver can be reloaded.
1694  */
1695 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
1696 {
1697         intel_runtime_pm_disable(dev_priv);
1698
1699         /* The i915.ko module is still not prepared to be loaded when
1700          * the power well is not enabled, so just enable it in case
1701          * we're going to unload/reload. */
1702         intel_display_set_init_power(dev_priv, true);
1703 }
1704
1705 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
1706 {
1707         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1708         struct i915_power_well *power_well;
1709         int i;
1710
1711         mutex_lock(&power_domains->lock);
1712         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1713                 power_well->ops->sync_hw(dev_priv, power_well);
1714                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
1715                                                                      power_well);
1716         }
1717         mutex_unlock(&power_domains->lock);
1718 }
1719
1720 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
1721 {
1722         struct i915_power_well *cmn =
1723                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1724         struct i915_power_well *disp2d =
1725                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
1726
1727         /* If the display might be already active skip this */
1728         if (cmn->ops->is_enabled(dev_priv, cmn) &&
1729             disp2d->ops->is_enabled(dev_priv, disp2d) &&
1730             I915_READ(DPIO_CTL) & DPIO_CMNRST)
1731                 return;
1732
1733         DRM_DEBUG_KMS("toggling display PHY side reset\n");
1734
1735         /* cmnlane needs DPLL registers */
1736         disp2d->ops->enable(dev_priv, disp2d);
1737
1738         /*
1739          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1740          * Need to assert and de-assert PHY SB reset by gating the
1741          * common lane power, then un-gating it.
1742          * Simply ungating isn't enough to reset the PHY enough to get
1743          * ports and lanes running.
1744          */
1745         cmn->ops->disable(dev_priv, cmn);
1746 }
1747
1748 /**
1749  * intel_power_domains_init_hw - initialize hardware power domain state
1750  * @dev_priv: i915 device instance
1751  *
1752  * This function initializes the hardware power domain state and enables all
1753  * power domains using intel_display_set_init_power().
1754  */
1755 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
1756 {
1757         struct drm_device *dev = dev_priv->dev;
1758         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1759
1760         power_domains->initializing = true;
1761
1762         if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
1763                 mutex_lock(&power_domains->lock);
1764                 vlv_cmnlane_wa(dev_priv);
1765                 mutex_unlock(&power_domains->lock);
1766         }
1767
1768         /* For now, we need the power well to be always enabled. */
1769         intel_display_set_init_power(dev_priv, true);
1770         intel_power_domains_resume(dev_priv);
1771         power_domains->initializing = false;
1772 }
1773
1774 /**
1775  * intel_aux_display_runtime_get - grab an auxiliary power domain reference
1776  * @dev_priv: i915 device instance
1777  *
1778  * This function grabs a power domain reference for the auxiliary power domain
1779  * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
1780  * parents are powered up. Therefore users should only grab a reference to the
1781  * innermost power domain they need.
1782  *
1783  * Any power domain reference obtained by this function must have a symmetric
1784  * call to intel_aux_display_runtime_put() to release the reference again.
1785  */
1786 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
1787 {
1788         intel_runtime_pm_get(dev_priv);
1789 }
1790
1791 /**
1792  * intel_aux_display_runtime_put - release an auxiliary power domain reference
1793  * @dev_priv: i915 device instance
1794  *
1795  * This function drops the auxiliary power domain reference obtained by
1796  * intel_aux_display_runtime_get() and might power down the corresponding
1797  * hardware block right away if this is the last reference.
1798  */
1799 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
1800 {
1801         intel_runtime_pm_put(dev_priv);
1802 }
1803
1804 /**
1805  * intel_runtime_pm_get - grab a runtime pm reference
1806  * @dev_priv: i915 device instance
1807  *
1808  * This function grabs a device-level runtime pm reference (mostly used for GEM
1809  * code to ensure the GTT or GT is on) and ensures that it is powered up.
1810  *
1811  * Any runtime pm reference obtained by this function must have a symmetric
1812  * call to intel_runtime_pm_put() to release the reference again.
1813  */
1814 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
1815 {
1816         struct drm_device *dev = dev_priv->dev;
1817         struct device *device = &dev->pdev->dev;
1818
1819         if (!HAS_RUNTIME_PM(dev))
1820                 return;
1821
1822         pm_runtime_get_sync(device);
1823         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
1824 }
1825
1826 /**
1827  * intel_runtime_pm_get_noresume - grab a runtime pm reference
1828  * @dev_priv: i915 device instance
1829  *
1830  * This function grabs a device-level runtime pm reference (mostly used for GEM
1831  * code to ensure the GTT or GT is on).
1832  *
1833  * It will _not_ power up the device but instead only check that it's powered
1834  * on.  Therefore it is only valid to call this functions from contexts where
1835  * the device is known to be powered up and where trying to power it up would
1836  * result in hilarity and deadlocks. That pretty much means only the system
1837  * suspend/resume code where this is used to grab runtime pm references for
1838  * delayed setup down in work items.
1839  *
1840  * Any runtime pm reference obtained by this function must have a symmetric
1841  * call to intel_runtime_pm_put() to release the reference again.
1842  */
1843 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
1844 {
1845         struct drm_device *dev = dev_priv->dev;
1846         struct device *device = &dev->pdev->dev;
1847
1848         if (!HAS_RUNTIME_PM(dev))
1849                 return;
1850
1851         WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
1852         pm_runtime_get_noresume(device);
1853 }
1854
1855 /**
1856  * intel_runtime_pm_put - release a runtime pm reference
1857  * @dev_priv: i915 device instance
1858  *
1859  * This function drops the device-level runtime pm reference obtained by
1860  * intel_runtime_pm_get() and might power down the corresponding
1861  * hardware block right away if this is the last reference.
1862  */
1863 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
1864 {
1865         struct drm_device *dev = dev_priv->dev;
1866         struct device *device = &dev->pdev->dev;
1867
1868         if (!HAS_RUNTIME_PM(dev))
1869                 return;
1870
1871         pm_runtime_mark_last_busy(device);
1872         pm_runtime_put_autosuspend(device);
1873 }
1874
1875 /**
1876  * intel_runtime_pm_enable - enable runtime pm
1877  * @dev_priv: i915 device instance
1878  *
1879  * This function enables runtime pm at the end of the driver load sequence.
1880  *
1881  * Note that this function does currently not enable runtime pm for the
1882  * subordinate display power domains. That is only done on the first modeset
1883  * using intel_display_set_init_power().
1884  */
1885 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
1886 {
1887         struct drm_device *dev = dev_priv->dev;
1888         struct device *device = &dev->pdev->dev;
1889
1890         if (!HAS_RUNTIME_PM(dev))
1891                 return;
1892
1893         pm_runtime_set_active(device);
1894
1895         /*
1896          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
1897          * requirement.
1898          */
1899         if (!intel_enable_rc6(dev)) {
1900                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
1901                 return;
1902         }
1903
1904         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
1905         pm_runtime_mark_last_busy(device);
1906         pm_runtime_use_autosuspend(device);
1907
1908         pm_runtime_put_autosuspend(device);
1909 }
1910