2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_rect.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_plane_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
43 format_is_yuv(uint32_t format)
56 static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
59 if (!mode->crtc_htotal)
62 return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal);
66 * intel_pipe_update_start() - start update of a set of display registers
67 * @crtc: the crtc of which the registers are going to be updated
68 * @start_vbl_count: vblank counter return pointer used for error checking
70 * Mark the start of an update to pipe registers that should be updated
71 * atomically regarding vblank. If the next vblank will happens within
72 * the next 100 us, this function waits until the vblank passes.
74 * After a successful call to this function, interrupts will be disabled
75 * until a subsequent call to intel_pipe_update_end(). That is done to
76 * avoid random delays. The value written to @start_vbl_count should be
77 * supplied to intel_pipe_update_end() for error checking.
79 * Return: true if the call was successful
81 bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
83 struct drm_device *dev = crtc->base.dev;
84 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
85 enum pipe pipe = crtc->pipe;
86 long timeout = msecs_to_jiffies_timeout(1);
87 int scanline, min, max, vblank_start;
88 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
91 vblank_start = mode->crtc_vblank_start;
92 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
93 vblank_start = DIV_ROUND_UP(vblank_start, 2);
95 /* FIXME needs to be calibrated sensibly */
96 min = vblank_start - usecs_to_scanlines(mode, 100);
97 max = vblank_start - 1;
99 if (min <= 0 || max <= 0)
102 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
107 trace_i915_pipe_update_start(crtc, min, max);
111 * prepare_to_wait() has a memory barrier, which guarantees
112 * other CPUs can see the task state update by the time we
115 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
117 scanline = intel_get_crtc_scanline(crtc);
118 if (scanline < min || scanline > max)
122 DRM_ERROR("Potential atomic update failure on pipe %c\n",
123 pipe_name(crtc->pipe));
129 timeout = schedule_timeout(timeout);
134 finish_wait(wq, &wait);
136 drm_crtc_vblank_put(&crtc->base);
138 *start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
140 trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count);
146 * intel_pipe_update_end() - end update of a set of display registers
147 * @crtc: the crtc of which the registers were updated
148 * @start_vbl_count: start vblank counter (used for error checking)
150 * Mark the end of an update started with intel_pipe_update_start(). This
151 * re-enables interrupts and verifies the update was actually completed
152 * before a vblank using the value of @start_vbl_count.
154 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count)
156 struct drm_device *dev = crtc->base.dev;
157 enum pipe pipe = crtc->pipe;
158 u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
160 trace_i915_pipe_update_end(crtc, end_vbl_count);
164 if (start_vbl_count != end_vbl_count)
165 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n",
166 pipe_name(pipe), start_vbl_count, end_vbl_count);
170 skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
171 struct drm_framebuffer *fb,
172 int crtc_x, int crtc_y,
173 unsigned int crtc_w, unsigned int crtc_h,
174 uint32_t x, uint32_t y,
175 uint32_t src_w, uint32_t src_h)
177 struct drm_device *dev = drm_plane->dev;
178 struct drm_i915_private *dev_priv = dev->dev_private;
179 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
180 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
181 const int pipe = intel_plane->pipe;
182 const int plane = intel_plane->plane + 1;
183 u32 plane_ctl, stride_div, stride;
184 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
185 const struct drm_intel_sprite_colorkey *key =
186 &to_intel_plane_state(drm_plane->state)->ckey;
187 unsigned long surf_addr;
188 u32 tile_height, plane_offset, plane_size;
189 unsigned int rotation;
190 int x_offset, y_offset;
191 struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
194 plane_ctl = PLANE_CTL_ENABLE |
195 PLANE_CTL_PIPE_CSC_ENABLE;
197 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
198 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
200 rotation = drm_plane->state->rotation;
201 plane_ctl |= skl_plane_ctl_rotation(rotation);
203 intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
205 src_w != crtc_w || src_h != crtc_h);
207 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
210 scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id;
212 /* Sizes are 0 based */
219 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
220 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
221 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
224 if (key->flags & I915_SET_COLORKEY_DESTINATION)
225 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
226 else if (key->flags & I915_SET_COLORKEY_SOURCE)
227 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
229 surf_addr = intel_plane_obj_offset(intel_plane, obj);
231 if (intel_rotation_90_or_270(rotation)) {
232 /* stride: Surface height in tiles */
233 tile_height = intel_tile_height(dev, fb->pixel_format,
235 stride = DIV_ROUND_UP(fb->height, tile_height);
236 plane_size = (src_w << 16) | src_h;
237 x_offset = stride * tile_height - y - (src_h + 1);
240 stride = fb->pitches[0] / stride_div;
241 plane_size = (src_h << 16) | src_w;
245 plane_offset = y_offset << 16 | x_offset;
247 I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
248 I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
249 I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
251 /* program plane scaler */
252 if (scaler_id >= 0) {
253 uint32_t ps_ctrl = 0;
255 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
256 PS_PLANE_SEL(plane));
257 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
258 crtc_state->scaler_state.scalers[scaler_id].mode;
259 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
260 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
261 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
262 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
263 ((crtc_w + 1) << 16)|(crtc_h + 1));
265 I915_WRITE(PLANE_POS(pipe, plane), 0);
267 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
270 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
271 I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
272 POSTING_READ(PLANE_SURF(pipe, plane));
276 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
278 struct drm_device *dev = dplane->dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
280 struct intel_plane *intel_plane = to_intel_plane(dplane);
281 const int pipe = intel_plane->pipe;
282 const int plane = intel_plane->plane + 1;
284 I915_WRITE(PLANE_CTL(pipe, plane), 0);
286 I915_WRITE(PLANE_SURF(pipe, plane), 0);
287 POSTING_READ(PLANE_SURF(pipe, plane));
289 intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
293 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
295 struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
296 int plane = intel_plane->plane;
298 /* Seems RGB data bypasses the CSC always */
299 if (!format_is_yuv(format))
303 * BT.601 limited range YCbCr -> full range RGB
305 * |r| | 6537 4769 0| |cr |
306 * |g| = |-3330 4769 -1605| x |y-64|
307 * |b| | 0 4769 8263| |cb |
309 * Cb and Cr apparently come in as signed already, so no
310 * need for any offset. For Y we need to remove the offset.
312 I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
313 I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
314 I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
316 I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
317 I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
318 I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
319 I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
320 I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
322 I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
323 I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
324 I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
326 I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
327 I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
328 I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
332 vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
333 struct drm_framebuffer *fb,
334 int crtc_x, int crtc_y,
335 unsigned int crtc_w, unsigned int crtc_h,
336 uint32_t x, uint32_t y,
337 uint32_t src_w, uint32_t src_h)
339 struct drm_device *dev = dplane->dev;
340 struct drm_i915_private *dev_priv = dev->dev_private;
341 struct intel_plane *intel_plane = to_intel_plane(dplane);
342 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
343 int pipe = intel_plane->pipe;
344 int plane = intel_plane->plane;
346 unsigned long sprsurf_offset, linear_offset;
347 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
348 const struct drm_intel_sprite_colorkey *key =
349 &to_intel_plane_state(dplane->state)->ckey;
353 switch (fb->pixel_format) {
354 case DRM_FORMAT_YUYV:
355 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
357 case DRM_FORMAT_YVYU:
358 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
360 case DRM_FORMAT_UYVY:
361 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
363 case DRM_FORMAT_VYUY:
364 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
366 case DRM_FORMAT_RGB565:
367 sprctl |= SP_FORMAT_BGR565;
369 case DRM_FORMAT_XRGB8888:
370 sprctl |= SP_FORMAT_BGRX8888;
372 case DRM_FORMAT_ARGB8888:
373 sprctl |= SP_FORMAT_BGRA8888;
375 case DRM_FORMAT_XBGR2101010:
376 sprctl |= SP_FORMAT_RGBX1010102;
378 case DRM_FORMAT_ABGR2101010:
379 sprctl |= SP_FORMAT_RGBA1010102;
381 case DRM_FORMAT_XBGR8888:
382 sprctl |= SP_FORMAT_RGBX8888;
384 case DRM_FORMAT_ABGR8888:
385 sprctl |= SP_FORMAT_RGBA8888;
389 * If we get here one of the upper layers failed to filter
390 * out the unsupported plane formats
397 * Enable gamma to match primary/cursor plane behaviour.
398 * FIXME should be user controllable via propertiesa.
400 sprctl |= SP_GAMMA_ENABLE;
402 if (obj->tiling_mode != I915_TILING_NONE)
405 /* Sizes are 0 based */
411 linear_offset = y * fb->pitches[0] + x * pixel_size;
412 sprsurf_offset = intel_gen4_compute_page_offset(dev_priv,
417 linear_offset -= sprsurf_offset;
419 if (dplane->state->rotation == BIT(DRM_ROTATE_180)) {
420 sprctl |= SP_ROTATE_180;
424 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
428 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
429 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
430 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
433 if (key->flags & I915_SET_COLORKEY_SOURCE)
434 sprctl |= SP_SOURCE_KEY;
436 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
437 chv_update_csc(intel_plane, fb->pixel_format);
439 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
440 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
442 if (obj->tiling_mode != I915_TILING_NONE)
443 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
445 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
447 I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
449 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
450 I915_WRITE(SPCNTR(pipe, plane), sprctl);
451 I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
453 POSTING_READ(SPSURF(pipe, plane));
457 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
459 struct drm_device *dev = dplane->dev;
460 struct drm_i915_private *dev_priv = dev->dev_private;
461 struct intel_plane *intel_plane = to_intel_plane(dplane);
462 int pipe = intel_plane->pipe;
463 int plane = intel_plane->plane;
465 I915_WRITE(SPCNTR(pipe, plane), 0);
467 I915_WRITE(SPSURF(pipe, plane), 0);
468 POSTING_READ(SPSURF(pipe, plane));
472 ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
473 struct drm_framebuffer *fb,
474 int crtc_x, int crtc_y,
475 unsigned int crtc_w, unsigned int crtc_h,
476 uint32_t x, uint32_t y,
477 uint32_t src_w, uint32_t src_h)
479 struct drm_device *dev = plane->dev;
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 struct intel_plane *intel_plane = to_intel_plane(plane);
482 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
483 enum pipe pipe = intel_plane->pipe;
484 u32 sprctl, sprscale = 0;
485 unsigned long sprsurf_offset, linear_offset;
486 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
487 const struct drm_intel_sprite_colorkey *key =
488 &to_intel_plane_state(plane->state)->ckey;
490 sprctl = SPRITE_ENABLE;
492 switch (fb->pixel_format) {
493 case DRM_FORMAT_XBGR8888:
494 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
496 case DRM_FORMAT_XRGB8888:
497 sprctl |= SPRITE_FORMAT_RGBX888;
499 case DRM_FORMAT_YUYV:
500 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
502 case DRM_FORMAT_YVYU:
503 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
505 case DRM_FORMAT_UYVY:
506 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
508 case DRM_FORMAT_VYUY:
509 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
516 * Enable gamma to match primary/cursor plane behaviour.
517 * FIXME should be user controllable via propertiesa.
519 sprctl |= SPRITE_GAMMA_ENABLE;
521 if (obj->tiling_mode != I915_TILING_NONE)
522 sprctl |= SPRITE_TILED;
524 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
525 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
527 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
529 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
530 sprctl |= SPRITE_PIPE_CSC_ENABLE;
532 intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size,
534 src_w != crtc_w || src_h != crtc_h);
536 /* Sizes are 0 based */
542 if (crtc_w != src_w || crtc_h != src_h)
543 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
545 linear_offset = y * fb->pitches[0] + x * pixel_size;
547 intel_gen4_compute_page_offset(dev_priv,
548 &x, &y, obj->tiling_mode,
549 pixel_size, fb->pitches[0]);
550 linear_offset -= sprsurf_offset;
552 if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
553 sprctl |= SPRITE_ROTATE_180;
555 /* HSW and BDW does this automagically in hardware */
556 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
559 linear_offset += src_h * fb->pitches[0] +
565 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
566 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
567 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
570 if (key->flags & I915_SET_COLORKEY_DESTINATION)
571 sprctl |= SPRITE_DEST_KEY;
572 else if (key->flags & I915_SET_COLORKEY_SOURCE)
573 sprctl |= SPRITE_SOURCE_KEY;
575 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
576 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
578 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
580 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
581 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
582 else if (obj->tiling_mode != I915_TILING_NONE)
583 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
585 I915_WRITE(SPRLINOFF(pipe), linear_offset);
587 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
588 if (intel_plane->can_scale)
589 I915_WRITE(SPRSCALE(pipe), sprscale);
590 I915_WRITE(SPRCTL(pipe), sprctl);
591 I915_WRITE(SPRSURF(pipe),
592 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
593 POSTING_READ(SPRSURF(pipe));
597 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
599 struct drm_device *dev = plane->dev;
600 struct drm_i915_private *dev_priv = dev->dev_private;
601 struct intel_plane *intel_plane = to_intel_plane(plane);
602 int pipe = intel_plane->pipe;
604 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
605 /* Can't leave the scaler enabled... */
606 if (intel_plane->can_scale)
607 I915_WRITE(SPRSCALE(pipe), 0);
609 I915_WRITE(SPRSURF(pipe), 0);
610 POSTING_READ(SPRSURF(pipe));
614 ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
615 struct drm_framebuffer *fb,
616 int crtc_x, int crtc_y,
617 unsigned int crtc_w, unsigned int crtc_h,
618 uint32_t x, uint32_t y,
619 uint32_t src_w, uint32_t src_h)
621 struct drm_device *dev = plane->dev;
622 struct drm_i915_private *dev_priv = dev->dev_private;
623 struct intel_plane *intel_plane = to_intel_plane(plane);
624 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
625 int pipe = intel_plane->pipe;
626 unsigned long dvssurf_offset, linear_offset;
627 u32 dvscntr, dvsscale;
628 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
629 const struct drm_intel_sprite_colorkey *key =
630 &to_intel_plane_state(plane->state)->ckey;
632 dvscntr = DVS_ENABLE;
634 switch (fb->pixel_format) {
635 case DRM_FORMAT_XBGR8888:
636 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
638 case DRM_FORMAT_XRGB8888:
639 dvscntr |= DVS_FORMAT_RGBX888;
641 case DRM_FORMAT_YUYV:
642 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
644 case DRM_FORMAT_YVYU:
645 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
647 case DRM_FORMAT_UYVY:
648 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
650 case DRM_FORMAT_VYUY:
651 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
658 * Enable gamma to match primary/cursor plane behaviour.
659 * FIXME should be user controllable via propertiesa.
661 dvscntr |= DVS_GAMMA_ENABLE;
663 if (obj->tiling_mode != I915_TILING_NONE)
664 dvscntr |= DVS_TILED;
667 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
669 intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
671 src_w != crtc_w || src_h != crtc_h);
673 /* Sizes are 0 based */
680 if (crtc_w != src_w || crtc_h != src_h)
681 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
683 linear_offset = y * fb->pitches[0] + x * pixel_size;
685 intel_gen4_compute_page_offset(dev_priv,
686 &x, &y, obj->tiling_mode,
687 pixel_size, fb->pitches[0]);
688 linear_offset -= dvssurf_offset;
690 if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
691 dvscntr |= DVS_ROTATE_180;
695 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
699 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
700 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
701 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
704 if (key->flags & I915_SET_COLORKEY_DESTINATION)
705 dvscntr |= DVS_DEST_KEY;
706 else if (key->flags & I915_SET_COLORKEY_SOURCE)
707 dvscntr |= DVS_SOURCE_KEY;
709 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
710 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
712 if (obj->tiling_mode != I915_TILING_NONE)
713 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
715 I915_WRITE(DVSLINOFF(pipe), linear_offset);
717 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
718 I915_WRITE(DVSSCALE(pipe), dvsscale);
719 I915_WRITE(DVSCNTR(pipe), dvscntr);
720 I915_WRITE(DVSSURF(pipe),
721 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
722 POSTING_READ(DVSSURF(pipe));
726 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
728 struct drm_device *dev = plane->dev;
729 struct drm_i915_private *dev_priv = dev->dev_private;
730 struct intel_plane *intel_plane = to_intel_plane(plane);
731 int pipe = intel_plane->pipe;
733 I915_WRITE(DVSCNTR(pipe), 0);
734 /* Disable the scaler */
735 I915_WRITE(DVSSCALE(pipe), 0);
737 I915_WRITE(DVSSURF(pipe), 0);
738 POSTING_READ(DVSSURF(pipe));
742 intel_check_sprite_plane(struct drm_plane *plane,
743 struct intel_crtc_state *crtc_state,
744 struct intel_plane_state *state)
746 struct drm_device *dev = plane->dev;
747 struct drm_crtc *crtc = state->base.crtc;
748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
749 struct intel_plane *intel_plane = to_intel_plane(plane);
750 struct drm_framebuffer *fb = state->base.fb;
752 unsigned int crtc_w, crtc_h;
753 uint32_t src_x, src_y, src_w, src_h;
754 struct drm_rect *src = &state->src;
755 struct drm_rect *dst = &state->dst;
756 const struct drm_rect *clip = &state->clip;
758 int max_scale, min_scale;
763 state->visible = false;
767 /* Don't modify another pipe's plane */
768 if (intel_plane->pipe != intel_crtc->pipe) {
769 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
773 /* FIXME check all gen limits */
774 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
775 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
779 /* setup can_scale, min_scale, max_scale */
780 if (INTEL_INFO(dev)->gen >= 9) {
781 /* use scaler when colorkey is not required */
782 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
785 max_scale = skl_max_scale(intel_crtc, crtc_state);
788 min_scale = DRM_PLANE_HELPER_NO_SCALING;
789 max_scale = DRM_PLANE_HELPER_NO_SCALING;
792 can_scale = intel_plane->can_scale;
793 max_scale = intel_plane->max_downscale << 16;
794 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
798 * FIXME the following code does a bunch of fuzzy adjustments to the
799 * coordinates and sizes. We probably need some way to decide whether
800 * more strict checking should be done instead.
802 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
803 state->base.rotation);
805 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
808 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
811 state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
815 crtc_w = drm_rect_width(dst);
816 crtc_h = drm_rect_height(dst);
818 if (state->visible) {
819 /* check again in case clipping clamped the results */
820 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
822 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
823 drm_rect_debug_print(src, true);
824 drm_rect_debug_print(dst, false);
829 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
831 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
832 drm_rect_debug_print(src, true);
833 drm_rect_debug_print(dst, false);
838 /* Make the source viewport size an exact multiple of the scaling factors. */
839 drm_rect_adjust_size(src,
840 drm_rect_width(dst) * hscale - drm_rect_width(src),
841 drm_rect_height(dst) * vscale - drm_rect_height(src));
843 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
844 state->base.rotation);
846 /* sanity check to make sure the src viewport wasn't enlarged */
847 WARN_ON(src->x1 < (int) state->base.src_x ||
848 src->y1 < (int) state->base.src_y ||
849 src->x2 > (int) state->base.src_x + state->base.src_w ||
850 src->y2 > (int) state->base.src_y + state->base.src_h);
853 * Hardware doesn't handle subpixel coordinates.
854 * Adjust to (macro)pixel boundary, but be careful not to
855 * increase the source viewport size, because that could
856 * push the downscaling factor out of bounds.
858 src_x = src->x1 >> 16;
859 src_w = drm_rect_width(src) >> 16;
860 src_y = src->y1 >> 16;
861 src_h = drm_rect_height(src) >> 16;
863 if (format_is_yuv(fb->pixel_format)) {
868 * Must keep src and dst the
869 * same if we can't scale.
875 state->visible = false;
879 /* Check size restrictions when scaling */
880 if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
881 unsigned int width_bytes;
885 /* FIXME interlacing min height is 6 */
887 if (crtc_w < 3 || crtc_h < 3)
888 state->visible = false;
890 if (src_w < 3 || src_h < 3)
891 state->visible = false;
893 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
894 width_bytes = ((src_x * pixel_size) & 63) +
897 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
898 width_bytes > 4096 || fb->pitches[0] > 4096)) {
899 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
904 if (state->visible) {
905 src->x1 = src_x << 16;
906 src->x2 = (src_x + src_w) << 16;
907 src->y1 = src_y << 16;
908 src->y2 = (src_y + src_h) << 16;
912 dst->x2 = crtc_x + crtc_w;
914 dst->y2 = crtc_y + crtc_h;
920 intel_commit_sprite_plane(struct drm_plane *plane,
921 struct intel_plane_state *state)
923 struct drm_crtc *crtc = state->base.crtc;
924 struct intel_plane *intel_plane = to_intel_plane(plane);
925 struct drm_framebuffer *fb = state->base.fb;
927 crtc = crtc ? crtc : plane->crtc;
931 if (!crtc->state->active)
934 if (state->visible) {
935 intel_plane->update_plane(plane, crtc, fb,
936 state->dst.x1, state->dst.y1,
937 drm_rect_width(&state->dst),
938 drm_rect_height(&state->dst),
941 drm_rect_width(&state->src) >> 16,
942 drm_rect_height(&state->src) >> 16);
944 intel_plane->disable_plane(plane, crtc);
948 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
949 struct drm_file *file_priv)
951 struct drm_intel_sprite_colorkey *set = data;
952 struct drm_plane *plane;
953 struct drm_plane_state *plane_state;
954 struct drm_atomic_state *state;
955 struct drm_modeset_acquire_ctx ctx;
958 /* Make sure we don't try to enable both src & dest simultaneously */
959 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
962 if (IS_VALLEYVIEW(dev) &&
963 set->flags & I915_SET_COLORKEY_DESTINATION)
966 plane = drm_plane_find(dev, set->plane_id);
967 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
970 drm_modeset_acquire_init(&ctx, 0);
972 state = drm_atomic_state_alloc(plane->dev);
977 state->acquire_ctx = &ctx;
980 plane_state = drm_atomic_get_plane_state(state, plane);
981 ret = PTR_ERR_OR_ZERO(plane_state);
983 to_intel_plane_state(plane_state)->ckey = *set;
984 ret = drm_atomic_commit(state);
990 drm_atomic_state_clear(state);
991 drm_modeset_backoff(&ctx);
995 drm_atomic_state_free(state);
998 drm_modeset_drop_locks(&ctx);
999 drm_modeset_acquire_fini(&ctx);
1003 static const uint32_t ilk_plane_formats[] = {
1004 DRM_FORMAT_XRGB8888,
1011 static const uint32_t snb_plane_formats[] = {
1012 DRM_FORMAT_XBGR8888,
1013 DRM_FORMAT_XRGB8888,
1020 static const uint32_t vlv_plane_formats[] = {
1022 DRM_FORMAT_ABGR8888,
1023 DRM_FORMAT_ARGB8888,
1024 DRM_FORMAT_XBGR8888,
1025 DRM_FORMAT_XRGB8888,
1026 DRM_FORMAT_XBGR2101010,
1027 DRM_FORMAT_ABGR2101010,
1034 static uint32_t skl_plane_formats[] = {
1036 DRM_FORMAT_ABGR8888,
1037 DRM_FORMAT_ARGB8888,
1038 DRM_FORMAT_XBGR8888,
1039 DRM_FORMAT_XRGB8888,
1047 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1049 struct intel_plane *intel_plane;
1050 struct intel_plane_state *state;
1051 unsigned long possible_crtcs;
1052 const uint32_t *plane_formats;
1053 int num_plane_formats;
1056 if (INTEL_INFO(dev)->gen < 5)
1059 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1063 state = intel_create_plane_state(&intel_plane->base);
1068 intel_plane->base.state = &state->base;
1070 switch (INTEL_INFO(dev)->gen) {
1073 intel_plane->can_scale = true;
1074 intel_plane->max_downscale = 16;
1075 intel_plane->update_plane = ilk_update_plane;
1076 intel_plane->disable_plane = ilk_disable_plane;
1079 plane_formats = snb_plane_formats;
1080 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1082 plane_formats = ilk_plane_formats;
1083 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1089 if (IS_IVYBRIDGE(dev)) {
1090 intel_plane->can_scale = true;
1091 intel_plane->max_downscale = 2;
1093 intel_plane->can_scale = false;
1094 intel_plane->max_downscale = 1;
1097 if (IS_VALLEYVIEW(dev)) {
1098 intel_plane->update_plane = vlv_update_plane;
1099 intel_plane->disable_plane = vlv_disable_plane;
1101 plane_formats = vlv_plane_formats;
1102 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1104 intel_plane->update_plane = ivb_update_plane;
1105 intel_plane->disable_plane = ivb_disable_plane;
1107 plane_formats = snb_plane_formats;
1108 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1112 intel_plane->can_scale = true;
1113 intel_plane->update_plane = skl_update_plane;
1114 intel_plane->disable_plane = skl_disable_plane;
1115 state->scaler_id = -1;
1117 plane_formats = skl_plane_formats;
1118 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1125 intel_plane->pipe = pipe;
1126 intel_plane->plane = plane;
1127 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe);
1128 intel_plane->check_plane = intel_check_sprite_plane;
1129 intel_plane->commit_plane = intel_commit_sprite_plane;
1130 possible_crtcs = (1 << pipe);
1131 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1133 plane_formats, num_plane_formats,
1134 DRM_PLANE_TYPE_OVERLAY);
1140 intel_create_rotation_property(dev, intel_plane);
1142 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);