drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 static bool
  43 format_is_yuv(uint32_t format)
  44 {
  45         switch (format) {
  46         case DRM_FORMAT_YUYV:
  47         case DRM_FORMAT_UYVY:
  48         case DRM_FORMAT_VYUY:
  49         case DRM_FORMAT_YVYU:
  50                 return true;
  51         default:
  52                 return false;
  53         }
  54 }
  55
  56 static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
  57 {
  58         /* paranoia */
  59         if (!mode->crtc_htotal)
  60                 return 1;
  61
  62         return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal);
  63 }
  64
  65 /**
  66  * intel_pipe_update_start() - start update of a set of display registers
  67  * @crtc: the crtc of which the registers are going to be updated
  68  * @start_vbl_count: vblank counter return pointer used for error checking
  69  *
  70  * Mark the start of an update to pipe registers that should be updated
  71  * atomically regarding vblank. If the next vblank will happens within
  72  * the next 100 us, this function waits until the vblank passes.
  73  *
  74  * After a successful call to this function, interrupts will be disabled
  75  * until a subsequent call to intel_pipe_update_end(). That is done to
  76  * avoid random delays. The value written to @start_vbl_count should be
  77  * supplied to intel_pipe_update_end() for error checking.
  78  *
  79  * Return: true if the call was successful
  80  */
  81 bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
  82 {
  83         struct drm_device *dev = crtc->base.dev;
  84         const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
  85         enum pipe pipe = crtc->pipe;
  86         long timeout = msecs_to_jiffies_timeout(1);
  87         int scanline, min, max, vblank_start;
  88         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  89         DEFINE_WAIT(wait);
  90
  91         vblank_start = mode->crtc_vblank_start;
  92         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  93                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  94
  95         /* FIXME needs to be calibrated sensibly */
  96         min = vblank_start - usecs_to_scanlines(mode, 100);
  97         max = vblank_start - 1;
  98
  99         if (min <= 0 || max <= 0)
 100                 return false;
 101
 102         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 103                 return false;
 104
 105         local_irq_disable();
 106
 107         trace_i915_pipe_update_start(crtc, min, max);
 108
 109         for (;;) {
 110                 /*
 111                  * prepare_to_wait() has a memory barrier, which guarantees
 112                  * other CPUs can see the task state update by the time we
 113                  * read the scanline.
 114                  */
 115                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 116
 117                 scanline = intel_get_crtc_scanline(crtc);
 118                 if (scanline < min || scanline > max)
 119                         break;
 120
 121                 if (timeout <= 0) {
 122                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 123                                   pipe_name(crtc->pipe));
 124                         break;
 125                 }
 126
 127                 local_irq_enable();
 128
 129                 timeout = schedule_timeout(timeout);
 130
 131                 local_irq_disable();
 132         }
 133
 134         finish_wait(wq, &wait);
 135
 136         drm_crtc_vblank_put(&crtc->base);
 137
 138         *start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 139
 140         trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count);
 141
 142         return true;
 143 }
 144
 145 /**
 146  * intel_pipe_update_end() - end update of a set of display registers
 147  * @crtc: the crtc of which the registers were updated
 148  * @start_vbl_count: start vblank counter (used for error checking)
 149  *
 150  * Mark the end of an update started with intel_pipe_update_start(). This
 151  * re-enables interrupts and verifies the update was actually completed
 152  * before a vblank using the value of @start_vbl_count.
 153  */
 154 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count)
 155 {
 156         struct drm_device *dev = crtc->base.dev;
 157         enum pipe pipe = crtc->pipe;
 158         u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 159
 160         trace_i915_pipe_update_end(crtc, end_vbl_count);
 161
 162         local_irq_enable();
 163
 164         if (start_vbl_count != end_vbl_count)
 165                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n",
 166                           pipe_name(pipe), start_vbl_count, end_vbl_count);
 167 }
 168
 169 static void
 170 skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 171                  struct drm_framebuffer *fb,
 172                  int crtc_x, int crtc_y,
 173                  unsigned int crtc_w, unsigned int crtc_h,
 174                  uint32_t x, uint32_t y,
 175                  uint32_t src_w, uint32_t src_h)
 176 {
 177         struct drm_device *dev = drm_plane->dev;
 178         struct drm_i915_private *dev_priv = dev->dev_private;
 179         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 180         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 181         const int pipe = intel_plane->pipe;
 182         const int plane = intel_plane->plane + 1;
 183         u32 plane_ctl, stride_div, stride;
 184         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 185         const struct drm_intel_sprite_colorkey *key =
 186                 &to_intel_plane_state(drm_plane->state)->ckey;
 187         unsigned long surf_addr;
 188         u32 tile_height, plane_offset, plane_size;
 189         unsigned int rotation;
 190         int x_offset, y_offset;
 191         struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
 192         int scaler_id;
 193
 194         plane_ctl = PLANE_CTL_ENABLE |
 195                 PLANE_CTL_PIPE_CSC_ENABLE;
 196
 197         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
 198         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
 199
 200         rotation = drm_plane->state->rotation;
 201         plane_ctl |= skl_plane_ctl_rotation(rotation);
 202
 203         intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
 204                                        pixel_size, true,
 205                                        src_w != crtc_w || src_h != crtc_h);
 206
 207         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
 208                                                fb->pixel_format);
 209
 210         scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id;
 211
 212         /* Sizes are 0 based */
 213         src_w--;
 214         src_h--;
 215         crtc_w--;
 216         crtc_h--;
 217
 218         if (key->flags) {
 219                 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
 220                 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
 221                 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
 222         }
 223
 224         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 225                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 226         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 227                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 228
 229         surf_addr = intel_plane_obj_offset(intel_plane, obj);
 230
 231         if (intel_rotation_90_or_270(rotation)) {
 232                 /* stride: Surface height in tiles */
 233                 tile_height = intel_tile_height(dev, fb->pixel_format,
 234                                                 fb->modifier[0]);
 235                 stride = DIV_ROUND_UP(fb->height, tile_height);
 236                 plane_size = (src_w << 16) | src_h;
 237                 x_offset = stride * tile_height - y - (src_h + 1);
 238                 y_offset = x;
 239         } else {
 240                 stride = fb->pitches[0] / stride_div;
 241                 plane_size = (src_h << 16) | src_w;
 242                 x_offset = x;
 243                 y_offset = y;
 244         }
 245         plane_offset = y_offset << 16 | x_offset;
 246
 247         I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
 248         I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
 249         I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
 250
 251         /* program plane scaler */
 252         if (scaler_id >= 0) {
 253                 uint32_t ps_ctrl = 0;
 254
 255                 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
 256                         PS_PLANE_SEL(plane));
 257                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
 258                         crtc_state->scaler_state.scalers[scaler_id].mode;
 259                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
 260                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 261                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 262                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
 263                         ((crtc_w + 1) << 16)|(crtc_h + 1));
 264
 265                 I915_WRITE(PLANE_POS(pipe, plane), 0);
 266         } else {
 267                 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
 268         }
 269
 270         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
 271         I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
 272         POSTING_READ(PLANE_SURF(pipe, plane));
 273 }
 274
 275 static void
 276 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 277 {
 278         struct drm_device *dev = dplane->dev;
 279         struct drm_i915_private *dev_priv = dev->dev_private;
 280         struct intel_plane *intel_plane = to_intel_plane(dplane);
 281         const int pipe = intel_plane->pipe;
 282         const int plane = intel_plane->plane + 1;
 283
 284         I915_WRITE(PLANE_CTL(pipe, plane), 0);
 285
 286         I915_WRITE(PLANE_SURF(pipe, plane), 0);
 287         POSTING_READ(PLANE_SURF(pipe, plane));
 288
 289         intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
 290 }
 291
 292 static void
 293 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 294 {
 295         struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
 296         int plane = intel_plane->plane;
 297
 298         /* Seems RGB data bypasses the CSC always */
 299         if (!format_is_yuv(format))
 300                 return;
 301
 302         /*
 303          * BT.601 limited range YCbCr -> full range RGB
 304          *
 305          * |r|   | 6537 4769     0|   |cr  |
 306          * |g| = |-3330 4769 -1605| x |y-64|
 307          * |b|   |    0 4769  8263|   |cb  |
 308          *
 309          * Cb and Cr apparently come in as signed already, so no
 310          * need for any offset. For Y we need to remove the offset.
 311          */
 312         I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 313         I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 314         I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 315
 316         I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
 317         I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
 318         I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
 319         I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
 320         I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
 321
 322         I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 323         I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 324         I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 325
 326         I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 327         I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 328         I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 329 }
 330
 331 static void
 332 vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 333                  struct drm_framebuffer *fb,
 334                  int crtc_x, int crtc_y,
 335                  unsigned int crtc_w, unsigned int crtc_h,
 336                  uint32_t x, uint32_t y,
 337                  uint32_t src_w, uint32_t src_h)
 338 {
 339         struct drm_device *dev = dplane->dev;
 340         struct drm_i915_private *dev_priv = dev->dev_private;
 341         struct intel_plane *intel_plane = to_intel_plane(dplane);
 342         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 343         int pipe = intel_plane->pipe;
 344         int plane = intel_plane->plane;
 345         u32 sprctl;
 346         unsigned long sprsurf_offset, linear_offset;
 347         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 348         const struct drm_intel_sprite_colorkey *key =
 349                 &to_intel_plane_state(dplane->state)->ckey;
 350
 351         sprctl = SP_ENABLE;
 352
 353         switch (fb->pixel_format) {
 354         case DRM_FORMAT_YUYV:
 355                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 356                 break;
 357         case DRM_FORMAT_YVYU:
 358                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 359                 break;
 360         case DRM_FORMAT_UYVY:
 361                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 362                 break;
 363         case DRM_FORMAT_VYUY:
 364                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 365                 break;
 366         case DRM_FORMAT_RGB565:
 367                 sprctl |= SP_FORMAT_BGR565;
 368                 break;
 369         case DRM_FORMAT_XRGB8888:
 370                 sprctl |= SP_FORMAT_BGRX8888;
 371                 break;
 372         case DRM_FORMAT_ARGB8888:
 373                 sprctl |= SP_FORMAT_BGRA8888;
 374                 break;
 375         case DRM_FORMAT_XBGR2101010:
 376                 sprctl |= SP_FORMAT_RGBX1010102;
 377                 break;
 378         case DRM_FORMAT_ABGR2101010:
 379                 sprctl |= SP_FORMAT_RGBA1010102;
 380                 break;
 381         case DRM_FORMAT_XBGR8888:
 382                 sprctl |= SP_FORMAT_RGBX8888;
 383                 break;
 384         case DRM_FORMAT_ABGR8888:
 385                 sprctl |= SP_FORMAT_RGBA8888;
 386                 break;
 387         default:
 388                 /*
 389                  * If we get here one of the upper layers failed to filter
 390                  * out the unsupported plane formats
 391                  */
 392                 BUG();
 393                 break;
 394         }
 395
 396         /*
 397          * Enable gamma to match primary/cursor plane behaviour.
 398          * FIXME should be user controllable via propertiesa.
 399          */
 400         sprctl |= SP_GAMMA_ENABLE;
 401
 402         if (obj->tiling_mode != I915_TILING_NONE)
 403                 sprctl |= SP_TILED;
 404
 405         intel_update_sprite_watermarks(dplane, crtc, src_w, src_h,
 406                                        pixel_size, true,
 407                                        src_w != crtc_w || src_h != crtc_h);
 408
 409         /* Sizes are 0 based */
 410         src_w--;
 411         src_h--;
 412         crtc_w--;
 413         crtc_h--;
 414
 415         linear_offset = y * fb->pitches[0] + x * pixel_size;
 416         sprsurf_offset = intel_gen4_compute_page_offset(dev_priv,
 417                                                         &x, &y,
 418                                                         obj->tiling_mode,
 419                                                         pixel_size,
 420                                                         fb->pitches[0]);
 421         linear_offset -= sprsurf_offset;
 422
 423         if (dplane->state->rotation == BIT(DRM_ROTATE_180)) {
 424                 sprctl |= SP_ROTATE_180;
 425
 426                 x += src_w;
 427                 y += src_h;
 428                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
 429         }
 430
 431         if (key->flags) {
 432                 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
 433                 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
 434                 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
 435         }
 436
 437         if (key->flags & I915_SET_COLORKEY_SOURCE)
 438                 sprctl |= SP_SOURCE_KEY;
 439
 440         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
 441                 chv_update_csc(intel_plane, fb->pixel_format);
 442
 443         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 444         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 445
 446         if (obj->tiling_mode != I915_TILING_NONE)
 447                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 448         else
 449                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
 450
 451         I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
 452
 453         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 454         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 455         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
 456                    sprsurf_offset);
 457         POSTING_READ(SPSURF(pipe, plane));
 458 }
 459
 460 static void
 461 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 462 {
 463         struct drm_device *dev = dplane->dev;
 464         struct drm_i915_private *dev_priv = dev->dev_private;
 465         struct intel_plane *intel_plane = to_intel_plane(dplane);
 466         int pipe = intel_plane->pipe;
 467         int plane = intel_plane->plane;
 468
 469         I915_WRITE(SPCNTR(pipe, plane), 0);
 470
 471         I915_WRITE(SPSURF(pipe, plane), 0);
 472         POSTING_READ(SPSURF(pipe, plane));
 473
 474         intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
 475 }
 476
 477 static void
 478 ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 479                  struct drm_framebuffer *fb,
 480                  int crtc_x, int crtc_y,
 481                  unsigned int crtc_w, unsigned int crtc_h,
 482                  uint32_t x, uint32_t y,
 483                  uint32_t src_w, uint32_t src_h)
 484 {
 485         struct drm_device *dev = plane->dev;
 486         struct drm_i915_private *dev_priv = dev->dev_private;
 487         struct intel_plane *intel_plane = to_intel_plane(plane);
 488         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 489         enum pipe pipe = intel_plane->pipe;
 490         u32 sprctl, sprscale = 0;
 491         unsigned long sprsurf_offset, linear_offset;
 492         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 493         const struct drm_intel_sprite_colorkey *key =
 494                 &to_intel_plane_state(plane->state)->ckey;
 495
 496         sprctl = SPRITE_ENABLE;
 497
 498         switch (fb->pixel_format) {
 499         case DRM_FORMAT_XBGR8888:
 500                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 501                 break;
 502         case DRM_FORMAT_XRGB8888:
 503                 sprctl |= SPRITE_FORMAT_RGBX888;
 504                 break;
 505         case DRM_FORMAT_YUYV:
 506                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 507                 break;
 508         case DRM_FORMAT_YVYU:
 509                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 510                 break;
 511         case DRM_FORMAT_UYVY:
 512                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 513                 break;
 514         case DRM_FORMAT_VYUY:
 515                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 516                 break;
 517         default:
 518                 BUG();
 519         }
 520
 521         /*
 522          * Enable gamma to match primary/cursor plane behaviour.
 523          * FIXME should be user controllable via propertiesa.
 524          */
 525         sprctl |= SPRITE_GAMMA_ENABLE;
 526
 527         if (obj->tiling_mode != I915_TILING_NONE)
 528                 sprctl |= SPRITE_TILED;
 529
 530         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 531                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 532         else
 533                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 534
 535         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 536                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 537
 538         intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size,
 539                                        true,
 540                                        src_w != crtc_w || src_h != crtc_h);
 541
 542         /* Sizes are 0 based */
 543         src_w--;
 544         src_h--;
 545         crtc_w--;
 546         crtc_h--;
 547
 548         if (crtc_w != src_w || crtc_h != src_h)
 549                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 550
 551         linear_offset = y * fb->pitches[0] + x * pixel_size;
 552         sprsurf_offset =
 553                 intel_gen4_compute_page_offset(dev_priv,
 554                                                &x, &y, obj->tiling_mode,
 555                                                pixel_size, fb->pitches[0]);
 556         linear_offset -= sprsurf_offset;
 557
 558         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
 559                 sprctl |= SPRITE_ROTATE_180;
 560
 561                 /* HSW and BDW does this automagically in hardware */
 562                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
 563                         x += src_w;
 564                         y += src_h;
 565                         linear_offset += src_h * fb->pitches[0] +
 566                                 src_w * pixel_size;
 567                 }
 568         }
 569
 570         if (key->flags) {
 571                 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
 572                 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
 573                 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
 574         }
 575
 576         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 577                 sprctl |= SPRITE_DEST_KEY;
 578         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 579                 sprctl |= SPRITE_SOURCE_KEY;
 580
 581         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 582         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 583
 584         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 585          * register */
 586         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 587                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 588         else if (obj->tiling_mode != I915_TILING_NONE)
 589                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 590         else
 591                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 592
 593         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 594         if (intel_plane->can_scale)
 595                 I915_WRITE(SPRSCALE(pipe), sprscale);
 596         I915_WRITE(SPRCTL(pipe), sprctl);
 597         I915_WRITE(SPRSURF(pipe),
 598                    i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
 599         POSTING_READ(SPRSURF(pipe));
 600 }
 601
 602 static void
 603 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 604 {
 605         struct drm_device *dev = plane->dev;
 606         struct drm_i915_private *dev_priv = dev->dev_private;
 607         struct intel_plane *intel_plane = to_intel_plane(plane);
 608         int pipe = intel_plane->pipe;
 609
 610         I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
 611         /* Can't leave the scaler enabled... */
 612         if (intel_plane->can_scale)
 613                 I915_WRITE(SPRSCALE(pipe), 0);
 614
 615         I915_WRITE(SPRSURF(pipe), 0);
 616         POSTING_READ(SPRSURF(pipe));
 617 }
 618
 619 static void
 620 ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 621                  struct drm_framebuffer *fb,
 622                  int crtc_x, int crtc_y,
 623                  unsigned int crtc_w, unsigned int crtc_h,
 624                  uint32_t x, uint32_t y,
 625                  uint32_t src_w, uint32_t src_h)
 626 {
 627         struct drm_device *dev = plane->dev;
 628         struct drm_i915_private *dev_priv = dev->dev_private;
 629         struct intel_plane *intel_plane = to_intel_plane(plane);
 630         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 631         int pipe = intel_plane->pipe;
 632         unsigned long dvssurf_offset, linear_offset;
 633         u32 dvscntr, dvsscale;
 634         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 635         const struct drm_intel_sprite_colorkey *key =
 636                 &to_intel_plane_state(plane->state)->ckey;
 637
 638         dvscntr = DVS_ENABLE;
 639
 640         switch (fb->pixel_format) {
 641         case DRM_FORMAT_XBGR8888:
 642                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 643                 break;
 644         case DRM_FORMAT_XRGB8888:
 645                 dvscntr |= DVS_FORMAT_RGBX888;
 646                 break;
 647         case DRM_FORMAT_YUYV:
 648                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 649                 break;
 650         case DRM_FORMAT_YVYU:
 651                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 652                 break;
 653         case DRM_FORMAT_UYVY:
 654                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 655                 break;
 656         case DRM_FORMAT_VYUY:
 657                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 658                 break;
 659         default:
 660                 BUG();
 661         }
 662
 663         /*
 664          * Enable gamma to match primary/cursor plane behaviour.
 665          * FIXME should be user controllable via propertiesa.
 666          */
 667         dvscntr |= DVS_GAMMA_ENABLE;
 668
 669         if (obj->tiling_mode != I915_TILING_NONE)
 670                 dvscntr |= DVS_TILED;
 671
 672         if (IS_GEN6(dev))
 673                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 674
 675         intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
 676                                        pixel_size, true,
 677                                        src_w != crtc_w || src_h != crtc_h);
 678
 679         /* Sizes are 0 based */
 680         src_w--;
 681         src_h--;
 682         crtc_w--;
 683         crtc_h--;
 684
 685         dvsscale = 0;
 686         if (crtc_w != src_w || crtc_h != src_h)
 687                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 688
 689         linear_offset = y * fb->pitches[0] + x * pixel_size;
 690         dvssurf_offset =
 691                 intel_gen4_compute_page_offset(dev_priv,
 692                                                &x, &y, obj->tiling_mode,
 693                                                pixel_size, fb->pitches[0]);
 694         linear_offset -= dvssurf_offset;
 695
 696         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
 697                 dvscntr |= DVS_ROTATE_180;
 698
 699                 x += src_w;
 700                 y += src_h;
 701                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
 702         }
 703
 704         if (key->flags) {
 705                 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
 706                 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
 707                 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
 708         }
 709
 710         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 711                 dvscntr |= DVS_DEST_KEY;
 712         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 713                 dvscntr |= DVS_SOURCE_KEY;
 714
 715         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 716         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 717
 718         if (obj->tiling_mode != I915_TILING_NONE)
 719                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 720         else
 721                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 722
 723         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 724         I915_WRITE(DVSSCALE(pipe), dvsscale);
 725         I915_WRITE(DVSCNTR(pipe), dvscntr);
 726         I915_WRITE(DVSSURF(pipe),
 727                    i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
 728         POSTING_READ(DVSSURF(pipe));
 729 }
 730
 731 static void
 732 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 733 {
 734         struct drm_device *dev = plane->dev;
 735         struct drm_i915_private *dev_priv = dev->dev_private;
 736         struct intel_plane *intel_plane = to_intel_plane(plane);
 737         int pipe = intel_plane->pipe;
 738
 739         I915_WRITE(DVSCNTR(pipe), 0);
 740         /* Disable the scaler */
 741         I915_WRITE(DVSSCALE(pipe), 0);
 742
 743         I915_WRITE(DVSSURF(pipe), 0);
 744         POSTING_READ(DVSSURF(pipe));
 745 }
 746
 747 static int
 748 intel_check_sprite_plane(struct drm_plane *plane,
 749                          struct intel_crtc_state *crtc_state,
 750                          struct intel_plane_state *state)
 751 {
 752         struct drm_device *dev = plane->dev;
 753         struct drm_crtc *crtc = state->base.crtc;
 754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 755         struct intel_plane *intel_plane = to_intel_plane(plane);
 756         struct drm_framebuffer *fb = state->base.fb;
 757         int crtc_x, crtc_y;
 758         unsigned int crtc_w, crtc_h;
 759         uint32_t src_x, src_y, src_w, src_h;
 760         struct drm_rect *src = &state->src;
 761         struct drm_rect *dst = &state->dst;
 762         const struct drm_rect *clip = &state->clip;
 763         int hscale, vscale;
 764         int max_scale, min_scale;
 765         bool can_scale;
 766         int pixel_size;
 767
 768         if (!fb) {
 769                 state->visible = false;
 770                 return 0;
 771         }
 772
 773         /* Don't modify another pipe's plane */
 774         if (intel_plane->pipe != intel_crtc->pipe) {
 775                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 776                 return -EINVAL;
 777         }
 778
 779         /* FIXME check all gen limits */
 780         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 781                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 782                 return -EINVAL;
 783         }
 784
 785         /* setup can_scale, min_scale, max_scale */
 786         if (INTEL_INFO(dev)->gen >= 9) {
 787                 /* use scaler when colorkey is not required */
 788                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 789                         can_scale = 1;
 790                         min_scale = 1;
 791                         max_scale = skl_max_scale(intel_crtc, crtc_state);
 792                 } else {
 793                         can_scale = 0;
 794                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 795                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 796                 }
 797         } else {
 798                 can_scale = intel_plane->can_scale;
 799                 max_scale = intel_plane->max_downscale << 16;
 800                 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
 801         }
 802
 803         /*
 804          * FIXME the following code does a bunch of fuzzy adjustments to the
 805          * coordinates and sizes. We probably need some way to decide whether
 806          * more strict checking should be done instead.
 807          */
 808         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 809                         state->base.rotation);
 810
 811         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 812         BUG_ON(hscale < 0);
 813
 814         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 815         BUG_ON(vscale < 0);
 816
 817         state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 818
 819         crtc_x = dst->x1;
 820         crtc_y = dst->y1;
 821         crtc_w = drm_rect_width(dst);
 822         crtc_h = drm_rect_height(dst);
 823
 824         if (state->visible) {
 825                 /* check again in case clipping clamped the results */
 826                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 827                 if (hscale < 0) {
 828                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 829                         drm_rect_debug_print(src, true);
 830                         drm_rect_debug_print(dst, false);
 831
 832                         return hscale;
 833                 }
 834
 835                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 836                 if (vscale < 0) {
 837                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 838                         drm_rect_debug_print(src, true);
 839                         drm_rect_debug_print(dst, false);
 840
 841                         return vscale;
 842                 }
 843
 844                 /* Make the source viewport size an exact multiple of the scaling factors. */
 845                 drm_rect_adjust_size(src,
 846                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 847                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 848
 849                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 850                                     state->base.rotation);
 851
 852                 /* sanity check to make sure the src viewport wasn't enlarged */
 853                 WARN_ON(src->x1 < (int) state->base.src_x ||
 854                         src->y1 < (int) state->base.src_y ||
 855                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 856                         src->y2 > (int) state->base.src_y + state->base.src_h);
 857
 858                 /*
 859                  * Hardware doesn't handle subpixel coordinates.
 860                  * Adjust to (macro)pixel boundary, but be careful not to
 861                  * increase the source viewport size, because that could
 862                  * push the downscaling factor out of bounds.
 863                  */
 864                 src_x = src->x1 >> 16;
 865                 src_w = drm_rect_width(src) >> 16;
 866                 src_y = src->y1 >> 16;
 867                 src_h = drm_rect_height(src) >> 16;
 868
 869                 if (format_is_yuv(fb->pixel_format)) {
 870                         src_x &= ~1;
 871                         src_w &= ~1;
 872
 873                         /*
 874                          * Must keep src and dst the
 875                          * same if we can't scale.
 876                          */
 877                         if (!can_scale)
 878                                 crtc_w &= ~1;
 879
 880                         if (crtc_w == 0)
 881                                 state->visible = false;
 882                 }
 883         }
 884
 885         /* Check size restrictions when scaling */
 886         if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
 887                 unsigned int width_bytes;
 888
 889                 WARN_ON(!can_scale);
 890
 891                 /* FIXME interlacing min height is 6 */
 892
 893                 if (crtc_w < 3 || crtc_h < 3)
 894                         state->visible = false;
 895
 896                 if (src_w < 3 || src_h < 3)
 897                         state->visible = false;
 898
 899                 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 900                 width_bytes = ((src_x * pixel_size) & 63) +
 901                                         src_w * pixel_size;
 902
 903                 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
 904                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 905                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 906                         return -EINVAL;
 907                 }
 908         }
 909
 910         if (state->visible) {
 911                 src->x1 = src_x << 16;
 912                 src->x2 = (src_x + src_w) << 16;
 913                 src->y1 = src_y << 16;
 914                 src->y2 = (src_y + src_h) << 16;
 915         }
 916
 917         dst->x1 = crtc_x;
 918         dst->x2 = crtc_x + crtc_w;
 919         dst->y1 = crtc_y;
 920         dst->y2 = crtc_y + crtc_h;
 921
 922         return 0;
 923 }
 924
 925 static void
 926 intel_commit_sprite_plane(struct drm_plane *plane,
 927                           struct intel_plane_state *state)
 928 {
 929         struct drm_crtc *crtc = state->base.crtc;
 930         struct intel_plane *intel_plane = to_intel_plane(plane);
 931         struct drm_framebuffer *fb = state->base.fb;
 932
 933         crtc = crtc ? crtc : plane->crtc;
 934
 935         plane->fb = fb;
 936
 937         if (!crtc->state->active)
 938                 return;
 939
 940         if (state->visible) {
 941                 intel_plane->update_plane(plane, crtc, fb,
 942                                           state->dst.x1, state->dst.y1,
 943                                           drm_rect_width(&state->dst),
 944                                           drm_rect_height(&state->dst),
 945                                           state->src.x1 >> 16,
 946                                           state->src.y1 >> 16,
 947                                           drm_rect_width(&state->src) >> 16,
 948                                           drm_rect_height(&state->src) >> 16);
 949         } else {
 950                 intel_plane->disable_plane(plane, crtc);
 951         }
 952 }
 953
 954 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 955                               struct drm_file *file_priv)
 956 {
 957         struct drm_intel_sprite_colorkey *set = data;
 958         struct drm_plane *plane;
 959         struct drm_plane_state *plane_state;
 960         struct drm_atomic_state *state;
 961         struct drm_modeset_acquire_ctx ctx;
 962         int ret = 0;
 963
 964         /* Make sure we don't try to enable both src & dest simultaneously */
 965         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 966                 return -EINVAL;
 967
 968         if (IS_VALLEYVIEW(dev) &&
 969             set->flags & I915_SET_COLORKEY_DESTINATION)
 970                 return -EINVAL;
 971
 972         plane = drm_plane_find(dev, set->plane_id);
 973         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
 974                 return -ENOENT;
 975
 976         drm_modeset_acquire_init(&ctx, 0);
 977
 978         state = drm_atomic_state_alloc(plane->dev);
 979         if (!state) {
 980                 ret = -ENOMEM;
 981                 goto out;
 982         }
 983         state->acquire_ctx = &ctx;
 984
 985         while (1) {
 986                 plane_state = drm_atomic_get_plane_state(state, plane);
 987                 ret = PTR_ERR_OR_ZERO(plane_state);
 988                 if (!ret) {
 989                         to_intel_plane_state(plane_state)->ckey = *set;
 990                         ret = drm_atomic_commit(state);
 991                 }
 992
 993                 if (ret != -EDEADLK)
 994                         break;
 995
 996                 drm_atomic_state_clear(state);
 997                 drm_modeset_backoff(&ctx);
 998         }
 999
1000         if (ret)
1001                 drm_atomic_state_free(state);
1002
1003 out:
1004         drm_modeset_drop_locks(&ctx);
1005         drm_modeset_acquire_fini(&ctx);
1006         return ret;
1007 }
1008
1009 static const uint32_t ilk_plane_formats[] = {
1010         DRM_FORMAT_XRGB8888,
1011         DRM_FORMAT_YUYV,
1012         DRM_FORMAT_YVYU,
1013         DRM_FORMAT_UYVY,
1014         DRM_FORMAT_VYUY,
1015 };
1016
1017 static const uint32_t snb_plane_formats[] = {
1018         DRM_FORMAT_XBGR8888,
1019         DRM_FORMAT_XRGB8888,
1020         DRM_FORMAT_YUYV,
1021         DRM_FORMAT_YVYU,
1022         DRM_FORMAT_UYVY,
1023         DRM_FORMAT_VYUY,
1024 };
1025
1026 static const uint32_t vlv_plane_formats[] = {
1027         DRM_FORMAT_RGB565,
1028         DRM_FORMAT_ABGR8888,
1029         DRM_FORMAT_ARGB8888,
1030         DRM_FORMAT_XBGR8888,
1031         DRM_FORMAT_XRGB8888,
1032         DRM_FORMAT_XBGR2101010,
1033         DRM_FORMAT_ABGR2101010,
1034         DRM_FORMAT_YUYV,
1035         DRM_FORMAT_YVYU,
1036         DRM_FORMAT_UYVY,
1037         DRM_FORMAT_VYUY,
1038 };
1039
1040 static uint32_t skl_plane_formats[] = {
1041         DRM_FORMAT_RGB565,
1042         DRM_FORMAT_ABGR8888,
1043         DRM_FORMAT_ARGB8888,
1044         DRM_FORMAT_XBGR8888,
1045         DRM_FORMAT_XRGB8888,
1046         DRM_FORMAT_YUYV,
1047         DRM_FORMAT_YVYU,
1048         DRM_FORMAT_UYVY,
1049         DRM_FORMAT_VYUY,
1050 };
1051
1052 int
1053 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1054 {
1055         struct intel_plane *intel_plane;
1056         struct intel_plane_state *state;
1057         unsigned long possible_crtcs;
1058         const uint32_t *plane_formats;
1059         int num_plane_formats;
1060         int ret;
1061
1062         if (INTEL_INFO(dev)->gen < 5)
1063                 return -ENODEV;
1064
1065         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1066         if (!intel_plane)
1067                 return -ENOMEM;
1068
1069         state = intel_create_plane_state(&intel_plane->base);
1070         if (!state) {
1071                 kfree(intel_plane);
1072                 return -ENOMEM;
1073         }
1074         intel_plane->base.state = &state->base;
1075
1076         switch (INTEL_INFO(dev)->gen) {
1077         case 5:
1078         case 6:
1079                 intel_plane->can_scale = true;
1080                 intel_plane->max_downscale = 16;
1081                 intel_plane->update_plane = ilk_update_plane;
1082                 intel_plane->disable_plane = ilk_disable_plane;
1083
1084                 if (IS_GEN6(dev)) {
1085                         plane_formats = snb_plane_formats;
1086                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1087                 } else {
1088                         plane_formats = ilk_plane_formats;
1089                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1090                 }
1091                 break;
1092
1093         case 7:
1094         case 8:
1095                 if (IS_IVYBRIDGE(dev)) {
1096                         intel_plane->can_scale = true;
1097                         intel_plane->max_downscale = 2;
1098                 } else {
1099                         intel_plane->can_scale = false;
1100                         intel_plane->max_downscale = 1;
1101                 }
1102
1103                 if (IS_VALLEYVIEW(dev)) {
1104                         intel_plane->update_plane = vlv_update_plane;
1105                         intel_plane->disable_plane = vlv_disable_plane;
1106
1107                         plane_formats = vlv_plane_formats;
1108                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1109                 } else {
1110                         intel_plane->update_plane = ivb_update_plane;
1111                         intel_plane->disable_plane = ivb_disable_plane;
1112
1113                         plane_formats = snb_plane_formats;
1114                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1115                 }
1116                 break;
1117         case 9:
1118                 intel_plane->can_scale = true;
1119                 intel_plane->update_plane = skl_update_plane;
1120                 intel_plane->disable_plane = skl_disable_plane;
1121                 state->scaler_id = -1;
1122
1123                 plane_formats = skl_plane_formats;
1124                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1125                 break;
1126         default:
1127                 kfree(intel_plane);
1128                 return -ENODEV;
1129         }
1130
1131         intel_plane->pipe = pipe;
1132         intel_plane->plane = plane;
1133         intel_plane->check_plane = intel_check_sprite_plane;
1134         intel_plane->commit_plane = intel_commit_sprite_plane;
1135         possible_crtcs = (1 << pipe);
1136         ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1137                                        &intel_plane_funcs,
1138                                        plane_formats, num_plane_formats,
1139                                        DRM_PLANE_TYPE_OVERLAY);
1140         if (ret) {
1141                 kfree(intel_plane);
1142                 goto out;
1143         }
1144
1145         intel_create_rotation_property(dev, intel_plane);
1146
1147         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1148
1149 out:
1150         return ret;
1151 }