2 * Copyright © 2006-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
30 * Integrated TV-out support for the 915GM and 945GM.
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
41 TV_MARGIN_LEFT, TV_MARGIN_TOP,
42 TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM
45 /** Private structure for the integrated TV support */
47 struct intel_encoder base;
50 const char *tv_format;
62 u32 save_TV_SC_CTL_1, save_TV_SC_CTL_2, save_TV_SC_CTL_3;
70 u32 save_TV_CLR_KNOBS;
71 u32 save_TV_CLR_LEVEL;
74 u32 save_TV_FILTER_CTL_1;
75 u32 save_TV_FILTER_CTL_2;
76 u32 save_TV_FILTER_CTL_3;
78 u32 save_TV_H_LUMA[60];
79 u32 save_TV_H_CHROMA[60];
80 u32 save_TV_V_LUMA[43];
81 u32 save_TV_V_CHROMA[43];
88 int blank, black, burst;
91 struct color_conversion {
97 static const u32 filter_table[] = {
98 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
99 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
100 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
101 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
102 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
103 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
104 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
105 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
106 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
107 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
108 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
109 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
110 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
111 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
112 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
113 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
114 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
115 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
116 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
117 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
118 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
119 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
120 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
121 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
122 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
123 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
124 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
125 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
126 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
127 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
128 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0,
129 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
130 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
131 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
132 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
133 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
134 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
135 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
136 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
137 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
138 0x28003100, 0x28002F00, 0x00003100, 0x36403000,
139 0x2D002CC0, 0x30003640, 0x2D0036C0,
140 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
141 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
142 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
143 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
144 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
145 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
146 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
147 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
148 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
149 0x28003100, 0x28002F00, 0x00003100,
153 * Color conversion values have 3 separate fixed point formats:
155 * 10 bit fields (ay, au)
156 * 1.9 fixed point (b.bbbbbbbbb)
157 * 11 bit fields (ry, by, ru, gu, gv)
158 * exp.mantissa (ee.mmmmmmmmm)
159 * ee = 00 = 10^-1 (0.mmmmmmmmm)
160 * ee = 01 = 10^-2 (0.0mmmmmmmmm)
161 * ee = 10 = 10^-3 (0.00mmmmmmmmm)
162 * ee = 11 = 10^-4 (0.000mmmmmmmmm)
163 * 12 bit fields (gy, rv, bu)
164 * exp.mantissa (eee.mmmmmmmmm)
165 * eee = 000 = 10^-1 (0.mmmmmmmmm)
166 * eee = 001 = 10^-2 (0.0mmmmmmmmm)
167 * eee = 010 = 10^-3 (0.00mmmmmmmmm)
168 * eee = 011 = 10^-4 (0.000mmmmmmmmm)
169 * eee = 100 = reserved
170 * eee = 101 = reserved
171 * eee = 110 = reserved
172 * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation)
174 * Saturation and contrast are 8 bits, with their own representation:
175 * 8 bit field (saturation, contrast)
176 * exp.mantissa (ee.mmmmmm)
177 * ee = 00 = 10^-1 (0.mmmmmm)
178 * ee = 01 = 10^0 (m.mmmmm)
179 * ee = 10 = 10^1 (mm.mmmm)
180 * ee = 11 = 10^2 (mmm.mmm)
182 * Simple conversion function:
185 * float_to_csc_11(float f)
198 * for (exp = 0; exp < 3 && f < 0.5; exp++)
200 * mant = (f * (1 << 9) + 0.5);
201 * if (mant >= (1 << 9))
202 * mant = (1 << 9) - 1;
204 * ret = (exp << 9) | mant;
210 * Behold, magic numbers! If we plant them they might grow a big
211 * s-video cable to the sky... or something.
213 * Pre-converted to appropriate hex value.
217 * PAL & NTSC values for composite & s-video connections
219 static const struct color_conversion ntsc_m_csc_composite = {
220 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
221 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
222 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
225 static const struct video_levels ntsc_m_levels_composite = {
226 .blank = 225, .black = 267, .burst = 113,
229 static const struct color_conversion ntsc_m_csc_svideo = {
230 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
231 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
232 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
235 static const struct video_levels ntsc_m_levels_svideo = {
236 .blank = 266, .black = 316, .burst = 133,
239 static const struct color_conversion ntsc_j_csc_composite = {
240 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119,
241 .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200,
242 .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200,
245 static const struct video_levels ntsc_j_levels_composite = {
246 .blank = 225, .black = 225, .burst = 113,
249 static const struct color_conversion ntsc_j_csc_svideo = {
250 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c,
251 .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200,
252 .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200,
255 static const struct video_levels ntsc_j_levels_svideo = {
256 .blank = 266, .black = 266, .burst = 133,
259 static const struct color_conversion pal_csc_composite = {
260 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113,
261 .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200,
262 .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200,
265 static const struct video_levels pal_levels_composite = {
266 .blank = 237, .black = 237, .burst = 118,
269 static const struct color_conversion pal_csc_svideo = {
270 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
271 .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200,
272 .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200,
275 static const struct video_levels pal_levels_svideo = {
276 .blank = 280, .black = 280, .burst = 139,
279 static const struct color_conversion pal_m_csc_composite = {
280 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
281 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
282 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
285 static const struct video_levels pal_m_levels_composite = {
286 .blank = 225, .black = 267, .burst = 113,
289 static const struct color_conversion pal_m_csc_svideo = {
290 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
291 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
292 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
295 static const struct video_levels pal_m_levels_svideo = {
296 .blank = 266, .black = 316, .burst = 133,
299 static const struct color_conversion pal_n_csc_composite = {
300 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
301 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
302 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
305 static const struct video_levels pal_n_levels_composite = {
306 .blank = 225, .black = 267, .burst = 118,
309 static const struct color_conversion pal_n_csc_svideo = {
310 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
311 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
312 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
315 static const struct video_levels pal_n_levels_svideo = {
316 .blank = 266, .black = 316, .burst = 139,
320 * Component connections
322 static const struct color_conversion sdtv_csc_yprpb = {
323 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
324 .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200,
325 .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200,
328 static const struct color_conversion sdtv_csc_rgb = {
329 .ry = 0x0000, .gy = 0x0f00, .by = 0x0000, .ay = 0x0166,
330 .ru = 0x0000, .gu = 0x0000, .bu = 0x0f00, .au = 0x0166,
331 .rv = 0x0f00, .gv = 0x0000, .bv = 0x0000, .av = 0x0166,
334 static const struct color_conversion hdtv_csc_yprpb = {
335 .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145,
336 .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200,
337 .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200,
340 static const struct color_conversion hdtv_csc_rgb = {
341 .ry = 0x0000, .gy = 0x0f00, .by = 0x0000, .ay = 0x0166,
342 .ru = 0x0000, .gu = 0x0000, .bu = 0x0f00, .au = 0x0166,
343 .rv = 0x0f00, .gv = 0x0000, .bv = 0x0000, .av = 0x0166,
346 static const struct video_levels component_levels = {
347 .blank = 279, .black = 279, .burst = 0,
354 int refresh; /* in millihertz (for precision) */
356 int hsync_end, hblank_start, hblank_end, htotal;
357 bool progressive, trilevel_sync, component_only;
358 int vsync_start_f1, vsync_start_f2, vsync_len;
360 int veq_start_f1, veq_start_f2, veq_len;
361 int vi_end_f1, vi_end_f2, nbr_end;
363 int hburst_start, hburst_len;
364 int vburst_start_f1, vburst_end_f1;
365 int vburst_start_f2, vburst_end_f2;
366 int vburst_start_f3, vburst_end_f3;
367 int vburst_start_f4, vburst_end_f4;
369 * subcarrier programming
371 int dda2_size, dda3_size, dda1_inc, dda2_inc, dda3_inc;
377 const struct video_levels *composite_levels, *svideo_levels;
378 const struct color_conversion *composite_color, *svideo_color;
379 const u32 *filter_table;
387 * I think this works as follows:
389 * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096
391 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value
394 * dda1_ideal = subcarrier/pixel * 4096
395 * dda1_inc = floor (dda1_ideal)
396 * dda2 = dda1_ideal - dda1_inc
398 * then pick a ratio for dda2 that gives the closest approximation. If
399 * you can't get close enough, you can play with dda3 as well. This
400 * seems likely to happen when dda2 is small as the jumps would be larger
404 * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size)
406 * The constants below were all computed using a 107.520MHz clock
410 * Register programming values for TV modes.
412 * These values account for -1s required.
415 static const struct tv_mode tv_modes[] = {
420 .oversample = TV_OVERSAMPLE_8X,
422 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
424 .hsync_end = 64, .hblank_end = 124,
425 .hblank_start = 836, .htotal = 857,
427 .progressive = false, .trilevel_sync = false,
429 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
432 .veq_ena = true, .veq_start_f1 = 0,
433 .veq_start_f2 = 1, .veq_len = 18,
435 .vi_end_f1 = 20, .vi_end_f2 = 21,
439 .hburst_start = 72, .hburst_len = 34,
440 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
441 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
442 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
443 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
445 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
447 .dda2_inc = 20800, .dda2_size = 27456,
448 .dda3_inc = 0, .dda3_size = 0,
449 .sc_reset = TV_SC_RESET_EVERY_4,
452 .composite_levels = &ntsc_m_levels_composite,
453 .composite_color = &ntsc_m_csc_composite,
454 .svideo_levels = &ntsc_m_levels_svideo,
455 .svideo_color = &ntsc_m_csc_svideo,
457 .filter_table = filter_table,
463 .oversample = TV_OVERSAMPLE_8X,
465 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
466 .hsync_end = 64, .hblank_end = 124,
467 .hblank_start = 836, .htotal = 857,
469 .progressive = false, .trilevel_sync = false,
471 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
474 .veq_ena = true, .veq_start_f1 = 0,
475 .veq_start_f2 = 1, .veq_len = 18,
477 .vi_end_f1 = 20, .vi_end_f2 = 21,
481 .hburst_start = 72, .hburst_len = 34,
482 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
483 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
484 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
485 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
487 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
489 .dda2_inc = 4093, .dda2_size = 27456,
490 .dda3_inc = 310, .dda3_size = 525,
491 .sc_reset = TV_SC_RESET_NEVER,
494 .composite_levels = &ntsc_m_levels_composite,
495 .composite_color = &ntsc_m_csc_composite,
496 .svideo_levels = &ntsc_m_levels_svideo,
497 .svideo_color = &ntsc_m_csc_svideo,
499 .filter_table = filter_table,
505 .oversample = TV_OVERSAMPLE_8X,
508 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
509 .hsync_end = 64, .hblank_end = 124,
510 .hblank_start = 836, .htotal = 857,
512 .progressive = false, .trilevel_sync = false,
514 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
517 .veq_ena = true, .veq_start_f1 = 0,
518 .veq_start_f2 = 1, .veq_len = 18,
520 .vi_end_f1 = 20, .vi_end_f2 = 21,
524 .hburst_start = 72, .hburst_len = 34,
525 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
526 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
527 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
528 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
530 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
532 .dda2_inc = 20800, .dda2_size = 27456,
533 .dda3_inc = 0, .dda3_size = 0,
534 .sc_reset = TV_SC_RESET_EVERY_4,
537 .composite_levels = &ntsc_j_levels_composite,
538 .composite_color = &ntsc_j_csc_composite,
539 .svideo_levels = &ntsc_j_levels_svideo,
540 .svideo_color = &ntsc_j_csc_svideo,
542 .filter_table = filter_table,
548 .oversample = TV_OVERSAMPLE_8X,
551 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
552 .hsync_end = 64, .hblank_end = 124,
553 .hblank_start = 836, .htotal = 857,
555 .progressive = false, .trilevel_sync = false,
557 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
560 .veq_ena = true, .veq_start_f1 = 0,
561 .veq_start_f2 = 1, .veq_len = 18,
563 .vi_end_f1 = 20, .vi_end_f2 = 21,
567 .hburst_start = 72, .hburst_len = 34,
568 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
569 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
570 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
571 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
573 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
575 .dda2_inc = 16704, .dda2_size = 27456,
576 .dda3_inc = 0, .dda3_size = 0,
577 .sc_reset = TV_SC_RESET_EVERY_8,
580 .composite_levels = &pal_m_levels_composite,
581 .composite_color = &pal_m_csc_composite,
582 .svideo_levels = &pal_m_levels_svideo,
583 .svideo_color = &pal_m_csc_svideo,
585 .filter_table = filter_table,
588 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
592 .oversample = TV_OVERSAMPLE_8X,
595 .hsync_end = 64, .hblank_end = 128,
596 .hblank_start = 844, .htotal = 863,
598 .progressive = false, .trilevel_sync = false,
601 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
604 .veq_ena = true, .veq_start_f1 = 0,
605 .veq_start_f2 = 1, .veq_len = 18,
607 .vi_end_f1 = 24, .vi_end_f2 = 25,
611 .hburst_start = 73, .hburst_len = 34,
612 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
613 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
614 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
615 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
618 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
620 .dda2_inc = 23578, .dda2_size = 27648,
621 .dda3_inc = 134, .dda3_size = 625,
622 .sc_reset = TV_SC_RESET_EVERY_8,
625 .composite_levels = &pal_n_levels_composite,
626 .composite_color = &pal_n_csc_composite,
627 .svideo_levels = &pal_n_levels_svideo,
628 .svideo_color = &pal_n_csc_svideo,
630 .filter_table = filter_table,
633 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
637 .oversample = TV_OVERSAMPLE_8X,
640 .hsync_end = 64, .hblank_end = 142,
641 .hblank_start = 844, .htotal = 863,
643 .progressive = false, .trilevel_sync = false,
645 .vsync_start_f1 = 5, .vsync_start_f2 = 6,
648 .veq_ena = true, .veq_start_f1 = 0,
649 .veq_start_f2 = 1, .veq_len = 15,
651 .vi_end_f1 = 24, .vi_end_f2 = 25,
655 .hburst_start = 73, .hburst_len = 32,
656 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
657 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
658 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
659 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
661 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
663 .dda2_inc = 4122, .dda2_size = 27648,
664 .dda3_inc = 67, .dda3_size = 625,
665 .sc_reset = TV_SC_RESET_EVERY_8,
668 .composite_levels = &pal_levels_composite,
669 .composite_color = &pal_csc_composite,
670 .svideo_levels = &pal_levels_svideo,
671 .svideo_color = &pal_csc_svideo,
673 .filter_table = filter_table,
679 .oversample = TV_OVERSAMPLE_4X,
682 .hsync_end = 64, .hblank_end = 122,
683 .hblank_start = 842, .htotal = 857,
685 .progressive = true, .trilevel_sync = false,
687 .vsync_start_f1 = 12, .vsync_start_f2 = 12,
692 .vi_end_f1 = 44, .vi_end_f2 = 44,
697 .filter_table = filter_table,
703 .oversample = TV_OVERSAMPLE_4X,
706 .hsync_end = 64, .hblank_end = 139,
707 .hblank_start = 859, .htotal = 863,
709 .progressive = true, .trilevel_sync = false,
711 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
716 .vi_end_f1 = 48, .vi_end_f2 = 48,
721 .filter_table = filter_table,
727 .oversample = TV_OVERSAMPLE_2X,
730 .hsync_end = 80, .hblank_end = 300,
731 .hblank_start = 1580, .htotal = 1649,
733 .progressive = true, .trilevel_sync = true,
735 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
740 .vi_end_f1 = 29, .vi_end_f2 = 29,
745 .filter_table = filter_table,
751 .oversample = TV_OVERSAMPLE_2X,
754 .hsync_end = 80, .hblank_end = 300,
755 .hblank_start = 1580, .htotal = 1979,
757 .progressive = true, .trilevel_sync = true,
759 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
764 .vi_end_f1 = 29, .vi_end_f2 = 29,
769 .filter_table = filter_table,
773 .name = "1080i@50Hz",
776 .oversample = TV_OVERSAMPLE_2X,
779 .hsync_end = 88, .hblank_end = 235,
780 .hblank_start = 2155, .htotal = 2639,
782 .progressive = false, .trilevel_sync = true,
784 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
787 .veq_ena = true, .veq_start_f1 = 4,
788 .veq_start_f2 = 4, .veq_len = 10,
791 .vi_end_f1 = 21, .vi_end_f2 = 22,
796 .filter_table = filter_table,
799 .name = "1080i@60Hz",
802 .oversample = TV_OVERSAMPLE_2X,
805 .hsync_end = 88, .hblank_end = 235,
806 .hblank_start = 2155, .htotal = 2199,
808 .progressive = false, .trilevel_sync = true,
810 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
813 .veq_ena = true, .veq_start_f1 = 4,
814 .veq_start_f2 = 4, .veq_len = 10,
817 .vi_end_f1 = 21, .vi_end_f2 = 22,
822 .filter_table = filter_table,
826 static struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder)
828 return container_of(encoder, struct intel_tv, base.base);
831 static struct intel_tv *intel_attached_tv(struct drm_connector *connector)
833 return container_of(intel_attached_encoder(connector),
839 intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
841 struct drm_device *dev = encoder->base.dev;
842 struct drm_i915_private *dev_priv = dev->dev_private;
843 u32 tmp = I915_READ(TV_CTL);
845 if (!(tmp & TV_ENC_ENABLE))
848 *pipe = PORT_TO_PIPE(tmp);
854 intel_enable_tv(struct intel_encoder *encoder)
856 struct drm_device *dev = encoder->base.dev;
857 struct drm_i915_private *dev_priv = dev->dev_private;
859 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
863 intel_disable_tv(struct intel_encoder *encoder)
865 struct drm_device *dev = encoder->base.dev;
866 struct drm_i915_private *dev_priv = dev->dev_private;
868 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
871 static const struct tv_mode *
872 intel_tv_mode_lookup(const char *tv_format)
876 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
877 const struct tv_mode *tv_mode = &tv_modes[i];
879 if (!strcmp(tv_format, tv_mode->name))
885 static const struct tv_mode *
886 intel_tv_mode_find(struct intel_tv *intel_tv)
888 return intel_tv_mode_lookup(intel_tv->tv_format);
891 static enum drm_mode_status
892 intel_tv_mode_valid(struct drm_connector *connector,
893 struct drm_display_mode *mode)
895 struct intel_tv *intel_tv = intel_attached_tv(connector);
896 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
898 /* Ensure TV refresh is close to desired refresh */
899 if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
903 return MODE_CLOCK_RANGE;
908 intel_tv_mode_fixup(struct drm_encoder *encoder,
909 const struct drm_display_mode *mode,
910 struct drm_display_mode *adjusted_mode)
912 struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
913 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
918 if (intel_encoder_check_is_cloned(&intel_tv->base))
921 adjusted_mode->clock = tv_mode->clock;
926 intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
927 struct drm_display_mode *adjusted_mode)
929 struct drm_device *dev = encoder->dev;
930 struct drm_i915_private *dev_priv = dev->dev_private;
931 struct drm_crtc *crtc = encoder->crtc;
932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
933 struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
934 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
936 u32 hctl1, hctl2, hctl3;
937 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
938 u32 scctl1, scctl2, scctl3;
940 const struct video_levels *video_levels;
941 const struct color_conversion *color_conversion;
943 int pipe = intel_crtc->pipe;
946 return; /* can't happen (mode_prepare prevents this) */
948 tv_ctl = I915_READ(TV_CTL);
949 tv_ctl &= TV_CTL_SAVE;
951 switch (intel_tv->type) {
953 case DRM_MODE_CONNECTOR_Unknown:
954 case DRM_MODE_CONNECTOR_Composite:
955 tv_ctl |= TV_ENC_OUTPUT_COMPOSITE;
956 video_levels = tv_mode->composite_levels;
957 color_conversion = tv_mode->composite_color;
958 burst_ena = tv_mode->burst_ena;
960 case DRM_MODE_CONNECTOR_Component:
961 tv_ctl |= TV_ENC_OUTPUT_COMPONENT;
962 video_levels = &component_levels;
963 if (tv_mode->burst_ena)
964 color_conversion = &sdtv_csc_yprpb;
966 color_conversion = &hdtv_csc_yprpb;
969 case DRM_MODE_CONNECTOR_SVIDEO:
970 tv_ctl |= TV_ENC_OUTPUT_SVIDEO;
971 video_levels = tv_mode->svideo_levels;
972 color_conversion = tv_mode->svideo_color;
973 burst_ena = tv_mode->burst_ena;
976 hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
977 (tv_mode->htotal << TV_HTOTAL_SHIFT);
979 hctl2 = (tv_mode->hburst_start << 16) |
980 (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
983 hctl2 |= TV_BURST_ENA;
985 hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
986 (tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
988 vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
989 (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
990 (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
992 vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
993 (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
994 (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
996 vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
997 (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
998 (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
1000 if (tv_mode->veq_ena)
1001 vctl3 |= TV_EQUAL_ENA;
1003 vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
1004 (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
1006 vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
1007 (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
1009 vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
1010 (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
1012 vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
1013 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
1015 if (intel_crtc->pipe == 1)
1016 tv_ctl |= TV_ENC_PIPEB_SELECT;
1017 tv_ctl |= tv_mode->oversample;
1019 if (tv_mode->progressive)
1020 tv_ctl |= TV_PROGRESSIVE;
1021 if (tv_mode->trilevel_sync)
1022 tv_ctl |= TV_TRILEVEL_SYNC;
1023 if (tv_mode->pal_burst)
1024 tv_ctl |= TV_PAL_BURST;
1027 if (tv_mode->dda1_inc)
1028 scctl1 |= TV_SC_DDA1_EN;
1029 if (tv_mode->dda2_inc)
1030 scctl1 |= TV_SC_DDA2_EN;
1031 if (tv_mode->dda3_inc)
1032 scctl1 |= TV_SC_DDA3_EN;
1033 scctl1 |= tv_mode->sc_reset;
1035 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
1036 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT;
1038 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT |
1039 tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT;
1041 scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT |
1042 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
1044 /* Enable two fixes for the chips that need them. */
1045 if (dev->pci_device < 0x2772)
1046 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
1048 I915_WRITE(TV_H_CTL_1, hctl1);
1049 I915_WRITE(TV_H_CTL_2, hctl2);
1050 I915_WRITE(TV_H_CTL_3, hctl3);
1051 I915_WRITE(TV_V_CTL_1, vctl1);
1052 I915_WRITE(TV_V_CTL_2, vctl2);
1053 I915_WRITE(TV_V_CTL_3, vctl3);
1054 I915_WRITE(TV_V_CTL_4, vctl4);
1055 I915_WRITE(TV_V_CTL_5, vctl5);
1056 I915_WRITE(TV_V_CTL_6, vctl6);
1057 I915_WRITE(TV_V_CTL_7, vctl7);
1058 I915_WRITE(TV_SC_CTL_1, scctl1);
1059 I915_WRITE(TV_SC_CTL_2, scctl2);
1060 I915_WRITE(TV_SC_CTL_3, scctl3);
1062 if (color_conversion) {
1063 I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) |
1064 color_conversion->gy);
1065 I915_WRITE(TV_CSC_Y2, (color_conversion->by << 16) |
1066 color_conversion->ay);
1067 I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) |
1068 color_conversion->gu);
1069 I915_WRITE(TV_CSC_U2, (color_conversion->bu << 16) |
1070 color_conversion->au);
1071 I915_WRITE(TV_CSC_V, (color_conversion->rv << 16) |
1072 color_conversion->gv);
1073 I915_WRITE(TV_CSC_V2, (color_conversion->bv << 16) |
1074 color_conversion->av);
1077 if (INTEL_INFO(dev)->gen >= 4)
1078 I915_WRITE(TV_CLR_KNOBS, 0x00404000);
1080 I915_WRITE(TV_CLR_KNOBS, 0x00606000);
1083 I915_WRITE(TV_CLR_LEVEL,
1084 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
1085 (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
1087 int pipeconf_reg = PIPECONF(pipe);
1088 int dspcntr_reg = DSPCNTR(intel_crtc->plane);
1089 int pipeconf = I915_READ(pipeconf_reg);
1090 int dspcntr = I915_READ(dspcntr_reg);
1091 int dspbase_reg = DSPADDR(intel_crtc->plane);
1092 int xpos = 0x0, ypos = 0x0;
1093 unsigned int xsize, ysize;
1094 /* Pipe must be off here */
1095 I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE);
1096 /* Flush the plane changes */
1097 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1099 /* Wait for vblank for the disable to take effect */
1101 intel_wait_for_vblank(dev, intel_crtc->pipe);
1103 I915_WRITE(pipeconf_reg, pipeconf & ~PIPECONF_ENABLE);
1104 /* Wait for vblank for the disable to take effect. */
1105 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
1107 /* Filter ctl must be set before TV_WIN_SIZE */
1108 I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE);
1109 xsize = tv_mode->hblank_start - tv_mode->hblank_end;
1110 if (tv_mode->progressive)
1111 ysize = tv_mode->nbr_end + 1;
1113 ysize = 2*tv_mode->nbr_end + 1;
1115 xpos += intel_tv->margin[TV_MARGIN_LEFT];
1116 ypos += intel_tv->margin[TV_MARGIN_TOP];
1117 xsize -= (intel_tv->margin[TV_MARGIN_LEFT] +
1118 intel_tv->margin[TV_MARGIN_RIGHT]);
1119 ysize -= (intel_tv->margin[TV_MARGIN_TOP] +
1120 intel_tv->margin[TV_MARGIN_BOTTOM]);
1121 I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
1122 I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);
1124 I915_WRITE(pipeconf_reg, pipeconf);
1125 I915_WRITE(dspcntr_reg, dspcntr);
1126 /* Flush the plane changes */
1127 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1131 for (i = 0; i < 60; i++)
1132 I915_WRITE(TV_H_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
1133 for (i = 0; i < 60; i++)
1134 I915_WRITE(TV_H_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
1135 for (i = 0; i < 43; i++)
1136 I915_WRITE(TV_V_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
1137 for (i = 0; i < 43; i++)
1138 I915_WRITE(TV_V_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
1139 I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE);
1140 I915_WRITE(TV_CTL, tv_ctl);
1143 static const struct drm_display_mode reported_modes[] = {
1145 .name = "NTSC 480i",
1148 .hsync_start = 1368,
1153 .vsync_start = 1027,
1156 .type = DRM_MODE_TYPE_DRIVER,
1161 * Detects TV presence by checking for load.
1163 * Requires that the current pipe's DPLL is active.
1165 * \return true if TV is connected.
1166 * \return false if TV is disconnected.
1169 intel_tv_detect_type(struct intel_tv *intel_tv,
1170 struct drm_connector *connector)
1172 struct drm_encoder *encoder = &intel_tv->base.base;
1173 struct drm_crtc *crtc = encoder->crtc;
1174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1175 struct drm_device *dev = encoder->dev;
1176 struct drm_i915_private *dev_priv = dev->dev_private;
1177 unsigned long irqflags;
1178 u32 tv_ctl, save_tv_ctl;
1179 u32 tv_dac, save_tv_dac;
1182 /* Disable TV interrupts around load detect or we'll recurse */
1183 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1184 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1185 i915_disable_pipestat(dev_priv, 0,
1186 PIPE_HOTPLUG_INTERRUPT_ENABLE |
1187 PIPE_HOTPLUG_TV_INTERRUPT_ENABLE);
1188 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1191 save_tv_dac = tv_dac = I915_READ(TV_DAC);
1192 save_tv_ctl = tv_ctl = I915_READ(TV_CTL);
1194 /* Poll for TV detection */
1195 tv_ctl &= ~(TV_ENC_ENABLE | TV_TEST_MODE_MASK);
1196 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
1197 if (intel_crtc->pipe == 1)
1198 tv_ctl |= TV_ENC_PIPEB_SELECT;
1200 tv_ctl &= ~TV_ENC_PIPEB_SELECT;
1202 tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK);
1203 tv_dac |= (TVDAC_STATE_CHG_EN |
1214 * The TV sense state should be cleared to zero on cantiga platform. Otherwise
1215 * the TV is misdetected. This is hardware requirement.
1218 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
1219 TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
1221 I915_WRITE(TV_CTL, tv_ctl);
1222 I915_WRITE(TV_DAC, tv_dac);
1223 POSTING_READ(TV_DAC);
1225 intel_wait_for_vblank(intel_tv->base.base.dev,
1226 to_intel_crtc(intel_tv->base.base.crtc)->pipe);
1229 tv_dac = I915_READ(TV_DAC);
1230 DRM_DEBUG_KMS("TV detected: %x, %x\n", tv_ctl, tv_dac);
1237 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
1238 DRM_DEBUG_KMS("Detected Composite TV connection\n");
1239 type = DRM_MODE_CONNECTOR_Composite;
1240 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
1241 DRM_DEBUG_KMS("Detected S-Video TV connection\n");
1242 type = DRM_MODE_CONNECTOR_SVIDEO;
1243 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
1244 DRM_DEBUG_KMS("Detected Component TV connection\n");
1245 type = DRM_MODE_CONNECTOR_Component;
1247 DRM_DEBUG_KMS("Unrecognised TV connection\n");
1251 I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1252 I915_WRITE(TV_CTL, save_tv_ctl);
1253 POSTING_READ(TV_CTL);
1255 /* For unknown reasons the hw barfs if we don't do this vblank wait. */
1256 intel_wait_for_vblank(intel_tv->base.base.dev,
1257 to_intel_crtc(intel_tv->base.base.crtc)->pipe);
1259 /* Restore interrupt config */
1260 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1261 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1262 i915_enable_pipestat(dev_priv, 0,
1263 PIPE_HOTPLUG_INTERRUPT_ENABLE |
1264 PIPE_HOTPLUG_TV_INTERRUPT_ENABLE);
1265 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1272 * Here we set accurate tv format according to connector type
1273 * i.e Component TV should not be assigned by NTSC or PAL
1275 static void intel_tv_find_better_format(struct drm_connector *connector)
1277 struct intel_tv *intel_tv = intel_attached_tv(connector);
1278 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1281 if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
1282 tv_mode->component_only)
1286 for (i = 0; i < sizeof(tv_modes) / sizeof(*tv_modes); i++) {
1287 tv_mode = tv_modes + i;
1289 if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
1290 tv_mode->component_only)
1294 intel_tv->tv_format = tv_mode->name;
1295 drm_connector_property_set_value(connector,
1296 connector->dev->mode_config.tv_mode_property, i);
1300 * Detect the TV connection.
1302 * Currently this always returns CONNECTOR_STATUS_UNKNOWN, as we need to be sure
1303 * we have a pipe programmed in order to probe the TV.
1305 static enum drm_connector_status
1306 intel_tv_detect(struct drm_connector *connector, bool force)
1308 struct drm_display_mode mode;
1309 struct intel_tv *intel_tv = intel_attached_tv(connector);
1312 mode = reported_modes[0];
1315 struct intel_load_detect_pipe tmp;
1317 if (intel_get_load_detect_pipe(connector, &mode, &tmp)) {
1318 type = intel_tv_detect_type(intel_tv, connector);
1319 intel_release_load_detect_pipe(connector, &tmp);
1321 return connector_status_unknown;
1323 return connector->status;
1326 return connector_status_disconnected;
1328 intel_tv->type = type;
1329 intel_tv_find_better_format(connector);
1331 return connector_status_connected;
1334 static const struct input_res {
1337 } input_res_table[] = {
1338 {"640x480", 640, 480},
1339 {"800x600", 800, 600},
1340 {"1024x768", 1024, 768},
1341 {"1280x1024", 1280, 1024},
1342 {"848x480", 848, 480},
1343 {"1280x720", 1280, 720},
1344 {"1920x1080", 1920, 1080},
1348 * Chose preferred mode according to line number of TV format
1351 intel_tv_chose_preferred_modes(struct drm_connector *connector,
1352 struct drm_display_mode *mode_ptr)
1354 struct intel_tv *intel_tv = intel_attached_tv(connector);
1355 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1357 if (tv_mode->nbr_end < 480 && mode_ptr->vdisplay == 480)
1358 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1359 else if (tv_mode->nbr_end > 480) {
1360 if (tv_mode->progressive == true && tv_mode->nbr_end < 720) {
1361 if (mode_ptr->vdisplay == 720)
1362 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1363 } else if (mode_ptr->vdisplay == 1080)
1364 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1369 * Stub get_modes function.
1371 * This should probably return a set of fixed modes, unless we can figure out
1372 * how to probe modes off of TV connections.
1376 intel_tv_get_modes(struct drm_connector *connector)
1378 struct drm_display_mode *mode_ptr;
1379 struct intel_tv *intel_tv = intel_attached_tv(connector);
1380 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1384 for (j = 0; j < ARRAY_SIZE(input_res_table);
1386 const struct input_res *input = &input_res_table[j];
1387 unsigned int hactive_s = input->w;
1388 unsigned int vactive_s = input->h;
1390 if (tv_mode->max_srcw && input->w > tv_mode->max_srcw)
1393 if (input->w > 1024 && (!tv_mode->progressive
1394 && !tv_mode->component_only))
1397 mode_ptr = drm_mode_create(connector->dev);
1400 strncpy(mode_ptr->name, input->name, DRM_DISPLAY_MODE_LEN);
1402 mode_ptr->hdisplay = hactive_s;
1403 mode_ptr->hsync_start = hactive_s + 1;
1404 mode_ptr->hsync_end = hactive_s + 64;
1405 if (mode_ptr->hsync_end <= mode_ptr->hsync_start)
1406 mode_ptr->hsync_end = mode_ptr->hsync_start + 1;
1407 mode_ptr->htotal = hactive_s + 96;
1409 mode_ptr->vdisplay = vactive_s;
1410 mode_ptr->vsync_start = vactive_s + 1;
1411 mode_ptr->vsync_end = vactive_s + 32;
1412 if (mode_ptr->vsync_end <= mode_ptr->vsync_start)
1413 mode_ptr->vsync_end = mode_ptr->vsync_start + 1;
1414 mode_ptr->vtotal = vactive_s + 33;
1416 tmp = (u64) tv_mode->refresh * mode_ptr->vtotal;
1417 tmp *= mode_ptr->htotal;
1418 tmp = div_u64(tmp, 1000000);
1419 mode_ptr->clock = (int) tmp;
1421 mode_ptr->type = DRM_MODE_TYPE_DRIVER;
1422 intel_tv_chose_preferred_modes(connector, mode_ptr);
1423 drm_mode_probed_add(connector, mode_ptr);
1431 intel_tv_destroy(struct drm_connector *connector)
1433 drm_sysfs_connector_remove(connector);
1434 drm_connector_cleanup(connector);
1440 intel_tv_set_property(struct drm_connector *connector, struct drm_property *property,
1443 struct drm_device *dev = connector->dev;
1444 struct intel_tv *intel_tv = intel_attached_tv(connector);
1445 struct drm_crtc *crtc = intel_tv->base.base.crtc;
1447 bool changed = false;
1449 ret = drm_connector_property_set_value(connector, property, val);
1453 if (property == dev->mode_config.tv_left_margin_property &&
1454 intel_tv->margin[TV_MARGIN_LEFT] != val) {
1455 intel_tv->margin[TV_MARGIN_LEFT] = val;
1457 } else if (property == dev->mode_config.tv_right_margin_property &&
1458 intel_tv->margin[TV_MARGIN_RIGHT] != val) {
1459 intel_tv->margin[TV_MARGIN_RIGHT] = val;
1461 } else if (property == dev->mode_config.tv_top_margin_property &&
1462 intel_tv->margin[TV_MARGIN_TOP] != val) {
1463 intel_tv->margin[TV_MARGIN_TOP] = val;
1465 } else if (property == dev->mode_config.tv_bottom_margin_property &&
1466 intel_tv->margin[TV_MARGIN_BOTTOM] != val) {
1467 intel_tv->margin[TV_MARGIN_BOTTOM] = val;
1469 } else if (property == dev->mode_config.tv_mode_property) {
1470 if (val >= ARRAY_SIZE(tv_modes)) {
1474 if (!strcmp(intel_tv->tv_format, tv_modes[val].name))
1477 intel_tv->tv_format = tv_modes[val].name;
1484 if (changed && crtc)
1485 intel_set_mode(crtc, &crtc->mode,
1486 crtc->x, crtc->y, crtc->fb);
1491 static const struct drm_encoder_helper_funcs intel_tv_helper_funcs = {
1492 .mode_fixup = intel_tv_mode_fixup,
1493 .mode_set = intel_tv_mode_set,
1494 .disable = intel_encoder_noop,
1497 static const struct drm_connector_funcs intel_tv_connector_funcs = {
1498 .dpms = intel_connector_dpms,
1499 .detect = intel_tv_detect,
1500 .destroy = intel_tv_destroy,
1501 .set_property = intel_tv_set_property,
1502 .fill_modes = drm_helper_probe_single_connector_modes,
1505 static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = {
1506 .mode_valid = intel_tv_mode_valid,
1507 .get_modes = intel_tv_get_modes,
1508 .best_encoder = intel_best_encoder,
1511 static const struct drm_encoder_funcs intel_tv_enc_funcs = {
1512 .destroy = intel_encoder_destroy,
1516 * Enumerate the child dev array parsed from VBT to check whether
1517 * the integrated TV is present.
1518 * If it is present, return 1.
1519 * If it is not present, return false.
1520 * If no child dev is parsed from VBT, it assumes that the TV is present.
1522 static int tv_is_present_in_vbt(struct drm_device *dev)
1524 struct drm_i915_private *dev_priv = dev->dev_private;
1525 struct child_device_config *p_child;
1528 if (!dev_priv->child_dev_num)
1532 for (i = 0; i < dev_priv->child_dev_num; i++) {
1533 p_child = dev_priv->child_dev + i;
1535 * If the device type is not TV, continue.
1537 if (p_child->device_type != DEVICE_TYPE_INT_TV &&
1538 p_child->device_type != DEVICE_TYPE_TV)
1540 /* Only when the addin_offset is non-zero, it is regarded
1543 if (p_child->addin_offset) {
1552 intel_tv_init(struct drm_device *dev)
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 struct drm_connector *connector;
1556 struct intel_tv *intel_tv;
1557 struct intel_encoder *intel_encoder;
1558 struct intel_connector *intel_connector;
1559 u32 tv_dac_on, tv_dac_off, save_tv_dac;
1560 char *tv_format_names[ARRAY_SIZE(tv_modes)];
1561 int i, initial_mode = 0;
1563 if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
1566 if (!tv_is_present_in_vbt(dev)) {
1567 DRM_DEBUG_KMS("Integrated TV is not present.\n");
1570 /* Even if we have an encoder we may not have a connector */
1571 if (!dev_priv->int_tv_support)
1575 * Sanity check the TV output by checking to see if the
1576 * DAC register holds a value
1578 save_tv_dac = I915_READ(TV_DAC);
1580 I915_WRITE(TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
1581 tv_dac_on = I915_READ(TV_DAC);
1583 I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1584 tv_dac_off = I915_READ(TV_DAC);
1586 I915_WRITE(TV_DAC, save_tv_dac);
1589 * If the register does not hold the state change enable
1590 * bit, (either as a 0 or a 1), assume it doesn't really
1593 if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
1594 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
1597 intel_tv = kzalloc(sizeof(struct intel_tv), GFP_KERNEL);
1602 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1603 if (!intel_connector) {
1608 intel_encoder = &intel_tv->base;
1609 connector = &intel_connector->base;
1611 /* The documentation, for the older chipsets at least, recommend
1612 * using a polling method rather than hotplug detection for TVs.
1613 * This is because in order to perform the hotplug detection, the PLLs
1614 * for the TV must be kept alive increasing power drain and starving
1615 * bandwidth from other encoders. Notably for instance, it causes
1616 * pipe underruns on Crestline when this encoder is supposedly idle.
1618 * More recent chipsets favour HDMI rather than integrated S-Video.
1620 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1622 drm_connector_init(dev, connector, &intel_tv_connector_funcs,
1623 DRM_MODE_CONNECTOR_SVIDEO);
1625 drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs,
1626 DRM_MODE_ENCODER_TVDAC);
1628 intel_encoder->enable = intel_enable_tv;
1629 intel_encoder->disable = intel_disable_tv;
1630 intel_encoder->get_hw_state = intel_tv_get_hw_state;
1631 intel_connector->get_hw_state = intel_connector_get_hw_state;
1633 intel_connector_attach_encoder(intel_connector, intel_encoder);
1634 intel_encoder->type = INTEL_OUTPUT_TVOUT;
1635 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1636 intel_encoder->cloneable = false;
1637 intel_encoder->base.possible_crtcs = ((1 << 0) | (1 << 1));
1638 intel_encoder->base.possible_clones = (1 << INTEL_OUTPUT_TVOUT);
1639 intel_tv->type = DRM_MODE_CONNECTOR_Unknown;
1641 /* BIOS margin values */
1642 intel_tv->margin[TV_MARGIN_LEFT] = 54;
1643 intel_tv->margin[TV_MARGIN_TOP] = 36;
1644 intel_tv->margin[TV_MARGIN_RIGHT] = 46;
1645 intel_tv->margin[TV_MARGIN_BOTTOM] = 37;
1647 intel_tv->tv_format = tv_modes[initial_mode].name;
1649 drm_encoder_helper_add(&intel_encoder->base, &intel_tv_helper_funcs);
1650 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
1651 connector->interlace_allowed = false;
1652 connector->doublescan_allowed = false;
1654 /* Create TV properties then attach current values */
1655 for (i = 0; i < ARRAY_SIZE(tv_modes); i++)
1656 tv_format_names[i] = (char *)tv_modes[i].name;
1657 drm_mode_create_tv_properties(dev,
1658 ARRAY_SIZE(tv_modes),
1661 drm_connector_attach_property(connector, dev->mode_config.tv_mode_property,
1663 drm_connector_attach_property(connector,
1664 dev->mode_config.tv_left_margin_property,
1665 intel_tv->margin[TV_MARGIN_LEFT]);
1666 drm_connector_attach_property(connector,
1667 dev->mode_config.tv_top_margin_property,
1668 intel_tv->margin[TV_MARGIN_TOP]);
1669 drm_connector_attach_property(connector,
1670 dev->mode_config.tv_right_margin_property,
1671 intel_tv->margin[TV_MARGIN_RIGHT]);
1672 drm_connector_attach_property(connector,
1673 dev->mode_config.tv_bottom_margin_property,
1674 intel_tv->margin[TV_MARGIN_BOTTOM]);
1675 drm_sysfs_connector_add(connector);