2 * i.MX drm driver - LVDS display bridge
4 * Copyright (C) 2012 Sascha Hauer, Pengutronix
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/module.h>
17 #include <linux/clk.h>
18 #include <linux/component.h>
20 #include <drm/drm_fb_helper.h>
21 #include <drm/drm_crtc_helper.h>
22 #include <drm/drm_panel.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
25 #include <linux/of_device.h>
26 #include <linux/of_graph.h>
27 #include <video/of_videomode.h>
28 #include <linux/regmap.h>
29 #include <linux/videodev2.h>
33 #define DRIVER_NAME "imx-ldb"
35 #define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
36 #define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
37 #define LDB_CH0_MODE_EN_MASK (3 << 0)
38 #define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
39 #define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
40 #define LDB_CH1_MODE_EN_MASK (3 << 2)
41 #define LDB_SPLIT_MODE_EN (1 << 4)
42 #define LDB_DATA_WIDTH_CH0_24 (1 << 5)
43 #define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
44 #define LDB_DATA_WIDTH_CH1_24 (1 << 7)
45 #define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
46 #define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
47 #define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
48 #define LDB_BGREF_RMODE_INT (1 << 15)
50 #define con_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, connector)
51 #define enc_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, encoder)
55 struct imx_ldb_channel {
57 struct drm_connector connector;
58 struct drm_encoder encoder;
59 struct drm_panel *panel;
60 struct device_node *child;
64 struct drm_display_mode mode;
75 struct regmap *regmap;
77 struct imx_ldb_channel channel[2];
78 struct clk *clk[2]; /* our own clock */
79 struct clk *clk_sel[4]; /* parent of display clock */
80 struct clk *clk_parent[4]; /* original parent of clk_sel */
81 struct clk *clk_pll[2]; /* upstream clock we can adjust */
83 const struct bus_mux *lvds_mux;
86 static enum drm_connector_status imx_ldb_connector_detect(
87 struct drm_connector *connector, bool force)
89 return connector_status_connected;
92 static int imx_ldb_connector_get_modes(struct drm_connector *connector)
94 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
97 if (imx_ldb_ch->panel && imx_ldb_ch->panel->funcs &&
98 imx_ldb_ch->panel->funcs->get_modes) {
99 num_modes = imx_ldb_ch->panel->funcs->get_modes(imx_ldb_ch->panel);
104 if (imx_ldb_ch->edid) {
105 drm_mode_connector_update_edid_property(connector,
107 num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
110 if (imx_ldb_ch->mode_valid) {
111 struct drm_display_mode *mode;
113 mode = drm_mode_create(connector->dev);
116 drm_mode_copy(mode, &imx_ldb_ch->mode);
117 mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
118 drm_mode_probed_add(connector, mode);
125 static struct drm_encoder *imx_ldb_connector_best_encoder(
126 struct drm_connector *connector)
128 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
130 return &imx_ldb_ch->encoder;
133 static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode)
137 static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder,
138 const struct drm_display_mode *mode,
139 struct drm_display_mode *adjusted_mode)
144 static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
145 unsigned long serial_clk, unsigned long di_clk)
149 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
150 clk_get_rate(ldb->clk_pll[chno]), serial_clk);
151 clk_set_rate(ldb->clk_pll[chno], serial_clk);
153 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
154 clk_get_rate(ldb->clk_pll[chno]));
156 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
157 clk_get_rate(ldb->clk[chno]),
159 clk_set_rate(ldb->clk[chno], di_clk);
161 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
162 clk_get_rate(ldb->clk[chno]));
164 /* set display clock mux to LDB input clock */
165 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
168 "unable to set di%d parent clock to ldb_di%d\n", mux,
172 static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
174 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
175 struct imx_ldb *ldb = imx_ldb_ch->ldb;
178 switch (imx_ldb_ch->chno) {
180 bus_format = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH0_24) ?
181 MEDIA_BUS_FMT_RGB888_1X24 : MEDIA_BUS_FMT_RGB666_1X18;
184 bus_format = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH1_24) ?
185 MEDIA_BUS_FMT_RGB888_1X24 : MEDIA_BUS_FMT_RGB666_1X18;
188 dev_err(ldb->dev, "unable to config di%d panel format\n",
190 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
193 imx_drm_set_bus_format(encoder, bus_format);
196 static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
198 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
199 struct imx_ldb *ldb = imx_ldb_ch->ldb;
200 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
201 int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
203 drm_panel_prepare(imx_ldb_ch->panel);
206 clk_prepare_enable(ldb->clk[0]);
207 clk_prepare_enable(ldb->clk[1]);
210 if (imx_ldb_ch == &ldb->channel[0] || dual) {
211 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
212 if (mux == 0 || ldb->lvds_mux)
213 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
215 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
217 if (imx_ldb_ch == &ldb->channel[1] || dual) {
218 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
219 if (mux == 1 || ldb->lvds_mux)
220 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
222 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
226 const struct bus_mux *lvds_mux = NULL;
228 if (imx_ldb_ch == &ldb->channel[0])
229 lvds_mux = &ldb->lvds_mux[0];
230 else if (imx_ldb_ch == &ldb->channel[1])
231 lvds_mux = &ldb->lvds_mux[1];
233 regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
234 mux << lvds_mux->shift);
237 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
239 drm_panel_enable(imx_ldb_ch->panel);
242 static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder,
243 struct drm_display_mode *orig_mode,
244 struct drm_display_mode *mode)
246 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
247 struct imx_ldb *ldb = imx_ldb_ch->ldb;
248 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
249 unsigned long serial_clk;
250 unsigned long di_clk = mode->clock * 1000;
251 int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
253 if (mode->clock > 170000) {
255 "%s: mode exceeds 170 MHz pixel clock\n", __func__);
257 if (mode->clock > 85000 && !dual) {
259 "%s: mode exceeds 85 MHz pixel clock\n", __func__);
263 serial_clk = 3500UL * mode->clock;
264 imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
265 imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
267 serial_clk = 7000UL * mode->clock;
268 imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
272 /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
273 if (imx_ldb_ch == &ldb->channel[0]) {
274 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
275 ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
276 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
277 ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
279 if (imx_ldb_ch == &ldb->channel[1]) {
280 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
281 ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
282 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
283 ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
287 static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
289 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
290 struct imx_ldb *ldb = imx_ldb_ch->ldb;
294 * imx_ldb_encoder_disable is called by
295 * drm_helper_disable_unused_functions without
296 * the encoder being enabled before.
298 if (imx_ldb_ch == &ldb->channel[0] &&
299 (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0)
301 else if (imx_ldb_ch == &ldb->channel[1] &&
302 (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0)
305 drm_panel_disable(imx_ldb_ch->panel);
307 if (imx_ldb_ch == &ldb->channel[0])
308 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
309 else if (imx_ldb_ch == &ldb->channel[1])
310 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
312 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
314 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
315 clk_disable_unprepare(ldb->clk[0]);
316 clk_disable_unprepare(ldb->clk[1]);
320 const struct bus_mux *lvds_mux = NULL;
322 if (imx_ldb_ch == &ldb->channel[0])
323 lvds_mux = &ldb->lvds_mux[0];
324 else if (imx_ldb_ch == &ldb->channel[1])
325 lvds_mux = &ldb->lvds_mux[1];
327 regmap_read(ldb->regmap, lvds_mux->reg, &mux);
328 mux &= lvds_mux->mask;
329 mux >>= lvds_mux->shift;
331 mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
334 /* set display clock mux back to original input clock */
335 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
338 "unable to set di%d parent clock to original parent\n",
341 drm_panel_unprepare(imx_ldb_ch->panel);
344 static struct drm_connector_funcs imx_ldb_connector_funcs = {
345 .dpms = drm_helper_connector_dpms,
346 .fill_modes = drm_helper_probe_single_connector_modes,
347 .detect = imx_ldb_connector_detect,
348 .destroy = imx_drm_connector_destroy,
351 static struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
352 .get_modes = imx_ldb_connector_get_modes,
353 .best_encoder = imx_ldb_connector_best_encoder,
356 static struct drm_encoder_funcs imx_ldb_encoder_funcs = {
357 .destroy = imx_drm_encoder_destroy,
360 static struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
361 .dpms = imx_ldb_encoder_dpms,
362 .mode_fixup = imx_ldb_encoder_mode_fixup,
363 .prepare = imx_ldb_encoder_prepare,
364 .commit = imx_ldb_encoder_commit,
365 .mode_set = imx_ldb_encoder_mode_set,
366 .disable = imx_ldb_encoder_disable,
369 static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
373 snprintf(clkname, sizeof(clkname), "di%d", chno);
374 ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
375 if (IS_ERR(ldb->clk[chno]))
376 return PTR_ERR(ldb->clk[chno]);
378 snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
379 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
381 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
384 static int imx_ldb_register(struct drm_device *drm,
385 struct imx_ldb_channel *imx_ldb_ch)
387 struct imx_ldb *ldb = imx_ldb_ch->ldb;
390 ret = imx_drm_encoder_parse_of(drm, &imx_ldb_ch->encoder,
395 ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
399 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
400 ret = imx_ldb_get_clk(ldb, 1);
405 drm_encoder_helper_add(&imx_ldb_ch->encoder,
406 &imx_ldb_encoder_helper_funcs);
407 drm_encoder_init(drm, &imx_ldb_ch->encoder, &imx_ldb_encoder_funcs,
408 DRM_MODE_ENCODER_LVDS);
410 drm_connector_helper_add(&imx_ldb_ch->connector,
411 &imx_ldb_connector_helper_funcs);
412 drm_connector_init(drm, &imx_ldb_ch->connector,
413 &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS);
415 if (imx_ldb_ch->panel)
416 drm_panel_attach(imx_ldb_ch->panel, &imx_ldb_ch->connector);
418 drm_mode_connector_attach_encoder(&imx_ldb_ch->connector,
419 &imx_ldb_ch->encoder);
429 static const char * const imx_ldb_bit_mappings[] = {
430 [LVDS_BIT_MAP_SPWG] = "spwg",
431 [LVDS_BIT_MAP_JEIDA] = "jeida",
434 static const int of_get_data_mapping(struct device_node *np)
439 ret = of_property_read_string(np, "fsl,data-mapping", &bm);
443 for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++)
444 if (!strcasecmp(bm, imx_ldb_bit_mappings[i]))
450 static struct bus_mux imx6q_lvds_mux[2] = {
454 .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
458 .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
463 * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
464 * of_match_device will walk through this list and take the first entry
465 * matching any of its compatible values. Therefore, the more generic
466 * entries (in this case fsl,imx53-ldb) need to be ordered last.
468 static const struct of_device_id imx_ldb_dt_ids[] = {
469 { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
470 { .compatible = "fsl,imx53-ldb", .data = NULL, },
473 MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
475 static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
477 struct drm_device *drm = data;
478 struct device_node *np = dev->of_node;
479 const struct of_device_id *of_id =
480 of_match_device(imx_ldb_dt_ids, dev);
481 struct device_node *child;
483 struct imx_ldb *imx_ldb;
490 imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
494 imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
495 if (IS_ERR(imx_ldb->regmap)) {
496 dev_err(dev, "failed to get parent regmap\n");
497 return PTR_ERR(imx_ldb->regmap);
503 imx_ldb->lvds_mux = of_id->data;
505 dual = of_property_read_bool(np, "fsl,dual-channel");
507 imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
510 * There are three different possible clock mux configurations:
511 * i.MX53: ipu1_di0_sel, ipu1_di1_sel
512 * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
513 * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
514 * Map them all to di0_sel...di3_sel.
516 for (i = 0; i < 4; i++) {
519 sprintf(clkname, "di%d_sel", i);
520 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
521 if (IS_ERR(imx_ldb->clk_sel[i])) {
522 ret = PTR_ERR(imx_ldb->clk_sel[i]);
523 imx_ldb->clk_sel[i] = NULL;
527 imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
532 for_each_child_of_node(np, child) {
533 struct imx_ldb_channel *channel;
534 struct device_node *port;
536 ret = of_property_read_u32(child, "reg", &i);
537 if (ret || i < 0 || i > 1)
541 dev_warn(dev, "dual-channel mode, ignoring second output\n");
545 if (!of_device_is_available(child))
548 channel = &imx_ldb->channel[i];
549 channel->ldb = imx_ldb;
551 channel->child = child;
554 * The output port is port@4 with an external 4-port mux or
555 * port@2 with the internal 2-port mux.
557 port = of_graph_get_port_by_id(child, imx_ldb->lvds_mux ? 4 : 2);
559 struct device_node *endpoint, *remote;
561 endpoint = of_get_child_by_name(port, "endpoint");
563 remote = of_graph_get_remote_port_parent(endpoint);
565 channel->panel = of_drm_find_panel(remote);
567 return -EPROBE_DEFER;
568 if (!channel->panel) {
569 dev_err(dev, "panel not found: %s\n",
571 return -EPROBE_DEFER;
576 edidp = of_get_property(child, "edid", &channel->edid_len);
578 channel->edid = kmemdup(edidp, channel->edid_len,
580 } else if (!channel->panel) {
581 ret = of_get_drm_display_mode(child, &channel->mode, 0);
583 channel->mode_valid = 1;
586 ret = of_property_read_u32(child, "fsl,data-width", &datawidth);
589 else if (datawidth != 18 && datawidth != 24)
592 mapping = of_get_data_mapping(child);
594 case LVDS_BIT_MAP_SPWG:
595 if (datawidth == 24) {
598 LDB_DATA_WIDTH_CH0_24;
601 LDB_DATA_WIDTH_CH1_24;
604 case LVDS_BIT_MAP_JEIDA:
605 if (datawidth == 18) {
606 dev_err(dev, "JEIDA standard only supported in 24 bit\n");
610 imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
611 LDB_BIT_MAP_CH0_JEIDA;
613 imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
614 LDB_BIT_MAP_CH1_JEIDA;
617 dev_err(dev, "data mapping not specified or invalid\n");
621 ret = imx_ldb_register(drm, channel);
626 dev_set_drvdata(dev, imx_ldb);
631 static void imx_ldb_unbind(struct device *dev, struct device *master,
634 struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
637 for (i = 0; i < 2; i++) {
638 struct imx_ldb_channel *channel = &imx_ldb->channel[i];
640 if (!channel->connector.funcs)
643 channel->connector.funcs->destroy(&channel->connector);
644 channel->encoder.funcs->destroy(&channel->encoder);
646 kfree(channel->edid);
650 static const struct component_ops imx_ldb_ops = {
651 .bind = imx_ldb_bind,
652 .unbind = imx_ldb_unbind,
655 static int imx_ldb_probe(struct platform_device *pdev)
657 return component_add(&pdev->dev, &imx_ldb_ops);
660 static int imx_ldb_remove(struct platform_device *pdev)
662 component_del(&pdev->dev, &imx_ldb_ops);
666 static struct platform_driver imx_ldb_driver = {
667 .probe = imx_ldb_probe,
668 .remove = imx_ldb_remove,
670 .of_match_table = imx_ldb_dt_ids,
675 module_platform_driver(imx_ldb_driver);
677 MODULE_DESCRIPTION("i.MX LVDS driver");
678 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
679 MODULE_LICENSE("GPL");
680 MODULE_ALIAS("platform:" DRIVER_NAME);