2 * Copyright 2010 Matt Turner.
3 * Copyright 2012 Red Hat
5 * This file is subject to the terms and conditions of the GNU General
6 * Public License version 2. See the file COPYING in the main
7 * directory of this archive for more details.
9 * Authors: Matthew Garrett
14 #include <linux/delay.h>
17 #include <drm/drm_crtc_helper.h>
19 #include "mgag200_drv.h"
21 #define MGAG200_LUT_SIZE 256
24 * This file contains setup code for the CRTC.
27 static void mga_crtc_load_lut(struct drm_crtc *crtc)
29 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
30 struct drm_device *dev = crtc->dev;
31 struct mga_device *mdev = dev->dev_private;
37 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
39 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
41 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]);
42 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
43 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]);
47 static inline void mga_wait_vsync(struct mga_device *mdev)
49 unsigned long timeout = jiffies + HZ/10;
50 unsigned int status = 0;
53 status = RREG32(MGAREG_Status);
54 } while ((status & 0x08) && time_before(jiffies, timeout));
55 timeout = jiffies + HZ/10;
58 status = RREG32(MGAREG_Status);
59 } while (!(status & 0x08) && time_before(jiffies, timeout));
62 static inline void mga_wait_busy(struct mga_device *mdev)
64 unsigned long timeout = jiffies + HZ;
65 unsigned int status = 0;
67 status = RREG8(MGAREG_Status + 2);
68 } while ((status & 0x01) && time_before(jiffies, timeout));
72 * The core passes the desired mode to the CRTC code to see whether any
73 * CRTC-specific modifications need to be made to it. We're in a position
74 * to just pass that straight through, so this does nothing
76 static bool mga_crtc_mode_fixup(struct drm_crtc *crtc,
77 const struct drm_display_mode *mode,
78 struct drm_display_mode *adjusted_mode)
83 static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
85 unsigned int vcomax, vcomin, pllreffreq;
86 unsigned int delta, tmpdelta, permitteddelta;
87 unsigned int testp, testm, testn;
89 unsigned int computed;
97 permitteddelta = clock * 5 / 1000;
99 for (testp = 8; testp > 0; testp /= 2) {
100 if (clock * testp > vcomax)
102 if (clock * testp < vcomin)
105 for (testn = 17; testn < 256; testn++) {
106 for (testm = 1; testm < 32; testm++) {
107 computed = (pllreffreq * testn) /
109 if (computed > clock)
110 tmpdelta = computed - clock;
112 tmpdelta = clock - computed;
113 if (tmpdelta < delta) {
123 if (delta > permitteddelta) {
124 printk(KERN_WARNING "PLL delta too large\n");
128 WREG_DAC(MGA1064_PIX_PLLC_M, m);
129 WREG_DAC(MGA1064_PIX_PLLC_N, n);
130 WREG_DAC(MGA1064_PIX_PLLC_P, p);
134 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
136 unsigned int vcomax, vcomin, pllreffreq;
137 unsigned int delta, tmpdelta, permitteddelta;
138 unsigned int testp, testm, testn;
139 unsigned int p, m, n;
140 unsigned int computed;
141 int i, j, tmpcount, vcount;
142 bool pll_locked = false;
151 permitteddelta = clock * 5 / 1000;
153 for (testp = 1; testp < 9; testp++) {
154 if (clock * testp > vcomax)
156 if (clock * testp < vcomin)
159 for (testm = 1; testm < 17; testm++) {
160 for (testn = 1; testn < 151; testn++) {
161 computed = (pllreffreq * testn) /
163 if (computed > clock)
164 tmpdelta = computed - clock;
166 tmpdelta = clock - computed;
167 if (tmpdelta < delta) {
170 m = (testm - 1) | ((n >> 1) & 0x80);
177 for (i = 0; i <= 32 && pll_locked == false; i++) {
179 WREG8(MGAREG_CRTC_INDEX, 0x1e);
180 tmp = RREG8(MGAREG_CRTC_DATA);
182 WREG8(MGAREG_CRTC_DATA, tmp+1);
185 /* set pixclkdis to 1 */
186 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
187 tmp = RREG8(DAC_DATA);
188 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
189 WREG8(DAC_DATA, tmp);
191 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
192 tmp = RREG8(DAC_DATA);
193 tmp |= MGA1064_REMHEADCTL_CLKDIS;
194 WREG8(DAC_DATA, tmp);
196 /* select PLL Set C */
197 tmp = RREG8(MGAREG_MEM_MISC_READ);
199 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
201 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
202 tmp = RREG8(DAC_DATA);
203 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
204 WREG8(DAC_DATA, tmp);
209 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
210 tmp = RREG8(DAC_DATA);
212 WREG8(DAC_DATA, tmp);
216 /* program pixel pll register */
217 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
218 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
219 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
224 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
225 tmp = RREG8(DAC_DATA);
227 WREG_DAC(MGA1064_VREF_CTL, tmp);
231 /* select the pixel pll */
232 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
233 tmp = RREG8(DAC_DATA);
234 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
235 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
236 WREG8(DAC_DATA, tmp);
238 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
239 tmp = RREG8(DAC_DATA);
240 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
241 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
242 WREG8(DAC_DATA, tmp);
244 /* reset dotclock rate bit */
245 WREG8(MGAREG_SEQ_INDEX, 1);
246 tmp = RREG8(MGAREG_SEQ_DATA);
248 WREG8(MGAREG_SEQ_DATA, tmp);
250 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
251 tmp = RREG8(DAC_DATA);
252 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
253 WREG8(DAC_DATA, tmp);
255 vcount = RREG8(MGAREG_VCOUNT);
257 for (j = 0; j < 30 && pll_locked == false; j++) {
258 tmpcount = RREG8(MGAREG_VCOUNT);
259 if (tmpcount < vcount)
261 if ((tmpcount - vcount) > 2)
267 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
268 tmp = RREG8(DAC_DATA);
269 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
270 WREG_DAC(MGA1064_REMHEADCTL, tmp);
274 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
276 unsigned int vcomax, vcomin, pllreffreq;
277 unsigned int delta, tmpdelta, permitteddelta;
278 unsigned int testp, testm, testn;
279 unsigned int p, m, n;
280 unsigned int computed;
289 permitteddelta = clock * 5 / 1000;
291 for (testp = 16; testp > 0; testp--) {
292 if (clock * testp > vcomax)
294 if (clock * testp < vcomin)
297 for (testn = 1; testn < 257; testn++) {
298 for (testm = 1; testm < 17; testm++) {
299 computed = (pllreffreq * testn) /
301 if (computed > clock)
302 tmpdelta = computed - clock;
304 tmpdelta = clock - computed;
305 if (tmpdelta < delta) {
315 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
316 tmp = RREG8(DAC_DATA);
317 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
318 WREG8(DAC_DATA, tmp);
320 tmp = RREG8(MGAREG_MEM_MISC_READ);
322 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
324 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
325 tmp = RREG8(DAC_DATA);
326 WREG8(DAC_DATA, tmp & ~0x40);
328 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
329 tmp = RREG8(DAC_DATA);
330 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
331 WREG8(DAC_DATA, tmp);
333 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
334 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
335 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
339 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
340 tmp = RREG8(DAC_DATA);
341 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
342 WREG8(DAC_DATA, tmp);
346 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
347 tmp = RREG8(DAC_DATA);
348 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
349 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
350 WREG8(DAC_DATA, tmp);
352 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
353 tmp = RREG8(DAC_DATA);
354 WREG8(DAC_DATA, tmp | 0x40);
356 tmp = RREG8(MGAREG_MEM_MISC_READ);
358 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
360 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
361 tmp = RREG8(DAC_DATA);
362 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
363 WREG8(DAC_DATA, tmp);
368 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
370 unsigned int vcomax, vcomin, pllreffreq;
371 unsigned int delta, tmpdelta, permitteddelta;
372 unsigned int testp, testm, testn;
373 unsigned int p, m, n;
374 unsigned int computed;
375 int i, j, tmpcount, vcount;
377 bool pll_locked = false;
385 permitteddelta = clock * 5 / 1000;
387 for (testp = 16; testp > 0; testp >>= 1) {
388 if (clock * testp > vcomax)
390 if (clock * testp < vcomin)
393 for (testm = 1; testm < 33; testm++) {
394 for (testn = 17; testn < 257; testn++) {
395 computed = (pllreffreq * testn) /
397 if (computed > clock)
398 tmpdelta = computed - clock;
400 tmpdelta = clock - computed;
401 if (tmpdelta < delta) {
407 if ((clock * testp) >= 600000)
412 for (i = 0; i <= 32 && pll_locked == false; i++) {
413 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
414 tmp = RREG8(DAC_DATA);
415 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
416 WREG8(DAC_DATA, tmp);
418 tmp = RREG8(MGAREG_MEM_MISC_READ);
420 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
422 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
423 tmp = RREG8(DAC_DATA);
424 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
425 WREG8(DAC_DATA, tmp);
429 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
430 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
431 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
435 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
436 tmp = RREG8(DAC_DATA);
437 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
438 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
439 WREG8(DAC_DATA, tmp);
441 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
442 tmp = RREG8(DAC_DATA);
443 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
444 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
445 WREG8(DAC_DATA, tmp);
447 vcount = RREG8(MGAREG_VCOUNT);
449 for (j = 0; j < 30 && pll_locked == false; j++) {
450 tmpcount = RREG8(MGAREG_VCOUNT);
451 if (tmpcount < vcount)
453 if ((tmpcount - vcount) > 2)
463 static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
465 unsigned int vcomax, vcomin, pllreffreq;
466 unsigned int delta, tmpdelta;
467 int testr, testn, testm, testo;
468 unsigned int p, m, n;
469 unsigned int computed, vco;
471 const unsigned int m_div_val[] = { 1, 2, 4, 8 };
480 for (testr = 0; testr < 4; testr++) {
483 for (testn = 5; testn < 129; testn++) {
486 for (testm = 3; testm >= 0; testm--) {
489 for (testo = 5; testo < 33; testo++) {
490 vco = pllreffreq * (testn + 1) /
496 computed = vco / (m_div_val[testm] * (testo + 1));
497 if (computed > clock)
498 tmpdelta = computed - clock;
500 tmpdelta = clock - computed;
501 if (tmpdelta < delta) {
503 m = testm | (testo << 3);
505 p = testr | (testr << 3);
512 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
513 tmp = RREG8(DAC_DATA);
514 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
515 WREG8(DAC_DATA, tmp);
517 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
518 tmp = RREG8(DAC_DATA);
519 tmp |= MGA1064_REMHEADCTL_CLKDIS;
520 WREG8(DAC_DATA, tmp);
522 tmp = RREG8(MGAREG_MEM_MISC_READ);
523 tmp |= (0x3<<2) | 0xc0;
524 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
526 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
527 tmp = RREG8(DAC_DATA);
528 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
529 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
530 WREG8(DAC_DATA, tmp);
534 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
535 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
536 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
543 static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
548 return mga_g200se_set_plls(mdev, clock);
551 return mga_g200wb_set_plls(mdev, clock);
554 return mga_g200ev_set_plls(mdev, clock);
557 return mga_g200eh_set_plls(mdev, clock);
560 return mga_g200er_set_plls(mdev, clock);
566 static void mga_g200wb_prepare(struct drm_crtc *crtc)
568 struct mga_device *mdev = crtc->dev->dev_private;
572 /* 1- The first step is to warn the BMC of an upcoming mode change.
573 * We are putting the misc<0> to output.*/
575 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
576 tmp = RREG8(DAC_DATA);
578 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
580 /* we are putting a 1 on the misc<0> line */
581 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
582 tmp = RREG8(DAC_DATA);
584 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
586 /* 2- Second step to mask and further scan request
587 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
589 WREG8(DAC_INDEX, MGA1064_SPAREREG);
590 tmp = RREG8(DAC_DATA);
592 WREG_DAC(MGA1064_SPAREREG, tmp);
594 /* 3a- the third step is to verifu if there is an active scan
595 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
598 while (!(tmp & 0x1) && iter_max) {
599 WREG8(DAC_INDEX, MGA1064_SPAREREG);
600 tmp = RREG8(DAC_DATA);
605 /* 3b- this step occurs only if the remove is actually scanning
606 * we are waiting for the end of the frame which is a 1 on
607 * remvsyncsts (XSPAREREG<1>)
611 while ((tmp & 0x2) && iter_max) {
612 WREG8(DAC_INDEX, MGA1064_SPAREREG);
613 tmp = RREG8(DAC_DATA);
620 static void mga_g200wb_commit(struct drm_crtc *crtc)
623 struct mga_device *mdev = crtc->dev->dev_private;
625 /* 1- The first step is to ensure that the vrsten and hrsten are set */
626 WREG8(MGAREG_CRTCEXT_INDEX, 1);
627 tmp = RREG8(MGAREG_CRTCEXT_DATA);
628 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
630 /* 2- second step is to assert the rstlvl2 */
631 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
632 tmp = RREG8(DAC_DATA);
634 WREG8(DAC_DATA, tmp);
639 /* 3- deassert rstlvl2 */
641 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
642 WREG8(DAC_DATA, tmp);
644 /* 4- remove mask of scan request */
645 WREG8(DAC_INDEX, MGA1064_SPAREREG);
646 tmp = RREG8(DAC_DATA);
648 WREG8(DAC_DATA, tmp);
650 /* 5- put back a 0 on the misc<0> line */
651 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
652 tmp = RREG8(DAC_DATA);
654 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
658 This is how the framebuffer base address is stored in g200 cards:
659 * Assume @offset is the gpu_addr variable of the framebuffer object
660 * Then addr is the number of _pixels_ (not bytes) from the start of
661 VRAM to the first pixel we want to display. (divided by 2 for 32bit
663 * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
664 addr<20> -> CRTCEXT0<6>
665 addr<19-16> -> CRTCEXT0<3-0>
666 addr<15-8> -> CRTCC<7-0>
667 addr<7-0> -> CRTCD<7-0>
668 CRTCEXT0 has to be programmed last to trigger an update and make the
669 new addr variable take effect.
671 void mga_set_start_address(struct drm_crtc *crtc, unsigned offset)
673 struct mga_device *mdev = crtc->dev->dev_private;
678 while (RREG8(0x1fda) & 0x08);
679 while (!(RREG8(0x1fda) & 0x08));
681 count = RREG8(MGAREG_VCOUNT) + 2;
682 while (RREG8(MGAREG_VCOUNT) < count);
684 WREG8(MGAREG_CRTCEXT_INDEX, 0);
685 crtcext0 = RREG8(MGAREG_CRTCEXT_DATA);
688 /* Can't store addresses any higher than that...
689 but we also don't have more than 16MB of memory, so it should be fine. */
690 WARN_ON(addr > 0x1fffff);
691 crtcext0 |= (!!(addr & (1<<20)))<<6;
692 WREG_CRT(0x0d, (u8)(addr & 0xff));
693 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff);
694 WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0);
698 /* ast is different - we will force move buffers out of VRAM */
699 static int mga_crtc_do_set_base(struct drm_crtc *crtc,
700 struct drm_framebuffer *fb,
701 int x, int y, int atomic)
703 struct mga_device *mdev = crtc->dev->dev_private;
704 struct drm_gem_object *obj;
705 struct mga_framebuffer *mga_fb;
706 struct mgag200_bo *bo;
710 /* push the previous fb to system ram */
712 mga_fb = to_mga_framebuffer(fb);
714 bo = gem_to_mga_bo(obj);
715 ret = mgag200_bo_reserve(bo, false);
718 mgag200_bo_push_sysram(bo);
719 mgag200_bo_unreserve(bo);
722 mga_fb = to_mga_framebuffer(crtc->fb);
724 bo = gem_to_mga_bo(obj);
726 ret = mgag200_bo_reserve(bo, false);
730 ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
732 mgag200_bo_unreserve(bo);
736 if (&mdev->mfbdev->mfb == mga_fb) {
737 /* if pushing console in kmap it */
738 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
740 DRM_ERROR("failed to kmap fbcon\n");
743 mgag200_bo_unreserve(bo);
745 DRM_INFO("mga base %llx\n", gpu_addr);
747 mga_set_start_address(crtc, (u32)gpu_addr);
752 static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
753 struct drm_framebuffer *old_fb)
755 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
758 static int mga_crtc_mode_set(struct drm_crtc *crtc,
759 struct drm_display_mode *mode,
760 struct drm_display_mode *adjusted_mode,
761 int x, int y, struct drm_framebuffer *old_fb)
763 struct drm_device *dev = crtc->dev;
764 struct mga_device *mdev = dev->dev_private;
765 int hdisplay, hsyncstart, hsyncend, htotal;
766 int vdisplay, vsyncstart, vsyncend, vtotal;
768 int option = 0, option2 = 0;
770 unsigned char misc = 0;
771 unsigned char ext_vga[6];
774 static unsigned char dacvalue[] = {
775 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
776 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
777 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
778 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
779 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
780 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
781 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
782 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
783 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
784 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
787 bppshift = mdev->bpp_shifts[(crtc->fb->bits_per_pixel >> 3) - 1];
789 switch (mdev->type) {
792 dacvalue[MGA1064_VREF_CTL] = 0x03;
793 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
794 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
795 MGA1064_MISC_CTL_VGA8 |
796 MGA1064_MISC_CTL_DAC_RAM_CS;
801 option2 = 0x00008000;
804 dacvalue[MGA1064_VREF_CTL] = 0x07;
806 option2 = 0x0000b000;
809 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
810 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
811 MGA1064_MISC_CTL_DAC_RAM_CS;
813 option2 = 0x0000b000;
816 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
817 MGA1064_MISC_CTL_DAC_RAM_CS;
819 option2 = 0x0000b000;
825 switch (crtc->fb->bits_per_pixel) {
827 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits;
830 if (crtc->fb->depth == 15)
831 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits;
833 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits;
836 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits;
839 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits;
843 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
845 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
849 for (i = 0; i < sizeof(dacvalue); i++) {
853 ((i >= 0x1f) && (i <= 0x29)) ||
854 ((i >= 0x30) && (i <= 0x37)))
856 if (IS_G200_SE(mdev) &&
857 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
859 if ((mdev->type == G200_EV || mdev->type == G200_WB || mdev->type == G200_EH) &&
860 (i >= 0x44) && (i <= 0x4e))
863 WREG_DAC(i, dacvalue[i]);
866 if (mdev->type == G200_ER)
870 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
872 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
878 pitch = crtc->fb->pitches[0] / (crtc->fb->bits_per_pixel / 8);
879 if (crtc->fb->bits_per_pixel == 24)
880 pitch = pitch >> (4 - bppshift);
882 pitch = pitch >> (4 - bppshift);
884 hdisplay = mode->hdisplay / 8 - 1;
885 hsyncstart = mode->hsync_start / 8 - 1;
886 hsyncend = mode->hsync_end / 8 - 1;
887 htotal = mode->htotal / 8 - 1;
889 /* Work around hardware quirk */
890 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
893 vdisplay = mode->vdisplay - 1;
894 vsyncstart = mode->vsync_start - 1;
895 vsyncend = mode->vsync_end - 1;
896 vtotal = mode->vtotal - 2;
908 WREG_CRT(0, htotal - 4);
909 WREG_CRT(1, hdisplay);
910 WREG_CRT(2, hdisplay);
911 WREG_CRT(3, (htotal & 0x1F) | 0x80);
912 WREG_CRT(4, hsyncstart);
913 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
914 WREG_CRT(6, vtotal & 0xFF);
915 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
916 ((vdisplay & 0x100) >> 7) |
917 ((vsyncstart & 0x100) >> 6) |
918 ((vdisplay & 0x100) >> 5) |
919 ((vdisplay & 0x100) >> 4) | /* linecomp */
920 ((vtotal & 0x200) >> 4)|
921 ((vdisplay & 0x200) >> 3) |
922 ((vsyncstart & 0x200) >> 2));
923 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
924 ((vdisplay & 0x200) >> 3));
931 WREG_CRT(16, vsyncstart & 0xFF);
932 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
933 WREG_CRT(18, vdisplay & 0xFF);
934 WREG_CRT(19, pitch & 0xFF);
936 WREG_CRT(21, vdisplay & 0xFF);
937 WREG_CRT(22, (vtotal + 1) & 0xFF);
939 WREG_CRT(24, vdisplay & 0xFF);
946 ext_vga[0] |= (pitch & 0x300) >> 4;
947 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) |
948 ((hdisplay & 0x100) >> 7) |
949 ((hsyncstart & 0x100) >> 6) |
951 ext_vga[2] = ((vtotal & 0xc00) >> 10) |
952 ((vdisplay & 0x400) >> 8) |
953 ((vdisplay & 0xc00) >> 7) |
954 ((vsyncstart & 0xc00) >> 5) |
955 ((vdisplay & 0x400) >> 3);
956 if (crtc->fb->bits_per_pixel == 24)
957 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
959 ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
961 if (mdev->type == G200_WB)
964 /* Set pixel clocks */
966 WREG8(MGA_MISC_OUT, misc);
968 mga_crtc_set_plls(mdev, mode->clock);
970 for (i = 0; i < 6; i++) {
971 WREG_ECRT(i, ext_vga[i]);
974 if (mdev->type == G200_ER)
975 WREG_ECRT(0x24, 0x5);
977 if (mdev->type == G200_EV) {
981 WREG_ECRT(0, ext_vga[0]);
982 /* Enable mga pixel clock */
985 WREG8(MGA_MISC_OUT, misc);
988 memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode));
990 mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
993 if (mdev->type == G200_ER) {
994 u32 mem_ctl = RREG32(MGAREG_MEMCTL);
998 WREG8(MGAREG_SEQ_INDEX, 0x01);
999 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20;
1000 WREG8(MGAREG_SEQ_DATA, seq1);
1002 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000);
1004 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000);
1006 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20);
1010 if (IS_G200_SE(mdev)) {
1011 if (mdev->unique_rev_id >= 0x02) {
1016 if (crtc->fb->bits_per_pixel > 16)
1018 else if (crtc->fb->bits_per_pixel > 8)
1023 mb = (mode->clock * bpp) / 1000;
1037 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1038 WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl);
1040 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1041 if (mdev->unique_rev_id >= 0x01)
1042 WREG8(MGAREG_CRTCEXT_DATA, 0x03);
1044 WREG8(MGAREG_CRTCEXT_DATA, 0x04);
1050 #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
1051 static int mga_suspend(struct drm_crtc *crtc)
1053 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1054 struct drm_device *dev = crtc->dev;
1055 struct mga_device *mdev = dev->dev_private;
1056 struct pci_dev *pdev = dev->pdev;
1059 if (mdev->suspended)
1064 /* Disable the pixel clock */
1065 WREG_DAC(0x1a, 0x05);
1066 /* Power down the DAC */
1067 WREG_DAC(0x1e, 0x18);
1068 /* Power down the pixel PLL */
1069 WREG_DAC(0x1a, 0x0d);
1071 /* Disable PLLs and clocks */
1072 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1073 option &= ~(0x1F8024);
1074 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1075 pci_set_power_state(pdev, PCI_D3hot);
1076 pci_disable_device(pdev);
1078 mdev->suspended = true;
1083 static int mga_resume(struct drm_crtc *crtc)
1085 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1086 struct drm_device *dev = crtc->dev;
1087 struct mga_device *mdev = dev->dev_private;
1088 struct pci_dev *pdev = dev->pdev;
1091 if (!mdev->suspended)
1094 pci_set_power_state(pdev, PCI_D0);
1095 pci_enable_device(pdev);
1097 /* Disable sysclk */
1098 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1100 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1102 mdev->suspended = false;
1109 static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
1111 struct drm_device *dev = crtc->dev;
1112 struct mga_device *mdev = dev->dev_private;
1113 u8 seq1 = 0, crtcext1 = 0;
1116 case DRM_MODE_DPMS_ON:
1119 mga_crtc_load_lut(crtc);
1121 case DRM_MODE_DPMS_STANDBY:
1125 case DRM_MODE_DPMS_SUSPEND:
1129 case DRM_MODE_DPMS_OFF:
1136 if (mode == DRM_MODE_DPMS_OFF) {
1140 WREG8(MGAREG_SEQ_INDEX, 0x01);
1141 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
1142 mga_wait_vsync(mdev);
1143 mga_wait_busy(mdev);
1144 WREG8(MGAREG_SEQ_DATA, seq1);
1146 WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
1147 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
1148 WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
1151 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) {
1153 drm_helper_resume_force_mode(dev);
1159 * This is called before a mode is programmed. A typical use might be to
1160 * enable DPMS during the programming to avoid seeing intermediate stages,
1161 * but that's not relevant to us
1163 static void mga_crtc_prepare(struct drm_crtc *crtc)
1165 struct drm_device *dev = crtc->dev;
1166 struct mga_device *mdev = dev->dev_private;
1169 /* mga_resume(crtc);*/
1171 WREG8(MGAREG_CRTC_INDEX, 0x11);
1172 tmp = RREG8(MGAREG_CRTC_DATA);
1173 WREG_CRT(0x11, tmp | 0x80);
1175 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1181 WREG8(MGAREG_SEQ_INDEX, 0x1);
1182 tmp = RREG8(MGAREG_SEQ_DATA);
1184 /* start sync reset */
1186 WREG_SEQ(1, tmp | 0x20);
1189 if (mdev->type == G200_WB)
1190 mga_g200wb_prepare(crtc);
1196 * This is called after a mode is programmed. It should reverse anything done
1197 * by the prepare function
1199 static void mga_crtc_commit(struct drm_crtc *crtc)
1201 struct drm_device *dev = crtc->dev;
1202 struct mga_device *mdev = dev->dev_private;
1203 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1206 if (mdev->type == G200_WB)
1207 mga_g200wb_commit(crtc);
1209 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1215 WREG8(MGAREG_SEQ_INDEX, 0x1);
1216 tmp = RREG8(MGAREG_SEQ_DATA);
1222 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1226 * The core can pass us a set of gamma values to program. We actually only
1227 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
1228 * but it's a requirement that we provide the function
1230 static void mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1231 u16 *blue, uint32_t start, uint32_t size)
1233 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1234 int end = (start + size > MGAG200_LUT_SIZE) ? MGAG200_LUT_SIZE : start + size;
1237 for (i = start; i < end; i++) {
1238 mga_crtc->lut_r[i] = red[i] >> 8;
1239 mga_crtc->lut_g[i] = green[i] >> 8;
1240 mga_crtc->lut_b[i] = blue[i] >> 8;
1242 mga_crtc_load_lut(crtc);
1245 /* Simple cleanup function */
1246 static void mga_crtc_destroy(struct drm_crtc *crtc)
1248 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1250 drm_crtc_cleanup(crtc);
1254 /* These provide the minimum set of functions required to handle a CRTC */
1255 static const struct drm_crtc_funcs mga_crtc_funcs = {
1256 .gamma_set = mga_crtc_gamma_set,
1257 .set_config = drm_crtc_helper_set_config,
1258 .destroy = mga_crtc_destroy,
1261 static const struct drm_crtc_helper_funcs mga_helper_funcs = {
1262 .dpms = mga_crtc_dpms,
1263 .mode_fixup = mga_crtc_mode_fixup,
1264 .mode_set = mga_crtc_mode_set,
1265 .mode_set_base = mga_crtc_mode_set_base,
1266 .prepare = mga_crtc_prepare,
1267 .commit = mga_crtc_commit,
1268 .load_lut = mga_crtc_load_lut,
1272 static void mga_crtc_init(struct mga_device *mdev)
1274 struct mga_crtc *mga_crtc;
1277 mga_crtc = kzalloc(sizeof(struct mga_crtc) +
1278 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)),
1281 if (mga_crtc == NULL)
1284 drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs);
1286 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE);
1287 mdev->mode_info.crtc = mga_crtc;
1289 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
1290 mga_crtc->lut_r[i] = i;
1291 mga_crtc->lut_g[i] = i;
1292 mga_crtc->lut_b[i] = i;
1295 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs);
1298 /** Sets the color ramps on behalf of fbcon */
1299 void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1300 u16 blue, int regno)
1302 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1304 mga_crtc->lut_r[regno] = red >> 8;
1305 mga_crtc->lut_g[regno] = green >> 8;
1306 mga_crtc->lut_b[regno] = blue >> 8;
1309 /** Gets the color ramps on behalf of fbcon */
1310 void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
1311 u16 *blue, int regno)
1313 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1315 *red = (u16)mga_crtc->lut_r[regno] << 8;
1316 *green = (u16)mga_crtc->lut_g[regno] << 8;
1317 *blue = (u16)mga_crtc->lut_b[regno] << 8;
1321 * The encoder comes after the CRTC in the output pipeline, but before
1322 * the connector. It's responsible for ensuring that the digital
1323 * stream is appropriately converted into the output format. Setup is
1324 * very simple in this case - all we have to do is inform qemu of the
1325 * colour depth in order to ensure that it displays appropriately
1329 * These functions are analagous to those in the CRTC code, but are intended
1330 * to handle any encoder-specific limitations
1332 static bool mga_encoder_mode_fixup(struct drm_encoder *encoder,
1333 const struct drm_display_mode *mode,
1334 struct drm_display_mode *adjusted_mode)
1339 static void mga_encoder_mode_set(struct drm_encoder *encoder,
1340 struct drm_display_mode *mode,
1341 struct drm_display_mode *adjusted_mode)
1346 static void mga_encoder_dpms(struct drm_encoder *encoder, int state)
1351 static void mga_encoder_prepare(struct drm_encoder *encoder)
1355 static void mga_encoder_commit(struct drm_encoder *encoder)
1359 void mga_encoder_destroy(struct drm_encoder *encoder)
1361 struct mga_encoder *mga_encoder = to_mga_encoder(encoder);
1362 drm_encoder_cleanup(encoder);
1366 static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = {
1367 .dpms = mga_encoder_dpms,
1368 .mode_fixup = mga_encoder_mode_fixup,
1369 .mode_set = mga_encoder_mode_set,
1370 .prepare = mga_encoder_prepare,
1371 .commit = mga_encoder_commit,
1374 static const struct drm_encoder_funcs mga_encoder_encoder_funcs = {
1375 .destroy = mga_encoder_destroy,
1378 static struct drm_encoder *mga_encoder_init(struct drm_device *dev)
1380 struct drm_encoder *encoder;
1381 struct mga_encoder *mga_encoder;
1383 mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL);
1387 encoder = &mga_encoder->base;
1388 encoder->possible_crtcs = 0x1;
1390 drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs,
1391 DRM_MODE_ENCODER_DAC);
1392 drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs);
1398 static int mga_vga_get_modes(struct drm_connector *connector)
1400 struct mga_connector *mga_connector = to_mga_connector(connector);
1404 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1406 drm_mode_connector_update_edid_property(connector, edid);
1407 ret = drm_add_edid_modes(connector, edid);
1413 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
1416 uint32_t total_area, divisor;
1417 int64_t active_area, pixels_per_second, bandwidth;
1418 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
1422 if (!mode->htotal || !mode->vtotal || !mode->clock)
1425 active_area = mode->hdisplay * mode->vdisplay;
1426 total_area = mode->htotal * mode->vtotal;
1428 pixels_per_second = active_area * mode->clock * 1000;
1429 do_div(pixels_per_second, total_area);
1431 bandwidth = pixels_per_second * bytes_per_pixel * 100;
1432 do_div(bandwidth, divisor);
1434 return (uint32_t)(bandwidth);
1437 #define MODE_BANDWIDTH MODE_BAD
1439 static int mga_vga_mode_valid(struct drm_connector *connector,
1440 struct drm_display_mode *mode)
1442 struct drm_device *dev = connector->dev;
1443 struct mga_device *mdev = (struct mga_device*)dev->dev_private;
1444 struct mga_fbdev *mfbdev = mdev->mfbdev;
1445 struct drm_fb_helper *fb_helper = &mfbdev->helper;
1446 struct drm_fb_helper_connector *fb_helper_conn = NULL;
1450 if (IS_G200_SE(mdev)) {
1451 if (mdev->unique_rev_id == 0x01) {
1452 if (mode->hdisplay > 1600)
1453 return MODE_VIRTUAL_X;
1454 if (mode->vdisplay > 1200)
1455 return MODE_VIRTUAL_Y;
1456 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1458 return MODE_BANDWIDTH;
1459 } else if (mdev->unique_rev_id >= 0x02) {
1460 if (mode->hdisplay > 1920)
1461 return MODE_VIRTUAL_X;
1462 if (mode->vdisplay > 1200)
1463 return MODE_VIRTUAL_Y;
1464 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1466 return MODE_BANDWIDTH;
1468 } else if (mdev->type == G200_WB) {
1469 if (mode->hdisplay > 1280)
1470 return MODE_VIRTUAL_X;
1471 if (mode->vdisplay > 1024)
1472 return MODE_VIRTUAL_Y;
1473 if (mga_vga_calculate_mode_bandwidth(mode,
1474 bpp > (31877 * 1024)))
1475 return MODE_BANDWIDTH;
1476 } else if (mdev->type == G200_EV &&
1477 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1478 > (32700 * 1024))) {
1479 return MODE_BANDWIDTH;
1480 } else if (mdev->type == G200_EH &&
1481 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1482 > (37500 * 1024))) {
1483 return MODE_BANDWIDTH;
1484 } else if (mdev->type == G200_ER &&
1485 (mga_vga_calculate_mode_bandwidth(mode,
1486 bpp) > (55000 * 1024))) {
1487 return MODE_BANDWIDTH;
1490 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1491 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1492 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1493 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1497 /* Validate the mode input by the user */
1498 for (i = 0; i < fb_helper->connector_count; i++) {
1499 if (fb_helper->connector_info[i]->connector == connector) {
1500 /* Found the helper for this connector */
1501 fb_helper_conn = fb_helper->connector_info[i];
1502 if (fb_helper_conn->cmdline_mode.specified) {
1503 if (fb_helper_conn->cmdline_mode.bpp_specified) {
1504 bpp = fb_helper_conn->cmdline_mode.bpp;
1510 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) {
1512 fb_helper_conn->cmdline_mode.specified = false;
1519 struct drm_encoder *mga_connector_best_encoder(struct drm_connector
1522 int enc_id = connector->encoder_ids[0];
1523 struct drm_mode_object *obj;
1524 struct drm_encoder *encoder;
1526 /* pick the encoder ids */
1529 drm_mode_object_find(connector->dev, enc_id,
1530 DRM_MODE_OBJECT_ENCODER);
1533 encoder = obj_to_encoder(obj);
1539 static enum drm_connector_status mga_vga_detect(struct drm_connector
1540 *connector, bool force)
1542 return connector_status_connected;
1545 static void mga_connector_destroy(struct drm_connector *connector)
1547 struct mga_connector *mga_connector = to_mga_connector(connector);
1548 mgag200_i2c_destroy(mga_connector->i2c);
1549 drm_connector_cleanup(connector);
1553 struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1554 .get_modes = mga_vga_get_modes,
1555 .mode_valid = mga_vga_mode_valid,
1556 .best_encoder = mga_connector_best_encoder,
1559 struct drm_connector_funcs mga_vga_connector_funcs = {
1560 .dpms = drm_helper_connector_dpms,
1561 .detect = mga_vga_detect,
1562 .fill_modes = drm_helper_probe_single_connector_modes,
1563 .destroy = mga_connector_destroy,
1566 static struct drm_connector *mga_vga_init(struct drm_device *dev)
1568 struct drm_connector *connector;
1569 struct mga_connector *mga_connector;
1571 mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL);
1575 connector = &mga_connector->base;
1577 drm_connector_init(dev, connector,
1578 &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1580 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1582 mga_connector->i2c = mgag200_i2c_create(dev);
1583 if (!mga_connector->i2c)
1584 DRM_ERROR("failed to add ddc bus\n");
1590 int mgag200_modeset_init(struct mga_device *mdev)
1592 struct drm_encoder *encoder;
1593 struct drm_connector *connector;
1596 mdev->mode_info.mode_config_initialized = true;
1598 mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1599 mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1601 mdev->dev->mode_config.fb_base = mdev->mc.vram_base;
1603 mga_crtc_init(mdev);
1605 encoder = mga_encoder_init(mdev->dev);
1607 DRM_ERROR("mga_encoder_init failed\n");
1611 connector = mga_vga_init(mdev->dev);
1613 DRM_ERROR("mga_vga_init failed\n");
1617 drm_mode_connector_attach_encoder(connector, encoder);
1619 ret = mgag200_fbdev_init(mdev);
1621 DRM_ERROR("mga_fbdev_init failed\n");
1628 void mgag200_modeset_fini(struct mga_device *mdev)