2 * Copyright 2010 Matt Turner.
3 * Copyright 2012 Red Hat
5 * This file is subject to the terms and conditions of the GNU General
6 * Public License version 2. See the file COPYING in the main
7 * directory of this archive for more details.
9 * Authors: Matthew Garrett
14 #include <linux/delay.h>
17 #include <drm/drm_crtc_helper.h>
18 #include <drm/drm_plane_helper.h>
20 #include "mgag200_drv.h"
22 #define MGAG200_LUT_SIZE 256
25 * This file contains setup code for the CRTC.
28 static void mga_crtc_load_lut(struct drm_crtc *crtc)
30 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
31 struct drm_device *dev = crtc->dev;
32 struct mga_device *mdev = dev->dev_private;
33 struct drm_framebuffer *fb = crtc->primary->fb;
39 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
41 if (fb && fb->bits_per_pixel == 16) {
42 int inc = (fb->depth == 15) ? 8 : 4;
44 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
45 if (fb->depth == 16) {
46 if (i > (MGAG200_LUT_SIZE >> 1)) {
49 r = mga_crtc->lut_r[i << 1];
50 b = mga_crtc->lut_b[i << 1];
53 r = mga_crtc->lut_r[i];
54 b = mga_crtc->lut_b[i];
57 WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
58 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
59 WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
63 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
65 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]);
66 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
67 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]);
71 static inline void mga_wait_vsync(struct mga_device *mdev)
73 unsigned long timeout = jiffies + HZ/10;
74 unsigned int status = 0;
77 status = RREG32(MGAREG_Status);
78 } while ((status & 0x08) && time_before(jiffies, timeout));
79 timeout = jiffies + HZ/10;
82 status = RREG32(MGAREG_Status);
83 } while (!(status & 0x08) && time_before(jiffies, timeout));
86 static inline void mga_wait_busy(struct mga_device *mdev)
88 unsigned long timeout = jiffies + HZ;
89 unsigned int status = 0;
91 status = RREG8(MGAREG_Status + 2);
92 } while ((status & 0x01) && time_before(jiffies, timeout));
96 * The core passes the desired mode to the CRTC code to see whether any
97 * CRTC-specific modifications need to be made to it. We're in a position
98 * to just pass that straight through, so this does nothing
100 static bool mga_crtc_mode_fixup(struct drm_crtc *crtc,
101 const struct drm_display_mode *mode,
102 struct drm_display_mode *adjusted_mode)
107 static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
109 unsigned int vcomax, vcomin, pllreffreq;
110 unsigned int delta, tmpdelta, permitteddelta;
111 unsigned int testp, testm, testn;
112 unsigned int p, m, n;
113 unsigned int computed;
121 permitteddelta = clock * 5 / 1000;
123 for (testp = 8; testp > 0; testp /= 2) {
124 if (clock * testp > vcomax)
126 if (clock * testp < vcomin)
129 for (testn = 17; testn < 256; testn++) {
130 for (testm = 1; testm < 32; testm++) {
131 computed = (pllreffreq * testn) /
133 if (computed > clock)
134 tmpdelta = computed - clock;
136 tmpdelta = clock - computed;
137 if (tmpdelta < delta) {
147 if (delta > permitteddelta) {
148 printk(KERN_WARNING "PLL delta too large\n");
152 WREG_DAC(MGA1064_PIX_PLLC_M, m);
153 WREG_DAC(MGA1064_PIX_PLLC_N, n);
154 WREG_DAC(MGA1064_PIX_PLLC_P, p);
158 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
160 unsigned int vcomax, vcomin, pllreffreq;
161 unsigned int delta, tmpdelta;
162 unsigned int testp, testm, testn;
163 unsigned int p, m, n;
164 unsigned int computed;
165 int i, j, tmpcount, vcount;
166 bool pll_locked = false;
176 for (testp = 1; testp < 9; testp++) {
177 if (clock * testp > vcomax)
179 if (clock * testp < vcomin)
182 for (testm = 1; testm < 17; testm++) {
183 for (testn = 1; testn < 151; testn++) {
184 computed = (pllreffreq * testn) /
186 if (computed > clock)
187 tmpdelta = computed - clock;
189 tmpdelta = clock - computed;
190 if (tmpdelta < delta) {
193 m = (testm - 1) | ((n >> 1) & 0x80);
200 for (i = 0; i <= 32 && pll_locked == false; i++) {
202 WREG8(MGAREG_CRTC_INDEX, 0x1e);
203 tmp = RREG8(MGAREG_CRTC_DATA);
205 WREG8(MGAREG_CRTC_DATA, tmp+1);
208 /* set pixclkdis to 1 */
209 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
210 tmp = RREG8(DAC_DATA);
211 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
212 WREG8(DAC_DATA, tmp);
214 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
215 tmp = RREG8(DAC_DATA);
216 tmp |= MGA1064_REMHEADCTL_CLKDIS;
217 WREG8(DAC_DATA, tmp);
219 /* select PLL Set C */
220 tmp = RREG8(MGAREG_MEM_MISC_READ);
222 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
224 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
225 tmp = RREG8(DAC_DATA);
226 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
227 WREG8(DAC_DATA, tmp);
232 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
233 tmp = RREG8(DAC_DATA);
235 WREG8(DAC_DATA, tmp);
239 /* program pixel pll register */
240 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
241 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
242 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
247 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
248 tmp = RREG8(DAC_DATA);
250 WREG_DAC(MGA1064_VREF_CTL, tmp);
254 /* select the pixel pll */
255 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
256 tmp = RREG8(DAC_DATA);
257 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
258 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
259 WREG8(DAC_DATA, tmp);
261 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
262 tmp = RREG8(DAC_DATA);
263 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
264 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
265 WREG8(DAC_DATA, tmp);
267 /* reset dotclock rate bit */
268 WREG8(MGAREG_SEQ_INDEX, 1);
269 tmp = RREG8(MGAREG_SEQ_DATA);
271 WREG8(MGAREG_SEQ_DATA, tmp);
273 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
274 tmp = RREG8(DAC_DATA);
275 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
276 WREG8(DAC_DATA, tmp);
278 vcount = RREG8(MGAREG_VCOUNT);
280 for (j = 0; j < 30 && pll_locked == false; j++) {
281 tmpcount = RREG8(MGAREG_VCOUNT);
282 if (tmpcount < vcount)
284 if ((tmpcount - vcount) > 2)
290 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
291 tmp = RREG8(DAC_DATA);
292 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
293 WREG_DAC(MGA1064_REMHEADCTL, tmp);
297 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
299 unsigned int vcomax, vcomin, pllreffreq;
300 unsigned int delta, tmpdelta;
301 unsigned int testp, testm, testn;
302 unsigned int p, m, n;
303 unsigned int computed;
313 for (testp = 16; testp > 0; testp--) {
314 if (clock * testp > vcomax)
316 if (clock * testp < vcomin)
319 for (testn = 1; testn < 257; testn++) {
320 for (testm = 1; testm < 17; testm++) {
321 computed = (pllreffreq * testn) /
323 if (computed > clock)
324 tmpdelta = computed - clock;
326 tmpdelta = clock - computed;
327 if (tmpdelta < delta) {
337 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
338 tmp = RREG8(DAC_DATA);
339 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
340 WREG8(DAC_DATA, tmp);
342 tmp = RREG8(MGAREG_MEM_MISC_READ);
344 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
346 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
347 tmp = RREG8(DAC_DATA);
348 WREG8(DAC_DATA, tmp & ~0x40);
350 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
351 tmp = RREG8(DAC_DATA);
352 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
353 WREG8(DAC_DATA, tmp);
355 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
356 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
357 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
361 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
362 tmp = RREG8(DAC_DATA);
363 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
364 WREG8(DAC_DATA, tmp);
368 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
369 tmp = RREG8(DAC_DATA);
370 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
371 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
372 WREG8(DAC_DATA, tmp);
374 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
375 tmp = RREG8(DAC_DATA);
376 WREG8(DAC_DATA, tmp | 0x40);
378 tmp = RREG8(MGAREG_MEM_MISC_READ);
380 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
382 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
383 tmp = RREG8(DAC_DATA);
384 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
385 WREG8(DAC_DATA, tmp);
390 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
392 unsigned int vcomax, vcomin, pllreffreq;
393 unsigned int delta, tmpdelta;
394 unsigned int testp, testm, testn;
395 unsigned int p, m, n;
396 unsigned int computed;
397 int i, j, tmpcount, vcount;
399 bool pll_locked = false;
408 for (testp = 16; testp > 0; testp >>= 1) {
409 if (clock * testp > vcomax)
411 if (clock * testp < vcomin)
414 for (testm = 1; testm < 33; testm++) {
415 for (testn = 17; testn < 257; testn++) {
416 computed = (pllreffreq * testn) /
418 if (computed > clock)
419 tmpdelta = computed - clock;
421 tmpdelta = clock - computed;
422 if (tmpdelta < delta) {
428 if ((clock * testp) >= 600000)
433 for (i = 0; i <= 32 && pll_locked == false; i++) {
434 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
435 tmp = RREG8(DAC_DATA);
436 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
437 WREG8(DAC_DATA, tmp);
439 tmp = RREG8(MGAREG_MEM_MISC_READ);
441 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
443 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
444 tmp = RREG8(DAC_DATA);
445 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
446 WREG8(DAC_DATA, tmp);
450 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
451 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
452 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
456 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
457 tmp = RREG8(DAC_DATA);
458 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
459 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
460 WREG8(DAC_DATA, tmp);
462 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
463 tmp = RREG8(DAC_DATA);
464 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
465 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
466 WREG8(DAC_DATA, tmp);
468 vcount = RREG8(MGAREG_VCOUNT);
470 for (j = 0; j < 30 && pll_locked == false; j++) {
471 tmpcount = RREG8(MGAREG_VCOUNT);
472 if (tmpcount < vcount)
474 if ((tmpcount - vcount) > 2)
484 static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
486 unsigned int vcomax, vcomin, pllreffreq;
487 unsigned int delta, tmpdelta;
488 int testr, testn, testm, testo;
489 unsigned int p, m, n;
490 unsigned int computed, vco;
492 const unsigned int m_div_val[] = { 1, 2, 4, 8 };
501 for (testr = 0; testr < 4; testr++) {
504 for (testn = 5; testn < 129; testn++) {
507 for (testm = 3; testm >= 0; testm--) {
510 for (testo = 5; testo < 33; testo++) {
511 vco = pllreffreq * (testn + 1) /
517 computed = vco / (m_div_val[testm] * (testo + 1));
518 if (computed > clock)
519 tmpdelta = computed - clock;
521 tmpdelta = clock - computed;
522 if (tmpdelta < delta) {
524 m = testm | (testo << 3);
526 p = testr | (testr << 3);
533 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
534 tmp = RREG8(DAC_DATA);
535 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
536 WREG8(DAC_DATA, tmp);
538 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
539 tmp = RREG8(DAC_DATA);
540 tmp |= MGA1064_REMHEADCTL_CLKDIS;
541 WREG8(DAC_DATA, tmp);
543 tmp = RREG8(MGAREG_MEM_MISC_READ);
544 tmp |= (0x3<<2) | 0xc0;
545 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
547 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
548 tmp = RREG8(DAC_DATA);
549 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
550 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
551 WREG8(DAC_DATA, tmp);
555 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
556 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
557 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
564 static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
569 return mga_g200se_set_plls(mdev, clock);
572 return mga_g200wb_set_plls(mdev, clock);
575 return mga_g200ev_set_plls(mdev, clock);
578 return mga_g200eh_set_plls(mdev, clock);
581 return mga_g200er_set_plls(mdev, clock);
587 static void mga_g200wb_prepare(struct drm_crtc *crtc)
589 struct mga_device *mdev = crtc->dev->dev_private;
593 /* 1- The first step is to warn the BMC of an upcoming mode change.
594 * We are putting the misc<0> to output.*/
596 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
597 tmp = RREG8(DAC_DATA);
599 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
601 /* we are putting a 1 on the misc<0> line */
602 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
603 tmp = RREG8(DAC_DATA);
605 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
607 /* 2- Second step to mask and further scan request
608 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
610 WREG8(DAC_INDEX, MGA1064_SPAREREG);
611 tmp = RREG8(DAC_DATA);
613 WREG_DAC(MGA1064_SPAREREG, tmp);
615 /* 3a- the third step is to verifu if there is an active scan
616 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
619 while (!(tmp & 0x1) && iter_max) {
620 WREG8(DAC_INDEX, MGA1064_SPAREREG);
621 tmp = RREG8(DAC_DATA);
626 /* 3b- this step occurs only if the remove is actually scanning
627 * we are waiting for the end of the frame which is a 1 on
628 * remvsyncsts (XSPAREREG<1>)
632 while ((tmp & 0x2) && iter_max) {
633 WREG8(DAC_INDEX, MGA1064_SPAREREG);
634 tmp = RREG8(DAC_DATA);
641 static void mga_g200wb_commit(struct drm_crtc *crtc)
644 struct mga_device *mdev = crtc->dev->dev_private;
646 /* 1- The first step is to ensure that the vrsten and hrsten are set */
647 WREG8(MGAREG_CRTCEXT_INDEX, 1);
648 tmp = RREG8(MGAREG_CRTCEXT_DATA);
649 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
651 /* 2- second step is to assert the rstlvl2 */
652 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
653 tmp = RREG8(DAC_DATA);
655 WREG8(DAC_DATA, tmp);
660 /* 3- deassert rstlvl2 */
662 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
663 WREG8(DAC_DATA, tmp);
665 /* 4- remove mask of scan request */
666 WREG8(DAC_INDEX, MGA1064_SPAREREG);
667 tmp = RREG8(DAC_DATA);
669 WREG8(DAC_DATA, tmp);
671 /* 5- put back a 0 on the misc<0> line */
672 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
673 tmp = RREG8(DAC_DATA);
675 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
679 This is how the framebuffer base address is stored in g200 cards:
680 * Assume @offset is the gpu_addr variable of the framebuffer object
681 * Then addr is the number of _pixels_ (not bytes) from the start of
682 VRAM to the first pixel we want to display. (divided by 2 for 32bit
684 * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
685 addr<20> -> CRTCEXT0<6>
686 addr<19-16> -> CRTCEXT0<3-0>
687 addr<15-8> -> CRTCC<7-0>
688 addr<7-0> -> CRTCD<7-0>
689 CRTCEXT0 has to be programmed last to trigger an update and make the
690 new addr variable take effect.
692 static void mga_set_start_address(struct drm_crtc *crtc, unsigned offset)
694 struct mga_device *mdev = crtc->dev->dev_private;
699 while (RREG8(0x1fda) & 0x08);
700 while (!(RREG8(0x1fda) & 0x08));
702 count = RREG8(MGAREG_VCOUNT) + 2;
703 while (RREG8(MGAREG_VCOUNT) < count);
705 WREG8(MGAREG_CRTCEXT_INDEX, 0);
706 crtcext0 = RREG8(MGAREG_CRTCEXT_DATA);
709 /* Can't store addresses any higher than that...
710 but we also don't have more than 16MB of memory, so it should be fine. */
711 WARN_ON(addr > 0x1fffff);
712 crtcext0 |= (!!(addr & (1<<20)))<<6;
713 WREG_CRT(0x0d, (u8)(addr & 0xff));
714 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff);
715 WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0);
719 /* ast is different - we will force move buffers out of VRAM */
720 static int mga_crtc_do_set_base(struct drm_crtc *crtc,
721 struct drm_framebuffer *fb,
722 int x, int y, int atomic)
724 struct mga_device *mdev = crtc->dev->dev_private;
725 struct drm_gem_object *obj;
726 struct mga_framebuffer *mga_fb;
727 struct mgag200_bo *bo;
731 /* push the previous fb to system ram */
733 mga_fb = to_mga_framebuffer(fb);
735 bo = gem_to_mga_bo(obj);
736 ret = mgag200_bo_reserve(bo, false);
739 mgag200_bo_push_sysram(bo);
740 mgag200_bo_unreserve(bo);
743 mga_fb = to_mga_framebuffer(crtc->primary->fb);
745 bo = gem_to_mga_bo(obj);
747 ret = mgag200_bo_reserve(bo, false);
751 ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
753 mgag200_bo_unreserve(bo);
757 if (&mdev->mfbdev->mfb == mga_fb) {
758 /* if pushing console in kmap it */
759 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
761 DRM_ERROR("failed to kmap fbcon\n");
764 mgag200_bo_unreserve(bo);
766 mga_set_start_address(crtc, (u32)gpu_addr);
771 static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
772 struct drm_framebuffer *old_fb)
774 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
777 static int mga_crtc_mode_set(struct drm_crtc *crtc,
778 struct drm_display_mode *mode,
779 struct drm_display_mode *adjusted_mode,
780 int x, int y, struct drm_framebuffer *old_fb)
782 struct drm_device *dev = crtc->dev;
783 struct mga_device *mdev = dev->dev_private;
784 int hdisplay, hsyncstart, hsyncend, htotal;
785 int vdisplay, vsyncstart, vsyncend, vtotal;
787 int option = 0, option2 = 0;
789 unsigned char misc = 0;
790 unsigned char ext_vga[6];
793 static unsigned char dacvalue[] = {
794 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
795 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
796 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
797 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
798 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
799 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
800 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
801 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
802 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
803 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
806 bppshift = mdev->bpp_shifts[(crtc->primary->fb->bits_per_pixel >> 3) - 1];
808 switch (mdev->type) {
811 dacvalue[MGA1064_VREF_CTL] = 0x03;
812 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
813 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
814 MGA1064_MISC_CTL_VGA8 |
815 MGA1064_MISC_CTL_DAC_RAM_CS;
820 option2 = 0x00008000;
823 dacvalue[MGA1064_VREF_CTL] = 0x07;
825 option2 = 0x0000b000;
828 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
829 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
830 MGA1064_MISC_CTL_DAC_RAM_CS;
832 option2 = 0x0000b000;
835 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
836 MGA1064_MISC_CTL_DAC_RAM_CS;
838 option2 = 0x0000b000;
844 switch (crtc->primary->fb->bits_per_pixel) {
846 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits;
849 if (crtc->primary->fb->depth == 15)
850 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits;
852 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits;
855 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits;
858 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits;
862 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
864 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
868 for (i = 0; i < sizeof(dacvalue); i++) {
872 ((i >= 0x1f) && (i <= 0x29)) ||
873 ((i >= 0x30) && (i <= 0x37)))
875 if (IS_G200_SE(mdev) &&
876 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
878 if ((mdev->type == G200_EV || mdev->type == G200_WB || mdev->type == G200_EH) &&
879 (i >= 0x44) && (i <= 0x4e))
882 WREG_DAC(i, dacvalue[i]);
885 if (mdev->type == G200_ER)
889 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
891 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
897 pitch = crtc->primary->fb->pitches[0] / (crtc->primary->fb->bits_per_pixel / 8);
898 if (crtc->primary->fb->bits_per_pixel == 24)
899 pitch = (pitch * 3) >> (4 - bppshift);
901 pitch = pitch >> (4 - bppshift);
903 hdisplay = mode->hdisplay / 8 - 1;
904 hsyncstart = mode->hsync_start / 8 - 1;
905 hsyncend = mode->hsync_end / 8 - 1;
906 htotal = mode->htotal / 8 - 1;
908 /* Work around hardware quirk */
909 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
912 vdisplay = mode->vdisplay - 1;
913 vsyncstart = mode->vsync_start - 1;
914 vsyncend = mode->vsync_end - 1;
915 vtotal = mode->vtotal - 2;
927 WREG_CRT(0, htotal - 4);
928 WREG_CRT(1, hdisplay);
929 WREG_CRT(2, hdisplay);
930 WREG_CRT(3, (htotal & 0x1F) | 0x80);
931 WREG_CRT(4, hsyncstart);
932 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
933 WREG_CRT(6, vtotal & 0xFF);
934 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
935 ((vdisplay & 0x100) >> 7) |
936 ((vsyncstart & 0x100) >> 6) |
937 ((vdisplay & 0x100) >> 5) |
938 ((vdisplay & 0x100) >> 4) | /* linecomp */
939 ((vtotal & 0x200) >> 4)|
940 ((vdisplay & 0x200) >> 3) |
941 ((vsyncstart & 0x200) >> 2));
942 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
943 ((vdisplay & 0x200) >> 3));
950 WREG_CRT(16, vsyncstart & 0xFF);
951 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
952 WREG_CRT(18, vdisplay & 0xFF);
953 WREG_CRT(19, pitch & 0xFF);
955 WREG_CRT(21, vdisplay & 0xFF);
956 WREG_CRT(22, (vtotal + 1) & 0xFF);
958 WREG_CRT(24, vdisplay & 0xFF);
965 ext_vga[0] |= (pitch & 0x300) >> 4;
966 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) |
967 ((hdisplay & 0x100) >> 7) |
968 ((hsyncstart & 0x100) >> 6) |
970 ext_vga[2] = ((vtotal & 0xc00) >> 10) |
971 ((vdisplay & 0x400) >> 8) |
972 ((vdisplay & 0xc00) >> 7) |
973 ((vsyncstart & 0xc00) >> 5) |
974 ((vdisplay & 0x400) >> 3);
975 if (crtc->primary->fb->bits_per_pixel == 24)
976 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
978 ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
980 if (mdev->type == G200_WB)
983 /* Set pixel clocks */
985 WREG8(MGA_MISC_OUT, misc);
987 mga_crtc_set_plls(mdev, mode->clock);
989 for (i = 0; i < 6; i++) {
990 WREG_ECRT(i, ext_vga[i]);
993 if (mdev->type == G200_ER)
994 WREG_ECRT(0x24, 0x5);
996 if (mdev->type == G200_EV) {
1000 WREG_ECRT(0, ext_vga[0]);
1001 /* Enable mga pixel clock */
1004 WREG8(MGA_MISC_OUT, misc);
1007 memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode));
1009 mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
1012 if (mdev->type == G200_ER) {
1013 u32 mem_ctl = RREG32(MGAREG_MEMCTL);
1017 WREG8(MGAREG_SEQ_INDEX, 0x01);
1018 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20;
1019 WREG8(MGAREG_SEQ_DATA, seq1);
1021 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000);
1023 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000);
1025 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20);
1029 if (IS_G200_SE(mdev)) {
1030 if (mdev->unique_rev_id >= 0x02) {
1035 if (crtc->primary->fb->bits_per_pixel > 16)
1037 else if (crtc->primary->fb->bits_per_pixel > 8)
1042 mb = (mode->clock * bpp) / 1000;
1056 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1057 WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl);
1059 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1060 if (mdev->unique_rev_id >= 0x01)
1061 WREG8(MGAREG_CRTCEXT_DATA, 0x03);
1063 WREG8(MGAREG_CRTCEXT_DATA, 0x04);
1069 #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
1070 static int mga_suspend(struct drm_crtc *crtc)
1072 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1073 struct drm_device *dev = crtc->dev;
1074 struct mga_device *mdev = dev->dev_private;
1075 struct pci_dev *pdev = dev->pdev;
1078 if (mdev->suspended)
1083 /* Disable the pixel clock */
1084 WREG_DAC(0x1a, 0x05);
1085 /* Power down the DAC */
1086 WREG_DAC(0x1e, 0x18);
1087 /* Power down the pixel PLL */
1088 WREG_DAC(0x1a, 0x0d);
1090 /* Disable PLLs and clocks */
1091 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1092 option &= ~(0x1F8024);
1093 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1094 pci_set_power_state(pdev, PCI_D3hot);
1095 pci_disable_device(pdev);
1097 mdev->suspended = true;
1102 static int mga_resume(struct drm_crtc *crtc)
1104 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1105 struct drm_device *dev = crtc->dev;
1106 struct mga_device *mdev = dev->dev_private;
1107 struct pci_dev *pdev = dev->pdev;
1110 if (!mdev->suspended)
1113 pci_set_power_state(pdev, PCI_D0);
1114 pci_enable_device(pdev);
1116 /* Disable sysclk */
1117 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1119 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1121 mdev->suspended = false;
1128 static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
1130 struct drm_device *dev = crtc->dev;
1131 struct mga_device *mdev = dev->dev_private;
1132 u8 seq1 = 0, crtcext1 = 0;
1135 case DRM_MODE_DPMS_ON:
1138 mga_crtc_load_lut(crtc);
1140 case DRM_MODE_DPMS_STANDBY:
1144 case DRM_MODE_DPMS_SUSPEND:
1148 case DRM_MODE_DPMS_OFF:
1155 if (mode == DRM_MODE_DPMS_OFF) {
1159 WREG8(MGAREG_SEQ_INDEX, 0x01);
1160 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
1161 mga_wait_vsync(mdev);
1162 mga_wait_busy(mdev);
1163 WREG8(MGAREG_SEQ_DATA, seq1);
1165 WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
1166 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
1167 WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
1170 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) {
1172 drm_helper_resume_force_mode(dev);
1178 * This is called before a mode is programmed. A typical use might be to
1179 * enable DPMS during the programming to avoid seeing intermediate stages,
1180 * but that's not relevant to us
1182 static void mga_crtc_prepare(struct drm_crtc *crtc)
1184 struct drm_device *dev = crtc->dev;
1185 struct mga_device *mdev = dev->dev_private;
1188 /* mga_resume(crtc);*/
1190 WREG8(MGAREG_CRTC_INDEX, 0x11);
1191 tmp = RREG8(MGAREG_CRTC_DATA);
1192 WREG_CRT(0x11, tmp | 0x80);
1194 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1200 WREG8(MGAREG_SEQ_INDEX, 0x1);
1201 tmp = RREG8(MGAREG_SEQ_DATA);
1203 /* start sync reset */
1205 WREG_SEQ(1, tmp | 0x20);
1208 if (mdev->type == G200_WB)
1209 mga_g200wb_prepare(crtc);
1215 * This is called after a mode is programmed. It should reverse anything done
1216 * by the prepare function
1218 static void mga_crtc_commit(struct drm_crtc *crtc)
1220 struct drm_device *dev = crtc->dev;
1221 struct mga_device *mdev = dev->dev_private;
1222 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1225 if (mdev->type == G200_WB)
1226 mga_g200wb_commit(crtc);
1228 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1234 WREG8(MGAREG_SEQ_INDEX, 0x1);
1235 tmp = RREG8(MGAREG_SEQ_DATA);
1241 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1245 * The core can pass us a set of gamma values to program. We actually only
1246 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
1247 * but it's a requirement that we provide the function
1249 static void mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1250 u16 *blue, uint32_t start, uint32_t size)
1252 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1253 int end = (start + size > MGAG200_LUT_SIZE) ? MGAG200_LUT_SIZE : start + size;
1256 for (i = start; i < end; i++) {
1257 mga_crtc->lut_r[i] = red[i] >> 8;
1258 mga_crtc->lut_g[i] = green[i] >> 8;
1259 mga_crtc->lut_b[i] = blue[i] >> 8;
1261 mga_crtc_load_lut(crtc);
1264 /* Simple cleanup function */
1265 static void mga_crtc_destroy(struct drm_crtc *crtc)
1267 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1269 drm_crtc_cleanup(crtc);
1273 static void mga_crtc_disable(struct drm_crtc *crtc)
1276 DRM_DEBUG_KMS("\n");
1277 mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1278 if (crtc->primary->fb) {
1279 struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb);
1280 struct drm_gem_object *obj = mga_fb->obj;
1281 struct mgag200_bo *bo = gem_to_mga_bo(obj);
1282 ret = mgag200_bo_reserve(bo, false);
1285 mgag200_bo_push_sysram(bo);
1286 mgag200_bo_unreserve(bo);
1288 crtc->primary->fb = NULL;
1291 /* These provide the minimum set of functions required to handle a CRTC */
1292 static const struct drm_crtc_funcs mga_crtc_funcs = {
1293 .cursor_set = mga_crtc_cursor_set,
1294 .cursor_move = mga_crtc_cursor_move,
1295 .gamma_set = mga_crtc_gamma_set,
1296 .set_config = drm_crtc_helper_set_config,
1297 .destroy = mga_crtc_destroy,
1300 static const struct drm_crtc_helper_funcs mga_helper_funcs = {
1301 .disable = mga_crtc_disable,
1302 .dpms = mga_crtc_dpms,
1303 .mode_fixup = mga_crtc_mode_fixup,
1304 .mode_set = mga_crtc_mode_set,
1305 .mode_set_base = mga_crtc_mode_set_base,
1306 .prepare = mga_crtc_prepare,
1307 .commit = mga_crtc_commit,
1308 .load_lut = mga_crtc_load_lut,
1312 static void mga_crtc_init(struct mga_device *mdev)
1314 struct mga_crtc *mga_crtc;
1317 mga_crtc = kzalloc(sizeof(struct mga_crtc) +
1318 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)),
1321 if (mga_crtc == NULL)
1324 drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs);
1326 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE);
1327 mdev->mode_info.crtc = mga_crtc;
1329 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
1330 mga_crtc->lut_r[i] = i;
1331 mga_crtc->lut_g[i] = i;
1332 mga_crtc->lut_b[i] = i;
1335 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs);
1338 /** Sets the color ramps on behalf of fbcon */
1339 void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1340 u16 blue, int regno)
1342 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1344 mga_crtc->lut_r[regno] = red >> 8;
1345 mga_crtc->lut_g[regno] = green >> 8;
1346 mga_crtc->lut_b[regno] = blue >> 8;
1349 /** Gets the color ramps on behalf of fbcon */
1350 void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
1351 u16 *blue, int regno)
1353 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1355 *red = (u16)mga_crtc->lut_r[regno] << 8;
1356 *green = (u16)mga_crtc->lut_g[regno] << 8;
1357 *blue = (u16)mga_crtc->lut_b[regno] << 8;
1361 * The encoder comes after the CRTC in the output pipeline, but before
1362 * the connector. It's responsible for ensuring that the digital
1363 * stream is appropriately converted into the output format. Setup is
1364 * very simple in this case - all we have to do is inform qemu of the
1365 * colour depth in order to ensure that it displays appropriately
1369 * These functions are analagous to those in the CRTC code, but are intended
1370 * to handle any encoder-specific limitations
1372 static bool mga_encoder_mode_fixup(struct drm_encoder *encoder,
1373 const struct drm_display_mode *mode,
1374 struct drm_display_mode *adjusted_mode)
1379 static void mga_encoder_mode_set(struct drm_encoder *encoder,
1380 struct drm_display_mode *mode,
1381 struct drm_display_mode *adjusted_mode)
1386 static void mga_encoder_dpms(struct drm_encoder *encoder, int state)
1391 static void mga_encoder_prepare(struct drm_encoder *encoder)
1395 static void mga_encoder_commit(struct drm_encoder *encoder)
1399 static void mga_encoder_destroy(struct drm_encoder *encoder)
1401 struct mga_encoder *mga_encoder = to_mga_encoder(encoder);
1402 drm_encoder_cleanup(encoder);
1406 static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = {
1407 .dpms = mga_encoder_dpms,
1408 .mode_fixup = mga_encoder_mode_fixup,
1409 .mode_set = mga_encoder_mode_set,
1410 .prepare = mga_encoder_prepare,
1411 .commit = mga_encoder_commit,
1414 static const struct drm_encoder_funcs mga_encoder_encoder_funcs = {
1415 .destroy = mga_encoder_destroy,
1418 static struct drm_encoder *mga_encoder_init(struct drm_device *dev)
1420 struct drm_encoder *encoder;
1421 struct mga_encoder *mga_encoder;
1423 mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL);
1427 encoder = &mga_encoder->base;
1428 encoder->possible_crtcs = 0x1;
1430 drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs,
1431 DRM_MODE_ENCODER_DAC);
1432 drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs);
1438 static int mga_vga_get_modes(struct drm_connector *connector)
1440 struct mga_connector *mga_connector = to_mga_connector(connector);
1444 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1446 drm_mode_connector_update_edid_property(connector, edid);
1447 ret = drm_add_edid_modes(connector, edid);
1453 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
1456 uint32_t total_area, divisor;
1457 int64_t active_area, pixels_per_second, bandwidth;
1458 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
1462 if (!mode->htotal || !mode->vtotal || !mode->clock)
1465 active_area = mode->hdisplay * mode->vdisplay;
1466 total_area = mode->htotal * mode->vtotal;
1468 pixels_per_second = active_area * mode->clock * 1000;
1469 do_div(pixels_per_second, total_area);
1471 bandwidth = pixels_per_second * bytes_per_pixel * 100;
1472 do_div(bandwidth, divisor);
1474 return (uint32_t)(bandwidth);
1477 #define MODE_BANDWIDTH MODE_BAD
1479 static int mga_vga_mode_valid(struct drm_connector *connector,
1480 struct drm_display_mode *mode)
1482 struct drm_device *dev = connector->dev;
1483 struct mga_device *mdev = (struct mga_device*)dev->dev_private;
1486 if (IS_G200_SE(mdev)) {
1487 if (mdev->unique_rev_id == 0x01) {
1488 if (mode->hdisplay > 1600)
1489 return MODE_VIRTUAL_X;
1490 if (mode->vdisplay > 1200)
1491 return MODE_VIRTUAL_Y;
1492 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1494 return MODE_BANDWIDTH;
1495 } else if (mdev->unique_rev_id >= 0x02) {
1496 if (mode->hdisplay > 1920)
1497 return MODE_VIRTUAL_X;
1498 if (mode->vdisplay > 1200)
1499 return MODE_VIRTUAL_Y;
1500 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1502 return MODE_BANDWIDTH;
1504 } else if (mdev->type == G200_WB) {
1505 if (mode->hdisplay > 1280)
1506 return MODE_VIRTUAL_X;
1507 if (mode->vdisplay > 1024)
1508 return MODE_VIRTUAL_Y;
1509 if (mga_vga_calculate_mode_bandwidth(mode,
1510 bpp > (31877 * 1024)))
1511 return MODE_BANDWIDTH;
1512 } else if (mdev->type == G200_EV &&
1513 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1514 > (32700 * 1024))) {
1515 return MODE_BANDWIDTH;
1516 } else if (mdev->type == G200_EH &&
1517 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1518 > (37500 * 1024))) {
1519 return MODE_BANDWIDTH;
1520 } else if (mdev->type == G200_ER &&
1521 (mga_vga_calculate_mode_bandwidth(mode,
1522 bpp) > (55000 * 1024))) {
1523 return MODE_BANDWIDTH;
1526 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
1527 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
1528 return MODE_H_ILLEGAL;
1531 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1532 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1533 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1534 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1538 /* Validate the mode input by the user */
1539 if (connector->cmdline_mode.specified) {
1540 if (connector->cmdline_mode.bpp_specified)
1541 bpp = connector->cmdline_mode.bpp;
1544 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) {
1545 if (connector->cmdline_mode.specified)
1546 connector->cmdline_mode.specified = false;
1553 static struct drm_encoder *mga_connector_best_encoder(struct drm_connector
1556 int enc_id = connector->encoder_ids[0];
1557 /* pick the encoder ids */
1559 return drm_encoder_find(connector->dev, enc_id);
1563 static enum drm_connector_status mga_vga_detect(struct drm_connector
1564 *connector, bool force)
1566 return connector_status_connected;
1569 static void mga_connector_destroy(struct drm_connector *connector)
1571 struct mga_connector *mga_connector = to_mga_connector(connector);
1572 mgag200_i2c_destroy(mga_connector->i2c);
1573 drm_connector_cleanup(connector);
1577 struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1578 .get_modes = mga_vga_get_modes,
1579 .mode_valid = mga_vga_mode_valid,
1580 .best_encoder = mga_connector_best_encoder,
1583 struct drm_connector_funcs mga_vga_connector_funcs = {
1584 .dpms = drm_helper_connector_dpms,
1585 .detect = mga_vga_detect,
1586 .fill_modes = drm_helper_probe_single_connector_modes,
1587 .destroy = mga_connector_destroy,
1590 static struct drm_connector *mga_vga_init(struct drm_device *dev)
1592 struct drm_connector *connector;
1593 struct mga_connector *mga_connector;
1595 mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL);
1599 connector = &mga_connector->base;
1601 drm_connector_init(dev, connector,
1602 &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1604 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1606 drm_connector_register(connector);
1608 mga_connector->i2c = mgag200_i2c_create(dev);
1609 if (!mga_connector->i2c)
1610 DRM_ERROR("failed to add ddc bus\n");
1616 int mgag200_modeset_init(struct mga_device *mdev)
1618 struct drm_encoder *encoder;
1619 struct drm_connector *connector;
1622 mdev->mode_info.mode_config_initialized = true;
1624 mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1625 mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1627 mdev->dev->mode_config.fb_base = mdev->mc.vram_base;
1629 mga_crtc_init(mdev);
1631 encoder = mga_encoder_init(mdev->dev);
1633 DRM_ERROR("mga_encoder_init failed\n");
1637 connector = mga_vga_init(mdev->dev);
1639 DRM_ERROR("mga_vga_init failed\n");
1643 drm_mode_connector_attach_encoder(connector, encoder);
1645 ret = mgag200_fbdev_init(mdev);
1647 DRM_ERROR("mga_fbdev_init failed\n");
1654 void mgag200_modeset_fini(struct mga_device *mdev)