drivers/gpu/drm/msm/adreno/a4xx.xml.h

   1 #ifndef A4XX_XML
   2 #define A4XX_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
  12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
  13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
  14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
  15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15053 bytes, from 2014-11-09 15:45:47)
  16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  63169 bytes, from 2014-11-13 22:44:18)
  17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  49097 bytes, from 2014-11-14 15:38:00)
  18
  19 Copyright (C) 2013-2014 by the following authors:
  20 - Rob Clark <robdclark@gmail.com> (robclark)
  21
  22 Permission is hereby granted, free of charge, to any person obtaining
  23 a copy of this software and associated documentation files (the
  24 "Software"), to deal in the Software without restriction, including
  25 without limitation the rights to use, copy, modify, merge, publish,
  26 distribute, sublicense, and/or sell copies of the Software, and to
  27 permit persons to whom the Software is furnished to do so, subject to
  28 the following conditions:
  29
  30 The above copyright notice and this permission notice (including the
  31 next paragraph) shall be included in all copies or substantial
  32 portions of the Software.
  33
  34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  41 */
  42
  43
  44 enum a4xx_color_fmt {
  45         RB4_A8_UNORM = 1,
  46         RB4_R5G6R5_UNORM = 14,
  47         RB4_Z16_UNORM = 15,
  48         RB4_R8G8B8_UNORM = 25,
  49         RB4_R8G8B8A8_UNORM = 26,
  50 };
  51
  52 enum a4xx_tile_mode {
  53         TILE4_LINEAR = 0,
  54         TILE4_3 = 3,
  55 };
  56
  57 enum a4xx_rb_blend_opcode {
  58         BLEND_DST_PLUS_SRC = 0,
  59         BLEND_SRC_MINUS_DST = 1,
  60         BLEND_DST_MINUS_SRC = 2,
  61         BLEND_MIN_DST_SRC = 3,
  62         BLEND_MAX_DST_SRC = 4,
  63 };
  64
  65 enum a4xx_vtx_fmt {
  66         VFMT4_FLOAT_32 = 1,
  67         VFMT4_FLOAT_32_32 = 2,
  68         VFMT4_FLOAT_32_32_32 = 3,
  69         VFMT4_FLOAT_32_32_32_32 = 4,
  70         VFMT4_FLOAT_16 = 5,
  71         VFMT4_FLOAT_16_16 = 6,
  72         VFMT4_FLOAT_16_16_16 = 7,
  73         VFMT4_FLOAT_16_16_16_16 = 8,
  74         VFMT4_FIXED_32 = 9,
  75         VFMT4_FIXED_32_32 = 10,
  76         VFMT4_FIXED_32_32_32 = 11,
  77         VFMT4_FIXED_32_32_32_32 = 12,
  78         VFMT4_SHORT_16 = 16,
  79         VFMT4_SHORT_16_16 = 17,
  80         VFMT4_SHORT_16_16_16 = 18,
  81         VFMT4_SHORT_16_16_16_16 = 19,
  82         VFMT4_USHORT_16 = 20,
  83         VFMT4_USHORT_16_16 = 21,
  84         VFMT4_USHORT_16_16_16 = 22,
  85         VFMT4_USHORT_16_16_16_16 = 23,
  86         VFMT4_NORM_SHORT_16 = 24,
  87         VFMT4_NORM_SHORT_16_16 = 25,
  88         VFMT4_NORM_SHORT_16_16_16 = 26,
  89         VFMT4_NORM_SHORT_16_16_16_16 = 27,
  90         VFMT4_NORM_USHORT_16 = 28,
  91         VFMT4_NORM_USHORT_16_16 = 29,
  92         VFMT4_NORM_USHORT_16_16_16 = 30,
  93         VFMT4_NORM_USHORT_16_16_16_16 = 31,
  94         VFMT4_UBYTE_8 = 40,
  95         VFMT4_UBYTE_8_8 = 41,
  96         VFMT4_UBYTE_8_8_8 = 42,
  97         VFMT4_UBYTE_8_8_8_8 = 43,
  98         VFMT4_NORM_UBYTE_8 = 44,
  99         VFMT4_NORM_UBYTE_8_8 = 45,
 100         VFMT4_NORM_UBYTE_8_8_8 = 46,
 101         VFMT4_NORM_UBYTE_8_8_8_8 = 47,
 102         VFMT4_BYTE_8 = 48,
 103         VFMT4_BYTE_8_8 = 49,
 104         VFMT4_BYTE_8_8_8 = 50,
 105         VFMT4_BYTE_8_8_8_8 = 51,
 106         VFMT4_NORM_BYTE_8 = 52,
 107         VFMT4_NORM_BYTE_8_8 = 53,
 108         VFMT4_NORM_BYTE_8_8_8 = 54,
 109         VFMT4_NORM_BYTE_8_8_8_8 = 55,
 110         VFMT4_UINT_10_10_10_2 = 60,
 111         VFMT4_NORM_UINT_10_10_10_2 = 61,
 112         VFMT4_INT_10_10_10_2 = 62,
 113         VFMT4_NORM_INT_10_10_10_2 = 63,
 114 };
 115
 116 enum a4xx_tex_fmt {
 117         TFMT4_NORM_USHORT_565 = 11,
 118         TFMT4_NORM_USHORT_5551 = 10,
 119         TFMT4_NORM_USHORT_4444 = 8,
 120         TFMT4_NORM_UINT_X8Z24 = 71,
 121         TFMT4_NORM_UINT_2_10_10_10 = 33,
 122         TFMT4_NORM_UINT_A8 = 3,
 123         TFMT4_NORM_UINT_L8_A8 = 13,
 124         TFMT4_NORM_UINT_8 = 4,
 125         TFMT4_NORM_UINT_8_8_8_8 = 28,
 126         TFMT4_FLOAT_16 = 20,
 127         TFMT4_FLOAT_16_16 = 40,
 128         TFMT4_FLOAT_16_16_16_16 = 53,
 129         TFMT4_FLOAT_32 = 43,
 130         TFMT4_FLOAT_32_32 = 56,
 131         TFMT4_FLOAT_32_32_32_32 = 63,
 132 };
 133
 134 enum a4xx_depth_format {
 135         DEPTH4_NONE = 0,
 136         DEPTH4_16 = 1,
 137         DEPTH4_24_8 = 2,
 138 };
 139
 140 enum a4xx_tex_filter {
 141         A4XX_TEX_NEAREST = 0,
 142         A4XX_TEX_LINEAR = 1,
 143 };
 144
 145 enum a4xx_tex_clamp {
 146         A4XX_TEX_REPEAT = 0,
 147         A4XX_TEX_CLAMP_TO_EDGE = 1,
 148         A4XX_TEX_MIRROR_REPEAT = 2,
 149         A4XX_TEX_CLAMP_NONE = 3,
 150 };
 151
 152 enum a4xx_tex_swiz {
 153         A4XX_TEX_X = 0,
 154         A4XX_TEX_Y = 1,
 155         A4XX_TEX_Z = 2,
 156         A4XX_TEX_W = 3,
 157         A4XX_TEX_ZERO = 4,
 158         A4XX_TEX_ONE = 5,
 159 };
 160
 161 enum a4xx_tex_type {
 162         A4XX_TEX_1D = 0,
 163         A4XX_TEX_2D = 1,
 164         A4XX_TEX_CUBE = 2,
 165         A4XX_TEX_3D = 3,
 166 };
 167
 168 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK                           0x00700000
 169 #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT                          20
 170 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
 171 {
 172         return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
 173 }
 174 #define A4XX_INT0_RBBM_GPU_IDLE                                 0x00000001
 175 #define A4XX_INT0_RBBM_AHB_ERROR                                0x00000002
 176 #define A4XX_INT0_RBBM_REG_TIMEOUT                              0x00000004
 177 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT                            0x00000008
 178 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT                           0x00000010
 179 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW                         0x00000020
 180 #define A4XX_INT0_VFD_ERROR                                     0x00000040
 181 #define A4XX_INT0_CP_SW_INT                                     0x00000080
 182 #define A4XX_INT0_CP_T0_PACKET_IN_IB                            0x00000100
 183 #define A4XX_INT0_CP_OPCODE_ERROR                               0x00000200
 184 #define A4XX_INT0_CP_RESERVED_BIT_ERROR                         0x00000400
 185 #define A4XX_INT0_CP_HW_FAULT                                   0x00000800
 186 #define A4XX_INT0_CP_DMA                                        0x00001000
 187 #define A4XX_INT0_CP_IB2_INT                                    0x00002000
 188 #define A4XX_INT0_CP_IB1_INT                                    0x00004000
 189 #define A4XX_INT0_CP_RB_INT                                     0x00008000
 190 #define A4XX_INT0_CP_REG_PROTECT_FAULT                          0x00010000
 191 #define A4XX_INT0_CP_RB_DONE_TS                                 0x00020000
 192 #define A4XX_INT0_CP_VS_DONE_TS                                 0x00040000
 193 #define A4XX_INT0_CP_PS_DONE_TS                                 0x00080000
 194 #define A4XX_INT0_CACHE_FLUSH_TS                                0x00100000
 195 #define A4XX_INT0_CP_AHB_ERROR_HALT                             0x00200000
 196 #define A4XX_INT0_MISC_HANG_DETECT                              0x01000000
 197 #define A4XX_INT0_UCHE_OOB_ACCESS                               0x02000000
 198 #define REG_A4XX_RB_GMEM_BASE_ADDR                              0x00000cc0
 199
 200 #define REG_A4XX_RB_PERFCTR_RB_SEL_0                            0x00000cc7
 201
 202 #define REG_A4XX_RB_PERFCTR_RB_SEL_1                            0x00000cc8
 203
 204 #define REG_A4XX_RB_PERFCTR_RB_SEL_2                            0x00000cc9
 205
 206 #define REG_A4XX_RB_PERFCTR_RB_SEL_3                            0x00000cca
 207
 208 #define REG_A4XX_RB_PERFCTR_RB_SEL_4                            0x00000ccb
 209
 210 #define REG_A4XX_RB_PERFCTR_RB_SEL_5                            0x00000ccc
 211
 212 #define REG_A4XX_RB_PERFCTR_RB_SEL_6                            0x00000ccd
 213
 214 #define REG_A4XX_RB_PERFCTR_RB_SEL_7                            0x00000cce
 215
 216 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3                           0x00000cd2
 217
 218 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION                      0x00000ce0
 219 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK              0x00003fff
 220 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT             0
 221 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
 222 {
 223         return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
 224 }
 225 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK             0x3fff0000
 226 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT            16
 227 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
 228 {
 229         return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
 230 }
 231
 232 #define REG_A4XX_RB_CLEAR_COLOR_DW0                             0x000020cc
 233
 234 #define REG_A4XX_RB_CLEAR_COLOR_DW1                             0x000020cd
 235
 236 #define REG_A4XX_RB_CLEAR_COLOR_DW2                             0x000020ce
 237
 238 #define REG_A4XX_RB_CLEAR_COLOR_DW3                             0x000020cf
 239
 240 #define REG_A4XX_RB_MODE_CONTROL                                0x000020a0
 241 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK                        0x0000003f
 242 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT                       0
 243 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
 244 {
 245         return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
 246 }
 247 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK                       0x00003f00
 248 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT                      8
 249 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
 250 {
 251         return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
 252 }
 253
 254 #define REG_A4XX_RB_RENDER_CONTROL                              0x000020a1
 255 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS                     0x00000001
 256 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE               0x00000020
 257
 258 #define REG_A4XX_RB_MSAA_CONTROL                                0x000020a2
 259 #define A4XX_RB_MSAA_CONTROL_DISABLE                            0x00001000
 260 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK                      0x0000e000
 261 #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT                     13
 262 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
 263 {
 264         return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
 265 }
 266
 267 #define REG_A4XX_RB_MSAA_CONTROL2                               0x000020a3
 268 #define A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__MASK                0x00000380
 269 #define A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__SHIFT               7
 270 static inline uint32_t A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES(uint32_t val)
 271 {
 272         return ((val) << A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__MASK;
 273 }
 274 #define A4XX_RB_MSAA_CONTROL2_VARYING                           0x00001000
 275
 276 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
 277
 278 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
 279 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE                    0x00000008
 280 #define A4XX_RB_MRT_CONTROL_BLEND                               0x00000010
 281 #define A4XX_RB_MRT_CONTROL_BLEND2                              0x00000020
 282 #define A4XX_RB_MRT_CONTROL_FASTCLEAR                           0x00000400
 283 #define A4XX_RB_MRT_CONTROL_B11                                 0x00000800
 284 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK              0x0f000000
 285 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT             24
 286 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
 287 {
 288         return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
 289 }
 290
 291 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
 292 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK                 0x0000003f
 293 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT                0
 294 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
 295 {
 296         return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
 297 }
 298 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK                  0x00000600
 299 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT                 9
 300 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
 301 {
 302         return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
 303 }
 304 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK                   0x00001800
 305 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT                  11
 306 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
 307 {
 308         return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
 309 }
 310 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK              0x007fc000
 311 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT             14
 312 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
 313 {
 314         return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
 315 }
 316
 317 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
 318
 319 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
 320 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK                       0x0001fff8
 321 #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT                      3
 322 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
 323 {
 324         return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK;
 325 }
 326
 327 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
 328 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK          0x0000001f
 329 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT         0
 330 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
 331 {
 332         return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
 333 }
 334 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK        0x000000e0
 335 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT       5
 336 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
 337 {
 338         return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
 339 }
 340 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK         0x00001f00
 341 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT        8
 342 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
 343 {
 344         return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
 345 }
 346 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK        0x001f0000
 347 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT       16
 348 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
 349 {
 350         return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
 351 }
 352 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK      0x00e00000
 353 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT     21
 354 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
 355 {
 356         return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
 357 }
 358 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK       0x1f000000
 359 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT      24
 360 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
 361 {
 362         return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
 363 }
 364
 365 #define REG_A4XX_RB_ALPHA_CONTROL                               0x000020f8
 366 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST                        0x00000100
 367 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK             0x00000e00
 368 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT            9
 369 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
 370 {
 371         return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
 372 }
 373
 374 #define REG_A4XX_RB_FS_OUTPUT                                   0x000020f9
 375 #define A4XX_RB_FS_OUTPUT_ENABLE_COLOR_PIPE                     0x00000001
 376 #define A4XX_RB_FS_OUTPUT_FAST_CLEAR                            0x00000100
 377 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK                     0xffff0000
 378 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT                    16
 379 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
 380 {
 381         return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
 382 }
 383
 384 #define REG_A4XX_RB_RENDER_CONTROL3                             0x000020fb
 385 #define A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__MASK          0x0000001f
 386 #define A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__SHIFT         0
 387 static inline uint32_t A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE(uint32_t val)
 388 {
 389         return ((val) << A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__SHIFT) & A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__MASK;
 390 }
 391
 392 #define REG_A4XX_RB_COPY_CONTROL                                0x000020fc
 393 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK                 0x00000003
 394 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT                0
 395 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
 396 {
 397         return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
 398 }
 399 #define A4XX_RB_COPY_CONTROL_MODE__MASK                         0x00000070
 400 #define A4XX_RB_COPY_CONTROL_MODE__SHIFT                        4
 401 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
 402 {
 403         return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK;
 404 }
 405 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK                    0x00000f00
 406 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT                   8
 407 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
 408 {
 409         return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
 410 }
 411 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK                    0xffffc000
 412 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT                   14
 413 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
 414 {
 415         return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
 416 }
 417
 418 #define REG_A4XX_RB_COPY_DEST_BASE                              0x000020fd
 419 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK                       0xfffffff0
 420 #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT                      4
 421 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
 422 {
 423         return ((val >> 4) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
 424 }
 425
 426 #define REG_A4XX_RB_COPY_DEST_PITCH                             0x000020fe
 427 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK                     0xffffffff
 428 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT                    0
 429 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
 430 {
 431         return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
 432 }
 433
 434 #define REG_A4XX_RB_COPY_DEST_INFO                              0x000020ff
 435 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK                     0x000000fc
 436 #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT                    2
 437 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
 438 {
 439         return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK;
 440 }
 441 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK                       0x00000300
 442 #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT                      8
 443 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
 444 {
 445         return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK;
 446 }
 447 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK                0x00000c00
 448 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT               10
 449 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
 450 {
 451         return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
 452 }
 453 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK           0x0003c000
 454 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT          14
 455 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
 456 {
 457         return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
 458 }
 459 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK                     0x001c0000
 460 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT                    18
 461 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
 462 {
 463         return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
 464 }
 465 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK                       0x03000000
 466 #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT                      24
 467 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
 468 {
 469         return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK;
 470 }
 471
 472 #define REG_A4XX_RB_FS_OUTPUT_REG                               0x00002100
 473 #define A4XX_RB_FS_OUTPUT_REG_COLOR_PIPE_ENABLE                 0x00000001
 474 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z                     0x00000020
 475
 476 #define REG_A4XX_RB_DEPTH_CONTROL                               0x00002101
 477 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z                     0x00000001
 478 #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE                          0x00000002
 479 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE                    0x00000004
 480 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK                       0x00000070
 481 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT                      4
 482 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
 483 {
 484         return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
 485 }
 486 #define A4XX_RB_DEPTH_CONTROL_BF_ENABLE                         0x00000080
 487 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE                   0x00010000
 488 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE                     0x80000000
 489
 490 #define REG_A4XX_RB_DEPTH_CLEAR                                 0x00002102
 491
 492 #define REG_A4XX_RB_DEPTH_INFO                                  0x00002103
 493 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK                   0x00000003
 494 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT                  0
 495 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
 496 {
 497         return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
 498 }
 499 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK                     0xfffff000
 500 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT                    12
 501 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
 502 {
 503         return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
 504 }
 505
 506 #define REG_A4XX_RB_DEPTH_PITCH                                 0x00002104
 507 #define A4XX_RB_DEPTH_PITCH__MASK                               0xffffffff
 508 #define A4XX_RB_DEPTH_PITCH__SHIFT                              0
 509 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
 510 {
 511         return ((val >> 4) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
 512 }
 513
 514 #define REG_A4XX_RB_DEPTH_PITCH2                                0x00002105
 515 #define A4XX_RB_DEPTH_PITCH2__MASK                              0xffffffff
 516 #define A4XX_RB_DEPTH_PITCH2__SHIFT                             0
 517 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
 518 {
 519         return ((val >> 4) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
 520 }
 521
 522 #define REG_A4XX_RB_STENCIL_CONTROL                             0x00002106
 523 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE                  0x00000001
 524 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF               0x00000002
 525 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ                    0x00000004
 526 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK                      0x00000700
 527 #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT                     8
 528 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
 529 {
 530         return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK;
 531 }
 532 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK                      0x00003800
 533 #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT                     11
 534 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
 535 {
 536         return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK;
 537 }
 538 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK                     0x0001c000
 539 #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT                    14
 540 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
 541 {
 542         return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK;
 543 }
 544 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK                     0x000e0000
 545 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT                    17
 546 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
 547 {
 548         return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
 549 }
 550 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK                   0x00700000
 551 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT                  20
 552 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
 553 {
 554         return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
 555 }
 556 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK                   0x03800000
 557 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT                  23
 558 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
 559 {
 560         return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
 561 }
 562 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK                  0x1c000000
 563 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT                 26
 564 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
 565 {
 566         return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
 567 }
 568 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK                  0xe0000000
 569 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT                 29
 570 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
 571 {
 572         return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
 573 }
 574
 575 #define REG_A4XX_RB_STENCIL_CONTROL2                            0x00002107
 576 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER                 0x00000001
 577
 578 #define REG_A4XX_RB_STENCILREFMASK                              0x0000210b
 579 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK                 0x000000ff
 580 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT                0
 581 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
 582 {
 583         return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK;
 584 }
 585 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK                0x0000ff00
 586 #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT               8
 587 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
 588 {
 589         return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK;
 590 }
 591 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK           0x00ff0000
 592 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT          16
 593 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
 594 {
 595         return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
 596 }
 597
 598 #define REG_A4XX_RB_STENCILREFMASK_BF                           0x0000210c
 599 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK              0x000000ff
 600 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT             0
 601 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
 602 {
 603         return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
 604 }
 605 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK             0x0000ff00
 606 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT            8
 607 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
 608 {
 609         return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
 610 }
 611 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK        0x00ff0000
 612 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT       16
 613 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
 614 {
 615         return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
 616 }
 617
 618 #define REG_A4XX_RB_BIN_OFFSET                                  0x0000210d
 619 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE                0x80000000
 620 #define A4XX_RB_BIN_OFFSET_X__MASK                              0x00007fff
 621 #define A4XX_RB_BIN_OFFSET_X__SHIFT                             0
 622 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
 623 {
 624         return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK;
 625 }
 626 #define A4XX_RB_BIN_OFFSET_Y__MASK                              0x7fff0000
 627 #define A4XX_RB_BIN_OFFSET_Y__SHIFT                             16
 628 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
 629 {
 630         return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
 631 }
 632
 633 #define REG_A4XX_RB_VPORT_Z_CLAMP_MAX_15                        0x0000213f
 634
 635 #define REG_A4XX_RBBM_HW_VERSION                                0x00000000
 636
 637 #define REG_A4XX_RBBM_HW_CONFIGURATION                          0x00000002
 638
 639 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }
 640
 641 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
 642
 643 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }
 644
 645 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
 646
 647 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }
 648
 649 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
 650
 651 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }
 652
 653 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
 654
 655 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE                            0x00000014
 656
 657 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE                           0x00000015
 658
 659 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE                           0x00000016
 660
 661 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE                           0x00000017
 662
 663 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE                           0x00000018
 664
 665 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE                          0x00000019
 666
 667 #define REG_A4XX_RBBM_CLOCK_MODE_GPC                            0x0000001a
 668
 669 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC                           0x0000001b
 670
 671 #define REG_A4XX_RBBM_CLOCK_HYST_GPC                            0x0000001c
 672
 673 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM                    0x0000001d
 674
 675 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM                   0x0000001e
 676
 677 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM                  0x0000001f
 678
 679 #define REG_A4XX_RBBM_CLOCK_CTL                                 0x00000020
 680
 681 #define REG_A4XX_RBBM_SP_HYST_CNT                               0x00000021
 682
 683 #define REG_A4XX_RBBM_SW_RESET_CMD                              0x00000022
 684
 685 #define REG_A4XX_RBBM_AHB_CTL0                                  0x00000023
 686
 687 #define REG_A4XX_RBBM_AHB_CTL1                                  0x00000024
 688
 689 #define REG_A4XX_RBBM_AHB_CMD                                   0x00000025
 690
 691 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL                      0x00000026
 692
 693 #define REG_A4XX_RBBM_RAM_ACC_63_32                             0x00000028
 694
 695 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL                      0x0000002b
 696
 697 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL                    0x0000002f
 698
 699 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4                  0x00000034
 700
 701 #define REG_A4XX_RBBM_INT_CLEAR_CMD                             0x00000036
 702
 703 #define REG_A4XX_RBBM_INT_0_MASK                                0x00000037
 704
 705 #define REG_A4XX_RBBM_RBBM_CTL                                  0x0000003e
 706
 707 #define REG_A4XX_RBBM_AHB_DEBUG_CTL                             0x0000003f
 708
 709 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL                            0x00000041
 710
 711 #define REG_A4XX_RBBM_CLOCK_CTL2                                0x00000042
 712
 713 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD                        0x00000045
 714
 715 #define REG_A4XX_RBBM_RESET_CYCLES                              0x00000047
 716
 717 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL                         0x00000049
 718
 719 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A                          0x0000004a
 720
 721 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B                          0x0000004b
 722
 723 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C                          0x0000004c
 724
 725 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D                          0x0000004d
 726
 727 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO                           0x0000009c
 728
 729 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
 730
 731 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
 732
 733 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
 734
 735 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
 736
 737 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }
 738
 739 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
 740
 741 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }
 742
 743 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
 744
 745 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }
 746
 747 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
 748
 749 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }
 750
 751 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
 752
 753 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }
 754
 755 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
 756
 757 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; }
 758
 759 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
 760
 761 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM                       0x00000080
 762
 763 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM                        0x00000081
 764
 765 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ                            0x0000008a
 766
 767 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ                           0x0000008b
 768
 769 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ                          0x0000008c
 770
 771 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM                      0x0000008d
 772
 773 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
 774
 775 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
 776
 777 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO                          0x00000168
 778
 779 #define REG_A4XX_RBBM_PERFCTR_CTL                               0x00000170
 780
 781 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0                         0x00000171
 782
 783 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1                         0x00000172
 784
 785 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2                         0x00000173
 786
 787 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO                     0x00000174
 788
 789 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI                     0x00000175
 790
 791 #define REG_A4XX_RBBM_GPU_BUSY_MASKED                           0x0000017a
 792
 793 #define REG_A4XX_RBBM_INT_0_STATUS                              0x0000017d
 794
 795 #define REG_A4XX_RBBM_CLOCK_STATUS                              0x00000182
 796
 797 #define REG_A4XX_RBBM_AHB_STATUS                                0x00000189
 798
 799 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS                       0x0000018c
 800
 801 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS                      0x0000018d
 802
 803 #define REG_A4XX_RBBM_AHB_ERROR_STATUS                          0x0000018f
 804
 805 #define REG_A4XX_RBBM_STATUS                                    0x00000191
 806 #define A4XX_RBBM_STATUS_HI_BUSY                                0x00000001
 807 #define A4XX_RBBM_STATUS_CP_ME_BUSY                             0x00000002
 808 #define A4XX_RBBM_STATUS_CP_PFP_BUSY                            0x00000004
 809 #define A4XX_RBBM_STATUS_CP_NRT_BUSY                            0x00004000
 810 #define A4XX_RBBM_STATUS_VBIF_BUSY                              0x00008000
 811 #define A4XX_RBBM_STATUS_TSE_BUSY                               0x00010000
 812 #define A4XX_RBBM_STATUS_RAS_BUSY                               0x00020000
 813 #define A4XX_RBBM_STATUS_RB_BUSY                                0x00040000
 814 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY                          0x00080000
 815 #define A4XX_RBBM_STATUS_PC_VSD_BUSY                            0x00100000
 816 #define A4XX_RBBM_STATUS_VFD_BUSY                               0x00200000
 817 #define A4XX_RBBM_STATUS_VPC_BUSY                               0x00400000
 818 #define A4XX_RBBM_STATUS_UCHE_BUSY                              0x00800000
 819 #define A4XX_RBBM_STATUS_SP_BUSY                                0x01000000
 820 #define A4XX_RBBM_STATUS_TPL1_BUSY                              0x02000000
 821 #define A4XX_RBBM_STATUS_MARB_BUSY                              0x04000000
 822 #define A4XX_RBBM_STATUS_VSC_BUSY                               0x08000000
 823 #define A4XX_RBBM_STATUS_ARB_BUSY                               0x10000000
 824 #define A4XX_RBBM_STATUS_HLSQ_BUSY                              0x20000000
 825 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC                          0x40000000
 826 #define A4XX_RBBM_STATUS_GPU_BUSY                               0x80000000
 827
 828 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5                    0x0000019f
 829
 830 #define REG_A4XX_CP_SCRATCH_UMASK                               0x00000228
 831
 832 #define REG_A4XX_CP_SCRATCH_ADDR                                0x00000229
 833
 834 #define REG_A4XX_CP_RB_BASE                                     0x00000200
 835
 836 #define REG_A4XX_CP_RB_CNTL                                     0x00000201
 837
 838 #define REG_A4XX_CP_RB_WPTR                                     0x00000205
 839
 840 #define REG_A4XX_CP_RB_RPTR_ADDR                                0x00000203
 841
 842 #define REG_A4XX_CP_RB_RPTR                                     0x00000204
 843
 844 #define REG_A4XX_CP_IB1_BASE                                    0x00000206
 845
 846 #define REG_A4XX_CP_IB1_BUFSZ                                   0x00000207
 847
 848 #define REG_A4XX_CP_IB2_BASE                                    0x00000208
 849
 850 #define REG_A4XX_CP_IB2_BUFSZ                                   0x00000209
 851
 852 #define REG_A4XX_CP_ME_RB_DONE_DATA                             0x00000217
 853
 854 #define REG_A4XX_CP_QUEUE_THRESH2                               0x00000219
 855
 856 #define REG_A4XX_CP_MERCIU_SIZE                                 0x0000021b
 857
 858 #define REG_A4XX_CP_ROQ_ADDR                                    0x0000021c
 859
 860 #define REG_A4XX_CP_ROQ_DATA                                    0x0000021d
 861
 862 #define REG_A4XX_CP_MEQ_ADDR                                    0x0000021e
 863
 864 #define REG_A4XX_CP_MEQ_DATA                                    0x0000021f
 865
 866 #define REG_A4XX_CP_MERCIU_ADDR                                 0x00000220
 867
 868 #define REG_A4XX_CP_MERCIU_DATA                                 0x00000221
 869
 870 #define REG_A4XX_CP_MERCIU_DATA2                                0x00000222
 871
 872 #define REG_A4XX_CP_PFP_UCODE_ADDR                              0x00000223
 873
 874 #define REG_A4XX_CP_PFP_UCODE_DATA                              0x00000224
 875
 876 #define REG_A4XX_CP_ME_RAM_WADDR                                0x00000225
 877
 878 #define REG_A4XX_CP_ME_RAM_RADDR                                0x00000226
 879
 880 #define REG_A4XX_CP_ME_RAM_DATA                                 0x00000227
 881
 882 #define REG_A4XX_CP_PREEMPT                                     0x0000022a
 883
 884 #define REG_A4XX_CP_CNTL                                        0x0000022c
 885
 886 #define REG_A4XX_CP_ME_CNTL                                     0x0000022d
 887
 888 #define REG_A4XX_CP_DEBUG                                       0x0000022e
 889
 890 #define REG_A4XX_CP_DEBUG_ECO_CONTROL                           0x00000231
 891
 892 #define REG_A4XX_CP_DRAW_STATE_ADDR                             0x00000232
 893
 894 #define REG_A4XX_CP_PROTECT_REG_0                               0x00000240
 895
 896 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
 897
 898 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
 899
 900 #define REG_A4XX_CP_PROTECT_CTRL                                0x00000250
 901
 902 #define REG_A4XX_CP_ST_BASE                                     0x000004c0
 903
 904 #define REG_A4XX_CP_STQ_AVAIL                                   0x000004ce
 905
 906 #define REG_A4XX_CP_MERCIU_STAT                                 0x000004d0
 907
 908 #define REG_A4XX_CP_WFI_PEND_CTR                                0x000004d2
 909
 910 #define REG_A4XX_CP_HW_FAULT                                    0x000004d8
 911
 912 #define REG_A4XX_CP_PROTECT_STATUS                              0x000004da
 913
 914 #define REG_A4XX_CP_EVENTS_IN_FLIGHT                            0x000004dd
 915
 916 #define REG_A4XX_CP_PERFCTR_CP_SEL_0                            0x00000500
 917
 918 #define REG_A4XX_CP_PERFCOMBINER_SELECT                         0x0000050b
 919
 920 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
 921
 922 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
 923
 924 #define REG_A4XX_SP_VS_STATUS                                   0x00000ec0
 925
 926 #define REG_A4XX_SP_PERFCTR_SP_SEL_11                           0x00000ecf
 927
 928 #define REG_A4XX_SP_SP_CTRL_REG                                 0x000022c0
 929 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS                        0x00080000
 930
 931 #define REG_A4XX_SP_INSTR_CACHE_CTRL                            0x000022c1
 932
 933 #define REG_A4XX_SP_VS_CTRL_REG0                                0x000022c4
 934 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK                   0x00000001
 935 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT                  0
 936 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
 937 {
 938         return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
 939 }
 940 #define A4XX_SP_VS_CTRL_REG0_VARYING                            0x00000002
 941 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID                       0x00000004
 942 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
 943 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
 944 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
 945 {
 946         return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
 947 }
 948 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0003fc00
 949 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
 950 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
 951 {
 952         return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
 953 }
 954 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK              0x000c0000
 955 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT             18
 956 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
 957 {
 958         return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
 959 }
 960 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
 961 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT                  20
 962 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
 963 {
 964         return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
 965 }
 966 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE                    0x00200000
 967 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE                       0x00400000
 968
 969 #define REG_A4XX_SP_VS_CTRL_REG1                                0x000022c5
 970 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK                  0x000000ff
 971 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT                 0
 972 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
 973 {
 974         return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
 975 }
 976 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK           0x7f000000
 977 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT          24
 978 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
 979 {
 980         return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
 981 }
 982
 983 #define REG_A4XX_SP_VS_PARAM_REG                                0x000022c6
 984 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK                     0x000000ff
 985 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT                    0
 986 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
 987 {
 988         return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK;
 989 }
 990 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK                   0x0000ff00
 991 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT                  8
 992 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
 993 {
 994         return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
 995 }
 996 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK                0xfff00000
 997 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT               20
 998 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
 999 {
1000         return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
1001 }
1002
1003 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
1004
1005 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
1006 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK                        0x000001ff
1007 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT                       0
1008 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
1009 {
1010         return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK;
1011 }
1012 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK                     0x00001e00
1013 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT                    9
1014 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
1015 {
1016         return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
1017 }
1018 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK                        0x01ff0000
1019 #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT                       16
1020 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
1021 {
1022         return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK;
1023 }
1024 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK                     0x1e000000
1025 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT                    25
1026 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
1027 {
1028         return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
1029 }
1030
1031 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
1032
1033 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
1034 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK                    0x000000ff
1035 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT                   0
1036 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
1037 {
1038         return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
1039 }
1040 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK                    0x0000ff00
1041 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT                   8
1042 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
1043 {
1044         return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
1045 }
1046 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK                    0x00ff0000
1047 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT                   16
1048 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
1049 {
1050         return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
1051 }
1052 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK                    0xff000000
1053 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT                   24
1054 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
1055 {
1056         return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
1057 }
1058
1059 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG                           0x000022e0
1060 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
1061 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
1062 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1063 {
1064         return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1065 }
1066 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
1067 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
1068 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1069 {
1070         return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1071 }
1072
1073 #define REG_A4XX_SP_VS_OBJ_START                                0x000022e1
1074
1075 #define REG_A4XX_SP_VS_PVT_MEM_PARAM                            0x000022e2
1076
1077 #define REG_A4XX_SP_VS_PVT_MEM_ADDR                             0x000022e3
1078
1079 #define REG_A4XX_SP_VS_LENGTH_REG                               0x000022e5
1080
1081 #define REG_A4XX_SP_FS_CTRL_REG0                                0x000022e8
1082 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK                   0x00000001
1083 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT                  0
1084 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
1085 {
1086         return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
1087 }
1088 #define A4XX_SP_FS_CTRL_REG0_VARYING                            0x00000002
1089 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID                       0x00000004
1090 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
1091 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
1092 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
1093 {
1094         return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
1095 }
1096 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0003fc00
1097 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
1098 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
1099 {
1100         return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
1101 }
1102 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK              0x000c0000
1103 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT             18
1104 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
1105 {
1106         return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
1107 }
1108 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
1109 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT                  20
1110 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
1111 {
1112         return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
1113 }
1114 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE                    0x00200000
1115 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE                       0x00400000
1116
1117 #define REG_A4XX_SP_FS_CTRL_REG1                                0x000022e9
1118 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK                  0x000000ff
1119 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT                 0
1120 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
1121 {
1122         return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
1123 }
1124 #define A4XX_SP_FS_CTRL_REG1_VARYING                            0x00100000
1125
1126 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG                           0x000022ea
1127 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
1128 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
1129 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1130 {
1131         return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1132 }
1133 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
1134 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
1135 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1136 {
1137         return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1138 }
1139
1140 #define REG_A4XX_SP_FS_OBJ_START                                0x000022eb
1141
1142 #define REG_A4XX_SP_FS_PVT_MEM_PARAM                            0x000022ec
1143
1144 #define REG_A4XX_SP_FS_PVT_MEM_ADDR                             0x000022ed
1145
1146 #define REG_A4XX_SP_FS_LENGTH_REG                               0x000022ef
1147
1148 #define REG_A4XX_SP_FS_OUTPUT_REG                               0x000022f0
1149 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE                      0x00000080
1150 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK                 0x0000ff00
1151 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT                8
1152 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
1153 {
1154         return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
1155 }
1156
1157 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
1158
1159 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
1160 #define A4XX_SP_FS_MRT_REG_REGID__MASK                          0x000000ff
1161 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT                         0
1162 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
1163 {
1164         return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
1165 }
1166 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION                       0x00000100
1167 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK                      0x0003f000
1168 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT                     12
1169 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
1170 {
1171         return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
1172 }
1173
1174 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG                           0x0000230d
1175 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
1176 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
1177 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1178 {
1179         return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1180 }
1181 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
1182 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
1183 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1184 {
1185         return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1186 }
1187
1188 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG                           0x00002334
1189 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
1190 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
1191 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1192 {
1193         return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1194 }
1195 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
1196 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
1197 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1198 {
1199         return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1200 }
1201
1202 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG                           0x0000235b
1203 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
1204 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
1205 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1206 {
1207         return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1208 }
1209 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
1210 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
1211 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1212 {
1213         return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1214 }
1215
1216 #define REG_A4XX_SP_GS_LENGTH_REG                               0x00002360
1217
1218 #define REG_A4XX_VPC_DEBUG_RAM_SEL                              0x00000e60
1219
1220 #define REG_A4XX_VPC_DEBUG_RAM_READ                             0x00000e61
1221
1222 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL                          0x00000e64
1223
1224 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3                          0x00000e68
1225
1226 #define REG_A4XX_VPC_ATTR                                       0x00002140
1227 #define A4XX_VPC_ATTR_TOTALATTR__MASK                           0x000001ff
1228 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT                          0
1229 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
1230 {
1231         return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;
1232 }
1233 #define A4XX_VPC_ATTR_PSIZE                                     0x00000200
1234 #define A4XX_VPC_ATTR_THRDASSIGN__MASK                          0x00003000
1235 #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT                         12
1236 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
1237 {
1238         return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK;
1239 }
1240 #define A4XX_VPC_ATTR_ENABLE                                    0x02000000
1241
1242 #define REG_A4XX_VPC_PACK                                       0x00002141
1243 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK                        0x000000ff
1244 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT                       0
1245 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
1246 {
1247         return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK;
1248 }
1249 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK                      0x0000ff00
1250 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT                     8
1251 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
1252 {
1253         return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
1254 }
1255 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK                      0x00ff0000
1256 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT                     16
1257 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
1258 {
1259         return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
1260 }
1261
1262 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }
1263
1264 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
1265
1266 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }
1267
1268 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
1269
1270 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3                           0x0000216e
1271
1272 #define REG_A4XX_VSC_BIN_SIZE                                   0x00000c00
1273 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK                           0x0000001f
1274 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT                          0
1275 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
1276 {
1277         return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
1278 }
1279 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK                          0x000003e0
1280 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT                         5
1281 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
1282 {
1283         return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
1284 }
1285
1286 #define REG_A4XX_VSC_SIZE_ADDRESS                               0x00000c01
1287
1288 #define REG_A4XX_VSC_SIZE_ADDRESS2                              0x00000c02
1289
1290 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL                          0x00000c03
1291
1292 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
1293
1294 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
1295 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK                        0x000003ff
1296 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT                       0
1297 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
1298 {
1299         return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK;
1300 }
1301 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK                        0x000ffc00
1302 #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT                       10
1303 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
1304 {
1305         return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK;
1306 }
1307 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK                        0x00f00000
1308 #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT                       20
1309 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
1310 {
1311         return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK;
1312 }
1313 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK                        0x0f000000
1314 #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT                       24
1315 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
1316 {
1317         return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
1318 }
1319
1320 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1321
1322 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1323
1324 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
1325
1326 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
1327
1328 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1                        0x00000c41
1329
1330 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0                          0x00000c50
1331
1332 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1                          0x00000c51
1333
1334 #define REG_A4XX_VFD_DEBUG_CONTROL                              0x00000e40
1335
1336 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7                          0x00000e4a
1337
1338 #define REG_A4XX_VFD_CONTROL_0                                  0x00002200
1339 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK                  0x000000ff
1340 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT                 0
1341 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
1342 {
1343         return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
1344 }
1345 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK                  0x0001fe00
1346 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT                 9
1347 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
1348 {
1349         return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK;
1350 }
1351 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK                0x03f00000
1352 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT               20
1353 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
1354 {
1355         return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
1356 }
1357 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK              0xfc000000
1358 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT             26
1359 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
1360 {
1361         return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
1362 }
1363
1364 #define REG_A4XX_VFD_CONTROL_1                                  0x00002201
1365 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK                     0x0000ffff
1366 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT                    0
1367 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
1368 {
1369         return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
1370 }
1371 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK                      0x00ff0000
1372 #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT                     16
1373 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
1374 {
1375         return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK;
1376 }
1377 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK                     0xff000000
1378 #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT                    24
1379 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
1380 {
1381         return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK;
1382 }
1383
1384 #define REG_A4XX_VFD_CONTROL_2                                  0x00002202
1385
1386 #define REG_A4XX_VFD_CONTROL_3                                  0x00002203
1387
1388 #define REG_A4XX_VFD_CONTROL_4                                  0x00002204
1389
1390 #define REG_A4XX_VFD_INDEX_OFFSET                               0x00002208
1391
1392 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }
1393
1394 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
1395 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK                  0x0000007f
1396 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT                 0
1397 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
1398 {
1399         return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
1400 }
1401 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK                  0x0001ff80
1402 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT                 7
1403 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
1404 {
1405         return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
1406 }
1407 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT                       0x00080000
1408 #define A4XX_VFD_FETCH_INSTR_0_STEPRATE__MASK                   0xff000000
1409 #define A4XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT                  24
1410 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val)
1411 {
1412         return ((val) << A4XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_STEPRATE__MASK;
1413 }
1414
1415 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
1416
1417 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
1418 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK                       0xfffffff0
1419 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT                      4
1420 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
1421 {
1422         return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
1423 }
1424
1425 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
1426
1427 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
1428
1429 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
1430 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK                   0x0000000f
1431 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT                  0
1432 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
1433 {
1434         return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
1435 }
1436 #define A4XX_VFD_DECODE_INSTR_CONSTFILL                         0x00000010
1437 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK                      0x00000fc0
1438 #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT                     6
1439 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
1440 {
1441         return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK;
1442 }
1443 #define A4XX_VFD_DECODE_INSTR_REGID__MASK                       0x000ff000
1444 #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT                      12
1445 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
1446 {
1447         return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
1448 }
1449 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK                        0x00c00000
1450 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT                       22
1451 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
1452 {
1453         return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK;
1454 }
1455 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK                    0x1f000000
1456 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT                   24
1457 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
1458 {
1459         return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
1460 }
1461 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID                     0x20000000
1462 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT                        0x40000000
1463
1464 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL                         0x00000f00
1465
1466 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7                          0x00000f0b
1467
1468 #define REG_A4XX_TPL1_TP_TEX_OFFSET                             0x00002380
1469
1470 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR                 0x000023a6
1471
1472 #define REG_A4XX_GRAS_TSE_STATUS                                0x00000c80
1473
1474 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL                         0x00000c81
1475
1476 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0                         0x00000c88
1477
1478 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3                         0x00000c8b
1479
1480 #define REG_A4XX_GRAS_CL_CLIP_CNTL                              0x00002000
1481
1482 #define REG_A4XX_GRAS_CLEAR_CNTL                                0x00002003
1483 #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR                      0x00000001
1484
1485 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ                            0x00002004
1486 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK                     0x000003ff
1487 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT                    0
1488 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
1489 {
1490         return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
1491 }
1492 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK                     0x000ffc00
1493 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT                    10
1494 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
1495 {
1496         return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
1497 }
1498
1499 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0                        0x00002008
1500 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK                      0xffffffff
1501 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT                     0
1502 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
1503 {
1504         return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
1505 }
1506
1507 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0                         0x00002009
1508 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK                       0xffffffff
1509 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT                      0
1510 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
1511 {
1512         return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK;
1513 }
1514
1515 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0                        0x0000200a
1516 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK                      0xffffffff
1517 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT                     0
1518 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
1519 {
1520         return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
1521 }
1522
1523 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0                         0x0000200b
1524 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK                       0xffffffff
1525 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT                      0
1526 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
1527 {
1528         return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK;
1529 }
1530
1531 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0                        0x0000200c
1532 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK                      0xffffffff
1533 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT                     0
1534 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
1535 {
1536         return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
1537 }
1538
1539 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0                         0x0000200d
1540 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK                       0xffffffff
1541 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT                      0
1542 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
1543 {
1544         return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
1545 }
1546
1547 #define REG_A4XX_GRAS_SU_POINT_MINMAX                           0x00002070
1548 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK                     0x0000ffff
1549 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT                    0
1550 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
1551 {
1552         return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
1553 }
1554 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK                     0xffff0000
1555 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT                    16
1556 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
1557 {
1558         return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
1559 }
1560
1561 #define REG_A4XX_GRAS_SU_POINT_SIZE                             0x00002071
1562 #define A4XX_GRAS_SU_POINT_SIZE__MASK                           0xffffffff
1563 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT                          0
1564 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
1565 {
1566         return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
1567 }
1568
1569 #define REG_A4XX_GRAS_ALPHA_CONTROL                             0x00002073
1570 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE               0x00000004
1571
1572 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE                      0x00002074
1573 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK                    0xffffffff
1574 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT                   0
1575 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
1576 {
1577         return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
1578 }
1579
1580 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET                     0x00002075
1581 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK                   0xffffffff
1582 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT                  0
1583 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
1584 {
1585         return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
1586 }
1587
1588 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL                       0x0000209f
1589
1590 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL                      0x0000207c
1591 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE    0x80000000
1592 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK                  0x00007fff
1593 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT                 0
1594 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
1595 {
1596         return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
1597 }
1598 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK                  0x7fff0000
1599 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT                 16
1600 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
1601 {
1602         return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
1603 }
1604
1605 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR                      0x0000207d
1606 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE    0x80000000
1607 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK                  0x00007fff
1608 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT                 0
1609 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
1610 {
1611         return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
1612 }
1613 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK                  0x7fff0000
1614 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT                 16
1615 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
1616 {
1617         return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
1618 }
1619
1620 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR                      0x0000209c
1621 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE    0x80000000
1622 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK                  0x00007fff
1623 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT                 0
1624 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
1625 {
1626         return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
1627 }
1628 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK                  0x7fff0000
1629 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT                 16
1630 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
1631 {
1632         return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
1633 }
1634
1635 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL                      0x0000209d
1636 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE    0x80000000
1637 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK                  0x00007fff
1638 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT                 0
1639 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
1640 {
1641         return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
1642 }
1643 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK                  0x7fff0000
1644 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT                 16
1645 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
1646 {
1647         return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
1648 }
1649
1650 #define REG_A4XX_GRAS_DEPTH_CONTROL                             0x00002077
1651 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK                    0x00000003
1652 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT                   0
1653 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
1654 {
1655         return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
1656 }
1657
1658 #define REG_A4XX_GRAS_SU_MODE_CONTROL                           0x00002078
1659 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT                    0x00000001
1660 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK                     0x00000002
1661 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW                      0x00000004
1662 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK           0x000007f8
1663 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT          3
1664 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
1665 {
1666         return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
1667 }
1668 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET                   0x00000800
1669 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS                0x00100000
1670
1671 #define REG_A4XX_GRAS_SC_CONTROL                                0x0000207b
1672 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK                  0x0000000c
1673 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT                 2
1674 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
1675 {
1676         return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
1677 }
1678 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK                 0x00000380
1679 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT                7
1680 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
1681 {
1682         return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
1683 }
1684 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE                       0x00000800
1685 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK                  0x0000f000
1686 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT                 12
1687 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
1688 {
1689         return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
1690 }
1691
1692 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL                        0x00000e80
1693
1694 #define REG_A4XX_UCHE_TRAP_BASE_LO                              0x00000e83
1695
1696 #define REG_A4XX_UCHE_TRAP_BASE_HI                              0x00000e84
1697
1698 #define REG_A4XX_UCHE_CACHE_STATUS                              0x00000e88
1699
1700 #define REG_A4XX_UCHE_INVALIDATE0                               0x00000e8a
1701
1702 #define REG_A4XX_UCHE_INVALIDATE1                               0x00000e8b
1703
1704 #define REG_A4XX_UCHE_CACHE_WAYS_VFD                            0x00000e8c
1705
1706 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7                        0x00000e95
1707
1708 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD                         0x00000e00
1709
1710 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL                         0x00000e04
1711
1712 #define REG_A4XX_HLSQ_PERF_PIPE_MASK                            0x00000e0e
1713
1714 #define REG_A4XX_HLSQ_CONTROL_0_REG                             0x000023c0
1715 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK              0x00000010
1716 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT             4
1717 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
1718 {
1719         return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
1720 }
1721 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE             0x00000040
1722 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART                 0x00000200
1723 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2                       0x00000400
1724 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE                    0x04000000
1725 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK                 0x08000000
1726 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT                27
1727 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
1728 {
1729         return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
1730 }
1731 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE               0x10000000
1732 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE               0x20000000
1733 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE                    0x40000000
1734 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT                   0x80000000
1735
1736 #define REG_A4XX_HLSQ_CONTROL_1_REG                             0x000023c1
1737 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK              0x00000040
1738 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT             6
1739 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
1740 {
1741         return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
1742 }
1743 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE             0x00000100
1744 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1                       0x00000200
1745 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORD                         0x02000000
1746
1747 #define REG_A4XX_HLSQ_CONTROL_2_REG                             0x000023c2
1748 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK        0xfc000000
1749 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT       26
1750 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
1751 {
1752         return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
1753 }
1754
1755 #define REG_A4XX_HLSQ_CONTROL_3_REG                             0x000023c3
1756 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK                     0x000000ff
1757 #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT                    0
1758 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
1759 {
1760         return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
1761 }
1762
1763 #define REG_A4XX_HLSQ_VS_CONTROL_REG                            0x000023c5
1764 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK              0x000000ff
1765 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT             0
1766 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
1767 {
1768         return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
1769 }
1770 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK        0x0000ff00
1771 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT       8
1772 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
1773 {
1774         return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
1775 }
1776 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK          0x00fe0000
1777 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT         17
1778 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
1779 {
1780         return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
1781 }
1782 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
1783 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT             24
1784 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
1785 {
1786         return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
1787 }
1788
1789 #define REG_A4XX_HLSQ_FS_CONTROL_REG                            0x000023c6
1790 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK              0x000000ff
1791 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT             0
1792 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
1793 {
1794         return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
1795 }
1796 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK        0x0000ff00
1797 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT       8
1798 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
1799 {
1800         return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
1801 }
1802 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK          0x00fe0000
1803 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT         17
1804 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
1805 {
1806         return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
1807 }
1808 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
1809 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT             24
1810 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
1811 {
1812         return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
1813 }
1814
1815 #define REG_A4XX_HLSQ_HS_CONTROL_REG                            0x000023c7
1816 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK              0x000000ff
1817 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT             0
1818 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
1819 {
1820         return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
1821 }
1822 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK        0x0000ff00
1823 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT       8
1824 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
1825 {
1826         return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
1827 }
1828 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK          0x00fe0000
1829 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT         17
1830 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
1831 {
1832         return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
1833 }
1834 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
1835 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT             24
1836 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
1837 {
1838         return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK;
1839 }
1840
1841 #define REG_A4XX_HLSQ_DS_CONTROL_REG                            0x000023c8
1842 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK              0x000000ff
1843 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT             0
1844 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
1845 {
1846         return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
1847 }
1848 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK        0x0000ff00
1849 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT       8
1850 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
1851 {
1852         return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
1853 }
1854 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK          0x00fe0000
1855 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT         17
1856 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
1857 {
1858         return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
1859 }
1860 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
1861 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT             24
1862 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
1863 {
1864         return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK;
1865 }
1866
1867 #define REG_A4XX_HLSQ_GS_CONTROL_REG                            0x000023c9
1868 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK              0x000000ff
1869 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT             0
1870 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
1871 {
1872         return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
1873 }
1874 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK        0x0000ff00
1875 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT       8
1876 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
1877 {
1878         return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
1879 }
1880 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK          0x00fe0000
1881 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT         17
1882 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
1883 {
1884         return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
1885 }
1886 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
1887 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT             24
1888 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
1889 {
1890         return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
1891 }
1892
1893 #define REG_A4XX_HLSQ_UPDATE_CONTROL                            0x000023db
1894
1895 #define REG_A4XX_PC_BINNING_COMMAND                             0x00000d00
1896 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE                  0x00000001
1897
1898 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE                     0x00000d0c
1899
1900 #define REG_A4XX_PC_PERFCTR_PC_SEL_0                            0x00000d10
1901
1902 #define REG_A4XX_PC_PERFCTR_PC_SEL_7                            0x00000d17
1903
1904 #define REG_A4XX_PC_BIN_BASE                                    0x000021c0
1905
1906 #define REG_A4XX_PC_PRIM_VTX_CNTL                               0x000021c4
1907 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT                            0x00000001
1908 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST                0x02000000
1909 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE                             0x04000000
1910
1911 #define REG_A4XX_UNKNOWN_21C5                                   0x000021c5
1912
1913 #define REG_A4XX_PC_RESTART_INDEX                               0x000021c6
1914
1915 #define REG_A4XX_PC_GS_PARAM                                    0x000021e5
1916
1917 #define REG_A4XX_PC_HS_PARAM                                    0x000021e7
1918
1919 #define REG_A4XX_VBIF_VERSION                                   0x00003000
1920
1921 #define REG_A4XX_VBIF_CLKON                                     0x00003001
1922 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS                        0x00000001
1923
1924 #define REG_A4XX_VBIF_ABIT_SORT                                 0x0000301c
1925
1926 #define REG_A4XX_VBIF_ABIT_SORT_CONF                            0x0000301d
1927
1928 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN                         0x0000302a
1929
1930 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0                           0x0000302c
1931
1932 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1                           0x0000302d
1933
1934 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0                           0x00003030
1935
1936 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1                           0x00003031
1937
1938 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB                       0x00003049
1939
1940 #define REG_A4XX_UNKNOWN_0CC5                                   0x00000cc5
1941
1942 #define REG_A4XX_UNKNOWN_0CC6                                   0x00000cc6
1943
1944 #define REG_A4XX_UNKNOWN_0D01                                   0x00000d01
1945
1946 #define REG_A4XX_UNKNOWN_0E05                                   0x00000e05
1947
1948 #define REG_A4XX_UNKNOWN_0E42                                   0x00000e42
1949
1950 #define REG_A4XX_UNKNOWN_0EC2                                   0x00000ec2
1951
1952 #define REG_A4XX_UNKNOWN_0EC3                                   0x00000ec3
1953
1954 #define REG_A4XX_UNKNOWN_0F03                                   0x00000f03
1955
1956 #define REG_A4XX_UNKNOWN_2001                                   0x00002001
1957
1958 #define REG_A4XX_UNKNOWN_209B                                   0x0000209b
1959
1960 #define REG_A4XX_UNKNOWN_20EF                                   0x000020ef
1961
1962 #define REG_A4XX_UNKNOWN_20F0                                   0x000020f0
1963
1964 #define REG_A4XX_UNKNOWN_20F1                                   0x000020f1
1965
1966 #define REG_A4XX_UNKNOWN_20F2                                   0x000020f2
1967
1968 #define REG_A4XX_UNKNOWN_20F3                                   0x000020f3
1969
1970 #define REG_A4XX_UNKNOWN_20F4                                   0x000020f4
1971
1972 #define REG_A4XX_UNKNOWN_20F5                                   0x000020f5
1973
1974 #define REG_A4XX_UNKNOWN_20F6                                   0x000020f6
1975
1976 #define REG_A4XX_UNKNOWN_20F7                                   0x000020f7
1977
1978 #define REG_A4XX_UNKNOWN_2152                                   0x00002152
1979
1980 #define REG_A4XX_UNKNOWN_2153                                   0x00002153
1981
1982 #define REG_A4XX_UNKNOWN_2154                                   0x00002154
1983
1984 #define REG_A4XX_UNKNOWN_2155                                   0x00002155
1985
1986 #define REG_A4XX_UNKNOWN_2156                                   0x00002156
1987
1988 #define REG_A4XX_UNKNOWN_2157                                   0x00002157
1989
1990 #define REG_A4XX_UNKNOWN_21C3                                   0x000021c3
1991
1992 #define REG_A4XX_UNKNOWN_21E6                                   0x000021e6
1993
1994 #define REG_A4XX_UNKNOWN_2209                                   0x00002209
1995
1996 #define REG_A4XX_UNKNOWN_22D7                                   0x000022d7
1997
1998 #define REG_A4XX_UNKNOWN_2381                                   0x00002381
1999
2000 #define REG_A4XX_UNKNOWN_23A0                                   0x000023a0
2001
2002 #define REG_A4XX_TEX_SAMP_0                                     0x00000000
2003 #define A4XX_TEX_SAMP_0_XY_MAG__MASK                            0x00000006
2004 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT                           1
2005 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
2006 {
2007         return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK;
2008 }
2009 #define A4XX_TEX_SAMP_0_XY_MIN__MASK                            0x00000018
2010 #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT                           3
2011 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
2012 {
2013         return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK;
2014 }
2015 #define A4XX_TEX_SAMP_0_WRAP_S__MASK                            0x000000e0
2016 #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT                           5
2017 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
2018 {
2019         return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK;
2020 }
2021 #define A4XX_TEX_SAMP_0_WRAP_T__MASK                            0x00000700
2022 #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT                           8
2023 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
2024 {
2025         return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK;
2026 }
2027 #define A4XX_TEX_SAMP_0_WRAP_R__MASK                            0x00003800
2028 #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT                           11
2029 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
2030 {
2031         return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
2032 }
2033
2034 #define REG_A4XX_TEX_SAMP_1                                     0x00000001
2035 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK                      0x0000000e
2036 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT                     1
2037 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
2038 {
2039         return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
2040 }
2041 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK                           0x000fff00
2042 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT                          8
2043 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
2044 {
2045         return ((((uint32_t)(val * 64.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
2046 }
2047 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK                           0xfff00000
2048 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT                          20
2049 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
2050 {
2051         return ((((uint32_t)(val * 64.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
2052 }
2053
2054 #define REG_A4XX_TEX_CONST_0                                    0x00000000
2055 #define A4XX_TEX_CONST_0_TILED                                  0x00000001
2056 #define A4XX_TEX_CONST_0_SWIZ_X__MASK                           0x00000070
2057 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT                          4
2058 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
2059 {
2060         return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK;
2061 }
2062 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK                           0x00000380
2063 #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT                          7
2064 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
2065 {
2066         return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK;
2067 }
2068 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK                           0x00001c00
2069 #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT                          10
2070 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
2071 {
2072         return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK;
2073 }
2074 #define A4XX_TEX_CONST_0_SWIZ_W__MASK                           0x0000e000
2075 #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT                          13
2076 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
2077 {
2078         return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
2079 }
2080 #define A4XX_TEX_CONST_0_FMT__MASK                              0x1fc00000
2081 #define A4XX_TEX_CONST_0_FMT__SHIFT                             22
2082 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
2083 {
2084         return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
2085 }
2086 #define A4XX_TEX_CONST_0_TYPE__MASK                             0x60000000
2087 #define A4XX_TEX_CONST_0_TYPE__SHIFT                            29
2088 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
2089 {
2090         return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK;
2091 }
2092
2093 #define REG_A4XX_TEX_CONST_1                                    0x00000001
2094 #define A4XX_TEX_CONST_1_HEIGHT__MASK                           0x00007fff
2095 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT                          0
2096 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
2097 {
2098         return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
2099 }
2100 #define A4XX_TEX_CONST_1_WIDTH__MASK                            0x1fff8000
2101 #define A4XX_TEX_CONST_1_WIDTH__SHIFT                           15
2102 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
2103 {
2104         return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
2105 }
2106
2107 #define REG_A4XX_TEX_CONST_2                                    0x00000002
2108 #define A4XX_TEX_CONST_2_PITCH__MASK                            0x3ffffe00
2109 #define A4XX_TEX_CONST_2_PITCH__SHIFT                           9
2110 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
2111 {
2112         return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK;
2113 }
2114 #define A4XX_TEX_CONST_2_SWAP__MASK                             0xc0000000
2115 #define A4XX_TEX_CONST_2_SWAP__SHIFT                            30
2116 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
2117 {
2118         return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK;
2119 }
2120
2121 #define REG_A4XX_TEX_CONST_3                                    0x00000003
2122 #define A4XX_TEX_CONST_3_LAYERSZ__MASK                          0x0000000f
2123 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT                         0
2124 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
2125 {
2126         return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
2127 }
2128
2129 #define REG_A4XX_TEX_CONST_4                                    0x00000004
2130 #define A4XX_TEX_CONST_4_BASE__MASK                             0xffffffff
2131 #define A4XX_TEX_CONST_4_BASE__SHIFT                            0
2132 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
2133 {
2134         return ((val) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
2135 }
2136
2137 #define REG_A4XX_TEX_CONST_5                                    0x00000005
2138
2139 #define REG_A4XX_TEX_CONST_6                                    0x00000006
2140
2141 #define REG_A4XX_TEX_CONST_7                                    0x00000007
2142
2143
2144 #endif /* A4XX_XML */