2 * Copyright (C) 2013-2014 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include "adreno_gpu.h"
20 #if defined(CONFIG_MSM_BUS_SCALING) && !defined(CONFIG_OF)
21 # include <mach/kgsl.h>
26 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
28 static const struct adreno_info gpulist[] = {
30 .rev = ADRENO_REV(3, 0, 5, ANY_ID),
33 .pm4fw = "a300_pm4.fw",
34 .pfpfw = "a300_pfp.fw",
36 .init = a3xx_gpu_init,
38 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
41 .pm4fw = "a300_pm4.fw",
42 .pfpfw = "a300_pfp.fw",
44 .init = a3xx_gpu_init,
46 .rev = ADRENO_REV(3, 3, 0, ANY_ID),
49 .pm4fw = "a330_pm4.fw",
50 .pfpfw = "a330_pfp.fw",
52 .init = a3xx_gpu_init,
56 MODULE_FIRMWARE("a300_pm4.fw");
57 MODULE_FIRMWARE("a300_pfp.fw");
58 MODULE_FIRMWARE("a330_pm4.fw");
59 MODULE_FIRMWARE("a330_pfp.fw");
61 static inline bool _rev_match(uint8_t entry, uint8_t id)
63 return (entry == ANY_ID) || (entry == id);
66 const struct adreno_info *adreno_info(struct adreno_rev rev)
71 for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
72 const struct adreno_info *info = &gpulist[i];
73 if (_rev_match(info->rev.core, rev.core) &&
74 _rev_match(info->rev.major, rev.major) &&
75 _rev_match(info->rev.minor, rev.minor) &&
76 _rev_match(info->rev.patchid, rev.patchid))
83 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
85 struct msm_drm_private *priv = dev->dev_private;
86 struct platform_device *pdev = priv->gpu_pdev;
87 struct adreno_platform_config *config;
88 struct adreno_rev rev;
89 const struct adreno_info *info;
90 struct msm_gpu *gpu = NULL;
93 dev_err(dev->dev, "no adreno device\n");
97 config = pdev->dev.platform_data;
99 info = adreno_info(config->rev);
102 dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
103 rev.core, rev.major, rev.minor, rev.patchid);
107 DBG("Found GPU: %u.%u.%u.%u", rev.core, rev.major,
108 rev.minor, rev.patchid);
110 gpu = info->init(dev);
112 dev_warn(dev->dev, "failed to load adreno gpu\n");
119 mutex_lock(&dev->struct_mutex);
120 gpu->funcs->pm_resume(gpu);
121 mutex_unlock(&dev->struct_mutex);
122 ret = gpu->funcs->hw_init(gpu);
124 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
125 gpu->funcs->destroy(gpu);
128 /* give inactive pm a chance to kick in: */
136 static void set_gpu_pdev(struct drm_device *dev,
137 struct platform_device *pdev)
139 struct msm_drm_private *priv = dev->dev_private;
140 priv->gpu_pdev = pdev;
143 static int adreno_bind(struct device *dev, struct device *master, void *data)
145 static struct adreno_platform_config config = {};
147 struct device_node *child, *node = dev->of_node;
151 ret = of_property_read_u32(node, "qcom,chipid", &val);
153 dev_err(dev, "could not find chipid: %d\n", ret);
157 config.rev = ADRENO_REV((val >> 24) & 0xff,
158 (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
160 /* find clock rates: */
161 config.fast_rate = 0;
162 config.slow_rate = ~0;
163 for_each_child_of_node(node, child) {
164 if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
165 struct device_node *pwrlvl;
166 for_each_child_of_node(child, pwrlvl) {
167 ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
169 dev_err(dev, "could not find gpu-freq: %d\n", ret);
172 config.fast_rate = max(config.fast_rate, val);
173 config.slow_rate = min(config.slow_rate, val);
178 if (!config.fast_rate) {
179 dev_err(dev, "could not find clk rates\n");
184 struct kgsl_device_platform_data *pdata = dev->platform_data;
185 uint32_t version = socinfo_get_version();
186 if (cpu_is_apq8064ab()) {
187 config.fast_rate = 450000000;
188 config.slow_rate = 27000000;
190 config.rev = ADRENO_REV(3, 2, 1, 0);
191 } else if (cpu_is_apq8064()) {
192 config.fast_rate = 400000000;
193 config.slow_rate = 27000000;
196 if (SOCINFO_VERSION_MAJOR(version) == 2)
197 config.rev = ADRENO_REV(3, 2, 0, 2);
198 else if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
199 (SOCINFO_VERSION_MINOR(version) == 1))
200 config.rev = ADRENO_REV(3, 2, 0, 1);
202 config.rev = ADRENO_REV(3, 2, 0, 0);
204 } else if (cpu_is_msm8960ab()) {
205 config.fast_rate = 400000000;
206 config.slow_rate = 320000000;
209 if (SOCINFO_VERSION_MINOR(version) == 0)
210 config.rev = ADRENO_REV(3, 2, 1, 0);
212 config.rev = ADRENO_REV(3, 2, 1, 1);
214 } else if (cpu_is_msm8930()) {
215 config.fast_rate = 400000000;
216 config.slow_rate = 27000000;
219 if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
220 (SOCINFO_VERSION_MINOR(version) == 2))
221 config.rev = ADRENO_REV(3, 0, 5, 2);
223 config.rev = ADRENO_REV(3, 0, 5, 0);
226 # ifdef CONFIG_MSM_BUS_SCALING
227 config.bus_scale_table = pdata->bus_scale_table;
230 dev->platform_data = &config;
231 set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
235 static void adreno_unbind(struct device *dev, struct device *master,
238 set_gpu_pdev(dev_get_drvdata(master), NULL);
241 static const struct component_ops a3xx_ops = {
243 .unbind = adreno_unbind,
246 static int adreno_probe(struct platform_device *pdev)
248 return component_add(&pdev->dev, &a3xx_ops);
251 static int adreno_remove(struct platform_device *pdev)
253 component_del(&pdev->dev, &a3xx_ops);
257 static const struct of_device_id dt_match[] = {
258 { .compatible = "qcom,adreno-3xx" },
259 /* for backwards compat w/ downstream kgsl DT files: */
260 { .compatible = "qcom,kgsl-3d0" },
264 static struct platform_driver adreno_driver = {
265 .probe = adreno_probe,
266 .remove = adreno_remove,
269 .of_match_table = dt_match,
273 void __init adreno_register(void)
275 platform_driver_register(&adreno_driver);
278 void __exit adreno_unregister(void)
280 platform_driver_unregister(&adreno_driver);