drivers/gpu/drm/msm/adreno/adreno_device.c

   1 /*
   2  * Copyright (C) 2013-2014 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "adreno_gpu.h"
  19
  20 #if defined(CONFIG_MSM_BUS_SCALING) && !defined(CONFIG_OF)
  21 #  include <mach/kgsl.h>
  22 #endif
  23
  24 #define ANY_ID 0xff
  25
  26 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
  27
  28 static const struct adreno_info gpulist[] = {
  29         {
  30                 .rev   = ADRENO_REV(3, 0, 5, ANY_ID),
  31                 .revn  = 305,
  32                 .name  = "A305",
  33                 .pm4fw = "a300_pm4.fw",
  34                 .pfpfw = "a300_pfp.fw",
  35                 .gmem  = SZ_256K,
  36                 .init  = a3xx_gpu_init,
  37         }, {
  38                 .rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
  39                 .revn  = 320,
  40                 .name  = "A320",
  41                 .pm4fw = "a300_pm4.fw",
  42                 .pfpfw = "a300_pfp.fw",
  43                 .gmem  = SZ_512K,
  44                 .init  = a3xx_gpu_init,
  45         }, {
  46                 .rev   = ADRENO_REV(3, 3, 0, ANY_ID),
  47                 .revn  = 330,
  48                 .name  = "A330",
  49                 .pm4fw = "a330_pm4.fw",
  50                 .pfpfw = "a330_pfp.fw",
  51                 .gmem  = SZ_1M,
  52                 .init  = a3xx_gpu_init,
  53         },
  54 };
  55
  56 MODULE_FIRMWARE("a300_pm4.fw");
  57 MODULE_FIRMWARE("a300_pfp.fw");
  58 MODULE_FIRMWARE("a330_pm4.fw");
  59 MODULE_FIRMWARE("a330_pfp.fw");
  60
  61 static inline bool _rev_match(uint8_t entry, uint8_t id)
  62 {
  63         return (entry == ANY_ID) || (entry == id);
  64 }
  65
  66 const struct adreno_info *adreno_info(struct adreno_rev rev)
  67 {
  68         int i;
  69
  70         /* identify gpu: */
  71         for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
  72                 const struct adreno_info *info = &gpulist[i];
  73                 if (_rev_match(info->rev.core, rev.core) &&
  74                                 _rev_match(info->rev.major, rev.major) &&
  75                                 _rev_match(info->rev.minor, rev.minor) &&
  76                                 _rev_match(info->rev.patchid, rev.patchid))
  77                         return info;
  78         }
  79
  80         return NULL;
  81 }
  82
  83 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
  84 {
  85         struct msm_drm_private *priv = dev->dev_private;
  86         struct platform_device *pdev = priv->gpu_pdev;
  87         struct adreno_platform_config *config;
  88         struct adreno_rev rev;
  89         const struct adreno_info *info;
  90         struct msm_gpu *gpu = NULL;
  91
  92         if (!pdev) {
  93                 dev_err(dev->dev, "no adreno device\n");
  94                 return NULL;
  95         }
  96
  97         config = pdev->dev.platform_data;
  98         rev = config->rev;
  99         info = adreno_info(config->rev);
 100
 101         if (!info) {
 102                 dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
 103                                 rev.core, rev.major, rev.minor, rev.patchid);
 104                 return NULL;
 105         }
 106
 107         DBG("Found GPU: %u.%u.%u.%u",  rev.core, rev.major,
 108                         rev.minor, rev.patchid);
 109
 110         gpu = info->init(dev);
 111         if (IS_ERR(gpu)) {
 112                 dev_warn(dev->dev, "failed to load adreno gpu\n");
 113                 gpu = NULL;
 114                 /* not fatal */
 115         }
 116
 117         if (gpu) {
 118                 int ret;
 119                 mutex_lock(&dev->struct_mutex);
 120                 gpu->funcs->pm_resume(gpu);
 121                 mutex_unlock(&dev->struct_mutex);
 122                 ret = gpu->funcs->hw_init(gpu);
 123                 if (ret) {
 124                         dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
 125                         gpu->funcs->destroy(gpu);
 126                         gpu = NULL;
 127                 } else {
 128                         /* give inactive pm a chance to kick in: */
 129                         msm_gpu_retire(gpu);
 130                 }
 131         }
 132
 133         return gpu;
 134 }
 135
 136 static void set_gpu_pdev(struct drm_device *dev,
 137                 struct platform_device *pdev)
 138 {
 139         struct msm_drm_private *priv = dev->dev_private;
 140         priv->gpu_pdev = pdev;
 141 }
 142
 143 static int adreno_bind(struct device *dev, struct device *master, void *data)
 144 {
 145         static struct adreno_platform_config config = {};
 146 #ifdef CONFIG_OF
 147         struct device_node *child, *node = dev->of_node;
 148         u32 val;
 149         int ret;
 150
 151         ret = of_property_read_u32(node, "qcom,chipid", &val);
 152         if (ret) {
 153                 dev_err(dev, "could not find chipid: %d\n", ret);
 154                 return ret;
 155         }
 156
 157         config.rev = ADRENO_REV((val >> 24) & 0xff,
 158                         (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
 159
 160         /* find clock rates: */
 161         config.fast_rate = 0;
 162         config.slow_rate = ~0;
 163         for_each_child_of_node(node, child) {
 164                 if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
 165                         struct device_node *pwrlvl;
 166                         for_each_child_of_node(child, pwrlvl) {
 167                                 ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
 168                                 if (ret) {
 169                                         dev_err(dev, "could not find gpu-freq: %d\n", ret);
 170                                         return ret;
 171                                 }
 172                                 config.fast_rate = max(config.fast_rate, val);
 173                                 config.slow_rate = min(config.slow_rate, val);
 174                         }
 175                 }
 176         }
 177
 178         if (!config.fast_rate) {
 179                 dev_err(dev, "could not find clk rates\n");
 180                 return -ENXIO;
 181         }
 182
 183 #else
 184         struct kgsl_device_platform_data *pdata = dev->platform_data;
 185         uint32_t version = socinfo_get_version();
 186         if (cpu_is_apq8064ab()) {
 187                 config.fast_rate = 450000000;
 188                 config.slow_rate = 27000000;
 189                 config.bus_freq  = 4;
 190                 config.rev = ADRENO_REV(3, 2, 1, 0);
 191         } else if (cpu_is_apq8064()) {
 192                 config.fast_rate = 400000000;
 193                 config.slow_rate = 27000000;
 194                 config.bus_freq  = 4;
 195
 196                 if (SOCINFO_VERSION_MAJOR(version) == 2)
 197                         config.rev = ADRENO_REV(3, 2, 0, 2);
 198                 else if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
 199                                 (SOCINFO_VERSION_MINOR(version) == 1))
 200                         config.rev = ADRENO_REV(3, 2, 0, 1);
 201                 else
 202                         config.rev = ADRENO_REV(3, 2, 0, 0);
 203
 204         } else if (cpu_is_msm8960ab()) {
 205                 config.fast_rate = 400000000;
 206                 config.slow_rate = 320000000;
 207                 config.bus_freq  = 4;
 208
 209                 if (SOCINFO_VERSION_MINOR(version) == 0)
 210                         config.rev = ADRENO_REV(3, 2, 1, 0);
 211                 else
 212                         config.rev = ADRENO_REV(3, 2, 1, 1);
 213
 214         } else if (cpu_is_msm8930()) {
 215                 config.fast_rate = 400000000;
 216                 config.slow_rate = 27000000;
 217                 config.bus_freq  = 3;
 218
 219                 if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
 220                         (SOCINFO_VERSION_MINOR(version) == 2))
 221                         config.rev = ADRENO_REV(3, 0, 5, 2);
 222                 else
 223                         config.rev = ADRENO_REV(3, 0, 5, 0);
 224
 225         }
 226 #  ifdef CONFIG_MSM_BUS_SCALING
 227         config.bus_scale_table = pdata->bus_scale_table;
 228 #  endif
 229 #endif
 230         dev->platform_data = &config;
 231         set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
 232         return 0;
 233 }
 234
 235 static void adreno_unbind(struct device *dev, struct device *master,
 236                 void *data)
 237 {
 238         set_gpu_pdev(dev_get_drvdata(master), NULL);
 239 }
 240
 241 static const struct component_ops a3xx_ops = {
 242                 .bind   = adreno_bind,
 243                 .unbind = adreno_unbind,
 244 };
 245
 246 static int adreno_probe(struct platform_device *pdev)
 247 {
 248         return component_add(&pdev->dev, &a3xx_ops);
 249 }
 250
 251 static int adreno_remove(struct platform_device *pdev)
 252 {
 253         component_del(&pdev->dev, &a3xx_ops);
 254         return 0;
 255 }
 256
 257 static const struct of_device_id dt_match[] = {
 258         { .compatible = "qcom,adreno-3xx" },
 259         /* for backwards compat w/ downstream kgsl DT files: */
 260         { .compatible = "qcom,kgsl-3d0" },
 261         {}
 262 };
 263
 264 static struct platform_driver adreno_driver = {
 265         .probe = adreno_probe,
 266         .remove = adreno_remove,
 267         .driver = {
 268                 .name = "adreno",
 269                 .of_match_table = dt_match,
 270         },
 271 };
 272
 273 void __init adreno_register(void)
 274 {
 275         platform_driver_register(&adreno_driver);
 276 }
 277
 278 void __exit adreno_unregister(void)
 279 {
 280         platform_driver_unregister(&adreno_driver);
 281 }