2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __MDP4_KMS_H__
19 #define __MDP4_KMS_H__
23 #include "mdp/mdp_kms.h"
29 struct drm_device *dev;
33 /* mapper-id used to request GEM buffer mapped for scanout: */
38 struct regulator *dsi_pll_vdda;
39 struct regulator *dsi_pll_vddio;
40 struct regulator *vdd;
47 struct mdp_irq error_handler;
49 /* empty/blank cursor bo to use when cursor is "disabled" */
50 struct drm_gem_object *blank_cursor_bo;
51 uint32_t blank_cursor_iova;
53 #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
55 /* platform config data (ie. from DT, or pdata) */
56 struct mdp4_platform_config {
57 struct iommu_domain *iommu;
61 static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
63 msm_writel(data, mdp4_kms->mmio + reg);
66 static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
68 return msm_readl(mdp4_kms->mmio + reg);
71 static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
74 case VG1: return MDP4_OVERLAY_FLUSH_VG1;
75 case VG2: return MDP4_OVERLAY_FLUSH_VG2;
76 case RGB1: return MDP4_OVERLAY_FLUSH_RGB1;
77 case RGB2: return MDP4_OVERLAY_FLUSH_RGB2;
82 static inline uint32_t ovlp2flush(int ovlp)
85 case 0: return MDP4_OVERLAY_FLUSH_OVLP0;
86 case 1: return MDP4_OVERLAY_FLUSH_OVLP1;
91 static inline uint32_t dma2irq(enum mdp4_dma dma)
94 case DMA_P: return MDP4_IRQ_DMA_P_DONE;
95 case DMA_S: return MDP4_IRQ_DMA_S_DONE;
96 case DMA_E: return MDP4_IRQ_DMA_E_DONE;
101 static inline uint32_t dma2err(enum mdp4_dma dma)
104 case DMA_P: return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
105 case DMA_S: return 0; // ???
106 case DMA_E: return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
111 static inline uint32_t mixercfg(int mixer, enum mdp4_pipe pipe,
112 enum mdp_mixer_stage_id stage)
114 uint32_t mixer_cfg = 0;
118 mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) |
119 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
122 mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) |
123 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
126 mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) |
127 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
130 mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) |
131 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
134 mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) |
135 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
138 mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) |
139 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
142 mixer_cfg = MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) |
143 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
146 WARN_ON("invalid pipe");
153 int mdp4_disable(struct mdp4_kms *mdp4_kms);
154 int mdp4_enable(struct mdp4_kms *mdp4_kms);
156 void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask);
157 void mdp4_irq_preinstall(struct msm_kms *kms);
158 int mdp4_irq_postinstall(struct msm_kms *kms);
159 void mdp4_irq_uninstall(struct msm_kms *kms);
160 irqreturn_t mdp4_irq(struct msm_kms *kms);
161 int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
162 void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
165 uint32_t mdp4_get_formats(enum mdp4_pipe pipe_id, uint32_t *pixel_formats,
166 uint32_t max_formats)
168 /* TODO when we have YUV, we need to filter supported formats
171 return mdp_get_formats(pixel_formats, max_formats);
174 void mdp4_plane_install_properties(struct drm_plane *plane,
175 struct drm_mode_object *obj);
176 void mdp4_plane_set_scanout(struct drm_plane *plane,
177 struct drm_framebuffer *fb);
178 int mdp4_plane_mode_set(struct drm_plane *plane,
179 struct drm_crtc *crtc, struct drm_framebuffer *fb,
180 int crtc_x, int crtc_y,
181 unsigned int crtc_w, unsigned int crtc_h,
182 uint32_t src_x, uint32_t src_y,
183 uint32_t src_w, uint32_t src_h);
184 enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
185 struct drm_plane *mdp4_plane_init(struct drm_device *dev,
186 enum mdp4_pipe pipe_id, bool private_plane);
188 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
189 void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
190 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
191 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf);
192 void mdp4_crtc_attach(struct drm_crtc *crtc, struct drm_plane *plane);
193 void mdp4_crtc_detach(struct drm_crtc *crtc, struct drm_plane *plane);
194 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
195 struct drm_plane *plane, int id, int ovlp_id,
196 enum mdp4_dma dma_id);
198 long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
199 struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev);
201 #ifdef CONFIG_MSM_BUS_SCALING
202 static inline int match_dev_name(struct device *dev, void *data)
204 return !strcmp(dev_name(dev), data);
206 /* bus scaling data is associated with extra pointless platform devices,
207 * "dtv", etc.. this is a bit of a hack, but we need a way for encoders
208 * to find their pdata to make the bus-scaling stuff work.
210 static inline void *mdp4_find_pdata(const char *devname)
213 dev = bus_find_device(&platform_bus_type, NULL,
214 (void *)devname, match_dev_name);
215 return dev ? dev->platform_data : NULL;
219 #endif /* __MDP4_KMS_H__ */