2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <core/object.h>
26 #include <core/parent.h>
27 #include <core/handle.h>
28 #include <core/class.h>
30 #include <engine/software.h>
31 #include <engine/disp.h>
33 #include <subdev/bios.h>
34 #include <subdev/bios/dcb.h>
35 #include <subdev/bios/disp.h>
36 #include <subdev/bios/init.h>
37 #include <subdev/bios/pll.h>
38 #include <subdev/timer.h>
39 #include <subdev/fb.h>
40 #include <subdev/bar.h>
41 #include <subdev/clock.h>
45 /*******************************************************************************
46 * EVO channel base class
47 ******************************************************************************/
50 nv50_disp_chan_create_(struct nouveau_object *parent,
51 struct nouveau_object *engine,
52 struct nouveau_oclass *oclass, int chid,
53 int length, void **pobject)
55 struct nv50_disp_base *base = (void *)parent;
56 struct nv50_disp_chan *chan;
59 if (base->chan & (1 << chid))
61 base->chan |= (1 << chid);
63 ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL,
64 (1ULL << NVDEV_ENGINE_DMAOBJ),
75 nv50_disp_chan_destroy(struct nv50_disp_chan *chan)
77 struct nv50_disp_base *base = (void *)nv_object(chan)->parent;
78 base->chan &= ~(1 << chan->chid);
79 nouveau_namedb_destroy(&chan->base);
83 nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr)
85 struct nv50_disp_priv *priv = (void *)object->engine;
86 struct nv50_disp_chan *chan = (void *)object;
87 return nv_rd32(priv, 0x640000 + (chan->chid * 0x1000) + addr);
91 nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data)
93 struct nv50_disp_priv *priv = (void *)object->engine;
94 struct nv50_disp_chan *chan = (void *)object;
95 nv_wr32(priv, 0x640000 + (chan->chid * 0x1000) + addr, data);
98 /*******************************************************************************
99 * EVO DMA channel base class
100 ******************************************************************************/
103 nv50_disp_dmac_object_attach(struct nouveau_object *parent,
104 struct nouveau_object *object, u32 name)
106 struct nv50_disp_base *base = (void *)parent->parent;
107 struct nv50_disp_chan *chan = (void *)parent;
108 u32 addr = nv_gpuobj(object)->node->offset;
109 u32 chid = chan->chid;
110 u32 data = (chid << 28) | (addr << 10) | chid;
111 return nouveau_ramht_insert(base->ramht, chid, name, data);
115 nv50_disp_dmac_object_detach(struct nouveau_object *parent, int cookie)
117 struct nv50_disp_base *base = (void *)parent->parent;
118 nouveau_ramht_remove(base->ramht, cookie);
122 nv50_disp_dmac_create_(struct nouveau_object *parent,
123 struct nouveau_object *engine,
124 struct nouveau_oclass *oclass, u32 pushbuf, int chid,
125 int length, void **pobject)
127 struct nv50_disp_dmac *dmac;
130 ret = nv50_disp_chan_create_(parent, engine, oclass, chid,
136 dmac->pushdma = (void *)nouveau_handle_ref(parent, pushbuf);
140 switch (nv_mclass(dmac->pushdma)) {
143 if (dmac->pushdma->limit - dmac->pushdma->start != 0xfff)
146 switch (dmac->pushdma->target) {
147 case NV_MEM_TARGET_VRAM:
148 dmac->push = 0x00000000 | dmac->pushdma->start >> 8;
150 case NV_MEM_TARGET_PCI_NOSNOOP:
151 dmac->push = 0x00000003 | dmac->pushdma->start >> 8;
165 nv50_disp_dmac_dtor(struct nouveau_object *object)
167 struct nv50_disp_dmac *dmac = (void *)object;
168 nouveau_object_ref(NULL, (struct nouveau_object **)&dmac->pushdma);
169 nv50_disp_chan_destroy(&dmac->base);
173 nv50_disp_dmac_init(struct nouveau_object *object)
175 struct nv50_disp_priv *priv = (void *)object->engine;
176 struct nv50_disp_dmac *dmac = (void *)object;
177 int chid = dmac->base.chid;
180 ret = nv50_disp_chan_init(&dmac->base);
184 /* enable error reporting */
185 nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00010001 << chid);
187 /* initialise channel for dma command submission */
188 nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push);
189 nv_wr32(priv, 0x610208 + (chid * 0x0010), 0x00010000);
190 nv_wr32(priv, 0x61020c + (chid * 0x0010), chid);
191 nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010);
192 nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000);
193 nv_wr32(priv, 0x610200 + (chid * 0x0010), 0x00000013);
195 /* wait for it to go inactive */
196 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) {
197 nv_error(dmac, "init timeout, 0x%08x\n",
198 nv_rd32(priv, 0x610200 + (chid * 0x10)));
206 nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend)
208 struct nv50_disp_priv *priv = (void *)object->engine;
209 struct nv50_disp_dmac *dmac = (void *)object;
210 int chid = dmac->base.chid;
212 /* deactivate channel */
213 nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000);
214 nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000);
215 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x001e0000, 0x00000000)) {
216 nv_error(dmac, "fini timeout, 0x%08x\n",
217 nv_rd32(priv, 0x610200 + (chid * 0x10)));
222 /* disable error reporting */
223 nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid);
225 return nv50_disp_chan_fini(&dmac->base, suspend);
228 /*******************************************************************************
229 * EVO master channel object
230 ******************************************************************************/
233 nv50_disp_mast_ctor(struct nouveau_object *parent,
234 struct nouveau_object *engine,
235 struct nouveau_oclass *oclass, void *data, u32 size,
236 struct nouveau_object **pobject)
238 struct nv50_display_mast_class *args = data;
239 struct nv50_disp_dmac *mast;
242 if (size < sizeof(*args))
245 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
246 0, sizeof(*mast), (void **)&mast);
247 *pobject = nv_object(mast);
251 nv_parent(mast)->object_attach = nv50_disp_dmac_object_attach;
252 nv_parent(mast)->object_detach = nv50_disp_dmac_object_detach;
257 nv50_disp_mast_init(struct nouveau_object *object)
259 struct nv50_disp_priv *priv = (void *)object->engine;
260 struct nv50_disp_dmac *mast = (void *)object;
263 ret = nv50_disp_chan_init(&mast->base);
267 /* enable error reporting */
268 nv_mask(priv, 0x610028, 0x00010001, 0x00010001);
270 /* attempt to unstick channel from some unknown state */
271 if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000)
272 nv_mask(priv, 0x610200, 0x00800000, 0x00800000);
273 if ((nv_rd32(priv, 0x610200) & 0x003f0000) == 0x00030000)
274 nv_mask(priv, 0x610200, 0x00600000, 0x00600000);
276 /* initialise channel for dma command submission */
277 nv_wr32(priv, 0x610204, mast->push);
278 nv_wr32(priv, 0x610208, 0x00010000);
279 nv_wr32(priv, 0x61020c, 0x00000000);
280 nv_mask(priv, 0x610200, 0x00000010, 0x00000010);
281 nv_wr32(priv, 0x640000, 0x00000000);
282 nv_wr32(priv, 0x610200, 0x01000013);
284 /* wait for it to go inactive */
285 if (!nv_wait(priv, 0x610200, 0x80000000, 0x00000000)) {
286 nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610200));
294 nv50_disp_mast_fini(struct nouveau_object *object, bool suspend)
296 struct nv50_disp_priv *priv = (void *)object->engine;
297 struct nv50_disp_dmac *mast = (void *)object;
299 /* deactivate channel */
300 nv_mask(priv, 0x610200, 0x00000010, 0x00000000);
301 nv_mask(priv, 0x610200, 0x00000003, 0x00000000);
302 if (!nv_wait(priv, 0x610200, 0x001e0000, 0x00000000)) {
303 nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610200));
308 /* disable error reporting */
309 nv_mask(priv, 0x610028, 0x00010001, 0x00000000);
311 return nv50_disp_chan_fini(&mast->base, suspend);
314 struct nouveau_ofuncs
315 nv50_disp_mast_ofuncs = {
316 .ctor = nv50_disp_mast_ctor,
317 .dtor = nv50_disp_dmac_dtor,
318 .init = nv50_disp_mast_init,
319 .fini = nv50_disp_mast_fini,
320 .rd32 = nv50_disp_chan_rd32,
321 .wr32 = nv50_disp_chan_wr32,
324 /*******************************************************************************
325 * EVO sync channel objects
326 ******************************************************************************/
329 nv50_disp_sync_ctor(struct nouveau_object *parent,
330 struct nouveau_object *engine,
331 struct nouveau_oclass *oclass, void *data, u32 size,
332 struct nouveau_object **pobject)
334 struct nv50_display_sync_class *args = data;
335 struct nv50_disp_dmac *dmac;
338 if (size < sizeof(*data) || args->head > 1)
341 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
342 1 + args->head, sizeof(*dmac),
344 *pobject = nv_object(dmac);
348 nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach;
349 nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach;
353 struct nouveau_ofuncs
354 nv50_disp_sync_ofuncs = {
355 .ctor = nv50_disp_sync_ctor,
356 .dtor = nv50_disp_dmac_dtor,
357 .init = nv50_disp_dmac_init,
358 .fini = nv50_disp_dmac_fini,
359 .rd32 = nv50_disp_chan_rd32,
360 .wr32 = nv50_disp_chan_wr32,
363 /*******************************************************************************
364 * EVO overlay channel objects
365 ******************************************************************************/
368 nv50_disp_ovly_ctor(struct nouveau_object *parent,
369 struct nouveau_object *engine,
370 struct nouveau_oclass *oclass, void *data, u32 size,
371 struct nouveau_object **pobject)
373 struct nv50_display_ovly_class *args = data;
374 struct nv50_disp_dmac *dmac;
377 if (size < sizeof(*data) || args->head > 1)
380 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
381 3 + args->head, sizeof(*dmac),
383 *pobject = nv_object(dmac);
387 nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach;
388 nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach;
392 struct nouveau_ofuncs
393 nv50_disp_ovly_ofuncs = {
394 .ctor = nv50_disp_ovly_ctor,
395 .dtor = nv50_disp_dmac_dtor,
396 .init = nv50_disp_dmac_init,
397 .fini = nv50_disp_dmac_fini,
398 .rd32 = nv50_disp_chan_rd32,
399 .wr32 = nv50_disp_chan_wr32,
402 /*******************************************************************************
403 * EVO PIO channel base class
404 ******************************************************************************/
407 nv50_disp_pioc_create_(struct nouveau_object *parent,
408 struct nouveau_object *engine,
409 struct nouveau_oclass *oclass, int chid,
410 int length, void **pobject)
412 return nv50_disp_chan_create_(parent, engine, oclass, chid,
417 nv50_disp_pioc_dtor(struct nouveau_object *object)
419 struct nv50_disp_pioc *pioc = (void *)object;
420 nv50_disp_chan_destroy(&pioc->base);
424 nv50_disp_pioc_init(struct nouveau_object *object)
426 struct nv50_disp_priv *priv = (void *)object->engine;
427 struct nv50_disp_pioc *pioc = (void *)object;
428 int chid = pioc->base.chid;
431 ret = nv50_disp_chan_init(&pioc->base);
435 nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00002000);
436 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) {
437 nv_error(pioc, "timeout0: 0x%08x\n",
438 nv_rd32(priv, 0x610200 + (chid * 0x10)));
442 nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00000001);
443 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) {
444 nv_error(pioc, "timeout1: 0x%08x\n",
445 nv_rd32(priv, 0x610200 + (chid * 0x10)));
453 nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend)
455 struct nv50_disp_priv *priv = (void *)object->engine;
456 struct nv50_disp_pioc *pioc = (void *)object;
457 int chid = pioc->base.chid;
459 nv_mask(priv, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000);
460 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00000000)) {
461 nv_error(pioc, "timeout: 0x%08x\n",
462 nv_rd32(priv, 0x610200 + (chid * 0x10)));
467 return nv50_disp_chan_fini(&pioc->base, suspend);
470 /*******************************************************************************
471 * EVO immediate overlay channel objects
472 ******************************************************************************/
475 nv50_disp_oimm_ctor(struct nouveau_object *parent,
476 struct nouveau_object *engine,
477 struct nouveau_oclass *oclass, void *data, u32 size,
478 struct nouveau_object **pobject)
480 struct nv50_display_oimm_class *args = data;
481 struct nv50_disp_pioc *pioc;
484 if (size < sizeof(*args) || args->head > 1)
487 ret = nv50_disp_pioc_create_(parent, engine, oclass, 5 + args->head,
488 sizeof(*pioc), (void **)&pioc);
489 *pobject = nv_object(pioc);
496 struct nouveau_ofuncs
497 nv50_disp_oimm_ofuncs = {
498 .ctor = nv50_disp_oimm_ctor,
499 .dtor = nv50_disp_pioc_dtor,
500 .init = nv50_disp_pioc_init,
501 .fini = nv50_disp_pioc_fini,
502 .rd32 = nv50_disp_chan_rd32,
503 .wr32 = nv50_disp_chan_wr32,
506 /*******************************************************************************
507 * EVO cursor channel objects
508 ******************************************************************************/
511 nv50_disp_curs_ctor(struct nouveau_object *parent,
512 struct nouveau_object *engine,
513 struct nouveau_oclass *oclass, void *data, u32 size,
514 struct nouveau_object **pobject)
516 struct nv50_display_curs_class *args = data;
517 struct nv50_disp_pioc *pioc;
520 if (size < sizeof(*args) || args->head > 1)
523 ret = nv50_disp_pioc_create_(parent, engine, oclass, 7 + args->head,
524 sizeof(*pioc), (void **)&pioc);
525 *pobject = nv_object(pioc);
532 struct nouveau_ofuncs
533 nv50_disp_curs_ofuncs = {
534 .ctor = nv50_disp_curs_ctor,
535 .dtor = nv50_disp_pioc_dtor,
536 .init = nv50_disp_pioc_init,
537 .fini = nv50_disp_pioc_fini,
538 .rd32 = nv50_disp_chan_rd32,
539 .wr32 = nv50_disp_chan_wr32,
542 /*******************************************************************************
543 * Base display object
544 ******************************************************************************/
547 nv50_disp_base_ctor(struct nouveau_object *parent,
548 struct nouveau_object *engine,
549 struct nouveau_oclass *oclass, void *data, u32 size,
550 struct nouveau_object **pobject)
552 struct nv50_disp_priv *priv = (void *)engine;
553 struct nv50_disp_base *base;
556 ret = nouveau_parent_create(parent, engine, oclass, 0,
557 priv->sclass, 0, &base);
558 *pobject = nv_object(base);
562 return nouveau_ramht_new(parent, parent, 0x1000, 0, &base->ramht);
566 nv50_disp_base_dtor(struct nouveau_object *object)
568 struct nv50_disp_base *base = (void *)object;
569 nouveau_ramht_ref(NULL, &base->ramht);
570 nouveau_parent_destroy(&base->base);
574 nv50_disp_base_init(struct nouveau_object *object)
576 struct nv50_disp_priv *priv = (void *)object->engine;
577 struct nv50_disp_base *base = (void *)object;
581 ret = nouveau_parent_init(&base->base);
585 /* The below segments of code copying values from one register to
586 * another appear to inform EVO of the display capabilities or
587 * something similar. NFI what the 0x614004 caps are for..
589 tmp = nv_rd32(priv, 0x614004);
590 nv_wr32(priv, 0x610184, tmp);
593 for (i = 0; i < priv->head.nr; i++) {
594 tmp = nv_rd32(priv, 0x616100 + (i * 0x800));
595 nv_wr32(priv, 0x610190 + (i * 0x10), tmp);
596 tmp = nv_rd32(priv, 0x616104 + (i * 0x800));
597 nv_wr32(priv, 0x610194 + (i * 0x10), tmp);
598 tmp = nv_rd32(priv, 0x616108 + (i * 0x800));
599 nv_wr32(priv, 0x610198 + (i * 0x10), tmp);
600 tmp = nv_rd32(priv, 0x61610c + (i * 0x800));
601 nv_wr32(priv, 0x61019c + (i * 0x10), tmp);
605 for (i = 0; i < priv->dac.nr; i++) {
606 tmp = nv_rd32(priv, 0x61a000 + (i * 0x800));
607 nv_wr32(priv, 0x6101d0 + (i * 0x04), tmp);
611 for (i = 0; i < priv->sor.nr; i++) {
612 tmp = nv_rd32(priv, 0x61c000 + (i * 0x800));
613 nv_wr32(priv, 0x6101e0 + (i * 0x04), tmp);
617 for (i = 0; i < 3; i++) {
618 tmp = nv_rd32(priv, 0x61e000 + (i * 0x800));
619 nv_wr32(priv, 0x6101f0 + (i * 0x04), tmp);
622 /* steal display away from vbios, or something like that */
623 if (nv_rd32(priv, 0x610024) & 0x00000100) {
624 nv_wr32(priv, 0x610024, 0x00000100);
625 nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000);
626 if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) {
627 nv_error(priv, "timeout acquiring display\n");
632 /* point at display engine memory area (hash table, objects) */
633 nv_wr32(priv, 0x610010, (nv_gpuobj(base->ramht)->addr >> 8) | 9);
635 /* enable supervisor interrupts, disable everything else */
636 nv_wr32(priv, 0x61002c, 0x00000370);
637 nv_wr32(priv, 0x610028, 0x00000000);
642 nv50_disp_base_fini(struct nouveau_object *object, bool suspend)
644 struct nv50_disp_priv *priv = (void *)object->engine;
645 struct nv50_disp_base *base = (void *)object;
647 /* disable all interrupts */
648 nv_wr32(priv, 0x610024, 0x00000000);
649 nv_wr32(priv, 0x610020, 0x00000000);
651 return nouveau_parent_fini(&base->base, suspend);
654 struct nouveau_ofuncs
655 nv50_disp_base_ofuncs = {
656 .ctor = nv50_disp_base_ctor,
657 .dtor = nv50_disp_base_dtor,
658 .init = nv50_disp_base_init,
659 .fini = nv50_disp_base_fini,
662 static struct nouveau_omthds
663 nv50_disp_base_omthds[] = {
664 { SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
665 { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
666 { DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
667 { DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
671 static struct nouveau_oclass
672 nv50_disp_base_oclass[] = {
673 { NV50_DISP_CLASS, &nv50_disp_base_ofuncs, nv50_disp_base_omthds },
677 static struct nouveau_oclass
678 nv50_disp_sclass[] = {
679 { NV50_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
680 { NV50_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
681 { NV50_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
682 { NV50_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
683 { NV50_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
687 /*******************************************************************************
688 * Display context, tracks instmem allocation and prevents more than one
689 * client using the display hardware at any time.
690 ******************************************************************************/
693 nv50_disp_data_ctor(struct nouveau_object *parent,
694 struct nouveau_object *engine,
695 struct nouveau_oclass *oclass, void *data, u32 size,
696 struct nouveau_object **pobject)
698 struct nv50_disp_priv *priv = (void *)engine;
699 struct nouveau_engctx *ectx;
702 /* no context needed for channel objects... */
703 if (nv_mclass(parent) != NV_DEVICE_CLASS) {
704 atomic_inc(&parent->refcount);
709 /* allocate display hardware to client */
710 mutex_lock(&nv_subdev(priv)->mutex);
711 if (list_empty(&nv_engine(priv)->contexts)) {
712 ret = nouveau_engctx_create(parent, engine, oclass, NULL,
714 NVOBJ_FLAG_HEAP, &ectx);
715 *pobject = nv_object(ectx);
717 mutex_unlock(&nv_subdev(priv)->mutex);
721 struct nouveau_oclass
723 .handle = NV_ENGCTX(DISP, 0x50),
724 .ofuncs = &(struct nouveau_ofuncs) {
725 .ctor = nv50_disp_data_ctor,
726 .dtor = _nouveau_engctx_dtor,
727 .init = _nouveau_engctx_init,
728 .fini = _nouveau_engctx_fini,
729 .rd32 = _nouveau_engctx_rd32,
730 .wr32 = _nouveau_engctx_wr32,
734 /*******************************************************************************
735 * Display engine implementation
736 ******************************************************************************/
739 nv50_disp_intr_error(struct nv50_disp_priv *priv)
741 u32 channels = (nv_rd32(priv, 0x610020) & 0x001f0000) >> 16;
745 for (chid = 0; chid < 5; chid++) {
746 if (!(channels & (1 << chid)))
749 nv_wr32(priv, 0x610020, 0x00010000 << chid);
750 addr = nv_rd32(priv, 0x610080 + (chid * 0x08));
751 data = nv_rd32(priv, 0x610084 + (chid * 0x08));
752 nv_wr32(priv, 0x610080 + (chid * 0x08), 0x90000000);
754 nv_error(priv, "chid %d mthd 0x%04x data 0x%08x 0x%08x\n",
755 chid, addr & 0xffc, data, addr);
760 nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
762 struct nouveau_bar *bar = nouveau_bar(priv);
763 struct nouveau_disp *disp = &priv->base;
764 struct nouveau_software_chan *chan, *temp;
767 spin_lock_irqsave(&disp->vblank.lock, flags);
768 list_for_each_entry_safe(chan, temp, &disp->vblank.list, vblank.head) {
769 if (chan->vblank.crtc != crtc)
772 if (nv_device(priv)->chipset >= 0xc0) {
773 nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
775 nv_wr32(priv, 0x06000c,
776 upper_32_bits(chan->vblank.offset));
777 nv_wr32(priv, 0x060010,
778 lower_32_bits(chan->vblank.offset));
779 nv_wr32(priv, 0x060014, chan->vblank.value);
781 nv_wr32(priv, 0x001704, chan->vblank.channel);
782 nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
784 if (nv_device(priv)->chipset == 0x50) {
785 nv_wr32(priv, 0x001570, chan->vblank.offset);
786 nv_wr32(priv, 0x001574, chan->vblank.value);
788 nv_wr32(priv, 0x060010, chan->vblank.offset);
789 nv_wr32(priv, 0x060014, chan->vblank.value);
793 list_del(&chan->vblank.head);
794 if (disp->vblank.put)
795 disp->vblank.put(disp->vblank.data, crtc);
797 spin_unlock_irqrestore(&disp->vblank.lock, flags);
799 if (disp->vblank.notify)
800 disp->vblank.notify(disp->vblank.data, crtc);
804 exec_lookup(struct nv50_disp_priv *priv, int head, int outp, u32 ctrl,
805 struct dcb_output *dcb, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
806 struct nvbios_outp *info)
808 struct nouveau_bios *bios = nouveau_bios(priv);
809 u16 mask, type, data;
812 type = DCB_OUTPUT_ANALOG;
816 switch (ctrl & 0x00000f00) {
817 case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break;
818 case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break;
819 case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break;
820 case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break;
821 case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break;
822 case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
824 nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl);
829 mask = 0x00c0 & (mask << 6);
830 mask |= 0x0001 << outp;
831 mask |= 0x0100 << head;
833 data = dcb_outp_match(bios, type, mask, ver, hdr, dcb);
837 return nvbios_outp_match(bios, type, mask, ver, hdr, cnt, len, info);
841 exec_script(struct nv50_disp_priv *priv, int head, int id)
843 struct nouveau_bios *bios = nouveau_bios(priv);
844 struct nvbios_outp info;
845 struct dcb_output dcb;
846 u8 ver, hdr, cnt, len;
848 u32 ctrl = 0x00000000;
851 for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)
852 ctrl = nv_rd32(priv, 0x610b5c + (i * 8));
854 if (nv_device(priv)->chipset < 0x90 ||
855 nv_device(priv)->chipset == 0x92 ||
856 nv_device(priv)->chipset == 0xa0) {
857 for (i = 0; !(ctrl & (1 << head)) && i < 2; i++)
858 ctrl = nv_rd32(priv, 0x610b74 + (i * 8));
861 for (i = 0; !(ctrl & (1 << head)) && i < 4; i++)
862 ctrl = nv_rd32(priv, 0x610798 + (i * 8));
866 if (!(ctrl & (1 << head)))
869 data = exec_lookup(priv, head, i, ctrl, &dcb, &ver, &hdr, &cnt, &len, &info);
871 struct nvbios_init init = {
872 .subdev = nv_subdev(priv),
874 .offset = info.script[id],
880 return nvbios_exec(&init) == 0;
887 exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk,
888 struct dcb_output *outp)
890 struct nouveau_bios *bios = nouveau_bios(priv);
891 struct nvbios_outp info1;
892 struct nvbios_ocfg info2;
893 u8 ver, hdr, cnt, len;
895 u32 ctrl = 0x00000000;
898 for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)
899 ctrl = nv_rd32(priv, 0x610b58 + (i * 8));
901 if (nv_device(priv)->chipset < 0x90 ||
902 nv_device(priv)->chipset == 0x92 ||
903 nv_device(priv)->chipset == 0xa0) {
904 for (i = 0; !(ctrl & (1 << head)) && i < 2; i++)
905 ctrl = nv_rd32(priv, 0x610b70 + (i * 8));
908 for (i = 0; !(ctrl & (1 << head)) && i < 4; i++)
909 ctrl = nv_rd32(priv, 0x610794 + (i * 8));
913 if (!(ctrl & (1 << head)))
916 data = exec_lookup(priv, head, i, ctrl, outp, &ver, &hdr, &cnt, &len, &info1);
920 switch (outp->type) {
921 case DCB_OUTPUT_TMDS:
922 conf = (ctrl & 0x00000f00) >> 8;
926 case DCB_OUTPUT_LVDS:
927 conf = priv->sor.lvdsconf;
930 conf = (ctrl & 0x00000f00) >> 8;
932 case DCB_OUTPUT_ANALOG:
938 data = nvbios_ocfg_match(bios, data, conf, &ver, &hdr, &cnt, &len, &info2);
940 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
942 struct nvbios_init init = {
943 .subdev = nv_subdev(priv),
951 if (nvbios_exec(&init))
961 nv50_disp_intr_unk10(struct nv50_disp_priv *priv, u32 super)
963 int head = ffs((super & 0x00000060) >> 5) - 1;
965 head = ffs((super & 0x00000180) >> 7) - 1;
967 exec_script(priv, head, 1);
970 nv_wr32(priv, 0x610024, 0x00000010);
971 nv_wr32(priv, 0x610030, 0x80000000);
975 nv50_disp_intr_unk20_dp(struct nv50_disp_priv *priv,
976 struct dcb_output *outp, u32 pclk)
978 const int link = !(outp->sorconf.link & 1);
979 const int or = ffs(outp->or) - 1;
980 const u32 soff = ( or * 0x800);
981 const u32 loff = (link * 0x080) + soff;
982 const u32 ctrl = nv_rd32(priv, 0x610794 + (or * 8));
983 const u32 symbol = 100000;
984 u32 dpctrl = nv_rd32(priv, 0x61c10c + loff) & 0x0000f0000;
985 u32 clksor = nv_rd32(priv, 0x614300 + soff);
986 int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
987 int TU, VTUi, VTUf, VTUa;
988 u64 link_data_rate, link_ratio, unk;
989 u32 best_diff = 64 * symbol;
990 u32 link_nr, link_bw, bits, r;
992 /* calculate packed data rate for each lane */
993 if (dpctrl > 0x00030000) link_nr = 4;
994 else if (dpctrl > 0x00010000) link_nr = 2;
997 if (clksor & 0x000c0000)
1002 if ((ctrl & 0xf0000) == 0x60000) bits = 30;
1003 else if ((ctrl & 0xf0000) == 0x50000) bits = 24;
1006 link_data_rate = (pclk * bits / 8) / link_nr;
1008 /* calculate ratio of packed data rate to link symbol rate */
1009 link_ratio = link_data_rate * symbol;
1010 r = do_div(link_ratio, link_bw);
1012 for (TU = 64; TU >= 32; TU--) {
1013 /* calculate average number of valid symbols in each TU */
1014 u32 tu_valid = link_ratio * TU;
1017 /* find a hw representation for the fraction.. */
1018 VTUi = tu_valid / symbol;
1019 calc = VTUi * symbol;
1020 diff = tu_valid - calc;
1022 if (diff >= (symbol / 2)) {
1023 VTUf = symbol / (symbol - diff);
1024 if (symbol - (VTUf * diff))
1029 calc += symbol - (symbol / VTUf);
1037 VTUf = min((int)(symbol / diff), 15);
1038 calc += symbol / VTUf;
1041 diff = calc - tu_valid;
1043 /* no remainder, but the hw doesn't like the fractional
1044 * part to be zero. decrement the integer part and
1045 * have the fraction add a whole symbol back
1052 if (diff < best_diff) {
1064 nv_error(priv, "unable to find suitable dp config\n");
1068 /* XXX close to vbios numbers, but not right */
1069 unk = (symbol - link_ratio) * bestTU;
1071 r = do_div(unk, symbol);
1072 r = do_div(unk, symbol);
1075 nv_mask(priv, 0x61c10c + loff, 0x000001fc, bestTU << 2);
1076 nv_mask(priv, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 |
1078 bestVTUi << 8 | unk);
1082 nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super)
1084 struct dcb_output outp;
1085 u32 addr, mask, data;
1088 /* finish detaching encoder? */
1089 head = ffs((super & 0x00000180) >> 7) - 1;
1091 exec_script(priv, head, 2);
1093 /* check whether a vpll change is required */
1094 head = ffs((super & 0x00000600) >> 9) - 1;
1096 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
1098 struct nouveau_clock *clk = nouveau_clock(priv);
1099 clk->pll_set(clk, PLL_VPLL0 + head, pclk);
1102 nv_mask(priv, 0x614200 + head * 0x800, 0x0000000f, 0x00000000);
1105 /* (re)attach the relevant OR to the head */
1106 head = ffs((super & 0x00000180) >> 7) - 1;
1108 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
1109 u32 conf = exec_clkcmp(priv, head, 0, pclk, &outp);
1111 if (outp.type == DCB_OUTPUT_ANALOG) {
1112 addr = 0x614280 + (ffs(outp.or) - 1) * 0x800;
1116 if (outp.type == DCB_OUTPUT_DP)
1117 nv50_disp_intr_unk20_dp(priv, &outp, pclk);
1118 addr = 0x614300 + (ffs(outp.or) - 1) * 0x800;
1120 data = (conf & 0x0100) ? 0x0101 : 0x0000;
1123 nv_mask(priv, addr, mask, data);
1127 nv_wr32(priv, 0x610024, 0x00000020);
1128 nv_wr32(priv, 0x610030, 0x80000000);
1131 /* If programming a TMDS output on a SOR that can also be configured for
1132 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
1134 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
1135 * the VBIOS scripts on at least one board I have only switch it off on
1136 * link 0, causing a blank display if the output has previously been
1137 * programmed for DisplayPort.
1140 nv50_disp_intr_unk40_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp)
1142 struct nouveau_bios *bios = nouveau_bios(priv);
1143 const int link = !(outp->sorconf.link & 1);
1144 const int or = ffs(outp->or) - 1;
1145 const u32 loff = (or * 0x800) + (link * 0x80);
1146 const u16 mask = (outp->sorconf.link << 6) | outp->or;
1149 if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, outp))
1150 nv_mask(priv, 0x61c10c + loff, 0x00000001, 0x00000000);
1154 nv50_disp_intr_unk40(struct nv50_disp_priv *priv, u32 super)
1156 int head = ffs((super & 0x00000180) >> 7) - 1;
1158 struct dcb_output outp;
1159 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
1160 if (pclk && exec_clkcmp(priv, head, 1, pclk, &outp)) {
1161 if (outp.type == DCB_OUTPUT_TMDS)
1162 nv50_disp_intr_unk40_tmds(priv, &outp);
1166 nv_wr32(priv, 0x610024, 0x00000040);
1167 nv_wr32(priv, 0x610030, 0x80000000);
1171 nv50_disp_intr_super(struct nv50_disp_priv *priv, u32 intr1)
1173 u32 super = nv_rd32(priv, 0x610030);
1175 nv_debug(priv, "supervisor 0x%08x 0x%08x\n", intr1, super);
1177 if (intr1 & 0x00000010)
1178 nv50_disp_intr_unk10(priv, super);
1179 if (intr1 & 0x00000020)
1180 nv50_disp_intr_unk20(priv, super);
1181 if (intr1 & 0x00000040)
1182 nv50_disp_intr_unk40(priv, super);
1186 nv50_disp_intr(struct nouveau_subdev *subdev)
1188 struct nv50_disp_priv *priv = (void *)subdev;
1189 u32 intr0 = nv_rd32(priv, 0x610020);
1190 u32 intr1 = nv_rd32(priv, 0x610024);
1192 if (intr0 & 0x001f0000) {
1193 nv50_disp_intr_error(priv);
1194 intr0 &= ~0x001f0000;
1197 if (intr1 & 0x00000004) {
1198 nv50_disp_intr_vblank(priv, 0);
1199 nv_wr32(priv, 0x610024, 0x00000004);
1200 intr1 &= ~0x00000004;
1203 if (intr1 & 0x00000008) {
1204 nv50_disp_intr_vblank(priv, 1);
1205 nv_wr32(priv, 0x610024, 0x00000008);
1206 intr1 &= ~0x00000008;
1209 if (intr1 & 0x00000070) {
1210 nv50_disp_intr_super(priv, intr1);
1211 intr1 &= ~0x00000070;
1216 nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
1217 struct nouveau_oclass *oclass, void *data, u32 size,
1218 struct nouveau_object **pobject)
1220 struct nv50_disp_priv *priv;
1223 ret = nouveau_disp_create(parent, engine, oclass, "PDISP",
1225 *pobject = nv_object(priv);
1229 nv_engine(priv)->sclass = nv50_disp_base_oclass;
1230 nv_engine(priv)->cclass = &nv50_disp_cclass;
1231 nv_subdev(priv)->intr = nv50_disp_intr;
1232 priv->sclass = nv50_disp_sclass;
1236 priv->dac.power = nv50_dac_power;
1237 priv->dac.sense = nv50_dac_sense;
1238 priv->sor.power = nv50_sor_power;
1240 INIT_LIST_HEAD(&priv->base.vblank.list);
1241 spin_lock_init(&priv->base.vblank.lock);
1245 struct nouveau_oclass
1246 nv50_disp_oclass = {
1247 .handle = NV_ENGINE(DISP, 0x50),
1248 .ofuncs = &(struct nouveau_ofuncs) {
1249 .ctor = nv50_disp_ctor,
1250 .dtor = _nouveau_disp_dtor,
1251 .init = _nouveau_disp_init,
1252 .fini = _nouveau_disp_fini,