2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <engine/software.h>
26 #include <engine/disp.h>
28 #include <nvif/class.h>
32 /*******************************************************************************
33 * EVO master channel object
34 ******************************************************************************/
36 const struct nv50_disp_mthd_list
37 nv84_disp_mast_mthd_dac = {
48 const struct nv50_disp_mthd_list
49 nv84_disp_mast_mthd_head = {
100 const struct nv50_disp_mthd_chan
101 nv84_disp_mast_mthd_chan = {
105 { "Global", 1, &nv50_disp_mast_mthd_base },
106 { "DAC", 3, &nv84_disp_mast_mthd_dac },
107 { "SOR", 2, &nv50_disp_mast_mthd_sor },
108 { "PIOR", 3, &nv50_disp_mast_mthd_pior },
109 { "HEAD", 2, &nv84_disp_mast_mthd_head },
114 /*******************************************************************************
115 * EVO sync channel objects
116 ******************************************************************************/
118 static const struct nv50_disp_mthd_list
119 nv84_disp_sync_mthd_base = {
123 { 0x0080, 0x000000 },
124 { 0x0084, 0x0008c4 },
125 { 0x0088, 0x0008d0 },
126 { 0x008c, 0x0008dc },
127 { 0x0090, 0x0008e4 },
128 { 0x0094, 0x610884 },
129 { 0x00a0, 0x6108a0 },
130 { 0x00a4, 0x610878 },
131 { 0x00c0, 0x61086c },
132 { 0x00c4, 0x610800 },
133 { 0x00c8, 0x61080c },
134 { 0x00cc, 0x610818 },
135 { 0x00e0, 0x610858 },
136 { 0x00e4, 0x610860 },
137 { 0x00e8, 0x6108ac },
138 { 0x00ec, 0x6108b4 },
139 { 0x00fc, 0x610824 },
140 { 0x0100, 0x610894 },
141 { 0x0104, 0x61082c },
142 { 0x0110, 0x6108bc },
143 { 0x0114, 0x61088c },
148 const struct nv50_disp_mthd_chan
149 nv84_disp_sync_mthd_chan = {
153 { "Global", 1, &nv84_disp_sync_mthd_base },
154 { "Image", 2, &nv50_disp_sync_mthd_image },
159 /*******************************************************************************
160 * EVO overlay channel objects
161 ******************************************************************************/
163 static const struct nv50_disp_mthd_list
164 nv84_disp_ovly_mthd_base = {
168 { 0x0080, 0x000000 },
169 { 0x0084, 0x6109a0 },
170 { 0x0088, 0x6109c0 },
171 { 0x008c, 0x6109c8 },
172 { 0x0090, 0x6109b4 },
173 { 0x0094, 0x610970 },
174 { 0x00a0, 0x610998 },
175 { 0x00a4, 0x610964 },
176 { 0x00c0, 0x610958 },
177 { 0x00e0, 0x6109a8 },
178 { 0x00e4, 0x6109d0 },
179 { 0x00e8, 0x6109d8 },
180 { 0x0100, 0x61094c },
181 { 0x0104, 0x610984 },
182 { 0x0108, 0x61098c },
183 { 0x0800, 0x6109f8 },
184 { 0x0808, 0x610a08 },
185 { 0x080c, 0x610a10 },
186 { 0x0810, 0x610a00 },
191 const struct nv50_disp_mthd_chan
192 nv84_disp_ovly_mthd_chan = {
196 { "Global", 1, &nv84_disp_ovly_mthd_base },
201 /*******************************************************************************
202 * Base display object
203 ******************************************************************************/
205 static struct nouveau_oclass
206 nv84_disp_sclass[] = {
207 { G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
208 { G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
209 { G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
210 { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
211 { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
215 static struct nouveau_oclass
216 nv84_disp_base_oclass[] = {
217 { G82_DISP, &nv50_disp_base_ofuncs },
221 /*******************************************************************************
222 * Display engine implementation
223 ******************************************************************************/
226 nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
227 struct nouveau_oclass *oclass, void *data, u32 size,
228 struct nouveau_object **pobject)
230 struct nv50_disp_priv *priv;
233 ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
235 *pobject = nv_object(priv);
239 nv_engine(priv)->sclass = nv84_disp_base_oclass;
240 nv_engine(priv)->cclass = &nv50_disp_cclass;
241 nv_subdev(priv)->intr = nv50_disp_intr;
242 INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
243 priv->sclass = nv84_disp_sclass;
248 priv->dac.power = nv50_dac_power;
249 priv->dac.sense = nv50_dac_sense;
250 priv->sor.power = nv50_sor_power;
251 priv->sor.hdmi = nv84_hdmi_ctrl;
252 priv->pior.power = nv50_pior_power;
256 struct nouveau_oclass *
257 nv84_disp_oclass = &(struct nv50_disp_impl) {
258 .base.base.handle = NV_ENGINE(DISP, 0x82),
259 .base.base.ofuncs = &(struct nouveau_ofuncs) {
260 .ctor = nv84_disp_ctor,
261 .dtor = _nouveau_disp_dtor,
262 .init = _nouveau_disp_init,
263 .fini = _nouveau_disp_fini,
265 .base.vblank = &nv50_disp_vblank_func,
266 .base.outp = nv50_disp_outp_sclass,
267 .mthd.core = &nv84_disp_mast_mthd_chan,
268 .mthd.base = &nv84_disp_sync_mthd_chan,
269 .mthd.ovly = &nv84_disp_ovly_mthd_chan,
270 .mthd.prev = 0x000004,
271 .head.scanoutpos = nv50_disp_base_scanoutpos,