2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <engine/software.h>
26 #include <engine/disp.h>
28 #include <nvif/class.h>
32 /*******************************************************************************
34 ******************************************************************************/
36 static struct nouveau_oclass
37 nva3_disp_sclass[] = {
38 { GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
39 { GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
40 { GT214_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
41 { GT214_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
42 { GT214_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
46 static struct nouveau_oclass
47 nva3_disp_base_oclass[] = {
48 { GT214_DISP, &nv50_disp_base_ofuncs },
52 /*******************************************************************************
53 * Display engine implementation
54 ******************************************************************************/
57 nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
58 struct nouveau_oclass *oclass, void *data, u32 size,
59 struct nouveau_object **pobject)
61 struct nv50_disp_priv *priv;
64 ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
66 *pobject = nv_object(priv);
70 ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
74 nv_engine(priv)->sclass = nva3_disp_base_oclass;
75 nv_engine(priv)->cclass = &nv50_disp_cclass;
76 nv_subdev(priv)->intr = nv50_disp_intr;
77 INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
78 priv->sclass = nva3_disp_sclass;
83 priv->dac.power = nv50_dac_power;
84 priv->dac.sense = nv50_dac_sense;
85 priv->sor.power = nv50_sor_power;
86 priv->sor.hda_eld = nva3_hda_eld;
87 priv->sor.hdmi = nva3_hdmi_ctrl;
88 priv->pior.power = nv50_pior_power;
92 struct nouveau_oclass *
93 nva3_disp_oclass = &(struct nv50_disp_impl) {
94 .base.base.handle = NV_ENGINE(DISP, 0x85),
95 .base.base.ofuncs = &(struct nouveau_ofuncs) {
96 .ctor = nva3_disp_ctor,
97 .dtor = _nouveau_disp_dtor,
98 .init = _nouveau_disp_init,
99 .fini = _nouveau_disp_fini,
101 .base.vblank = &nv50_disp_vblank_func,
102 .base.outp = nv94_disp_outp_sclass,
103 .mthd.core = &nv94_disp_mast_mthd_chan,
104 .mthd.base = &nv84_disp_sync_mthd_chan,
105 .mthd.ovly = &nv84_disp_ovly_mthd_chan,
106 .mthd.prev = 0x000004,
107 .head.scanoutpos = nv50_disp_base_scanoutpos,