2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <engine/software.h>
26 #include <engine/disp.h>
28 #include <nvif/class.h>
32 /*******************************************************************************
33 * EVO master channel object
34 ******************************************************************************/
36 static const struct nv50_disp_mthd_list
37 nve0_disp_mast_mthd_head = {
100 { 0x0518, 0x660518 },
101 { 0x051c, 0x66051c },
102 { 0x0520, 0x660520 },
103 { 0x0524, 0x660524 },
104 { 0x052c, 0x66052c },
105 { 0x0530, 0x660530 },
106 { 0x054c, 0x66054c },
107 { 0x0550, 0x660550 },
108 { 0x0554, 0x660554 },
109 { 0x0558, 0x660558 },
110 { 0x055c, 0x66055c },
115 const struct nv50_disp_mthd_chan
116 nve0_disp_mast_mthd_chan = {
120 { "Global", 1, &nvd0_disp_mast_mthd_base },
121 { "DAC", 3, &nvd0_disp_mast_mthd_dac },
122 { "SOR", 8, &nvd0_disp_mast_mthd_sor },
123 { "PIOR", 4, &nvd0_disp_mast_mthd_pior },
124 { "HEAD", 4, &nve0_disp_mast_mthd_head },
129 /*******************************************************************************
130 * EVO overlay channel objects
131 ******************************************************************************/
133 static const struct nv50_disp_mthd_list
134 nve0_disp_ovly_mthd_base = {
137 { 0x0080, 0x665080 },
138 { 0x0084, 0x665084 },
139 { 0x0088, 0x665088 },
140 { 0x008c, 0x66508c },
141 { 0x0090, 0x665090 },
142 { 0x0094, 0x665094 },
143 { 0x00a0, 0x6650a0 },
144 { 0x00a4, 0x6650a4 },
145 { 0x00b0, 0x6650b0 },
146 { 0x00b4, 0x6650b4 },
147 { 0x00b8, 0x6650b8 },
148 { 0x00c0, 0x6650c0 },
149 { 0x00c4, 0x6650c4 },
150 { 0x00e0, 0x6650e0 },
151 { 0x00e4, 0x6650e4 },
152 { 0x00e8, 0x6650e8 },
153 { 0x0100, 0x665100 },
154 { 0x0104, 0x665104 },
155 { 0x0108, 0x665108 },
156 { 0x010c, 0x66510c },
157 { 0x0110, 0x665110 },
158 { 0x0118, 0x665118 },
159 { 0x011c, 0x66511c },
160 { 0x0120, 0x665120 },
161 { 0x0124, 0x665124 },
162 { 0x0130, 0x665130 },
163 { 0x0134, 0x665134 },
164 { 0x0138, 0x665138 },
165 { 0x013c, 0x66513c },
166 { 0x0140, 0x665140 },
167 { 0x0144, 0x665144 },
168 { 0x0148, 0x665148 },
169 { 0x014c, 0x66514c },
170 { 0x0150, 0x665150 },
171 { 0x0154, 0x665154 },
172 { 0x0158, 0x665158 },
173 { 0x015c, 0x66515c },
174 { 0x0160, 0x665160 },
175 { 0x0164, 0x665164 },
176 { 0x0168, 0x665168 },
177 { 0x016c, 0x66516c },
178 { 0x0400, 0x665400 },
179 { 0x0404, 0x665404 },
180 { 0x0408, 0x665408 },
181 { 0x040c, 0x66540c },
182 { 0x0410, 0x665410 },
187 const struct nv50_disp_mthd_chan
188 nve0_disp_ovly_mthd_chan = {
192 { "Global", 1, &nve0_disp_ovly_mthd_base },
197 /*******************************************************************************
198 * Base display object
199 ******************************************************************************/
201 static struct nouveau_oclass
202 nve0_disp_sclass[] = {
203 { GK104_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
204 { GK104_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
205 { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
206 { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
207 { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
211 static struct nouveau_oclass
212 nve0_disp_base_oclass[] = {
213 { GK104_DISP, &nvd0_disp_base_ofuncs },
217 /*******************************************************************************
218 * Display engine implementation
219 ******************************************************************************/
222 nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
223 struct nouveau_oclass *oclass, void *data, u32 size,
224 struct nouveau_object **pobject)
226 struct nv50_disp_priv *priv;
227 int heads = nv_rd32(parent, 0x022448);
230 ret = nouveau_disp_create(parent, engine, oclass, heads,
231 "PDISP", "display", &priv);
232 *pobject = nv_object(priv);
236 nv_engine(priv)->sclass = nve0_disp_base_oclass;
237 nv_engine(priv)->cclass = &nv50_disp_cclass;
238 nv_subdev(priv)->intr = nvd0_disp_intr;
239 INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
240 priv->sclass = nve0_disp_sclass;
241 priv->head.nr = heads;
244 priv->dac.power = nv50_dac_power;
245 priv->dac.sense = nv50_dac_sense;
246 priv->sor.power = nv50_sor_power;
247 priv->sor.hda_eld = nvd0_hda_eld;
248 priv->sor.hdmi = nvd0_hdmi_ctrl;
252 struct nouveau_oclass *
253 nve0_disp_oclass = &(struct nv50_disp_impl) {
254 .base.base.handle = NV_ENGINE(DISP, 0x91),
255 .base.base.ofuncs = &(struct nouveau_ofuncs) {
256 .ctor = nve0_disp_ctor,
257 .dtor = _nouveau_disp_dtor,
258 .init = _nouveau_disp_init,
259 .fini = _nouveau_disp_fini,
261 .base.vblank = &nvd0_disp_vblank_func,
262 .base.outp = nvd0_disp_outp_sclass,
263 .mthd.core = &nve0_disp_mast_mthd_chan,
264 .mthd.base = &nvd0_disp_sync_mthd_chan,
265 .mthd.ovly = &nve0_disp_ovly_mthd_chan,
266 .mthd.prev = -0x020000,
267 .head.scanoutpos = nvd0_disp_base_scanoutpos,