drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <core/engctx.h>
  27 #include <core/ramht.h>
  28 #include <core/class.h>
  29 #include <core/math.h>
  30
  31 #include <subdev/timer.h>
  32 #include <subdev/bar.h>
  33
  34 #include <engine/dmaobj.h>
  35 #include <engine/fifo.h>
  36
  37 #include "nv50.h"
  38
  39 /*******************************************************************************
  40  * FIFO channel objects
  41  ******************************************************************************/
  42
  43 void
  44 nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
  45 {
  46         struct nouveau_bar *bar = nouveau_bar(priv);
  47         struct nouveau_gpuobj *cur;
  48         int i, p;
  49
  50         cur = priv->playlist[priv->cur_playlist];
  51         priv->cur_playlist = !priv->cur_playlist;
  52
  53         for (i = priv->base.min, p = 0; i < priv->base.max; i++) {
  54                 if (nv_rd32(priv, 0x002600 + (i * 4)) & 0x80000000)
  55                         nv_wo32(cur, p++ * 4, i);
  56         }
  57
  58         bar->flush(bar);
  59
  60         nv_wr32(priv, 0x0032f4, cur->addr >> 12);
  61         nv_wr32(priv, 0x0032ec, p);
  62         nv_wr32(priv, 0x002500, 0x00000101);
  63 }
  64
  65 static int
  66 nv50_fifo_context_attach(struct nouveau_object *parent,
  67                          struct nouveau_object *object)
  68 {
  69         struct nouveau_bar *bar = nouveau_bar(parent);
  70         struct nv50_fifo_base *base = (void *)parent->parent;
  71         struct nouveau_gpuobj *ectx = (void *)object;
  72         u64 limit = ectx->addr + ectx->size - 1;
  73         u64 start = ectx->addr;
  74         u32 addr;
  75
  76         switch (nv_engidx(object->engine)) {
  77         case NVDEV_ENGINE_SW   : return 0;
  78         case NVDEV_ENGINE_GR   : addr = 0x0000; break;
  79         case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
  80         default:
  81                 return -EINVAL;
  82         }
  83
  84         nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
  85         nv_wo32(base->eng, addr + 0x00, 0x00190000);
  86         nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
  87         nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
  88         nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
  89                                         upper_32_bits(start));
  90         nv_wo32(base->eng, addr + 0x10, 0x00000000);
  91         nv_wo32(base->eng, addr + 0x14, 0x00000000);
  92         bar->flush(bar);
  93         return 0;
  94 }
  95
  96 static int
  97 nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend,
  98                          struct nouveau_object *object)
  99 {
 100         struct nouveau_bar *bar = nouveau_bar(parent);
 101         struct nv50_fifo_priv *priv = (void *)parent->engine;
 102         struct nv50_fifo_base *base = (void *)parent->parent;
 103         struct nv50_fifo_chan *chan = (void *)parent;
 104         u32 addr, me;
 105         int ret = 0;
 106
 107         switch (nv_engidx(object->engine)) {
 108         case NVDEV_ENGINE_SW   : return 0;
 109         case NVDEV_ENGINE_GR   : addr = 0x0000; break;
 110         case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
 111         default:
 112                 return -EINVAL;
 113         }
 114
 115         /* HW bug workaround:
 116          *
 117          * PFIFO will hang forever if the connected engines don't report
 118          * that they've processed the context switch request.
 119          *
 120          * In order for the kickoff to work, we need to ensure all the
 121          * connected engines are in a state where they can answer.
 122          *
 123          * Newer chipsets don't seem to suffer from this issue, and well,
 124          * there's also a "ignore these engines" bitmask reg we can use
 125          * if we hit the issue there..
 126          */
 127         me = nv_mask(priv, 0x00b860, 0x00000001, 0x00000001);
 128
 129         /* do the kickoff... */
 130         nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
 131         if (!nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff)) {
 132                 nv_error(priv, "channel %d [%s] unload timeout\n",
 133                          chan->base.chid, nouveau_client_name(chan));
 134                 if (suspend)
 135                         ret = -EBUSY;
 136         }
 137         nv_wr32(priv, 0x00b860, me);
 138
 139         if (ret == 0) {
 140                 nv_wo32(base->eng, addr + 0x00, 0x00000000);
 141                 nv_wo32(base->eng, addr + 0x04, 0x00000000);
 142                 nv_wo32(base->eng, addr + 0x08, 0x00000000);
 143                 nv_wo32(base->eng, addr + 0x0c, 0x00000000);
 144                 nv_wo32(base->eng, addr + 0x10, 0x00000000);
 145                 nv_wo32(base->eng, addr + 0x14, 0x00000000);
 146                 bar->flush(bar);
 147         }
 148
 149         return ret;
 150 }
 151
 152 static int
 153 nv50_fifo_object_attach(struct nouveau_object *parent,
 154                         struct nouveau_object *object, u32 handle)
 155 {
 156         struct nv50_fifo_chan *chan = (void *)parent;
 157         u32 context;
 158
 159         if (nv_iclass(object, NV_GPUOBJ_CLASS))
 160                 context = nv_gpuobj(object)->node->offset >> 4;
 161         else
 162                 context = 0x00000004; /* just non-zero */
 163
 164         switch (nv_engidx(object->engine)) {
 165         case NVDEV_ENGINE_DMAOBJ:
 166         case NVDEV_ENGINE_SW    : context |= 0x00000000; break;
 167         case NVDEV_ENGINE_GR    : context |= 0x00100000; break;
 168         case NVDEV_ENGINE_MPEG  : context |= 0x00200000; break;
 169         default:
 170                 return -EINVAL;
 171         }
 172
 173         return nouveau_ramht_insert(chan->ramht, 0, handle, context);
 174 }
 175
 176 void
 177 nv50_fifo_object_detach(struct nouveau_object *parent, int cookie)
 178 {
 179         struct nv50_fifo_chan *chan = (void *)parent;
 180         nouveau_ramht_remove(chan->ramht, cookie);
 181 }
 182
 183 static int
 184 nv50_fifo_chan_ctor_dma(struct nouveau_object *parent,
 185                         struct nouveau_object *engine,
 186                         struct nouveau_oclass *oclass, void *data, u32 size,
 187                         struct nouveau_object **pobject)
 188 {
 189         struct nouveau_bar *bar = nouveau_bar(parent);
 190         struct nv50_fifo_base *base = (void *)parent;
 191         struct nv50_fifo_chan *chan;
 192         struct nv03_channel_dma_class *args = data;
 193         int ret;
 194
 195         if (size < sizeof(*args))
 196                 return -EINVAL;
 197
 198         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 199                                           0x2000, args->pushbuf,
 200                                           (1ULL << NVDEV_ENGINE_DMAOBJ) |
 201                                           (1ULL << NVDEV_ENGINE_SW) |
 202                                           (1ULL << NVDEV_ENGINE_GR) |
 203                                           (1ULL << NVDEV_ENGINE_MPEG), &chan);
 204         *pobject = nv_object(chan);
 205         if (ret)
 206                 return ret;
 207
 208         nv_parent(chan)->context_attach = nv50_fifo_context_attach;
 209         nv_parent(chan)->context_detach = nv50_fifo_context_detach;
 210         nv_parent(chan)->object_attach = nv50_fifo_object_attach;
 211         nv_parent(chan)->object_detach = nv50_fifo_object_detach;
 212
 213         ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
 214                                 &chan->ramht);
 215         if (ret)
 216                 return ret;
 217
 218         nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset));
 219         nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset));
 220         nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset));
 221         nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset));
 222         nv_wo32(base->ramfc, 0x3c, 0x003f6078);
 223         nv_wo32(base->ramfc, 0x44, 0x01003fff);
 224         nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
 225         nv_wo32(base->ramfc, 0x4c, 0xffffffff);
 226         nv_wo32(base->ramfc, 0x60, 0x7fffffff);
 227         nv_wo32(base->ramfc, 0x78, 0x00000000);
 228         nv_wo32(base->ramfc, 0x7c, 0x30000001);
 229         nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 230                                    (4 << 24) /* SEARCH_FULL */ |
 231                                    (chan->ramht->base.node->offset >> 4));
 232         bar->flush(bar);
 233         return 0;
 234 }
 235
 236 static int
 237 nv50_fifo_chan_ctor_ind(struct nouveau_object *parent,
 238                         struct nouveau_object *engine,
 239                         struct nouveau_oclass *oclass, void *data, u32 size,
 240                         struct nouveau_object **pobject)
 241 {
 242         struct nv50_channel_ind_class *args = data;
 243         struct nouveau_bar *bar = nouveau_bar(parent);
 244         struct nv50_fifo_base *base = (void *)parent;
 245         struct nv50_fifo_chan *chan;
 246         u64 ioffset, ilength;
 247         int ret;
 248
 249         if (size < sizeof(*args))
 250                 return -EINVAL;
 251
 252         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 253                                           0x2000, args->pushbuf,
 254                                           (1ULL << NVDEV_ENGINE_DMAOBJ) |
 255                                           (1ULL << NVDEV_ENGINE_SW) |
 256                                           (1ULL << NVDEV_ENGINE_GR) |
 257                                           (1ULL << NVDEV_ENGINE_MPEG), &chan);
 258         *pobject = nv_object(chan);
 259         if (ret)
 260                 return ret;
 261
 262         nv_parent(chan)->context_attach = nv50_fifo_context_attach;
 263         nv_parent(chan)->context_detach = nv50_fifo_context_detach;
 264         nv_parent(chan)->object_attach = nv50_fifo_object_attach;
 265         nv_parent(chan)->object_detach = nv50_fifo_object_detach;
 266
 267         ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
 268                                &chan->ramht);
 269         if (ret)
 270                 return ret;
 271
 272         ioffset = args->ioffset;
 273         ilength = log2i(args->ilength / 8);
 274
 275         nv_wo32(base->ramfc, 0x3c, 0x403f6078);
 276         nv_wo32(base->ramfc, 0x44, 0x01003fff);
 277         nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
 278         nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
 279         nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
 280         nv_wo32(base->ramfc, 0x60, 0x7fffffff);
 281         nv_wo32(base->ramfc, 0x78, 0x00000000);
 282         nv_wo32(base->ramfc, 0x7c, 0x30000001);
 283         nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 284                                    (4 << 24) /* SEARCH_FULL */ |
 285                                    (chan->ramht->base.node->offset >> 4));
 286         bar->flush(bar);
 287         return 0;
 288 }
 289
 290 void
 291 nv50_fifo_chan_dtor(struct nouveau_object *object)
 292 {
 293         struct nv50_fifo_chan *chan = (void *)object;
 294         nouveau_ramht_ref(NULL, &chan->ramht);
 295         nouveau_fifo_channel_destroy(&chan->base);
 296 }
 297
 298 static int
 299 nv50_fifo_chan_init(struct nouveau_object *object)
 300 {
 301         struct nv50_fifo_priv *priv = (void *)object->engine;
 302         struct nv50_fifo_base *base = (void *)object->parent;
 303         struct nv50_fifo_chan *chan = (void *)object;
 304         struct nouveau_gpuobj *ramfc = base->ramfc;
 305         u32 chid = chan->base.chid;
 306         int ret;
 307
 308         ret = nouveau_fifo_channel_init(&chan->base);
 309         if (ret)
 310                 return ret;
 311
 312         nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12);
 313         nv50_fifo_playlist_update(priv);
 314         return 0;
 315 }
 316
 317 int
 318 nv50_fifo_chan_fini(struct nouveau_object *object, bool suspend)
 319 {
 320         struct nv50_fifo_priv *priv = (void *)object->engine;
 321         struct nv50_fifo_chan *chan = (void *)object;
 322         u32 chid = chan->base.chid;
 323
 324         /* remove channel from playlist, fifo will unload context */
 325         nv_mask(priv, 0x002600 + (chid * 4), 0x80000000, 0x00000000);
 326         nv50_fifo_playlist_update(priv);
 327         nv_wr32(priv, 0x002600 + (chid * 4), 0x00000000);
 328
 329         return nouveau_fifo_channel_fini(&chan->base, suspend);
 330 }
 331
 332 static struct nouveau_ofuncs
 333 nv50_fifo_ofuncs_dma = {
 334         .ctor = nv50_fifo_chan_ctor_dma,
 335         .dtor = nv50_fifo_chan_dtor,
 336         .init = nv50_fifo_chan_init,
 337         .fini = nv50_fifo_chan_fini,
 338         .rd32 = _nouveau_fifo_channel_rd32,
 339         .wr32 = _nouveau_fifo_channel_wr32,
 340 };
 341
 342 static struct nouveau_ofuncs
 343 nv50_fifo_ofuncs_ind = {
 344         .ctor = nv50_fifo_chan_ctor_ind,
 345         .dtor = nv50_fifo_chan_dtor,
 346         .init = nv50_fifo_chan_init,
 347         .fini = nv50_fifo_chan_fini,
 348         .rd32 = _nouveau_fifo_channel_rd32,
 349         .wr32 = _nouveau_fifo_channel_wr32,
 350 };
 351
 352 static struct nouveau_oclass
 353 nv50_fifo_sclass[] = {
 354         { NV50_CHANNEL_DMA_CLASS, &nv50_fifo_ofuncs_dma },
 355         { NV50_CHANNEL_IND_CLASS, &nv50_fifo_ofuncs_ind },
 356         {}
 357 };
 358
 359 /*******************************************************************************
 360  * FIFO context - basically just the instmem reserved for the channel
 361  ******************************************************************************/
 362
 363 static int
 364 nv50_fifo_context_ctor(struct nouveau_object *parent,
 365                        struct nouveau_object *engine,
 366                        struct nouveau_oclass *oclass, void *data, u32 size,
 367                        struct nouveau_object **pobject)
 368 {
 369         struct nv50_fifo_base *base;
 370         int ret;
 371
 372         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
 373                                           0x1000, NVOBJ_FLAG_HEAP, &base);
 374         *pobject = nv_object(base);
 375         if (ret)
 376                 return ret;
 377
 378         ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200,
 379                                  0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
 380         if (ret)
 381                 return ret;
 382
 383         ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1200, 0,
 384                                  NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
 385         if (ret)
 386                 return ret;
 387
 388         ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, 0,
 389                                 &base->pgd);
 390         if (ret)
 391                 return ret;
 392
 393         ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
 394         if (ret)
 395                 return ret;
 396
 397         return 0;
 398 }
 399
 400 void
 401 nv50_fifo_context_dtor(struct nouveau_object *object)
 402 {
 403         struct nv50_fifo_base *base = (void *)object;
 404         nouveau_vm_ref(NULL, &base->vm, base->pgd);
 405         nouveau_gpuobj_ref(NULL, &base->pgd);
 406         nouveau_gpuobj_ref(NULL, &base->eng);
 407         nouveau_gpuobj_ref(NULL, &base->ramfc);
 408         nouveau_gpuobj_ref(NULL, &base->cache);
 409         nouveau_fifo_context_destroy(&base->base);
 410 }
 411
 412 static struct nouveau_oclass
 413 nv50_fifo_cclass = {
 414         .handle = NV_ENGCTX(FIFO, 0x50),
 415         .ofuncs = &(struct nouveau_ofuncs) {
 416                 .ctor = nv50_fifo_context_ctor,
 417                 .dtor = nv50_fifo_context_dtor,
 418                 .init = _nouveau_fifo_context_init,
 419                 .fini = _nouveau_fifo_context_fini,
 420                 .rd32 = _nouveau_fifo_context_rd32,
 421                 .wr32 = _nouveau_fifo_context_wr32,
 422         },
 423 };
 424
 425 /*******************************************************************************
 426  * PFIFO engine
 427  ******************************************************************************/
 428
 429 static int
 430 nv50_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 431                struct nouveau_oclass *oclass, void *data, u32 size,
 432                struct nouveau_object **pobject)
 433 {
 434         struct nv50_fifo_priv *priv;
 435         int ret;
 436
 437         ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
 438         *pobject = nv_object(priv);
 439         if (ret)
 440                 return ret;
 441
 442         ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
 443                                 &priv->playlist[0]);
 444         if (ret)
 445                 return ret;
 446
 447         ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
 448                                 &priv->playlist[1]);
 449         if (ret)
 450                 return ret;
 451
 452         nv_subdev(priv)->unit = 0x00000100;
 453         nv_subdev(priv)->intr = nv04_fifo_intr;
 454         nv_engine(priv)->cclass = &nv50_fifo_cclass;
 455         nv_engine(priv)->sclass = nv50_fifo_sclass;
 456         return 0;
 457 }
 458
 459 void
 460 nv50_fifo_dtor(struct nouveau_object *object)
 461 {
 462         struct nv50_fifo_priv *priv = (void *)object;
 463
 464         nouveau_gpuobj_ref(NULL, &priv->playlist[1]);
 465         nouveau_gpuobj_ref(NULL, &priv->playlist[0]);
 466
 467         nouveau_fifo_destroy(&priv->base);
 468 }
 469
 470 int
 471 nv50_fifo_init(struct nouveau_object *object)
 472 {
 473         struct nv50_fifo_priv *priv = (void *)object;
 474         int ret, i;
 475
 476         ret = nouveau_fifo_init(&priv->base);
 477         if (ret)
 478                 return ret;
 479
 480         nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
 481         nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
 482         nv_wr32(priv, 0x00250c, 0x6f3cfc34);
 483         nv_wr32(priv, 0x002044, 0x01003fff);
 484
 485         nv_wr32(priv, 0x002100, 0xffffffff);
 486         nv_wr32(priv, 0x002140, 0xbfffffff);
 487
 488         for (i = 0; i < 128; i++)
 489                 nv_wr32(priv, 0x002600 + (i * 4), 0x00000000);
 490         nv50_fifo_playlist_update(priv);
 491
 492         nv_wr32(priv, 0x003200, 0x00000001);
 493         nv_wr32(priv, 0x003250, 0x00000001);
 494         nv_wr32(priv, 0x002500, 0x00000001);
 495         return 0;
 496 }
 497
 498 struct nouveau_oclass
 499 nv50_fifo_oclass = {
 500         .handle = NV_ENGINE(FIFO, 0x50),
 501         .ofuncs = &(struct nouveau_ofuncs) {
 502                 .ctor = nv50_fifo_ctor,
 503                 .dtor = nv50_fifo_dtor,
 504                 .init = nv50_fifo_init,
 505                 .fini = _nouveau_fifo_fini,
 506         },
 507 };