drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "nvc0.h"
  26 #include "fuc/hubnvc0.fuc.h"
  27 #include "fuc/gpcnvc0.fuc.h"
  28
  29 /*******************************************************************************
  30  * Graphics object classes
  31  ******************************************************************************/
  32
  33 static struct nouveau_oclass
  34 nvc0_graph_sclass[] = {
  35         { 0x902d, &nouveau_object_ofuncs },
  36         { 0x9039, &nouveau_object_ofuncs },
  37         { 0x9097, &nouveau_object_ofuncs },
  38         { 0x90c0, &nouveau_object_ofuncs },
  39         {}
  40 };
  41
  42 static struct nouveau_oclass
  43 nvc1_graph_sclass[] = {
  44         { 0x902d, &nouveau_object_ofuncs },
  45         { 0x9039, &nouveau_object_ofuncs },
  46         { 0x9097, &nouveau_object_ofuncs },
  47         { 0x90c0, &nouveau_object_ofuncs },
  48         { 0x9197, &nouveau_object_ofuncs },
  49         {}
  50 };
  51
  52 static struct nouveau_oclass
  53 nvc8_graph_sclass[] = {
  54         { 0x902d, &nouveau_object_ofuncs },
  55         { 0x9039, &nouveau_object_ofuncs },
  56         { 0x9097, &nouveau_object_ofuncs },
  57         { 0x90c0, &nouveau_object_ofuncs },
  58         { 0x9197, &nouveau_object_ofuncs },
  59         { 0x9297, &nouveau_object_ofuncs },
  60         {}
  61 };
  62
  63 u64
  64 nvc0_graph_units(struct nouveau_graph *graph)
  65 {
  66         struct nvc0_graph_priv *priv = (void *)graph;
  67         u64 cfg;
  68
  69         cfg  = (u32)priv->gpc_nr;
  70         cfg |= (u32)priv->tpc_total << 8;
  71         cfg |= (u64)priv->rop_nr << 32;
  72
  73         return cfg;
  74 }
  75
  76 /*******************************************************************************
  77  * PGRAPH context
  78  ******************************************************************************/
  79
  80 int
  81 nvc0_graph_context_ctor(struct nouveau_object *parent,
  82                         struct nouveau_object *engine,
  83                         struct nouveau_oclass *oclass, void *args, u32 size,
  84                         struct nouveau_object **pobject)
  85 {
  86         struct nouveau_vm *vm = nouveau_client(parent)->vm;
  87         struct nvc0_graph_priv *priv = (void *)engine;
  88         struct nvc0_graph_data *data = priv->mmio_data;
  89         struct nvc0_graph_mmio *mmio = priv->mmio_list;
  90         struct nvc0_graph_chan *chan;
  91         int ret, i;
  92
  93         /* allocate memory for context, and fill with default values */
  94         ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
  95                                            priv->size, 0x100,
  96                                            NVOBJ_FLAG_ZERO_ALLOC, &chan);
  97         *pobject = nv_object(chan);
  98         if (ret)
  99                 return ret;
 100
 101         /* allocate memory for a "mmio list" buffer that's used by the HUB
 102          * fuc to modify some per-context register settings on first load
 103          * of the context.
 104          */
 105         ret = nouveau_gpuobj_new(parent, NULL, 0x1000, 0x100, 0, &chan->mmio);
 106         if (ret)
 107                 return ret;
 108
 109         ret = nouveau_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm,
 110                                     NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
 111                                     &chan->mmio_vma);
 112         if (ret)
 113                 return ret;
 114
 115         /* allocate buffers referenced by mmio list */
 116         for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) {
 117                 ret = nouveau_gpuobj_new(parent, NULL, data->size, data->align,
 118                                          0, &chan->data[i].mem);
 119                 if (ret)
 120                         return ret;
 121
 122                 ret = nouveau_gpuobj_map_vm(chan->data[i].mem, vm, data->access,
 123                                            &chan->data[i].vma);
 124                 if (ret)
 125                         return ret;
 126
 127                 data++;
 128         }
 129
 130         /* finally, fill in the mmio list and point the context at it */
 131         for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) {
 132                 u32 addr = mmio->addr;
 133                 u32 data = mmio->data;
 134
 135                 if (mmio->shift) {
 136                         u64 info = chan->data[mmio->buffer].vma.offset;
 137                         data |= info >> mmio->shift;
 138                 }
 139
 140                 nv_wo32(chan->mmio, chan->mmio_nr++ * 4, addr);
 141                 nv_wo32(chan->mmio, chan->mmio_nr++ * 4, data);
 142                 mmio++;
 143         }
 144
 145         for (i = 0; i < priv->size; i += 4)
 146                 nv_wo32(chan, i, priv->data[i / 4]);
 147
 148         if (!priv->firmware) {
 149                 nv_wo32(chan, 0x00, chan->mmio_nr / 2);
 150                 nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8);
 151         } else {
 152                 nv_wo32(chan, 0xf4, 0);
 153                 nv_wo32(chan, 0xf8, 0);
 154                 nv_wo32(chan, 0x10, chan->mmio_nr / 2);
 155                 nv_wo32(chan, 0x14, lower_32_bits(chan->mmio_vma.offset));
 156                 nv_wo32(chan, 0x18, upper_32_bits(chan->mmio_vma.offset));
 157                 nv_wo32(chan, 0x1c, 1);
 158                 nv_wo32(chan, 0x20, 0);
 159                 nv_wo32(chan, 0x28, 0);
 160                 nv_wo32(chan, 0x2c, 0);
 161         }
 162
 163         return 0;
 164 }
 165
 166 void
 167 nvc0_graph_context_dtor(struct nouveau_object *object)
 168 {
 169         struct nvc0_graph_chan *chan = (void *)object;
 170         int i;
 171
 172         for (i = 0; i < ARRAY_SIZE(chan->data); i++) {
 173                 nouveau_gpuobj_unmap(&chan->data[i].vma);
 174                 nouveau_gpuobj_ref(NULL, &chan->data[i].mem);
 175         }
 176
 177         nouveau_gpuobj_unmap(&chan->mmio_vma);
 178         nouveau_gpuobj_ref(NULL, &chan->mmio);
 179
 180         nouveau_graph_context_destroy(&chan->base);
 181 }
 182
 183 static struct nouveau_oclass
 184 nvc0_graph_cclass = {
 185         .ofuncs = &(struct nouveau_ofuncs) {
 186                 .ctor = nvc0_graph_context_ctor,
 187                 .dtor = nvc0_graph_context_dtor,
 188                 .init = _nouveau_graph_context_init,
 189                 .fini = _nouveau_graph_context_fini,
 190                 .rd32 = _nouveau_graph_context_rd32,
 191                 .wr32 = _nouveau_graph_context_wr32,
 192         },
 193 };
 194
 195 /*******************************************************************************
 196  * PGRAPH engine/subdev functions
 197  ******************************************************************************/
 198
 199 static void
 200 nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base)
 201 {
 202         nv_error(priv, "%06x - done 0x%08x\n", base,
 203                  nv_rd32(priv, base + 0x400));
 204         nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
 205                  nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804),
 206                  nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c));
 207         nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
 208                  nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814),
 209                  nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c));
 210 }
 211
 212 void
 213 nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv)
 214 {
 215         u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff;
 216         u32 gpc;
 217
 218         nvc0_graph_ctxctl_debug_unit(priv, 0x409000);
 219         for (gpc = 0; gpc < gpcnr; gpc++)
 220                 nvc0_graph_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
 221 }
 222
 223 static void
 224 nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
 225 {
 226         u32 ustat = nv_rd32(priv, 0x409c18);
 227
 228         if (ustat & 0x00000001)
 229                 nv_error(priv, "CTXCTRL ucode error\n");
 230         if (ustat & 0x00080000)
 231                 nv_error(priv, "CTXCTRL watchdog timeout\n");
 232         if (ustat & ~0x00080001)
 233                 nv_error(priv, "CTXCTRL 0x%08x\n", ustat);
 234
 235         nvc0_graph_ctxctl_debug(priv);
 236         nv_wr32(priv, 0x409c20, ustat);
 237 }
 238
 239 static void
 240 nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc)
 241 {
 242         u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508));
 243
 244         if (stat & 0x00000001) {
 245                 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224));
 246                 nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap);
 247                 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
 248                 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000001);
 249                 stat &= ~0x00000001;
 250         }
 251
 252         if (stat & 0x00000002) {
 253                 u32 trap0 = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0644));
 254                 u32 trap1 = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x064c));
 255                 nv_error(priv, "GPC%d/TPC%d/MP: 0x%08x 0x%08x\n",
 256                                gpc, tpc, trap0, trap1);
 257                 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0644), 0x001ffffe);
 258                 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x064c), 0x0000000f);
 259                 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000002);
 260                 stat &= ~0x00000002;
 261         }
 262
 263         if (stat & 0x00000004) {
 264                 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084));
 265                 nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap);
 266                 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
 267                 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000004);
 268                 stat &= ~0x00000004;
 269         }
 270
 271         if (stat & 0x00000008) {
 272                 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c));
 273                 nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap);
 274                 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
 275                 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000008);
 276                 stat &= ~0x00000008;
 277         }
 278
 279         if (stat) {
 280                 nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat);
 281                 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), stat);
 282         }
 283 }
 284
 285 static void
 286 nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
 287 {
 288         u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90));
 289         int tpc;
 290
 291         if (stat & 0x00000001) {
 292                 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0420));
 293                 nv_error(priv, "GPC%d/PROP: 0x%08x\n", gpc, trap);
 294                 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
 295                 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000001);
 296                 stat &= ~0x00000001;
 297         }
 298
 299         if (stat & 0x00000002) {
 300                 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900));
 301                 nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap);
 302                 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
 303                 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000002);
 304                 stat &= ~0x00000002;
 305         }
 306
 307         if (stat & 0x00000004) {
 308                 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028));
 309                 nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap);
 310                 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
 311                 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000004);
 312                 stat &= ~0x00000004;
 313         }
 314
 315         if (stat & 0x00000008) {
 316                 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824));
 317                 nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap);
 318                 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
 319                 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000008);
 320                 stat &= ~0x00000009;
 321         }
 322
 323         for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
 324                 u32 mask = 0x00010000 << tpc;
 325                 if (stat & mask) {
 326                         nvc0_graph_trap_tpc(priv, gpc, tpc);
 327                         nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask);
 328                         stat &= ~mask;
 329                 }
 330         }
 331
 332         if (stat) {
 333                 nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat);
 334                 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), stat);
 335         }
 336 }
 337
 338 static void
 339 nvc0_graph_trap_intr(struct nvc0_graph_priv *priv)
 340 {
 341         u32 trap = nv_rd32(priv, 0x400108);
 342         int rop, gpc;
 343
 344         if (trap & 0x00000001) {
 345                 u32 stat = nv_rd32(priv, 0x404000);
 346                 nv_error(priv, "DISPATCH 0x%08x\n", stat);
 347                 nv_wr32(priv, 0x404000, 0xc0000000);
 348                 nv_wr32(priv, 0x400108, 0x00000001);
 349                 trap &= ~0x00000001;
 350         }
 351
 352         if (trap & 0x00000002) {
 353                 u32 stat = nv_rd32(priv, 0x404600);
 354                 nv_error(priv, "M2MF 0x%08x\n", stat);
 355                 nv_wr32(priv, 0x404600, 0xc0000000);
 356                 nv_wr32(priv, 0x400108, 0x00000002);
 357                 trap &= ~0x00000002;
 358         }
 359
 360         if (trap & 0x00000008) {
 361                 u32 stat = nv_rd32(priv, 0x408030);
 362                 nv_error(priv, "CCACHE 0x%08x\n", stat);
 363                 nv_wr32(priv, 0x408030, 0xc0000000);
 364                 nv_wr32(priv, 0x400108, 0x00000008);
 365                 trap &= ~0x00000008;
 366         }
 367
 368         if (trap & 0x00000010) {
 369                 u32 stat = nv_rd32(priv, 0x405840);
 370                 nv_error(priv, "SHADER 0x%08x\n", stat);
 371                 nv_wr32(priv, 0x405840, 0xc0000000);
 372                 nv_wr32(priv, 0x400108, 0x00000010);
 373                 trap &= ~0x00000010;
 374         }
 375
 376         if (trap & 0x00000040) {
 377                 u32 stat = nv_rd32(priv, 0x40601c);
 378                 nv_error(priv, "UNK6 0x%08x\n", stat);
 379                 nv_wr32(priv, 0x40601c, 0xc0000000);
 380                 nv_wr32(priv, 0x400108, 0x00000040);
 381                 trap &= ~0x00000040;
 382         }
 383
 384         if (trap & 0x00000080) {
 385                 u32 stat = nv_rd32(priv, 0x404490);
 386                 nv_error(priv, "MACRO 0x%08x\n", stat);
 387                 nv_wr32(priv, 0x404490, 0xc0000000);
 388                 nv_wr32(priv, 0x400108, 0x00000080);
 389                 trap &= ~0x00000080;
 390         }
 391
 392         if (trap & 0x01000000) {
 393                 u32 stat = nv_rd32(priv, 0x400118);
 394                 for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) {
 395                         u32 mask = 0x00000001 << gpc;
 396                         if (stat & mask) {
 397                                 nvc0_graph_trap_gpc(priv, gpc);
 398                                 nv_wr32(priv, 0x400118, mask);
 399                                 stat &= ~mask;
 400                         }
 401                 }
 402                 nv_wr32(priv, 0x400108, 0x01000000);
 403                 trap &= ~0x01000000;
 404         }
 405
 406         if (trap & 0x02000000) {
 407                 for (rop = 0; rop < priv->rop_nr; rop++) {
 408                         u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070));
 409                         u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144));
 410                         nv_error(priv, "ROP%d 0x%08x 0x%08x\n",
 411                                  rop, statz, statc);
 412                         nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
 413                         nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
 414                 }
 415                 nv_wr32(priv, 0x400108, 0x02000000);
 416                 trap &= ~0x02000000;
 417         }
 418
 419         if (trap) {
 420                 nv_error(priv, "TRAP UNHANDLED 0x%08x\n", trap);
 421                 nv_wr32(priv, 0x400108, trap);
 422         }
 423 }
 424
 425 static void
 426 nvc0_graph_intr(struct nouveau_subdev *subdev)
 427 {
 428         struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
 429         struct nouveau_engine *engine = nv_engine(subdev);
 430         struct nouveau_object *engctx;
 431         struct nouveau_handle *handle;
 432         struct nvc0_graph_priv *priv = (void *)subdev;
 433         u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff;
 434         u32 stat = nv_rd32(priv, 0x400100);
 435         u32 addr = nv_rd32(priv, 0x400704);
 436         u32 mthd = (addr & 0x00003ffc);
 437         u32 subc = (addr & 0x00070000) >> 16;
 438         u32 data = nv_rd32(priv, 0x400708);
 439         u32 code = nv_rd32(priv, 0x400110);
 440         u32 class = nv_rd32(priv, 0x404200 + (subc * 4));
 441         int chid;
 442
 443         engctx = nouveau_engctx_get(engine, inst);
 444         chid   = pfifo->chid(pfifo, engctx);
 445
 446         if (stat & 0x00000010) {
 447                 handle = nouveau_handle_get_class(engctx, class);
 448                 if (!handle || nv_call(handle->object, mthd, data)) {
 449                         nv_error(priv,
 450                                  "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
 451                                  chid, inst << 12, nouveau_client_name(engctx),
 452                                  subc, class, mthd, data);
 453                 }
 454                 nouveau_handle_put(handle);
 455                 nv_wr32(priv, 0x400100, 0x00000010);
 456                 stat &= ~0x00000010;
 457         }
 458
 459         if (stat & 0x00000020) {
 460                 nv_error(priv,
 461                          "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
 462                          chid, inst << 12, nouveau_client_name(engctx), subc,
 463                          class, mthd, data);
 464                 nv_wr32(priv, 0x400100, 0x00000020);
 465                 stat &= ~0x00000020;
 466         }
 467
 468         if (stat & 0x00100000) {
 469                 nv_error(priv, "DATA_ERROR [");
 470                 nouveau_enum_print(nv50_data_error_names, code);
 471                 pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
 472                         chid, inst << 12, nouveau_client_name(engctx), subc,
 473                         class, mthd, data);
 474                 nv_wr32(priv, 0x400100, 0x00100000);
 475                 stat &= ~0x00100000;
 476         }
 477
 478         if (stat & 0x00200000) {
 479                 nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12,
 480                          nouveau_client_name(engctx));
 481                 nvc0_graph_trap_intr(priv);
 482                 nv_wr32(priv, 0x400100, 0x00200000);
 483                 stat &= ~0x00200000;
 484         }
 485
 486         if (stat & 0x00080000) {
 487                 nvc0_graph_ctxctl_isr(priv);
 488                 nv_wr32(priv, 0x400100, 0x00080000);
 489                 stat &= ~0x00080000;
 490         }
 491
 492         if (stat) {
 493                 nv_error(priv, "unknown stat 0x%08x\n", stat);
 494                 nv_wr32(priv, 0x400100, stat);
 495         }
 496
 497         nv_wr32(priv, 0x400500, 0x00010001);
 498         nouveau_engctx_put(engctx);
 499 }
 500
 501 int
 502 nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname,
 503                    struct nvc0_graph_fuc *fuc)
 504 {
 505         struct nouveau_device *device = nv_device(priv);
 506         const struct firmware *fw;
 507         char f[32];
 508         int ret;
 509
 510         snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname);
 511         ret = request_firmware(&fw, f, &device->pdev->dev);
 512         if (ret) {
 513                 snprintf(f, sizeof(f), "nouveau/%s", fwname);
 514                 ret = request_firmware(&fw, f, &device->pdev->dev);
 515                 if (ret) {
 516                         nv_error(priv, "failed to load %s\n", fwname);
 517                         return ret;
 518                 }
 519         }
 520
 521         fuc->size = fw->size;
 522         fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
 523         release_firmware(fw);
 524         return (fuc->data != NULL) ? 0 : -ENOMEM;
 525 }
 526
 527 static int
 528 nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 529                 struct nouveau_oclass *oclass, void *data, u32 size,
 530                 struct nouveau_object **pobject)
 531 {
 532         struct nouveau_device *device = nv_device(parent);
 533         struct nvc0_graph_priv *priv;
 534         bool enable = device->chipset != 0xd7;
 535         int ret, i;
 536
 537         ret = nouveau_graph_create(parent, engine, oclass, enable, &priv);
 538         *pobject = nv_object(priv);
 539         if (ret)
 540                 return ret;
 541
 542         nv_subdev(priv)->unit = 0x18001000;
 543         nv_subdev(priv)->intr = nvc0_graph_intr;
 544         nv_engine(priv)->cclass = &nvc0_graph_cclass;
 545
 546         priv->base.units = nvc0_graph_units;
 547
 548         if (nouveau_boolopt(device->cfgopt, "NvGrUseFW", false)) {
 549                 nv_info(priv, "using external firmware\n");
 550                 if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
 551                     nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
 552                     nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
 553                     nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
 554                         return -EINVAL;
 555                 priv->firmware = true;
 556         }
 557
 558         switch (nvc0_graph_class(priv)) {
 559         case 0x9097:
 560                 nv_engine(priv)->sclass = nvc0_graph_sclass;
 561                 break;
 562         case 0x9197:
 563                 nv_engine(priv)->sclass = nvc1_graph_sclass;
 564                 break;
 565         case 0x9297:
 566                 nv_engine(priv)->sclass = nvc8_graph_sclass;
 567                 break;
 568         }
 569
 570         ret = nouveau_gpuobj_new(parent, NULL, 0x1000, 256, 0, &priv->unk4188b4);
 571         if (ret)
 572                 return ret;
 573
 574         ret = nouveau_gpuobj_new(parent, NULL, 0x1000, 256, 0, &priv->unk4188b8);
 575         if (ret)
 576                 return ret;
 577
 578         for (i = 0; i < 0x1000; i += 4) {
 579                 nv_wo32(priv->unk4188b4, i, 0x00000010);
 580                 nv_wo32(priv->unk4188b8, i, 0x00000010);
 581         }
 582
 583         priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16;
 584         priv->gpc_nr =  nv_rd32(priv, 0x409604) & 0x0000001f;
 585         for (i = 0; i < priv->gpc_nr; i++) {
 586                 priv->tpc_nr[i]  = nv_rd32(priv, GPC_UNIT(i, 0x2608));
 587                 priv->tpc_total += priv->tpc_nr[i];
 588         }
 589
 590         /*XXX: these need figuring out... though it might not even matter */
 591         switch (nv_device(priv)->chipset) {
 592         case 0xc0:
 593                 if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
 594                         priv->magic_not_rop_nr = 0x07;
 595                 } else
 596                 if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
 597                         priv->magic_not_rop_nr = 0x05;
 598                 } else
 599                 if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
 600                         priv->magic_not_rop_nr = 0x06;
 601                 }
 602                 break;
 603         case 0xc3: /* 450, 4/0/0/0, 2 */
 604                 priv->magic_not_rop_nr = 0x03;
 605                 break;
 606         case 0xc4: /* 460, 3/4/0/0, 4 */
 607                 priv->magic_not_rop_nr = 0x01;
 608                 break;
 609         case 0xc1: /* 2/0/0/0, 1 */
 610                 priv->magic_not_rop_nr = 0x01;
 611                 break;
 612         case 0xc8: /* 4/4/3/4, 5 */
 613                 priv->magic_not_rop_nr = 0x06;
 614                 break;
 615         case 0xce: /* 4/4/0/0, 4 */
 616                 priv->magic_not_rop_nr = 0x03;
 617                 break;
 618         case 0xcf: /* 4/0/0/0, 3 */
 619                 priv->magic_not_rop_nr = 0x03;
 620                 break;
 621         case 0xd9: /* 1/0/0/0, 1 */
 622                 priv->magic_not_rop_nr = 0x01;
 623                 break;
 624         }
 625
 626         return 0;
 627 }
 628
 629 static void
 630 nvc0_graph_dtor_fw(struct nvc0_graph_fuc *fuc)
 631 {
 632         kfree(fuc->data);
 633         fuc->data = NULL;
 634 }
 635
 636 void
 637 nvc0_graph_dtor(struct nouveau_object *object)
 638 {
 639         struct nvc0_graph_priv *priv = (void *)object;
 640
 641         kfree(priv->data);
 642
 643         nvc0_graph_dtor_fw(&priv->fuc409c);
 644         nvc0_graph_dtor_fw(&priv->fuc409d);
 645         nvc0_graph_dtor_fw(&priv->fuc41ac);
 646         nvc0_graph_dtor_fw(&priv->fuc41ad);
 647
 648         nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
 649         nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
 650
 651         nouveau_graph_destroy(&priv->base);
 652 }
 653
 654 static void
 655 nvc0_graph_init_obj418880(struct nvc0_graph_priv *priv)
 656 {
 657         int i;
 658
 659         nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
 660         nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
 661         for (i = 0; i < 4; i++)
 662                 nv_wr32(priv, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
 663         nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
 664         nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
 665 }
 666
 667 static void
 668 nvc0_graph_init_regs(struct nvc0_graph_priv *priv)
 669 {
 670         nv_wr32(priv, 0x400080, 0x003083c2);
 671         nv_wr32(priv, 0x400088, 0x00006fe7);
 672         nv_wr32(priv, 0x40008c, 0x00000000);
 673         nv_wr32(priv, 0x400090, 0x00000030);
 674         nv_wr32(priv, 0x40013c, 0x013901f7);
 675         nv_wr32(priv, 0x400140, 0x00000100);
 676         nv_wr32(priv, 0x400144, 0x00000000);
 677         nv_wr32(priv, 0x400148, 0x00000110);
 678         nv_wr32(priv, 0x400138, 0x00000000);
 679         nv_wr32(priv, 0x400130, 0x00000000);
 680         nv_wr32(priv, 0x400134, 0x00000000);
 681         nv_wr32(priv, 0x400124, 0x00000002);
 682 }
 683
 684 static void
 685 nvc0_graph_init_gpc_0(struct nvc0_graph_priv *priv)
 686 {
 687         const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
 688         u32 data[TPC_MAX / 8];
 689         u8  tpcnr[GPC_MAX];
 690         int i, gpc, tpc;
 691
 692         nv_wr32(priv, TPC_UNIT(0, 0, 0x5c), 1); /* affects TFB offset queries */
 693
 694         /*
 695          *      TP      ROP UNKVAL(magic_not_rop_nr)
 696          * 450: 4/0/0/0 2        3
 697          * 460: 3/4/0/0 4        1
 698          * 465: 3/4/4/0 4        7
 699          * 470: 3/3/4/4 5        5
 700          * 480: 3/4/4/4 6        6
 701          */
 702
 703         memset(data, 0x00, sizeof(data));
 704         memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
 705         for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
 706                 do {
 707                         gpc = (gpc + 1) % priv->gpc_nr;
 708                 } while (!tpcnr[gpc]);
 709                 tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
 710
 711                 data[i / 8] |= tpc << ((i % 8) * 4);
 712         }
 713
 714         nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
 715         nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
 716         nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
 717         nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
 718
 719         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 720                 nv_wr32(priv, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
 721                                                   priv->tpc_nr[gpc]);
 722                 nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total);
 723                 nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
 724         }
 725
 726         nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918);
 727         nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
 728 }
 729
 730 static void
 731 nvc0_graph_init_units(struct nvc0_graph_priv *priv)
 732 {
 733         nv_wr32(priv, 0x409c24, 0x000f0000);
 734         nv_wr32(priv, 0x404000, 0xc0000000); /* DISPATCH */
 735         nv_wr32(priv, 0x404600, 0xc0000000); /* M2MF */
 736         nv_wr32(priv, 0x408030, 0xc0000000);
 737         nv_wr32(priv, 0x40601c, 0xc0000000);
 738         nv_wr32(priv, 0x404490, 0xc0000000); /* MACRO */
 739         nv_wr32(priv, 0x406018, 0xc0000000);
 740         nv_wr32(priv, 0x405840, 0xc0000000);
 741         nv_wr32(priv, 0x405844, 0x00ffffff);
 742         nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
 743         nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
 744 }
 745
 746 static void
 747 nvc0_graph_init_gpc_1(struct nvc0_graph_priv *priv)
 748 {
 749         int gpc, tpc;
 750
 751         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 752                 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
 753                 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
 754                 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
 755                 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
 756                 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
 757                         nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
 758                         nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
 759                         nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
 760                         nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
 761                         nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
 762                         nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
 763                         nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
 764                 }
 765                 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
 766                 nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
 767         }
 768 }
 769
 770 static void
 771 nvc0_graph_init_rop(struct nvc0_graph_priv *priv)
 772 {
 773         int rop;
 774
 775         for (rop = 0; rop < priv->rop_nr; rop++) {
 776                 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
 777                 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
 778                 nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
 779                 nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
 780         }
 781 }
 782
 783 void
 784 nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base,
 785                    struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
 786 {
 787         int i;
 788
 789         nv_wr32(priv, fuc_base + 0x01c0, 0x01000000);
 790         for (i = 0; i < data->size / 4; i++)
 791                 nv_wr32(priv, fuc_base + 0x01c4, data->data[i]);
 792
 793         nv_wr32(priv, fuc_base + 0x0180, 0x01000000);
 794         for (i = 0; i < code->size / 4; i++) {
 795                 if ((i & 0x3f) == 0)
 796                         nv_wr32(priv, fuc_base + 0x0188, i >> 6);
 797                 nv_wr32(priv, fuc_base + 0x0184, code->data[i]);
 798         }
 799 }
 800
 801 static int
 802 nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
 803 {
 804         u32 r000260;
 805         int i;
 806
 807         if (priv->firmware) {
 808                 /* load fuc microcode */
 809                 r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
 810                 nvc0_graph_init_fw(priv, 0x409000, &priv->fuc409c,
 811                                                    &priv->fuc409d);
 812                 nvc0_graph_init_fw(priv, 0x41a000, &priv->fuc41ac,
 813                                                    &priv->fuc41ad);
 814                 nv_wr32(priv, 0x000260, r000260);
 815
 816                 /* start both of them running */
 817                 nv_wr32(priv, 0x409840, 0xffffffff);
 818                 nv_wr32(priv, 0x41a10c, 0x00000000);
 819                 nv_wr32(priv, 0x40910c, 0x00000000);
 820                 nv_wr32(priv, 0x41a100, 0x00000002);
 821                 nv_wr32(priv, 0x409100, 0x00000002);
 822                 if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001))
 823                         nv_warn(priv, "0x409800 wait failed\n");
 824
 825                 nv_wr32(priv, 0x409840, 0xffffffff);
 826                 nv_wr32(priv, 0x409500, 0x7fffffff);
 827                 nv_wr32(priv, 0x409504, 0x00000021);
 828
 829                 nv_wr32(priv, 0x409840, 0xffffffff);
 830                 nv_wr32(priv, 0x409500, 0x00000000);
 831                 nv_wr32(priv, 0x409504, 0x00000010);
 832                 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
 833                         nv_error(priv, "fuc09 req 0x10 timeout\n");
 834                         return -EBUSY;
 835                 }
 836                 priv->size = nv_rd32(priv, 0x409800);
 837
 838                 nv_wr32(priv, 0x409840, 0xffffffff);
 839                 nv_wr32(priv, 0x409500, 0x00000000);
 840                 nv_wr32(priv, 0x409504, 0x00000016);
 841                 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
 842                         nv_error(priv, "fuc09 req 0x16 timeout\n");
 843                         return -EBUSY;
 844                 }
 845
 846                 nv_wr32(priv, 0x409840, 0xffffffff);
 847                 nv_wr32(priv, 0x409500, 0x00000000);
 848                 nv_wr32(priv, 0x409504, 0x00000025);
 849                 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
 850                         nv_error(priv, "fuc09 req 0x25 timeout\n");
 851                         return -EBUSY;
 852                 }
 853
 854                 if (priv->data == NULL) {
 855                         int ret = nvc0_grctx_generate(priv);
 856                         if (ret) {
 857                                 nv_error(priv, "failed to construct context\n");
 858                                 return ret;
 859                         }
 860                 }
 861
 862                 return 0;
 863         }
 864
 865         /* load HUB microcode */
 866         r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
 867         nv_wr32(priv, 0x4091c0, 0x01000000);
 868         for (i = 0; i < sizeof(nvc0_grhub_data) / 4; i++)
 869                 nv_wr32(priv, 0x4091c4, nvc0_grhub_data[i]);
 870
 871         nv_wr32(priv, 0x409180, 0x01000000);
 872         for (i = 0; i < sizeof(nvc0_grhub_code) / 4; i++) {
 873                 if ((i & 0x3f) == 0)
 874                         nv_wr32(priv, 0x409188, i >> 6);
 875                 nv_wr32(priv, 0x409184, nvc0_grhub_code[i]);
 876         }
 877
 878         /* load GPC microcode */
 879         nv_wr32(priv, 0x41a1c0, 0x01000000);
 880         for (i = 0; i < sizeof(nvc0_grgpc_data) / 4; i++)
 881                 nv_wr32(priv, 0x41a1c4, nvc0_grgpc_data[i]);
 882
 883         nv_wr32(priv, 0x41a180, 0x01000000);
 884         for (i = 0; i < sizeof(nvc0_grgpc_code) / 4; i++) {
 885                 if ((i & 0x3f) == 0)
 886                         nv_wr32(priv, 0x41a188, i >> 6);
 887                 nv_wr32(priv, 0x41a184, nvc0_grgpc_code[i]);
 888         }
 889         nv_wr32(priv, 0x000260, r000260);
 890
 891         /* start HUB ucode running, it'll init the GPCs */
 892         nv_wr32(priv, 0x409800, nv_device(priv)->chipset);
 893         nv_wr32(priv, 0x40910c, 0x00000000);
 894         nv_wr32(priv, 0x409100, 0x00000002);
 895         if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
 896                 nv_error(priv, "HUB_INIT timed out\n");
 897                 nvc0_graph_ctxctl_debug(priv);
 898                 return -EBUSY;
 899         }
 900
 901         priv->size = nv_rd32(priv, 0x409804);
 902         if (priv->data == NULL) {
 903                 int ret = nvc0_grctx_generate(priv);
 904                 if (ret) {
 905                         nv_error(priv, "failed to construct context\n");
 906                         return ret;
 907                 }
 908         }
 909
 910         return 0;
 911 }
 912
 913 static int
 914 nvc0_graph_init(struct nouveau_object *object)
 915 {
 916         struct nvc0_graph_priv *priv = (void *)object;
 917         int ret;
 918
 919         ret = nouveau_graph_init(&priv->base);
 920         if (ret)
 921                 return ret;
 922
 923         nvc0_graph_init_obj418880(priv);
 924         nvc0_graph_init_regs(priv);
 925         /*nvc0_graph_init_unitplemented_magics(priv);*/
 926         nvc0_graph_init_gpc_0(priv);
 927         /*nvc0_graph_init_unitplemented_c242(priv);*/
 928
 929         nv_wr32(priv, 0x400500, 0x00010001);
 930         nv_wr32(priv, 0x400100, 0xffffffff);
 931         nv_wr32(priv, 0x40013c, 0xffffffff);
 932
 933         nvc0_graph_init_units(priv);
 934         nvc0_graph_init_gpc_1(priv);
 935         nvc0_graph_init_rop(priv);
 936
 937         nv_wr32(priv, 0x400108, 0xffffffff);
 938         nv_wr32(priv, 0x400138, 0xffffffff);
 939         nv_wr32(priv, 0x400118, 0xffffffff);
 940         nv_wr32(priv, 0x400130, 0xffffffff);
 941         nv_wr32(priv, 0x40011c, 0xffffffff);
 942         nv_wr32(priv, 0x400134, 0xffffffff);
 943         nv_wr32(priv, 0x400054, 0x34ce3464);
 944
 945         ret = nvc0_graph_init_ctxctl(priv);
 946         if (ret)
 947                 return ret;
 948
 949         return 0;
 950 }
 951
 952 struct nouveau_oclass
 953 nvc0_graph_oclass = {
 954         .handle = NV_ENGINE(GR, 0xc0),
 955         .ofuncs = &(struct nouveau_ofuncs) {
 956                 .ctor = nvc0_graph_ctor,
 957                 .dtor = nvc0_graph_dtor,
 958                 .init = nvc0_graph_init,
 959                 .fini = _nouveau_graph_fini,
 960         },
 961 };