1 #ifndef __NVBIOS_PLL_H__
2 #define __NVBIOS_PLL_H__
5 struct nouveau_pll_vals {
9 uint8_t N1, M1, N2, M2;
11 uint8_t M1, N1, M2, N2;
16 } __attribute__((packed));
25 /* these match types in pll limits table version 0x40,
26 * nouveau uses them on all chipsets internally where a
27 * specific pll needs to be referenced, but the exact
28 * register isn't known.
30 enum nvbios_pll_type {
45 enum nvbios_pll_type type;
54 * for most pre nv50 cards setting a log2P of 7 (the common max_log2p
55 * value) is no different to 6 (at least for vplls) so allowing the MNP
56 * calc to use 7 causes the generated clock to be out by a factor of 2.
57 * however, max_log2p cannot be fixed-up during parsing as the
58 * unmodified max_log2p value is still needed for setting mplls, hence
59 * an additional max_usable_log2p member
75 int nvbios_pll_parse(struct nouveau_bios *, u32 type, struct nvbios_pll *);