1 #include <core/engine.h>
2 #include <core/device.h>
4 #include <subdev/bios.h>
5 #include <subdev/bios/conn.h>
6 #include <subdev/bios/bmp.h>
7 #include <subdev/bios/bit.h>
8 #include <subdev/bios/dcb.h>
9 #include <subdev/bios/dp.h>
10 #include <subdev/bios/init.h>
11 #include <subdev/devinit.h>
12 #include <subdev/clock.h>
13 #include <subdev/i2c.h>
14 #include <subdev/vga.h>
15 #include <subdev/gpio.h>
17 #define bioslog(lvl, fmt, args...) do { \
18 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
19 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
21 #define cont(fmt, args...) do { \
22 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
23 printk(fmt, ##args); \
25 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
26 #define warn(fmt, args...) bioslog(WARN, fmt, ##args)
27 #define error(fmt, args...) bioslog(ERROR, fmt, ##args)
29 /******************************************************************************
30 * init parser control flow helpers
31 *****************************************************************************/
34 init_exec(struct nvbios_init *init)
36 return (init->execute == 1) || ((init->execute & 5) == 5);
40 init_exec_set(struct nvbios_init *init, bool exec)
42 if (exec) init->execute &= 0xfd;
43 else init->execute |= 0x02;
47 init_exec_inv(struct nvbios_init *init)
49 init->execute ^= 0x02;
53 init_exec_force(struct nvbios_init *init, bool exec)
55 if (exec) init->execute |= 0x04;
56 else init->execute &= 0xfb;
59 /******************************************************************************
60 * init parser wrappers for normal register/i2c/whatever accessors
61 *****************************************************************************/
64 init_or(struct nvbios_init *init)
67 return ffs(init->outp->or) - 1;
68 error("script needs OR!!\n");
73 init_link(struct nvbios_init *init)
76 return !(init->outp->sorconf.link & 1);
77 error("script needs OR link\n");
82 init_crtc(struct nvbios_init *init)
86 error("script needs crtc\n");
91 init_conn(struct nvbios_init *init)
93 struct nouveau_bios *bios = init->bios;
97 u16 conn = dcb_conn(bios, init->outp->connector, &ver, &len);
99 return nv_ro08(bios, conn);
102 error("script needs connector type\n");
107 init_nvreg(struct nvbios_init *init, u32 reg)
109 /* C51 (at least) sometimes has the lower bits set which the VBIOS
110 * interprets to mean that access needs to go through certain IO
111 * ports instead. The NVIDIA binary driver has been seen to access
112 * these through the NV register address, so lets assume we can
117 /* GF8+ display scripts need register addresses mangled a bit to
118 * select a specific CRTC/OR
120 if (nv_device(init->bios)->card_type >= NV_50) {
121 if (reg & 0x80000000) {
122 reg += init_crtc(init) * 0x800;
126 if (reg & 0x40000000) {
127 reg += init_or(init) * 0x800;
129 if (reg & 0x20000000) {
130 reg += init_link(init) * 0x80;
136 if (reg & ~0x00fffffc)
137 warn("unknown bits in register 0x%08x\n", reg);
142 init_rd32(struct nvbios_init *init, u32 reg)
144 reg = init_nvreg(init, reg);
146 return nv_rd32(init->subdev, reg);
151 init_wr32(struct nvbios_init *init, u32 reg, u32 val)
153 reg = init_nvreg(init, reg);
155 nv_wr32(init->subdev, reg, val);
159 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
161 reg = init_nvreg(init, reg);
162 if (init_exec(init)) {
163 u32 tmp = nv_rd32(init->subdev, reg);
164 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
171 init_rdport(struct nvbios_init *init, u16 port)
174 return nv_rdport(init->subdev, init->crtc, port);
179 init_wrport(struct nvbios_init *init, u16 port, u8 value)
182 nv_wrport(init->subdev, init->crtc, port, value);
186 init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
188 struct nouveau_subdev *subdev = init->subdev;
189 if (init_exec(init)) {
190 int head = init->crtc < 0 ? 0 : init->crtc;
191 return nv_rdvgai(subdev, head, port, index);
197 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
199 /* force head 0 for updates to cr44, it only exists on first head */
200 if (nv_device(init->subdev)->card_type < NV_50) {
201 if (port == 0x03d4 && index == 0x44)
205 if (init_exec(init)) {
206 int head = init->crtc < 0 ? 0 : init->crtc;
207 nv_wrvgai(init->subdev, head, port, index, value);
210 /* select head 1 if cr44 write selected it */
211 if (nv_device(init->subdev)->card_type < NV_50) {
212 if (port == 0x03d4 && index == 0x44 && value == 3)
217 static struct nouveau_i2c_port *
218 init_i2c(struct nvbios_init *init, int index)
220 struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
223 index = NV_I2C_DEFAULT(0);
224 if (init->outp && init->outp->i2c_upper_default)
225 index = NV_I2C_DEFAULT(1);
229 error("script needs output for i2c\n");
233 index = init->outp->i2c_index;
236 return i2c->find(i2c, index);
240 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
242 struct nouveau_i2c_port *port = init_i2c(init, index);
243 if (port && init_exec(init))
244 return nv_rdi2cr(port, addr, reg);
249 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
251 struct nouveau_i2c_port *port = init_i2c(init, index);
252 if (port && init_exec(init))
253 return nv_wri2cr(port, addr, reg, val);
258 init_rdauxr(struct nvbios_init *init, u32 addr)
260 struct nouveau_i2c_port *port = init_i2c(init, -1);
263 if (port && init_exec(init)) {
264 int ret = nv_rdaux(port, addr, &data, 1);
274 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
276 struct nouveau_i2c_port *port = init_i2c(init, -1);
277 if (port && init_exec(init))
278 return nv_wraux(port, addr, &data, 1);
283 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
285 struct nouveau_clock *clk = nouveau_clock(init->bios);
286 if (clk && clk->pll_set && init_exec(init)) {
287 int ret = clk->pll_set(clk, id, freq);
289 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
293 /******************************************************************************
294 * parsing of bios structures that are required to execute init tables
295 *****************************************************************************/
298 init_table(struct nouveau_bios *bios, u16 *len)
300 struct bit_entry bit_I;
302 if (!bit_entry(bios, 'I', &bit_I)) {
307 if (bmp_version(bios) >= 0x0510) {
309 return bios->bmp_offset + 75;
316 init_table_(struct nvbios_init *init, u16 offset, const char *name)
318 struct nouveau_bios *bios = init->bios;
319 u16 len, data = init_table(bios, &len);
321 if (len >= offset + 2) {
322 data = nv_ro16(bios, data + offset);
326 warn("%s pointer invalid\n", name);
330 warn("init data too short for %s pointer", name);
334 warn("init data not found\n");
338 #define init_script_table(b) init_table_((b), 0x00, "script table")
339 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
340 #define init_macro_table(b) init_table_((b), 0x04, "macro table")
341 #define init_condition_table(b) init_table_((b), 0x06, "condition table")
342 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
343 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
344 #define init_function_table(b) init_table_((b), 0x0c, "function table")
345 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
348 init_script(struct nouveau_bios *bios, int index)
350 struct nvbios_init init = { .bios = bios };
353 if (bmp_version(bios) && bmp_version(bios) < 0x0510) {
357 data = bios->bmp_offset + (bios->version.major < 2 ? 14 : 18);
358 return nv_ro16(bios, data + (index * 2));
361 data = init_script_table(&init);
363 return nv_ro16(bios, data + (index * 2));
369 init_unknown_script(struct nouveau_bios *bios)
371 u16 len, data = init_table(bios, &len);
372 if (data && len >= 16)
373 return nv_ro16(bios, data + 14);
378 init_ram_restrict_table(struct nvbios_init *init)
380 struct nouveau_bios *bios = init->bios;
381 struct bit_entry bit_M;
384 if (!bit_entry(bios, 'M', &bit_M)) {
385 if (bit_M.version == 1 && bit_M.length >= 5)
386 data = nv_ro16(bios, bit_M.offset + 3);
387 if (bit_M.version == 2 && bit_M.length >= 3)
388 data = nv_ro16(bios, bit_M.offset + 1);
392 warn("ram restrict table not found\n");
397 init_ram_restrict_group_count(struct nvbios_init *init)
399 struct nouveau_bios *bios = init->bios;
400 struct bit_entry bit_M;
402 if (!bit_entry(bios, 'M', &bit_M)) {
403 if (bit_M.version == 1 && bit_M.length >= 5)
404 return nv_ro08(bios, bit_M.offset + 2);
405 if (bit_M.version == 2 && bit_M.length >= 3)
406 return nv_ro08(bios, bit_M.offset + 0);
413 init_ram_restrict(struct nvbios_init *init)
415 u32 strap = (init_rd32(init, 0x101000) & 0x0000003c) >> 2;
416 u16 table = init_ram_restrict_table(init);
418 return nv_ro08(init->bios, table + strap);
423 init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
425 struct nouveau_bios *bios = init->bios;
426 u16 table = init_xlat_table(init);
428 u16 data = nv_ro16(bios, table + (index * 2));
430 return nv_ro08(bios, data + offset);
431 warn("xlat table pointer %d invalid\n", index);
436 /******************************************************************************
437 * utility functions used by various init opcode handlers
438 *****************************************************************************/
441 init_condition_met(struct nvbios_init *init, u8 cond)
443 struct nouveau_bios *bios = init->bios;
444 u16 table = init_condition_table(init);
446 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
447 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
448 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
449 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
450 cond, reg, msk, val);
451 return (init_rd32(init, reg) & msk) == val;
457 init_io_condition_met(struct nvbios_init *init, u8 cond)
459 struct nouveau_bios *bios = init->bios;
460 u16 table = init_io_condition_table(init);
462 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
463 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
464 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
465 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
466 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
467 cond, port, index, mask, value);
468 return (init_rdvgai(init, port, index) & mask) == value;
474 init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
476 struct nouveau_bios *bios = init->bios;
477 u16 table = init_io_flag_condition_table(init);
479 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
480 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
481 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
482 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
483 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
484 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
485 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
486 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
487 return (nv_ro08(bios, data + ioval) & dmask) == value;
493 init_shift(u32 data, u8 shift)
496 return data >> shift;
497 return data << (0x100 - shift);
501 init_tmds_reg(struct nvbios_init *init, u8 tmds)
503 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
504 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
505 * CR58 for CR57 = 0 to index a table of offsets to the basic
507 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
508 * CR58 for CR57 = 0 to index a table of offsets to the basic
509 * 0x6808b0 address, and then flip the offset by 8.
512 const int pramdac_offset[13] = {
513 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
514 const u32 pramdac_table[4] = {
515 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
519 u32 dacoffset = pramdac_offset[init->outp->or];
522 return 0x6808b0 + dacoffset;
525 error("tmds opcodes need dcb\n");
527 if (tmds < ARRAY_SIZE(pramdac_table))
528 return pramdac_table[tmds];
530 error("tmds selector 0x%02x unknown\n", tmds);
536 /******************************************************************************
537 * init opcode handlers
538 *****************************************************************************/
541 * init_reserved - stub for various unknown/unused single-byte opcodes
545 init_reserved(struct nvbios_init *init)
547 u8 opcode = nv_ro08(init->bios, init->offset);
548 trace("RESERVED\t0x%02x\n", opcode);
553 * INIT_DONE - opcode 0x71
557 init_done(struct nvbios_init *init)
560 init->offset = 0x0000;
564 * INIT_IO_RESTRICT_PROG - opcode 0x32
568 init_io_restrict_prog(struct nvbios_init *init)
570 struct nouveau_bios *bios = init->bios;
571 u16 port = nv_ro16(bios, init->offset + 1);
572 u8 index = nv_ro08(bios, init->offset + 3);
573 u8 mask = nv_ro08(bios, init->offset + 4);
574 u8 shift = nv_ro08(bios, init->offset + 5);
575 u8 count = nv_ro08(bios, init->offset + 6);
576 u32 reg = nv_ro32(bios, init->offset + 7);
579 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
580 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
581 reg, port, index, mask, shift);
584 conf = (init_rdvgai(init, port, index) & mask) >> shift;
585 for (i = 0; i < count; i++) {
586 u32 data = nv_ro32(bios, init->offset);
589 trace("\t0x%08x *\n", data);
590 init_wr32(init, reg, data);
592 trace("\t0x%08x\n", data);
601 * INIT_REPEAT - opcode 0x33
605 init_repeat(struct nvbios_init *init)
607 struct nouveau_bios *bios = init->bios;
608 u8 count = nv_ro08(bios, init->offset + 1);
609 u16 repeat = init->repeat;
611 trace("REPEAT\t0x%02x\n", count);
614 init->repeat = init->offset;
615 init->repend = init->offset;
617 init->offset = init->repeat;
620 trace("REPEAT\t0x%02x\n", count);
622 init->offset = init->repend;
623 init->repeat = repeat;
627 * INIT_IO_RESTRICT_PLL - opcode 0x34
631 init_io_restrict_pll(struct nvbios_init *init)
633 struct nouveau_bios *bios = init->bios;
634 u16 port = nv_ro16(bios, init->offset + 1);
635 u8 index = nv_ro08(bios, init->offset + 3);
636 u8 mask = nv_ro08(bios, init->offset + 4);
637 u8 shift = nv_ro08(bios, init->offset + 5);
638 s8 iofc = nv_ro08(bios, init->offset + 6);
639 u8 count = nv_ro08(bios, init->offset + 7);
640 u32 reg = nv_ro32(bios, init->offset + 8);
643 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
644 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
645 reg, port, index, mask, shift, iofc);
648 conf = (init_rdvgai(init, port, index) & mask) >> shift;
649 for (i = 0; i < count; i++) {
650 u32 freq = nv_ro16(bios, init->offset) * 10;
653 trace("\t%dkHz *\n", freq);
654 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
656 init_prog_pll(init, reg, freq);
658 trace("\t%dkHz\n", freq);
667 * INIT_END_REPEAT - opcode 0x36
671 init_end_repeat(struct nvbios_init *init)
673 trace("END_REPEAT\n");
677 init->repend = init->offset;
683 * INIT_COPY - opcode 0x37
687 init_copy(struct nvbios_init *init)
689 struct nouveau_bios *bios = init->bios;
690 u32 reg = nv_ro32(bios, init->offset + 1);
691 u8 shift = nv_ro08(bios, init->offset + 5);
692 u8 smask = nv_ro08(bios, init->offset + 6);
693 u16 port = nv_ro16(bios, init->offset + 7);
694 u8 index = nv_ro08(bios, init->offset + 9);
695 u8 mask = nv_ro08(bios, init->offset + 10);
698 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
699 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
700 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
701 (shift & 0x80) ? (0x100 - shift) : shift, smask);
704 data = init_rdvgai(init, port, index) & mask;
705 data |= init_shift(init_rd32(init, reg), shift) & smask;
706 init_wrvgai(init, port, index, data);
710 * INIT_NOT - opcode 0x38
714 init_not(struct nvbios_init *init)
722 * INIT_IO_FLAG_CONDITION - opcode 0x39
726 init_io_flag_condition(struct nvbios_init *init)
728 struct nouveau_bios *bios = init->bios;
729 u8 cond = nv_ro08(bios, init->offset + 1);
731 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
734 if (!init_io_flag_condition_met(init, cond))
735 init_exec_set(init, false);
739 * INIT_DP_CONDITION - opcode 0x3a
743 init_dp_condition(struct nvbios_init *init)
745 struct nouveau_bios *bios = init->bios;
746 struct nvbios_dpout info;
747 u8 cond = nv_ro08(bios, init->offset + 1);
748 u8 unkn = nv_ro08(bios, init->offset + 2);
749 u8 ver, hdr, cnt, len;
752 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
757 if (init_conn(init) != DCB_CONNECTOR_eDP)
758 init_exec_set(init, false);
763 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
764 (init->outp->or << 0) |
765 (init->outp->sorconf.link << 6),
766 &ver, &hdr, &cnt, &len, &info)))
768 if (!(info.flags & cond))
769 init_exec_set(init, false);
773 warn("script needs dp output table data\n");
776 if (!(init_rdauxr(init, 0x0d) & 1))
777 init_exec_set(init, false);
780 warn("unknown dp condition 0x%02x\n", cond);
786 * INIT_IO_MASK_OR - opcode 0x3b
790 init_io_mask_or(struct nvbios_init *init)
792 struct nouveau_bios *bios = init->bios;
793 u8 index = nv_ro08(bios, init->offset + 1);
794 u8 or = init_or(init);
797 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)", index, or);
800 data = init_rdvgai(init, 0x03d4, index);
801 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
805 * INIT_IO_OR - opcode 0x3c
809 init_io_or(struct nvbios_init *init)
811 struct nouveau_bios *bios = init->bios;
812 u8 index = nv_ro08(bios, init->offset + 1);
813 u8 or = init_or(init);
816 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)", index, or);
819 data = init_rdvgai(init, 0x03d4, index);
820 init_wrvgai(init, 0x03d4, index, data | (1 << or));
824 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
828 init_idx_addr_latched(struct nvbios_init *init)
830 struct nouveau_bios *bios = init->bios;
831 u32 creg = nv_ro32(bios, init->offset + 1);
832 u32 dreg = nv_ro32(bios, init->offset + 5);
833 u32 mask = nv_ro32(bios, init->offset + 9);
834 u32 data = nv_ro32(bios, init->offset + 13);
835 u8 count = nv_ro08(bios, init->offset + 17);
837 trace("INDEX_ADDRESS_LATCHED\t"
838 "R[0x%06x] : R[0x%06x]\n\tCTRL &= 0x%08x |= 0x%08x\n",
839 creg, dreg, mask, data);
843 u8 iaddr = nv_ro08(bios, init->offset + 0);
844 u8 idata = nv_ro08(bios, init->offset + 1);
846 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
849 init_wr32(init, dreg, idata);
850 init_mask(init, creg, ~mask, data | idata);
855 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
859 init_io_restrict_pll2(struct nvbios_init *init)
861 struct nouveau_bios *bios = init->bios;
862 u16 port = nv_ro16(bios, init->offset + 1);
863 u8 index = nv_ro08(bios, init->offset + 3);
864 u8 mask = nv_ro08(bios, init->offset + 4);
865 u8 shift = nv_ro08(bios, init->offset + 5);
866 u8 count = nv_ro08(bios, init->offset + 6);
867 u32 reg = nv_ro32(bios, init->offset + 7);
870 trace("IO_RESTRICT_PLL2\t"
871 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
872 reg, port, index, mask, shift);
875 conf = (init_rdvgai(init, port, index) & mask) >> shift;
876 for (i = 0; i < count; i++) {
877 u32 freq = nv_ro32(bios, init->offset);
879 trace("\t%dkHz *\n", freq);
880 init_prog_pll(init, reg, freq);
882 trace("\t%dkHz\n", freq);
890 * INIT_PLL2 - opcode 0x4b
894 init_pll2(struct nvbios_init *init)
896 struct nouveau_bios *bios = init->bios;
897 u32 reg = nv_ro32(bios, init->offset + 1);
898 u32 freq = nv_ro32(bios, init->offset + 5);
900 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
903 init_prog_pll(init, reg, freq);
907 * INIT_I2C_BYTE - opcode 0x4c
911 init_i2c_byte(struct nvbios_init *init)
913 struct nouveau_bios *bios = init->bios;
914 u8 index = nv_ro08(bios, init->offset + 1);
915 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
916 u8 count = nv_ro08(bios, init->offset + 3);
918 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
922 u8 reg = nv_ro08(bios, init->offset + 0);
923 u8 mask = nv_ro08(bios, init->offset + 1);
924 u8 data = nv_ro08(bios, init->offset + 2);
927 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
930 val = init_rdi2cr(init, index, addr, reg);
933 init_wri2cr(init, index, addr, reg, (val & mask) | data);
938 * INIT_ZM_I2C_BYTE - opcode 0x4d
942 init_zm_i2c_byte(struct nvbios_init *init)
944 struct nouveau_bios *bios = init->bios;
945 u8 index = nv_ro08(bios, init->offset + 1);
946 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
947 u8 count = nv_ro08(bios, init->offset + 3);
949 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
953 u8 reg = nv_ro08(bios, init->offset + 0);
954 u8 data = nv_ro08(bios, init->offset + 1);
956 trace("\t[0x%02x] = 0x%02x\n", reg, data);
959 init_wri2cr(init, index, addr, reg, data);
965 * INIT_ZM_I2C - opcode 0x4e
969 init_zm_i2c(struct nvbios_init *init)
971 struct nouveau_bios *bios = init->bios;
972 u8 index = nv_ro08(bios, init->offset + 1);
973 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
974 u8 count = nv_ro08(bios, init->offset + 3);
977 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
980 for (i = 0; i < count; i++) {
981 data[i] = nv_ro08(bios, init->offset);
982 trace("\t0x%02x\n", data[i]);
986 if (init_exec(init)) {
987 struct nouveau_i2c_port *port = init_i2c(init, index);
988 struct i2c_msg msg = {
989 .addr = addr, .flags = 0, .len = count, .buf = data,
993 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
994 warn("i2c wr failed, %d\n", ret);
999 * INIT_TMDS - opcode 0x4f
1003 init_tmds(struct nvbios_init *init)
1005 struct nouveau_bios *bios = init->bios;
1006 u8 tmds = nv_ro08(bios, init->offset + 1);
1007 u8 addr = nv_ro08(bios, init->offset + 2);
1008 u8 mask = nv_ro08(bios, init->offset + 3);
1009 u8 data = nv_ro08(bios, init->offset + 4);
1010 u32 reg = init_tmds_reg(init, tmds);
1012 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1013 tmds, addr, mask, data);
1019 init_wr32(init, reg + 0, addr | 0x00010000);
1020 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1021 init_wr32(init, reg + 0, addr);
1025 * INIT_ZM_TMDS_GROUP - opcode 0x50
1029 init_zm_tmds_group(struct nvbios_init *init)
1031 struct nouveau_bios *bios = init->bios;
1032 u8 tmds = nv_ro08(bios, init->offset + 1);
1033 u8 count = nv_ro08(bios, init->offset + 2);
1034 u32 reg = init_tmds_reg(init, tmds);
1036 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1040 u8 addr = nv_ro08(bios, init->offset + 0);
1041 u8 data = nv_ro08(bios, init->offset + 1);
1043 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1046 init_wr32(init, reg + 4, data);
1047 init_wr32(init, reg + 0, addr);
1052 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1056 init_cr_idx_adr_latch(struct nvbios_init *init)
1058 struct nouveau_bios *bios = init->bios;
1059 u8 addr0 = nv_ro08(bios, init->offset + 1);
1060 u8 addr1 = nv_ro08(bios, init->offset + 2);
1061 u8 base = nv_ro08(bios, init->offset + 3);
1062 u8 count = nv_ro08(bios, init->offset + 4);
1065 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1068 save0 = init_rdvgai(init, 0x03d4, addr0);
1070 u8 data = nv_ro08(bios, init->offset);
1072 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1075 init_wrvgai(init, 0x03d4, addr0, base++);
1076 init_wrvgai(init, 0x03d4, addr1, data);
1078 init_wrvgai(init, 0x03d4, addr0, save0);
1082 * INIT_CR - opcode 0x52
1086 init_cr(struct nvbios_init *init)
1088 struct nouveau_bios *bios = init->bios;
1089 u8 addr = nv_ro08(bios, init->offset + 1);
1090 u8 mask = nv_ro08(bios, init->offset + 2);
1091 u8 data = nv_ro08(bios, init->offset + 3);
1094 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1097 val = init_rdvgai(init, 0x03d4, addr) & mask;
1098 init_wrvgai(init, 0x03d4, addr, val | data);
1102 * INIT_ZM_CR - opcode 0x53
1106 init_zm_cr(struct nvbios_init *init)
1108 struct nouveau_bios *bios = init->bios;
1109 u8 addr = nv_ro08(bios, init->offset + 1);
1110 u8 data = nv_ro08(bios, init->offset + 2);
1112 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1115 init_wrvgai(init, 0x03d4, addr, data);
1119 * INIT_ZM_CR_GROUP - opcode 0x54
1123 init_zm_cr_group(struct nvbios_init *init)
1125 struct nouveau_bios *bios = init->bios;
1126 u8 count = nv_ro08(bios, init->offset + 1);
1128 trace("ZM_CR_GROUP\n");
1132 u8 addr = nv_ro08(bios, init->offset + 0);
1133 u8 data = nv_ro08(bios, init->offset + 1);
1135 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1138 init_wrvgai(init, 0x03d4, addr, data);
1143 * INIT_CONDITION_TIME - opcode 0x56
1147 init_condition_time(struct nvbios_init *init)
1149 struct nouveau_bios *bios = init->bios;
1150 u8 cond = nv_ro08(bios, init->offset + 1);
1151 u8 retry = nv_ro08(bios, init->offset + 2);
1152 u8 wait = min((u16)retry * 50, 100);
1154 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1157 if (!init_exec(init))
1161 if (init_condition_met(init, cond))
1166 init_exec_set(init, false);
1170 * INIT_LTIME - opcode 0x57
1174 init_ltime(struct nvbios_init *init)
1176 struct nouveau_bios *bios = init->bios;
1177 u16 msec = nv_ro16(bios, init->offset + 1);
1179 trace("LTIME\t0x%04x\n", msec);
1182 if (init_exec(init))
1187 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1191 init_zm_reg_sequence(struct nvbios_init *init)
1193 struct nouveau_bios *bios = init->bios;
1194 u32 base = nv_ro32(bios, init->offset + 1);
1195 u8 count = nv_ro08(bios, init->offset + 5);
1197 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1201 u32 data = nv_ro32(bios, init->offset);
1203 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1206 init_wr32(init, base, data);
1212 * INIT_SUB_DIRECT - opcode 0x5b
1216 init_sub_direct(struct nvbios_init *init)
1218 struct nouveau_bios *bios = init->bios;
1219 u16 addr = nv_ro16(bios, init->offset + 1);
1222 trace("SUB_DIRECT\t0x%04x\n", addr);
1224 if (init_exec(init)) {
1225 save = init->offset;
1226 init->offset = addr;
1227 if (nvbios_exec(init)) {
1228 error("error parsing sub-table\n");
1231 init->offset = save;
1238 * INIT_JUMP - opcode 0x5c
1242 init_jump(struct nvbios_init *init)
1244 struct nouveau_bios *bios = init->bios;
1245 u16 offset = nv_ro16(bios, init->offset + 1);
1247 trace("JUMP\t0x%04x\n", offset);
1248 init->offset = offset;
1252 * INIT_I2C_IF - opcode 0x5e
1256 init_i2c_if(struct nvbios_init *init)
1258 struct nouveau_bios *bios = init->bios;
1259 u8 index = nv_ro08(bios, init->offset + 1);
1260 u8 addr = nv_ro08(bios, init->offset + 2);
1261 u8 reg = nv_ro08(bios, init->offset + 3);
1262 u8 mask = nv_ro08(bios, init->offset + 4);
1263 u8 data = nv_ro08(bios, init->offset + 5);
1266 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1267 index, addr, reg, mask, data);
1269 init_exec_force(init, true);
1271 value = init_rdi2cr(init, index, addr, reg);
1272 if ((value & mask) != data)
1273 init_exec_set(init, false);
1275 init_exec_force(init, false);
1279 * INIT_COPY_NV_REG - opcode 0x5f
1283 init_copy_nv_reg(struct nvbios_init *init)
1285 struct nouveau_bios *bios = init->bios;
1286 u32 sreg = nv_ro32(bios, init->offset + 1);
1287 u8 shift = nv_ro08(bios, init->offset + 5);
1288 u32 smask = nv_ro32(bios, init->offset + 6);
1289 u32 sxor = nv_ro32(bios, init->offset + 10);
1290 u32 dreg = nv_ro32(bios, init->offset + 14);
1291 u32 dmask = nv_ro32(bios, init->offset + 18);
1294 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1295 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1296 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1297 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1300 data = init_shift(init_rd32(init, sreg), shift);
1301 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1305 * INIT_ZM_INDEX_IO - opcode 0x62
1309 init_zm_index_io(struct nvbios_init *init)
1311 struct nouveau_bios *bios = init->bios;
1312 u16 port = nv_ro16(bios, init->offset + 1);
1313 u8 index = nv_ro08(bios, init->offset + 3);
1314 u8 data = nv_ro08(bios, init->offset + 4);
1316 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1319 init_wrvgai(init, port, index, data);
1323 * INIT_COMPUTE_MEM - opcode 0x63
1327 init_compute_mem(struct nvbios_init *init)
1329 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
1331 trace("COMPUTE_MEM\n");
1334 init_exec_force(init, true);
1335 if (init_exec(init) && devinit->meminit)
1336 devinit->meminit(devinit);
1337 init_exec_force(init, false);
1341 * INIT_RESET - opcode 0x65
1345 init_reset(struct nvbios_init *init)
1347 struct nouveau_bios *bios = init->bios;
1348 u32 reg = nv_ro32(bios, init->offset + 1);
1349 u32 data1 = nv_ro32(bios, init->offset + 5);
1350 u32 data2 = nv_ro32(bios, init->offset + 9);
1353 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1355 init_exec_force(init, true);
1357 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1358 init_wr32(init, reg, data1);
1360 init_wr32(init, reg, data2);
1361 init_wr32(init, 0x00184c, savepci19);
1362 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1364 init_exec_force(init, false);
1368 * INIT_CONFIGURE_MEM - opcode 0x66
1372 init_configure_mem_clk(struct nvbios_init *init)
1374 u16 mdata = bmp_mem_init_table(init->bios);
1376 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1381 init_configure_mem(struct nvbios_init *init)
1383 struct nouveau_bios *bios = init->bios;
1387 trace("CONFIGURE_MEM\n");
1390 if (bios->version.major > 2) {
1394 init_exec_force(init, true);
1396 mdata = init_configure_mem_clk(init);
1397 sdata = bmp_sdr_seq_table(bios);
1398 if (nv_ro08(bios, mdata) & 0x01)
1399 sdata = bmp_ddr_seq_table(bios);
1400 mdata += 6; /* skip to data */
1402 data = init_rdvgai(init, 0x03c4, 0x01);
1403 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1405 while ((addr = nv_ro32(bios, sdata)) != 0xffffffff) {
1407 case 0x10021c: /* CKE_NORMAL */
1408 case 0x1002d0: /* CMD_REFRESH */
1409 case 0x1002d4: /* CMD_PRECHARGE */
1413 data = nv_ro32(bios, mdata);
1415 if (data == 0xffffffff)
1420 init_wr32(init, addr, data);
1423 init_exec_force(init, false);
1427 * INIT_CONFIGURE_CLK - opcode 0x67
1431 init_configure_clk(struct nvbios_init *init)
1433 struct nouveau_bios *bios = init->bios;
1436 trace("CONFIGURE_CLK\n");
1439 if (bios->version.major > 2) {
1443 init_exec_force(init, true);
1445 mdata = init_configure_mem_clk(init);
1448 clock = nv_ro16(bios, mdata + 4) * 10;
1449 init_prog_pll(init, 0x680500, clock);
1452 clock = nv_ro16(bios, mdata + 2) * 10;
1453 if (nv_ro08(bios, mdata) & 0x01)
1455 init_prog_pll(init, 0x680504, clock);
1457 init_exec_force(init, false);
1461 * INIT_CONFIGURE_PREINIT - opcode 0x68
1465 init_configure_preinit(struct nvbios_init *init)
1467 struct nouveau_bios *bios = init->bios;
1470 trace("CONFIGURE_PREINIT\n");
1473 if (bios->version.major > 2) {
1477 init_exec_force(init, true);
1479 strap = init_rd32(init, 0x101000);
1480 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1481 init_wrvgai(init, 0x03d4, 0x3c, strap);
1483 init_exec_force(init, false);
1487 * INIT_IO - opcode 0x69
1491 init_io(struct nvbios_init *init)
1493 struct nouveau_bios *bios = init->bios;
1494 u16 port = nv_ro16(bios, init->offset + 1);
1495 u8 mask = nv_ro16(bios, init->offset + 3);
1496 u8 data = nv_ro16(bios, init->offset + 4);
1499 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1502 /* ummm.. yes.. should really figure out wtf this is and why it's
1503 * needed some day.. it's almost certainly wrong, but, it also
1504 * somehow makes things work...
1506 if (nv_device(init->bios)->card_type >= NV_50 &&
1507 port == 0x03c3 && data == 0x01) {
1508 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1509 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1510 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1511 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1513 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1514 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1515 init_wr32(init, 0x614100, 0x00800018);
1516 init_wr32(init, 0x614900, 0x00800018);
1518 init_wr32(init, 0x614100, 0x10000018);
1519 init_wr32(init, 0x614900, 0x10000018);
1523 value = init_rdport(init, port) & mask;
1524 init_wrport(init, port, data | value);
1528 * INIT_SUB - opcode 0x6b
1532 init_sub(struct nvbios_init *init)
1534 struct nouveau_bios *bios = init->bios;
1535 u8 index = nv_ro08(bios, init->offset + 1);
1538 trace("SUB\t0x%02x\n", index);
1540 addr = init_script(bios, index);
1541 if (addr && init_exec(init)) {
1542 save = init->offset;
1543 init->offset = addr;
1544 if (nvbios_exec(init)) {
1545 error("error parsing sub-table\n");
1548 init->offset = save;
1555 * INIT_RAM_CONDITION - opcode 0x6d
1559 init_ram_condition(struct nvbios_init *init)
1561 struct nouveau_bios *bios = init->bios;
1562 u8 mask = nv_ro08(bios, init->offset + 1);
1563 u8 value = nv_ro08(bios, init->offset + 2);
1565 trace("RAM_CONDITION\t"
1566 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1569 if ((init_rd32(init, 0x100000) & mask) != value)
1570 init_exec_set(init, false);
1574 * INIT_NV_REG - opcode 0x6e
1578 init_nv_reg(struct nvbios_init *init)
1580 struct nouveau_bios *bios = init->bios;
1581 u32 reg = nv_ro32(bios, init->offset + 1);
1582 u32 mask = nv_ro32(bios, init->offset + 5);
1583 u32 data = nv_ro32(bios, init->offset + 9);
1585 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1588 init_mask(init, reg, ~mask, data);
1592 * INIT_MACRO - opcode 0x6f
1596 init_macro(struct nvbios_init *init)
1598 struct nouveau_bios *bios = init->bios;
1599 u8 macro = nv_ro08(bios, init->offset + 1);
1602 trace("MACRO\t0x%02x\n", macro);
1604 table = init_macro_table(init);
1606 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1607 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1608 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1609 init_wr32(init, addr, data);
1616 * INIT_RESUME - opcode 0x72
1620 init_resume(struct nvbios_init *init)
1624 init_exec_set(init, true);
1628 * INIT_TIME - opcode 0x74
1632 init_time(struct nvbios_init *init)
1634 struct nouveau_bios *bios = init->bios;
1635 u16 usec = nv_ro16(bios, init->offset + 1);
1637 trace("TIME\t0x%04x\n", usec);
1640 if (init_exec(init)) {
1644 mdelay((usec + 900) / 1000);
1649 * INIT_CONDITION - opcode 0x75
1653 init_condition(struct nvbios_init *init)
1655 struct nouveau_bios *bios = init->bios;
1656 u8 cond = nv_ro08(bios, init->offset + 1);
1658 trace("CONDITION\t0x%02x\n", cond);
1661 if (!init_condition_met(init, cond))
1662 init_exec_set(init, false);
1666 * INIT_IO_CONDITION - opcode 0x76
1670 init_io_condition(struct nvbios_init *init)
1672 struct nouveau_bios *bios = init->bios;
1673 u8 cond = nv_ro08(bios, init->offset + 1);
1675 trace("IO_CONDITION\t0x%02x\n", cond);
1678 if (!init_io_condition_met(init, cond))
1679 init_exec_set(init, false);
1683 * INIT_INDEX_IO - opcode 0x78
1687 init_index_io(struct nvbios_init *init)
1689 struct nouveau_bios *bios = init->bios;
1690 u16 port = nv_ro16(bios, init->offset + 1);
1691 u8 index = nv_ro16(bios, init->offset + 3);
1692 u8 mask = nv_ro08(bios, init->offset + 4);
1693 u8 data = nv_ro08(bios, init->offset + 5);
1696 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1697 port, index, mask, data);
1700 value = init_rdvgai(init, port, index) & mask;
1701 init_wrvgai(init, port, index, data | value);
1705 * INIT_PLL - opcode 0x79
1709 init_pll(struct nvbios_init *init)
1711 struct nouveau_bios *bios = init->bios;
1712 u32 reg = nv_ro32(bios, init->offset + 1);
1713 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1715 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1718 init_prog_pll(init, reg, freq);
1722 * INIT_ZM_REG - opcode 0x7a
1726 init_zm_reg(struct nvbios_init *init)
1728 struct nouveau_bios *bios = init->bios;
1729 u32 addr = nv_ro32(bios, init->offset + 1);
1730 u32 data = nv_ro32(bios, init->offset + 5);
1732 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1735 if (addr == 0x000200)
1738 init_wr32(init, addr, data);
1742 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1746 init_ram_restrict_pll(struct nvbios_init *init)
1748 struct nouveau_bios *bios = init->bios;
1749 u8 type = nv_ro08(bios, init->offset + 1);
1750 u8 count = init_ram_restrict_group_count(init);
1751 u8 strap = init_ram_restrict(init);
1754 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1757 for (cconf = 0; cconf < count; cconf++) {
1758 u32 freq = nv_ro32(bios, init->offset);
1760 if (cconf == strap) {
1761 trace("%dkHz *\n", freq);
1762 init_prog_pll(init, type, freq);
1764 trace("%dkHz\n", freq);
1772 * INIT_GPIO - opcode 0x8e
1776 init_gpio(struct nvbios_init *init)
1778 struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
1783 if (init_exec(init) && gpio && gpio->reset)
1788 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1792 init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1794 struct nouveau_bios *bios = init->bios;
1795 u32 addr = nv_ro32(bios, init->offset + 1);
1796 u8 incr = nv_ro08(bios, init->offset + 5);
1797 u8 num = nv_ro08(bios, init->offset + 6);
1798 u8 count = init_ram_restrict_group_count(init);
1799 u8 index = init_ram_restrict(init);
1802 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1803 "R[%08x] 0x%02x 0x%02x\n", addr, incr, num);
1806 for (i = 0; i < num; i++) {
1807 trace("\tR[0x%06x] = {\n", addr);
1808 for (j = 0; j < count; j++) {
1809 u32 data = nv_ro32(bios, init->offset);
1812 trace("\t\t0x%08x *\n", data);
1813 init_wr32(init, addr, data);
1815 trace("\t\t0x%08x\n", data);
1826 * INIT_COPY_ZM_REG - opcode 0x90
1830 init_copy_zm_reg(struct nvbios_init *init)
1832 struct nouveau_bios *bios = init->bios;
1833 u32 sreg = nv_ro32(bios, init->offset + 1);
1834 u32 dreg = nv_ro32(bios, init->offset + 5);
1836 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", sreg, dreg);
1839 init_wr32(init, dreg, init_rd32(init, sreg));
1843 * INIT_ZM_REG_GROUP - opcode 0x91
1847 init_zm_reg_group(struct nvbios_init *init)
1849 struct nouveau_bios *bios = init->bios;
1850 u32 addr = nv_ro32(bios, init->offset + 1);
1851 u8 count = nv_ro08(bios, init->offset + 5);
1853 trace("ZM_REG_GROUP\tR[0x%06x] =\n");
1857 u32 data = nv_ro32(bios, init->offset);
1858 trace("\t0x%08x\n", data);
1859 init_wr32(init, addr, data);
1865 * INIT_XLAT - opcode 0x96
1869 init_xlat(struct nvbios_init *init)
1871 struct nouveau_bios *bios = init->bios;
1872 u32 saddr = nv_ro32(bios, init->offset + 1);
1873 u8 sshift = nv_ro08(bios, init->offset + 5);
1874 u8 smask = nv_ro08(bios, init->offset + 6);
1875 u8 index = nv_ro08(bios, init->offset + 7);
1876 u32 daddr = nv_ro32(bios, init->offset + 8);
1877 u32 dmask = nv_ro32(bios, init->offset + 12);
1878 u8 shift = nv_ro08(bios, init->offset + 16);
1881 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1882 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1883 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1884 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1887 data = init_shift(init_rd32(init, saddr), sshift) & smask;
1888 data = init_xlat_(init, index, data) << shift;
1889 init_mask(init, daddr, ~dmask, data);
1893 * INIT_ZM_MASK_ADD - opcode 0x97
1897 init_zm_mask_add(struct nvbios_init *init)
1899 struct nouveau_bios *bios = init->bios;
1900 u32 addr = nv_ro32(bios, init->offset + 1);
1901 u32 mask = nv_ro32(bios, init->offset + 5);
1902 u32 add = nv_ro32(bios, init->offset + 9);
1905 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1908 data = init_rd32(init, addr) & mask;
1909 data |= ((data + add) & ~mask);
1910 init_wr32(init, addr, data);
1914 * INIT_AUXCH - opcode 0x98
1918 init_auxch(struct nvbios_init *init)
1920 struct nouveau_bios *bios = init->bios;
1921 u32 addr = nv_ro32(bios, init->offset + 1);
1922 u8 count = nv_ro08(bios, init->offset + 5);
1924 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1928 u8 mask = nv_ro08(bios, init->offset + 0);
1929 u8 data = nv_ro08(bios, init->offset + 1);
1930 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1931 mask = init_rdauxr(init, addr) & mask;
1932 init_wrauxr(init, addr, mask | data);
1938 * INIT_AUXCH - opcode 0x99
1942 init_zm_auxch(struct nvbios_init *init)
1944 struct nouveau_bios *bios = init->bios;
1945 u32 addr = nv_ro32(bios, init->offset + 1);
1946 u8 count = nv_ro08(bios, init->offset + 5);
1948 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1952 u8 data = nv_ro08(bios, init->offset + 0);
1953 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
1954 init_wrauxr(init, addr, data);
1960 * INIT_I2C_LONG_IF - opcode 0x9a
1964 init_i2c_long_if(struct nvbios_init *init)
1966 struct nouveau_bios *bios = init->bios;
1967 u8 index = nv_ro08(bios, init->offset + 1);
1968 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1969 u8 reglo = nv_ro08(bios, init->offset + 3);
1970 u8 reghi = nv_ro08(bios, init->offset + 4);
1971 u8 mask = nv_ro08(bios, init->offset + 5);
1972 u8 data = nv_ro08(bios, init->offset + 6);
1973 struct nouveau_i2c_port *port;
1975 trace("I2C_LONG_IF\t"
1976 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
1977 index, addr, reglo, reghi, mask, data);
1980 port = init_i2c(init, index);
1982 u8 i[2] = { reghi, reglo };
1984 struct i2c_msg msg[] = {
1985 { .addr = addr, .flags = 0, .len = 2, .buf = i },
1986 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
1990 ret = i2c_transfer(&port->adapter, msg, 2);
1991 if (ret == 2 && ((o[0] & mask) == data))
1995 init_exec_set(init, false);
1998 static struct nvbios_init_opcode {
1999 void (*exec)(struct nvbios_init *);
2001 [0x32] = { init_io_restrict_prog },
2002 [0x33] = { init_repeat },
2003 [0x34] = { init_io_restrict_pll },
2004 [0x36] = { init_end_repeat },
2005 [0x37] = { init_copy },
2006 [0x38] = { init_not },
2007 [0x39] = { init_io_flag_condition },
2008 [0x3a] = { init_dp_condition },
2009 [0x3b] = { init_io_mask_or },
2010 [0x3c] = { init_io_or },
2011 [0x49] = { init_idx_addr_latched },
2012 [0x4a] = { init_io_restrict_pll2 },
2013 [0x4b] = { init_pll2 },
2014 [0x4c] = { init_i2c_byte },
2015 [0x4d] = { init_zm_i2c_byte },
2016 [0x4e] = { init_zm_i2c },
2017 [0x4f] = { init_tmds },
2018 [0x50] = { init_zm_tmds_group },
2019 [0x51] = { init_cr_idx_adr_latch },
2020 [0x52] = { init_cr },
2021 [0x53] = { init_zm_cr },
2022 [0x54] = { init_zm_cr_group },
2023 [0x56] = { init_condition_time },
2024 [0x57] = { init_ltime },
2025 [0x58] = { init_zm_reg_sequence },
2026 [0x5b] = { init_sub_direct },
2027 [0x5c] = { init_jump },
2028 [0x5e] = { init_i2c_if },
2029 [0x5f] = { init_copy_nv_reg },
2030 [0x62] = { init_zm_index_io },
2031 [0x63] = { init_compute_mem },
2032 [0x65] = { init_reset },
2033 [0x66] = { init_configure_mem },
2034 [0x67] = { init_configure_clk },
2035 [0x68] = { init_configure_preinit },
2036 [0x69] = { init_io },
2037 [0x6b] = { init_sub },
2038 [0x6d] = { init_ram_condition },
2039 [0x6e] = { init_nv_reg },
2040 [0x6f] = { init_macro },
2041 [0x71] = { init_done },
2042 [0x72] = { init_resume },
2043 [0x74] = { init_time },
2044 [0x75] = { init_condition },
2045 [0x76] = { init_io_condition },
2046 [0x78] = { init_index_io },
2047 [0x79] = { init_pll },
2048 [0x7a] = { init_zm_reg },
2049 [0x87] = { init_ram_restrict_pll },
2050 [0x8c] = { init_reserved },
2051 [0x8d] = { init_reserved },
2052 [0x8e] = { init_gpio },
2053 [0x8f] = { init_ram_restrict_zm_reg_group },
2054 [0x90] = { init_copy_zm_reg },
2055 [0x91] = { init_zm_reg_group },
2056 [0x92] = { init_reserved },
2057 [0x96] = { init_xlat },
2058 [0x97] = { init_zm_mask_add },
2059 [0x98] = { init_auxch },
2060 [0x99] = { init_zm_auxch },
2061 [0x9a] = { init_i2c_long_if },
2064 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2067 nvbios_exec(struct nvbios_init *init)
2070 while (init->offset) {
2071 u8 opcode = nv_ro08(init->bios, init->offset);
2072 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2073 error("unknown opcode 0x%02x\n", opcode);
2077 init_opcode[opcode].exec(init);
2084 nvbios_init(struct nouveau_subdev *subdev, bool execute)
2086 struct nouveau_bios *bios = nouveau_bios(subdev);
2092 nv_info(bios, "running init tables\n");
2093 while (!ret && (data = (init_script(bios, ++i)))) {
2094 struct nvbios_init init = {
2100 .execute = execute ? 1 : 0,
2103 ret = nvbios_exec(&init);
2106 /* the vbios parser will run this right after the normal init
2107 * tables, whereas the binary driver appears to run it later.
2109 if (!ret && (data = init_unknown_script(bios))) {
2110 struct nvbios_init init = {
2116 .execute = execute ? 1 : 0,
2119 ret = nvbios_exec(&init);