1 #include <core/engine.h>
2 #include <core/device.h>
4 #include <subdev/bios.h>
5 #include <subdev/bios/bmp.h>
6 #include <subdev/bios/bit.h>
7 #include <subdev/bios/conn.h>
8 #include <subdev/bios/dcb.h>
9 #include <subdev/bios/dp.h>
10 #include <subdev/bios/gpio.h>
11 #include <subdev/bios/init.h>
12 #include <subdev/devinit.h>
13 #include <subdev/clock.h>
14 #include <subdev/i2c.h>
15 #include <subdev/vga.h>
16 #include <subdev/gpio.h>
18 #define bioslog(lvl, fmt, args...) do { \
19 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
20 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
22 #define cont(fmt, args...) do { \
23 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
24 printk(fmt, ##args); \
26 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
27 #define warn(fmt, args...) bioslog(WARN, fmt, ##args)
28 #define error(fmt, args...) bioslog(ERROR, fmt, ##args)
30 /******************************************************************************
31 * init parser control flow helpers
32 *****************************************************************************/
35 init_exec(struct nvbios_init *init)
37 return (init->execute == 1) || ((init->execute & 5) == 5);
41 init_exec_set(struct nvbios_init *init, bool exec)
43 if (exec) init->execute &= 0xfd;
44 else init->execute |= 0x02;
48 init_exec_inv(struct nvbios_init *init)
50 init->execute ^= 0x02;
54 init_exec_force(struct nvbios_init *init, bool exec)
56 if (exec) init->execute |= 0x04;
57 else init->execute &= 0xfb;
60 /******************************************************************************
61 * init parser wrappers for normal register/i2c/whatever accessors
62 *****************************************************************************/
65 init_or(struct nvbios_init *init)
68 return ffs(init->outp->or) - 1;
69 error("script needs OR!!\n");
74 init_link(struct nvbios_init *init)
77 return !(init->outp->sorconf.link & 1);
78 error("script needs OR link\n");
83 init_crtc(struct nvbios_init *init)
87 error("script needs crtc\n");
92 init_conn(struct nvbios_init *init)
94 struct nouveau_bios *bios = init->bios;
98 u16 conn = dcb_conn(bios, init->outp->connector, &ver, &len);
100 return nv_ro08(bios, conn);
103 error("script needs connector type\n");
108 init_nvreg(struct nvbios_init *init, u32 reg)
110 /* C51 (at least) sometimes has the lower bits set which the VBIOS
111 * interprets to mean that access needs to go through certain IO
112 * ports instead. The NVIDIA binary driver has been seen to access
113 * these through the NV register address, so lets assume we can
118 /* GF8+ display scripts need register addresses mangled a bit to
119 * select a specific CRTC/OR
121 if (nv_device(init->bios)->card_type >= NV_50) {
122 if (reg & 0x80000000) {
123 reg += init_crtc(init) * 0x800;
127 if (reg & 0x40000000) {
128 reg += init_or(init) * 0x800;
130 if (reg & 0x20000000) {
131 reg += init_link(init) * 0x80;
137 if (reg & ~0x00fffffc)
138 warn("unknown bits in register 0x%08x\n", reg);
143 init_rd32(struct nvbios_init *init, u32 reg)
145 reg = init_nvreg(init, reg);
147 return nv_rd32(init->subdev, reg);
152 init_wr32(struct nvbios_init *init, u32 reg, u32 val)
154 reg = init_nvreg(init, reg);
156 nv_wr32(init->subdev, reg, val);
160 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
162 reg = init_nvreg(init, reg);
163 if (init_exec(init)) {
164 u32 tmp = nv_rd32(init->subdev, reg);
165 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
172 init_rdport(struct nvbios_init *init, u16 port)
175 return nv_rdport(init->subdev, init->crtc, port);
180 init_wrport(struct nvbios_init *init, u16 port, u8 value)
183 nv_wrport(init->subdev, init->crtc, port, value);
187 init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
189 struct nouveau_subdev *subdev = init->subdev;
190 if (init_exec(init)) {
191 int head = init->crtc < 0 ? 0 : init->crtc;
192 return nv_rdvgai(subdev, head, port, index);
198 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
200 /* force head 0 for updates to cr44, it only exists on first head */
201 if (nv_device(init->subdev)->card_type < NV_50) {
202 if (port == 0x03d4 && index == 0x44)
206 if (init_exec(init)) {
207 int head = init->crtc < 0 ? 0 : init->crtc;
208 nv_wrvgai(init->subdev, head, port, index, value);
211 /* select head 1 if cr44 write selected it */
212 if (nv_device(init->subdev)->card_type < NV_50) {
213 if (port == 0x03d4 && index == 0x44 && value == 3)
218 static struct nouveau_i2c_port *
219 init_i2c(struct nvbios_init *init, int index)
221 struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
224 index = NV_I2C_DEFAULT(0);
225 if (init->outp && init->outp->i2c_upper_default)
226 index = NV_I2C_DEFAULT(1);
230 error("script needs output for i2c\n");
234 index = init->outp->i2c_index;
237 return i2c->find(i2c, index);
241 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
243 struct nouveau_i2c_port *port = init_i2c(init, index);
244 if (port && init_exec(init))
245 return nv_rdi2cr(port, addr, reg);
250 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
252 struct nouveau_i2c_port *port = init_i2c(init, index);
253 if (port && init_exec(init))
254 return nv_wri2cr(port, addr, reg, val);
259 init_rdauxr(struct nvbios_init *init, u32 addr)
261 struct nouveau_i2c_port *port = init_i2c(init, -1);
264 if (port && init_exec(init)) {
265 int ret = nv_rdaux(port, addr, &data, 1);
275 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
277 struct nouveau_i2c_port *port = init_i2c(init, -1);
278 if (port && init_exec(init))
279 return nv_wraux(port, addr, &data, 1);
284 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
286 struct nouveau_clock *clk = nouveau_clock(init->bios);
287 if (clk && clk->pll_set && init_exec(init)) {
288 int ret = clk->pll_set(clk, id, freq);
290 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
294 /******************************************************************************
295 * parsing of bios structures that are required to execute init tables
296 *****************************************************************************/
299 init_table(struct nouveau_bios *bios, u16 *len)
301 struct bit_entry bit_I;
303 if (!bit_entry(bios, 'I', &bit_I)) {
308 if (bmp_version(bios) >= 0x0510) {
310 return bios->bmp_offset + 75;
317 init_table_(struct nvbios_init *init, u16 offset, const char *name)
319 struct nouveau_bios *bios = init->bios;
320 u16 len, data = init_table(bios, &len);
322 if (len >= offset + 2) {
323 data = nv_ro16(bios, data + offset);
327 warn("%s pointer invalid\n", name);
331 warn("init data too short for %s pointer", name);
335 warn("init data not found\n");
339 #define init_script_table(b) init_table_((b), 0x00, "script table")
340 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
341 #define init_macro_table(b) init_table_((b), 0x04, "macro table")
342 #define init_condition_table(b) init_table_((b), 0x06, "condition table")
343 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
344 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
345 #define init_function_table(b) init_table_((b), 0x0c, "function table")
346 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
349 init_script(struct nouveau_bios *bios, int index)
351 struct nvbios_init init = { .bios = bios };
354 if (bmp_version(bios) && bmp_version(bios) < 0x0510) {
358 data = bios->bmp_offset + (bios->version.major < 2 ? 14 : 18);
359 return nv_ro16(bios, data + (index * 2));
362 data = init_script_table(&init);
364 return nv_ro16(bios, data + (index * 2));
370 init_unknown_script(struct nouveau_bios *bios)
372 u16 len, data = init_table(bios, &len);
373 if (data && len >= 16)
374 return nv_ro16(bios, data + 14);
379 init_ram_restrict_table(struct nvbios_init *init)
381 struct nouveau_bios *bios = init->bios;
382 struct bit_entry bit_M;
385 if (!bit_entry(bios, 'M', &bit_M)) {
386 if (bit_M.version == 1 && bit_M.length >= 5)
387 data = nv_ro16(bios, bit_M.offset + 3);
388 if (bit_M.version == 2 && bit_M.length >= 3)
389 data = nv_ro16(bios, bit_M.offset + 1);
393 warn("ram restrict table not found\n");
398 init_ram_restrict_group_count(struct nvbios_init *init)
400 struct nouveau_bios *bios = init->bios;
401 struct bit_entry bit_M;
403 if (!bit_entry(bios, 'M', &bit_M)) {
404 if (bit_M.version == 1 && bit_M.length >= 5)
405 return nv_ro08(bios, bit_M.offset + 2);
406 if (bit_M.version == 2 && bit_M.length >= 3)
407 return nv_ro08(bios, bit_M.offset + 0);
414 init_ram_restrict_strap(struct nvbios_init *init)
416 /* This appears to be the behaviour of the VBIOS parser, and *is*
417 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
418 * avoid fucking up the memory controller (somehow) by reading it
419 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
421 * Preserving the non-caching behaviour on earlier chipsets just
422 * in case *not* re-reading the strap causes similar breakage.
424 if (!init->ramcfg || init->bios->version.major < 0x70)
425 init->ramcfg = init_rd32(init, 0x101000);
426 return (init->ramcfg & 0x00000003c) >> 2;
430 init_ram_restrict(struct nvbios_init *init)
432 u8 strap = init_ram_restrict_strap(init);
433 u16 table = init_ram_restrict_table(init);
435 return nv_ro08(init->bios, table + strap);
440 init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
442 struct nouveau_bios *bios = init->bios;
443 u16 table = init_xlat_table(init);
445 u16 data = nv_ro16(bios, table + (index * 2));
447 return nv_ro08(bios, data + offset);
448 warn("xlat table pointer %d invalid\n", index);
453 /******************************************************************************
454 * utility functions used by various init opcode handlers
455 *****************************************************************************/
458 init_condition_met(struct nvbios_init *init, u8 cond)
460 struct nouveau_bios *bios = init->bios;
461 u16 table = init_condition_table(init);
463 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
464 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
465 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
466 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
467 cond, reg, msk, val);
468 return (init_rd32(init, reg) & msk) == val;
474 init_io_condition_met(struct nvbios_init *init, u8 cond)
476 struct nouveau_bios *bios = init->bios;
477 u16 table = init_io_condition_table(init);
479 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
480 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
481 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
482 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
483 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
484 cond, port, index, mask, value);
485 return (init_rdvgai(init, port, index) & mask) == value;
491 init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
493 struct nouveau_bios *bios = init->bios;
494 u16 table = init_io_flag_condition_table(init);
496 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
497 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
498 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
499 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
500 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
501 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
502 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
503 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
504 return (nv_ro08(bios, data + ioval) & dmask) == value;
510 init_shift(u32 data, u8 shift)
513 return data >> shift;
514 return data << (0x100 - shift);
518 init_tmds_reg(struct nvbios_init *init, u8 tmds)
520 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
521 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
522 * CR58 for CR57 = 0 to index a table of offsets to the basic
524 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
525 * CR58 for CR57 = 0 to index a table of offsets to the basic
526 * 0x6808b0 address, and then flip the offset by 8.
529 const int pramdac_offset[13] = {
530 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
531 const u32 pramdac_table[4] = {
532 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
536 u32 dacoffset = pramdac_offset[init->outp->or];
539 return 0x6808b0 + dacoffset;
542 error("tmds opcodes need dcb\n");
544 if (tmds < ARRAY_SIZE(pramdac_table))
545 return pramdac_table[tmds];
547 error("tmds selector 0x%02x unknown\n", tmds);
553 /******************************************************************************
554 * init opcode handlers
555 *****************************************************************************/
558 * init_reserved - stub for various unknown/unused single-byte opcodes
562 init_reserved(struct nvbios_init *init)
564 u8 opcode = nv_ro08(init->bios, init->offset);
565 trace("RESERVED\t0x%02x\n", opcode);
570 * INIT_DONE - opcode 0x71
574 init_done(struct nvbios_init *init)
577 init->offset = 0x0000;
581 * INIT_IO_RESTRICT_PROG - opcode 0x32
585 init_io_restrict_prog(struct nvbios_init *init)
587 struct nouveau_bios *bios = init->bios;
588 u16 port = nv_ro16(bios, init->offset + 1);
589 u8 index = nv_ro08(bios, init->offset + 3);
590 u8 mask = nv_ro08(bios, init->offset + 4);
591 u8 shift = nv_ro08(bios, init->offset + 5);
592 u8 count = nv_ro08(bios, init->offset + 6);
593 u32 reg = nv_ro32(bios, init->offset + 7);
596 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
597 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
598 reg, port, index, mask, shift);
601 conf = (init_rdvgai(init, port, index) & mask) >> shift;
602 for (i = 0; i < count; i++) {
603 u32 data = nv_ro32(bios, init->offset);
606 trace("\t0x%08x *\n", data);
607 init_wr32(init, reg, data);
609 trace("\t0x%08x\n", data);
618 * INIT_REPEAT - opcode 0x33
622 init_repeat(struct nvbios_init *init)
624 struct nouveau_bios *bios = init->bios;
625 u8 count = nv_ro08(bios, init->offset + 1);
626 u16 repeat = init->repeat;
628 trace("REPEAT\t0x%02x\n", count);
631 init->repeat = init->offset;
632 init->repend = init->offset;
634 init->offset = init->repeat;
637 trace("REPEAT\t0x%02x\n", count);
639 init->offset = init->repend;
640 init->repeat = repeat;
644 * INIT_IO_RESTRICT_PLL - opcode 0x34
648 init_io_restrict_pll(struct nvbios_init *init)
650 struct nouveau_bios *bios = init->bios;
651 u16 port = nv_ro16(bios, init->offset + 1);
652 u8 index = nv_ro08(bios, init->offset + 3);
653 u8 mask = nv_ro08(bios, init->offset + 4);
654 u8 shift = nv_ro08(bios, init->offset + 5);
655 s8 iofc = nv_ro08(bios, init->offset + 6);
656 u8 count = nv_ro08(bios, init->offset + 7);
657 u32 reg = nv_ro32(bios, init->offset + 8);
660 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
661 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
662 reg, port, index, mask, shift, iofc);
665 conf = (init_rdvgai(init, port, index) & mask) >> shift;
666 for (i = 0; i < count; i++) {
667 u32 freq = nv_ro16(bios, init->offset) * 10;
670 trace("\t%dkHz *\n", freq);
671 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
673 init_prog_pll(init, reg, freq);
675 trace("\t%dkHz\n", freq);
684 * INIT_END_REPEAT - opcode 0x36
688 init_end_repeat(struct nvbios_init *init)
690 trace("END_REPEAT\n");
694 init->repend = init->offset;
700 * INIT_COPY - opcode 0x37
704 init_copy(struct nvbios_init *init)
706 struct nouveau_bios *bios = init->bios;
707 u32 reg = nv_ro32(bios, init->offset + 1);
708 u8 shift = nv_ro08(bios, init->offset + 5);
709 u8 smask = nv_ro08(bios, init->offset + 6);
710 u16 port = nv_ro16(bios, init->offset + 7);
711 u8 index = nv_ro08(bios, init->offset + 9);
712 u8 mask = nv_ro08(bios, init->offset + 10);
715 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
716 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
717 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
718 (shift & 0x80) ? (0x100 - shift) : shift, smask);
721 data = init_rdvgai(init, port, index) & mask;
722 data |= init_shift(init_rd32(init, reg), shift) & smask;
723 init_wrvgai(init, port, index, data);
727 * INIT_NOT - opcode 0x38
731 init_not(struct nvbios_init *init)
739 * INIT_IO_FLAG_CONDITION - opcode 0x39
743 init_io_flag_condition(struct nvbios_init *init)
745 struct nouveau_bios *bios = init->bios;
746 u8 cond = nv_ro08(bios, init->offset + 1);
748 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
751 if (!init_io_flag_condition_met(init, cond))
752 init_exec_set(init, false);
756 * INIT_DP_CONDITION - opcode 0x3a
760 init_dp_condition(struct nvbios_init *init)
762 struct nouveau_bios *bios = init->bios;
763 struct nvbios_dpout info;
764 u8 cond = nv_ro08(bios, init->offset + 1);
765 u8 unkn = nv_ro08(bios, init->offset + 2);
766 u8 ver, hdr, cnt, len;
769 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
774 if (init_conn(init) != DCB_CONNECTOR_eDP)
775 init_exec_set(init, false);
780 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
781 (init->outp->or << 0) |
782 (init->outp->sorconf.link << 6),
783 &ver, &hdr, &cnt, &len, &info)))
785 if (!(info.flags & cond))
786 init_exec_set(init, false);
790 warn("script needs dp output table data\n");
793 if (!(init_rdauxr(init, 0x0d) & 1))
794 init_exec_set(init, false);
797 warn("unknown dp condition 0x%02x\n", cond);
803 * INIT_IO_MASK_OR - opcode 0x3b
807 init_io_mask_or(struct nvbios_init *init)
809 struct nouveau_bios *bios = init->bios;
810 u8 index = nv_ro08(bios, init->offset + 1);
811 u8 or = init_or(init);
814 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)", index, or);
817 data = init_rdvgai(init, 0x03d4, index);
818 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
822 * INIT_IO_OR - opcode 0x3c
826 init_io_or(struct nvbios_init *init)
828 struct nouveau_bios *bios = init->bios;
829 u8 index = nv_ro08(bios, init->offset + 1);
830 u8 or = init_or(init);
833 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)", index, or);
836 data = init_rdvgai(init, 0x03d4, index);
837 init_wrvgai(init, 0x03d4, index, data | (1 << or));
841 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
845 init_idx_addr_latched(struct nvbios_init *init)
847 struct nouveau_bios *bios = init->bios;
848 u32 creg = nv_ro32(bios, init->offset + 1);
849 u32 dreg = nv_ro32(bios, init->offset + 5);
850 u32 mask = nv_ro32(bios, init->offset + 9);
851 u32 data = nv_ro32(bios, init->offset + 13);
852 u8 count = nv_ro08(bios, init->offset + 17);
854 trace("INDEX_ADDRESS_LATCHED\t"
855 "R[0x%06x] : R[0x%06x]\n\tCTRL &= 0x%08x |= 0x%08x\n",
856 creg, dreg, mask, data);
860 u8 iaddr = nv_ro08(bios, init->offset + 0);
861 u8 idata = nv_ro08(bios, init->offset + 1);
863 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
866 init_wr32(init, dreg, idata);
867 init_mask(init, creg, ~mask, data | idata);
872 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
876 init_io_restrict_pll2(struct nvbios_init *init)
878 struct nouveau_bios *bios = init->bios;
879 u16 port = nv_ro16(bios, init->offset + 1);
880 u8 index = nv_ro08(bios, init->offset + 3);
881 u8 mask = nv_ro08(bios, init->offset + 4);
882 u8 shift = nv_ro08(bios, init->offset + 5);
883 u8 count = nv_ro08(bios, init->offset + 6);
884 u32 reg = nv_ro32(bios, init->offset + 7);
887 trace("IO_RESTRICT_PLL2\t"
888 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
889 reg, port, index, mask, shift);
892 conf = (init_rdvgai(init, port, index) & mask) >> shift;
893 for (i = 0; i < count; i++) {
894 u32 freq = nv_ro32(bios, init->offset);
896 trace("\t%dkHz *\n", freq);
897 init_prog_pll(init, reg, freq);
899 trace("\t%dkHz\n", freq);
907 * INIT_PLL2 - opcode 0x4b
911 init_pll2(struct nvbios_init *init)
913 struct nouveau_bios *bios = init->bios;
914 u32 reg = nv_ro32(bios, init->offset + 1);
915 u32 freq = nv_ro32(bios, init->offset + 5);
917 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
920 init_prog_pll(init, reg, freq);
924 * INIT_I2C_BYTE - opcode 0x4c
928 init_i2c_byte(struct nvbios_init *init)
930 struct nouveau_bios *bios = init->bios;
931 u8 index = nv_ro08(bios, init->offset + 1);
932 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
933 u8 count = nv_ro08(bios, init->offset + 3);
935 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
939 u8 reg = nv_ro08(bios, init->offset + 0);
940 u8 mask = nv_ro08(bios, init->offset + 1);
941 u8 data = nv_ro08(bios, init->offset + 2);
944 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
947 val = init_rdi2cr(init, index, addr, reg);
950 init_wri2cr(init, index, addr, reg, (val & mask) | data);
955 * INIT_ZM_I2C_BYTE - opcode 0x4d
959 init_zm_i2c_byte(struct nvbios_init *init)
961 struct nouveau_bios *bios = init->bios;
962 u8 index = nv_ro08(bios, init->offset + 1);
963 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
964 u8 count = nv_ro08(bios, init->offset + 3);
966 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
970 u8 reg = nv_ro08(bios, init->offset + 0);
971 u8 data = nv_ro08(bios, init->offset + 1);
973 trace("\t[0x%02x] = 0x%02x\n", reg, data);
976 init_wri2cr(init, index, addr, reg, data);
982 * INIT_ZM_I2C - opcode 0x4e
986 init_zm_i2c(struct nvbios_init *init)
988 struct nouveau_bios *bios = init->bios;
989 u8 index = nv_ro08(bios, init->offset + 1);
990 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
991 u8 count = nv_ro08(bios, init->offset + 3);
994 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
997 for (i = 0; i < count; i++) {
998 data[i] = nv_ro08(bios, init->offset);
999 trace("\t0x%02x\n", data[i]);
1003 if (init_exec(init)) {
1004 struct nouveau_i2c_port *port = init_i2c(init, index);
1005 struct i2c_msg msg = {
1006 .addr = addr, .flags = 0, .len = count, .buf = data,
1010 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1011 warn("i2c wr failed, %d\n", ret);
1016 * INIT_TMDS - opcode 0x4f
1020 init_tmds(struct nvbios_init *init)
1022 struct nouveau_bios *bios = init->bios;
1023 u8 tmds = nv_ro08(bios, init->offset + 1);
1024 u8 addr = nv_ro08(bios, init->offset + 2);
1025 u8 mask = nv_ro08(bios, init->offset + 3);
1026 u8 data = nv_ro08(bios, init->offset + 4);
1027 u32 reg = init_tmds_reg(init, tmds);
1029 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1030 tmds, addr, mask, data);
1036 init_wr32(init, reg + 0, addr | 0x00010000);
1037 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1038 init_wr32(init, reg + 0, addr);
1042 * INIT_ZM_TMDS_GROUP - opcode 0x50
1046 init_zm_tmds_group(struct nvbios_init *init)
1048 struct nouveau_bios *bios = init->bios;
1049 u8 tmds = nv_ro08(bios, init->offset + 1);
1050 u8 count = nv_ro08(bios, init->offset + 2);
1051 u32 reg = init_tmds_reg(init, tmds);
1053 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1057 u8 addr = nv_ro08(bios, init->offset + 0);
1058 u8 data = nv_ro08(bios, init->offset + 1);
1060 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1063 init_wr32(init, reg + 4, data);
1064 init_wr32(init, reg + 0, addr);
1069 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1073 init_cr_idx_adr_latch(struct nvbios_init *init)
1075 struct nouveau_bios *bios = init->bios;
1076 u8 addr0 = nv_ro08(bios, init->offset + 1);
1077 u8 addr1 = nv_ro08(bios, init->offset + 2);
1078 u8 base = nv_ro08(bios, init->offset + 3);
1079 u8 count = nv_ro08(bios, init->offset + 4);
1082 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1085 save0 = init_rdvgai(init, 0x03d4, addr0);
1087 u8 data = nv_ro08(bios, init->offset);
1089 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1092 init_wrvgai(init, 0x03d4, addr0, base++);
1093 init_wrvgai(init, 0x03d4, addr1, data);
1095 init_wrvgai(init, 0x03d4, addr0, save0);
1099 * INIT_CR - opcode 0x52
1103 init_cr(struct nvbios_init *init)
1105 struct nouveau_bios *bios = init->bios;
1106 u8 addr = nv_ro08(bios, init->offset + 1);
1107 u8 mask = nv_ro08(bios, init->offset + 2);
1108 u8 data = nv_ro08(bios, init->offset + 3);
1111 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1114 val = init_rdvgai(init, 0x03d4, addr) & mask;
1115 init_wrvgai(init, 0x03d4, addr, val | data);
1119 * INIT_ZM_CR - opcode 0x53
1123 init_zm_cr(struct nvbios_init *init)
1125 struct nouveau_bios *bios = init->bios;
1126 u8 addr = nv_ro08(bios, init->offset + 1);
1127 u8 data = nv_ro08(bios, init->offset + 2);
1129 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1132 init_wrvgai(init, 0x03d4, addr, data);
1136 * INIT_ZM_CR_GROUP - opcode 0x54
1140 init_zm_cr_group(struct nvbios_init *init)
1142 struct nouveau_bios *bios = init->bios;
1143 u8 count = nv_ro08(bios, init->offset + 1);
1145 trace("ZM_CR_GROUP\n");
1149 u8 addr = nv_ro08(bios, init->offset + 0);
1150 u8 data = nv_ro08(bios, init->offset + 1);
1152 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1155 init_wrvgai(init, 0x03d4, addr, data);
1160 * INIT_CONDITION_TIME - opcode 0x56
1164 init_condition_time(struct nvbios_init *init)
1166 struct nouveau_bios *bios = init->bios;
1167 u8 cond = nv_ro08(bios, init->offset + 1);
1168 u8 retry = nv_ro08(bios, init->offset + 2);
1169 u8 wait = min((u16)retry * 50, 100);
1171 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1174 if (!init_exec(init))
1178 if (init_condition_met(init, cond))
1183 init_exec_set(init, false);
1187 * INIT_LTIME - opcode 0x57
1191 init_ltime(struct nvbios_init *init)
1193 struct nouveau_bios *bios = init->bios;
1194 u16 msec = nv_ro16(bios, init->offset + 1);
1196 trace("LTIME\t0x%04x\n", msec);
1199 if (init_exec(init))
1204 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1208 init_zm_reg_sequence(struct nvbios_init *init)
1210 struct nouveau_bios *bios = init->bios;
1211 u32 base = nv_ro32(bios, init->offset + 1);
1212 u8 count = nv_ro08(bios, init->offset + 5);
1214 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1218 u32 data = nv_ro32(bios, init->offset);
1220 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1223 init_wr32(init, base, data);
1229 * INIT_SUB_DIRECT - opcode 0x5b
1233 init_sub_direct(struct nvbios_init *init)
1235 struct nouveau_bios *bios = init->bios;
1236 u16 addr = nv_ro16(bios, init->offset + 1);
1239 trace("SUB_DIRECT\t0x%04x\n", addr);
1241 if (init_exec(init)) {
1242 save = init->offset;
1243 init->offset = addr;
1244 if (nvbios_exec(init)) {
1245 error("error parsing sub-table\n");
1248 init->offset = save;
1255 * INIT_JUMP - opcode 0x5c
1259 init_jump(struct nvbios_init *init)
1261 struct nouveau_bios *bios = init->bios;
1262 u16 offset = nv_ro16(bios, init->offset + 1);
1264 trace("JUMP\t0x%04x\n", offset);
1265 init->offset = offset;
1269 * INIT_I2C_IF - opcode 0x5e
1273 init_i2c_if(struct nvbios_init *init)
1275 struct nouveau_bios *bios = init->bios;
1276 u8 index = nv_ro08(bios, init->offset + 1);
1277 u8 addr = nv_ro08(bios, init->offset + 2);
1278 u8 reg = nv_ro08(bios, init->offset + 3);
1279 u8 mask = nv_ro08(bios, init->offset + 4);
1280 u8 data = nv_ro08(bios, init->offset + 5);
1283 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1284 index, addr, reg, mask, data);
1286 init_exec_force(init, true);
1288 value = init_rdi2cr(init, index, addr, reg);
1289 if ((value & mask) != data)
1290 init_exec_set(init, false);
1292 init_exec_force(init, false);
1296 * INIT_COPY_NV_REG - opcode 0x5f
1300 init_copy_nv_reg(struct nvbios_init *init)
1302 struct nouveau_bios *bios = init->bios;
1303 u32 sreg = nv_ro32(bios, init->offset + 1);
1304 u8 shift = nv_ro08(bios, init->offset + 5);
1305 u32 smask = nv_ro32(bios, init->offset + 6);
1306 u32 sxor = nv_ro32(bios, init->offset + 10);
1307 u32 dreg = nv_ro32(bios, init->offset + 14);
1308 u32 dmask = nv_ro32(bios, init->offset + 18);
1311 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1312 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1313 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1314 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1317 data = init_shift(init_rd32(init, sreg), shift);
1318 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1322 * INIT_ZM_INDEX_IO - opcode 0x62
1326 init_zm_index_io(struct nvbios_init *init)
1328 struct nouveau_bios *bios = init->bios;
1329 u16 port = nv_ro16(bios, init->offset + 1);
1330 u8 index = nv_ro08(bios, init->offset + 3);
1331 u8 data = nv_ro08(bios, init->offset + 4);
1333 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1336 init_wrvgai(init, port, index, data);
1340 * INIT_COMPUTE_MEM - opcode 0x63
1344 init_compute_mem(struct nvbios_init *init)
1346 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
1348 trace("COMPUTE_MEM\n");
1351 init_exec_force(init, true);
1352 if (init_exec(init) && devinit->meminit)
1353 devinit->meminit(devinit);
1354 init_exec_force(init, false);
1358 * INIT_RESET - opcode 0x65
1362 init_reset(struct nvbios_init *init)
1364 struct nouveau_bios *bios = init->bios;
1365 u32 reg = nv_ro32(bios, init->offset + 1);
1366 u32 data1 = nv_ro32(bios, init->offset + 5);
1367 u32 data2 = nv_ro32(bios, init->offset + 9);
1370 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1372 init_exec_force(init, true);
1374 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1375 init_wr32(init, reg, data1);
1377 init_wr32(init, reg, data2);
1378 init_wr32(init, 0x00184c, savepci19);
1379 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1381 init_exec_force(init, false);
1385 * INIT_CONFIGURE_MEM - opcode 0x66
1389 init_configure_mem_clk(struct nvbios_init *init)
1391 u16 mdata = bmp_mem_init_table(init->bios);
1393 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1398 init_configure_mem(struct nvbios_init *init)
1400 struct nouveau_bios *bios = init->bios;
1404 trace("CONFIGURE_MEM\n");
1407 if (bios->version.major > 2) {
1411 init_exec_force(init, true);
1413 mdata = init_configure_mem_clk(init);
1414 sdata = bmp_sdr_seq_table(bios);
1415 if (nv_ro08(bios, mdata) & 0x01)
1416 sdata = bmp_ddr_seq_table(bios);
1417 mdata += 6; /* skip to data */
1419 data = init_rdvgai(init, 0x03c4, 0x01);
1420 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1422 while ((addr = nv_ro32(bios, sdata)) != 0xffffffff) {
1424 case 0x10021c: /* CKE_NORMAL */
1425 case 0x1002d0: /* CMD_REFRESH */
1426 case 0x1002d4: /* CMD_PRECHARGE */
1430 data = nv_ro32(bios, mdata);
1432 if (data == 0xffffffff)
1437 init_wr32(init, addr, data);
1440 init_exec_force(init, false);
1444 * INIT_CONFIGURE_CLK - opcode 0x67
1448 init_configure_clk(struct nvbios_init *init)
1450 struct nouveau_bios *bios = init->bios;
1453 trace("CONFIGURE_CLK\n");
1456 if (bios->version.major > 2) {
1460 init_exec_force(init, true);
1462 mdata = init_configure_mem_clk(init);
1465 clock = nv_ro16(bios, mdata + 4) * 10;
1466 init_prog_pll(init, 0x680500, clock);
1469 clock = nv_ro16(bios, mdata + 2) * 10;
1470 if (nv_ro08(bios, mdata) & 0x01)
1472 init_prog_pll(init, 0x680504, clock);
1474 init_exec_force(init, false);
1478 * INIT_CONFIGURE_PREINIT - opcode 0x68
1482 init_configure_preinit(struct nvbios_init *init)
1484 struct nouveau_bios *bios = init->bios;
1487 trace("CONFIGURE_PREINIT\n");
1490 if (bios->version.major > 2) {
1494 init_exec_force(init, true);
1496 strap = init_rd32(init, 0x101000);
1497 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1498 init_wrvgai(init, 0x03d4, 0x3c, strap);
1500 init_exec_force(init, false);
1504 * INIT_IO - opcode 0x69
1508 init_io(struct nvbios_init *init)
1510 struct nouveau_bios *bios = init->bios;
1511 u16 port = nv_ro16(bios, init->offset + 1);
1512 u8 mask = nv_ro16(bios, init->offset + 3);
1513 u8 data = nv_ro16(bios, init->offset + 4);
1516 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1519 /* ummm.. yes.. should really figure out wtf this is and why it's
1520 * needed some day.. it's almost certainly wrong, but, it also
1521 * somehow makes things work...
1523 if (nv_device(init->bios)->card_type >= NV_50 &&
1524 port == 0x03c3 && data == 0x01) {
1525 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1526 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1527 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1528 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1530 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1531 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1532 init_wr32(init, 0x614100, 0x00800018);
1533 init_wr32(init, 0x614900, 0x00800018);
1535 init_wr32(init, 0x614100, 0x10000018);
1536 init_wr32(init, 0x614900, 0x10000018);
1540 value = init_rdport(init, port) & mask;
1541 init_wrport(init, port, data | value);
1545 * INIT_SUB - opcode 0x6b
1549 init_sub(struct nvbios_init *init)
1551 struct nouveau_bios *bios = init->bios;
1552 u8 index = nv_ro08(bios, init->offset + 1);
1555 trace("SUB\t0x%02x\n", index);
1557 addr = init_script(bios, index);
1558 if (addr && init_exec(init)) {
1559 save = init->offset;
1560 init->offset = addr;
1561 if (nvbios_exec(init)) {
1562 error("error parsing sub-table\n");
1565 init->offset = save;
1572 * INIT_RAM_CONDITION - opcode 0x6d
1576 init_ram_condition(struct nvbios_init *init)
1578 struct nouveau_bios *bios = init->bios;
1579 u8 mask = nv_ro08(bios, init->offset + 1);
1580 u8 value = nv_ro08(bios, init->offset + 2);
1582 trace("RAM_CONDITION\t"
1583 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1586 if ((init_rd32(init, 0x100000) & mask) != value)
1587 init_exec_set(init, false);
1591 * INIT_NV_REG - opcode 0x6e
1595 init_nv_reg(struct nvbios_init *init)
1597 struct nouveau_bios *bios = init->bios;
1598 u32 reg = nv_ro32(bios, init->offset + 1);
1599 u32 mask = nv_ro32(bios, init->offset + 5);
1600 u32 data = nv_ro32(bios, init->offset + 9);
1602 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1605 init_mask(init, reg, ~mask, data);
1609 * INIT_MACRO - opcode 0x6f
1613 init_macro(struct nvbios_init *init)
1615 struct nouveau_bios *bios = init->bios;
1616 u8 macro = nv_ro08(bios, init->offset + 1);
1619 trace("MACRO\t0x%02x\n", macro);
1621 table = init_macro_table(init);
1623 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1624 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1625 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1626 init_wr32(init, addr, data);
1633 * INIT_RESUME - opcode 0x72
1637 init_resume(struct nvbios_init *init)
1641 init_exec_set(init, true);
1645 * INIT_TIME - opcode 0x74
1649 init_time(struct nvbios_init *init)
1651 struct nouveau_bios *bios = init->bios;
1652 u16 usec = nv_ro16(bios, init->offset + 1);
1654 trace("TIME\t0x%04x\n", usec);
1657 if (init_exec(init)) {
1661 mdelay((usec + 900) / 1000);
1666 * INIT_CONDITION - opcode 0x75
1670 init_condition(struct nvbios_init *init)
1672 struct nouveau_bios *bios = init->bios;
1673 u8 cond = nv_ro08(bios, init->offset + 1);
1675 trace("CONDITION\t0x%02x\n", cond);
1678 if (!init_condition_met(init, cond))
1679 init_exec_set(init, false);
1683 * INIT_IO_CONDITION - opcode 0x76
1687 init_io_condition(struct nvbios_init *init)
1689 struct nouveau_bios *bios = init->bios;
1690 u8 cond = nv_ro08(bios, init->offset + 1);
1692 trace("IO_CONDITION\t0x%02x\n", cond);
1695 if (!init_io_condition_met(init, cond))
1696 init_exec_set(init, false);
1700 * INIT_INDEX_IO - opcode 0x78
1704 init_index_io(struct nvbios_init *init)
1706 struct nouveau_bios *bios = init->bios;
1707 u16 port = nv_ro16(bios, init->offset + 1);
1708 u8 index = nv_ro16(bios, init->offset + 3);
1709 u8 mask = nv_ro08(bios, init->offset + 4);
1710 u8 data = nv_ro08(bios, init->offset + 5);
1713 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1714 port, index, mask, data);
1717 value = init_rdvgai(init, port, index) & mask;
1718 init_wrvgai(init, port, index, data | value);
1722 * INIT_PLL - opcode 0x79
1726 init_pll(struct nvbios_init *init)
1728 struct nouveau_bios *bios = init->bios;
1729 u32 reg = nv_ro32(bios, init->offset + 1);
1730 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1732 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1735 init_prog_pll(init, reg, freq);
1739 * INIT_ZM_REG - opcode 0x7a
1743 init_zm_reg(struct nvbios_init *init)
1745 struct nouveau_bios *bios = init->bios;
1746 u32 addr = nv_ro32(bios, init->offset + 1);
1747 u32 data = nv_ro32(bios, init->offset + 5);
1749 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1752 if (addr == 0x000200)
1755 init_wr32(init, addr, data);
1759 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1763 init_ram_restrict_pll(struct nvbios_init *init)
1765 struct nouveau_bios *bios = init->bios;
1766 u8 type = nv_ro08(bios, init->offset + 1);
1767 u8 count = init_ram_restrict_group_count(init);
1768 u8 strap = init_ram_restrict(init);
1771 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1774 for (cconf = 0; cconf < count; cconf++) {
1775 u32 freq = nv_ro32(bios, init->offset);
1777 if (cconf == strap) {
1778 trace("%dkHz *\n", freq);
1779 init_prog_pll(init, type, freq);
1781 trace("%dkHz\n", freq);
1789 * INIT_GPIO - opcode 0x8e
1793 init_gpio(struct nvbios_init *init)
1795 struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
1800 if (init_exec(init) && gpio && gpio->reset)
1801 gpio->reset(gpio, DCB_GPIO_UNUSED);
1805 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1809 init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1811 struct nouveau_bios *bios = init->bios;
1812 u32 addr = nv_ro32(bios, init->offset + 1);
1813 u8 incr = nv_ro08(bios, init->offset + 5);
1814 u8 num = nv_ro08(bios, init->offset + 6);
1815 u8 count = init_ram_restrict_group_count(init);
1816 u8 index = init_ram_restrict(init);
1819 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1820 "R[%08x] 0x%02x 0x%02x\n", addr, incr, num);
1823 for (i = 0; i < num; i++) {
1824 trace("\tR[0x%06x] = {\n", addr);
1825 for (j = 0; j < count; j++) {
1826 u32 data = nv_ro32(bios, init->offset);
1829 trace("\t\t0x%08x *\n", data);
1830 init_wr32(init, addr, data);
1832 trace("\t\t0x%08x\n", data);
1843 * INIT_COPY_ZM_REG - opcode 0x90
1847 init_copy_zm_reg(struct nvbios_init *init)
1849 struct nouveau_bios *bios = init->bios;
1850 u32 sreg = nv_ro32(bios, init->offset + 1);
1851 u32 dreg = nv_ro32(bios, init->offset + 5);
1853 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", sreg, dreg);
1856 init_wr32(init, dreg, init_rd32(init, sreg));
1860 * INIT_ZM_REG_GROUP - opcode 0x91
1864 init_zm_reg_group(struct nvbios_init *init)
1866 struct nouveau_bios *bios = init->bios;
1867 u32 addr = nv_ro32(bios, init->offset + 1);
1868 u8 count = nv_ro08(bios, init->offset + 5);
1870 trace("ZM_REG_GROUP\tR[0x%06x] =\n");
1874 u32 data = nv_ro32(bios, init->offset);
1875 trace("\t0x%08x\n", data);
1876 init_wr32(init, addr, data);
1882 * INIT_XLAT - opcode 0x96
1886 init_xlat(struct nvbios_init *init)
1888 struct nouveau_bios *bios = init->bios;
1889 u32 saddr = nv_ro32(bios, init->offset + 1);
1890 u8 sshift = nv_ro08(bios, init->offset + 5);
1891 u8 smask = nv_ro08(bios, init->offset + 6);
1892 u8 index = nv_ro08(bios, init->offset + 7);
1893 u32 daddr = nv_ro32(bios, init->offset + 8);
1894 u32 dmask = nv_ro32(bios, init->offset + 12);
1895 u8 shift = nv_ro08(bios, init->offset + 16);
1898 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1899 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1900 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1901 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1904 data = init_shift(init_rd32(init, saddr), sshift) & smask;
1905 data = init_xlat_(init, index, data) << shift;
1906 init_mask(init, daddr, ~dmask, data);
1910 * INIT_ZM_MASK_ADD - opcode 0x97
1914 init_zm_mask_add(struct nvbios_init *init)
1916 struct nouveau_bios *bios = init->bios;
1917 u32 addr = nv_ro32(bios, init->offset + 1);
1918 u32 mask = nv_ro32(bios, init->offset + 5);
1919 u32 add = nv_ro32(bios, init->offset + 9);
1922 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1925 data = init_rd32(init, addr) & mask;
1926 data |= ((data + add) & ~mask);
1927 init_wr32(init, addr, data);
1931 * INIT_AUXCH - opcode 0x98
1935 init_auxch(struct nvbios_init *init)
1937 struct nouveau_bios *bios = init->bios;
1938 u32 addr = nv_ro32(bios, init->offset + 1);
1939 u8 count = nv_ro08(bios, init->offset + 5);
1941 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1945 u8 mask = nv_ro08(bios, init->offset + 0);
1946 u8 data = nv_ro08(bios, init->offset + 1);
1947 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1948 mask = init_rdauxr(init, addr) & mask;
1949 init_wrauxr(init, addr, mask | data);
1955 * INIT_AUXCH - opcode 0x99
1959 init_zm_auxch(struct nvbios_init *init)
1961 struct nouveau_bios *bios = init->bios;
1962 u32 addr = nv_ro32(bios, init->offset + 1);
1963 u8 count = nv_ro08(bios, init->offset + 5);
1965 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1969 u8 data = nv_ro08(bios, init->offset + 0);
1970 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
1971 init_wrauxr(init, addr, data);
1977 * INIT_I2C_LONG_IF - opcode 0x9a
1981 init_i2c_long_if(struct nvbios_init *init)
1983 struct nouveau_bios *bios = init->bios;
1984 u8 index = nv_ro08(bios, init->offset + 1);
1985 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1986 u8 reglo = nv_ro08(bios, init->offset + 3);
1987 u8 reghi = nv_ro08(bios, init->offset + 4);
1988 u8 mask = nv_ro08(bios, init->offset + 5);
1989 u8 data = nv_ro08(bios, init->offset + 6);
1990 struct nouveau_i2c_port *port;
1992 trace("I2C_LONG_IF\t"
1993 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
1994 index, addr, reglo, reghi, mask, data);
1997 port = init_i2c(init, index);
1999 u8 i[2] = { reghi, reglo };
2001 struct i2c_msg msg[] = {
2002 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2003 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2007 ret = i2c_transfer(&port->adapter, msg, 2);
2008 if (ret == 2 && ((o[0] & mask) == data))
2012 init_exec_set(init, false);
2016 * INIT_GPIO_NE - opcode 0xa9
2020 init_gpio_ne(struct nvbios_init *init)
2022 struct nouveau_bios *bios = init->bios;
2023 struct nouveau_gpio *gpio = nouveau_gpio(bios);
2024 struct dcb_gpio_func func;
2025 u8 count = nv_ro08(bios, init->offset + 1);
2026 u8 idx = 0, ver, len;
2032 for (i = init->offset; i < init->offset + count; i++)
2033 cont("0x%02x ", nv_ro08(bios, i));
2036 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2037 if (func.func != DCB_GPIO_UNUSED) {
2038 for (i = init->offset; i < init->offset + count; i++) {
2039 if (func.func == nv_ro08(bios, i))
2043 trace("\tFUNC[0x%02x]", func.func);
2044 if (i == (init->offset + count)) {
2046 if (init_exec(init) && gpio && gpio->reset)
2047 gpio->reset(gpio, func.func);
2053 init->offset += count;
2056 static struct nvbios_init_opcode {
2057 void (*exec)(struct nvbios_init *);
2059 [0x32] = { init_io_restrict_prog },
2060 [0x33] = { init_repeat },
2061 [0x34] = { init_io_restrict_pll },
2062 [0x36] = { init_end_repeat },
2063 [0x37] = { init_copy },
2064 [0x38] = { init_not },
2065 [0x39] = { init_io_flag_condition },
2066 [0x3a] = { init_dp_condition },
2067 [0x3b] = { init_io_mask_or },
2068 [0x3c] = { init_io_or },
2069 [0x49] = { init_idx_addr_latched },
2070 [0x4a] = { init_io_restrict_pll2 },
2071 [0x4b] = { init_pll2 },
2072 [0x4c] = { init_i2c_byte },
2073 [0x4d] = { init_zm_i2c_byte },
2074 [0x4e] = { init_zm_i2c },
2075 [0x4f] = { init_tmds },
2076 [0x50] = { init_zm_tmds_group },
2077 [0x51] = { init_cr_idx_adr_latch },
2078 [0x52] = { init_cr },
2079 [0x53] = { init_zm_cr },
2080 [0x54] = { init_zm_cr_group },
2081 [0x56] = { init_condition_time },
2082 [0x57] = { init_ltime },
2083 [0x58] = { init_zm_reg_sequence },
2084 [0x5b] = { init_sub_direct },
2085 [0x5c] = { init_jump },
2086 [0x5e] = { init_i2c_if },
2087 [0x5f] = { init_copy_nv_reg },
2088 [0x62] = { init_zm_index_io },
2089 [0x63] = { init_compute_mem },
2090 [0x65] = { init_reset },
2091 [0x66] = { init_configure_mem },
2092 [0x67] = { init_configure_clk },
2093 [0x68] = { init_configure_preinit },
2094 [0x69] = { init_io },
2095 [0x6b] = { init_sub },
2096 [0x6d] = { init_ram_condition },
2097 [0x6e] = { init_nv_reg },
2098 [0x6f] = { init_macro },
2099 [0x71] = { init_done },
2100 [0x72] = { init_resume },
2101 [0x74] = { init_time },
2102 [0x75] = { init_condition },
2103 [0x76] = { init_io_condition },
2104 [0x78] = { init_index_io },
2105 [0x79] = { init_pll },
2106 [0x7a] = { init_zm_reg },
2107 [0x87] = { init_ram_restrict_pll },
2108 [0x8c] = { init_reserved },
2109 [0x8d] = { init_reserved },
2110 [0x8e] = { init_gpio },
2111 [0x8f] = { init_ram_restrict_zm_reg_group },
2112 [0x90] = { init_copy_zm_reg },
2113 [0x91] = { init_zm_reg_group },
2114 [0x92] = { init_reserved },
2115 [0x96] = { init_xlat },
2116 [0x97] = { init_zm_mask_add },
2117 [0x98] = { init_auxch },
2118 [0x99] = { init_zm_auxch },
2119 [0x9a] = { init_i2c_long_if },
2120 [0xa9] = { init_gpio_ne },
2123 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2126 nvbios_exec(struct nvbios_init *init)
2129 while (init->offset) {
2130 u8 opcode = nv_ro08(init->bios, init->offset);
2131 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2132 error("unknown opcode 0x%02x\n", opcode);
2136 init_opcode[opcode].exec(init);
2143 nvbios_init(struct nouveau_subdev *subdev, bool execute)
2145 struct nouveau_bios *bios = nouveau_bios(subdev);
2151 nv_info(bios, "running init tables\n");
2152 while (!ret && (data = (init_script(bios, ++i)))) {
2153 struct nvbios_init init = {
2159 .execute = execute ? 1 : 0,
2162 ret = nvbios_exec(&init);
2165 /* the vbios parser will run this right after the normal init
2166 * tables, whereas the binary driver appears to run it later.
2168 if (!ret && (data = init_unknown_script(bios))) {
2169 struct nvbios_init init = {
2175 .execute = execute ? 1 : 0,
2178 ret = nvbios_exec(&init);