drivers/gpu/drm/nouveau/core/subdev/device/nv40.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/device.h>
  26 #include <subdev/bios.h>
  27 #include <subdev/gpio.h>
  28 #include <subdev/i2c.h>
  29 #include <subdev/clock.h>
  30 #include <subdev/devinit.h>
  31
  32 int
  33 nv40_identify(struct nouveau_device *device)
  34 {
  35         switch (device->chipset) {
  36         case 0x40:
  37                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  38                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
  39                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  40                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
  41                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
  42                 break;
  43         case 0x41:
  44                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  45                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
  46                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  47                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
  48                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
  49                 break;
  50         case 0x42:
  51                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  52                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
  53                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  54                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
  55                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
  56                 break;
  57         case 0x43:
  58                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  59                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
  60                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  61                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
  62                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
  63                 break;
  64         case 0x45:
  65                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  66                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
  67                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  68                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
  69                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
  70                 break;
  71         case 0x47:
  72                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  73                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
  74                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  75                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
  76                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
  77                 break;
  78         case 0x49:
  79                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  80                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
  81                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  82                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
  83                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
  84                 break;
  85         case 0x4b:
  86                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  87                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
  88                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  89                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
  90                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
  91                 break;
  92         case 0x44:
  93                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  94                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
  95                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  96                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
  97                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
  98                 break;
  99         case 0x46:
 100                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 101                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
 102                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 103                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
 104                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
 105                 break;
 106         case 0x4a:
 107                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 108                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
 109                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 110                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
 111                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
 112                 break;
 113         case 0x4c:
 114                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 115                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
 116                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 117                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
 118                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
 119                 break;
 120         case 0x4e:
 121                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 122                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
 123                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 124                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
 125                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
 126                 break;
 127         case 0x63:
 128                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 129                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
 130                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 131                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
 132                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
 133                 break;
 134         case 0x67:
 135                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 136                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
 137                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 138                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
 139                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
 140                 break;
 141         case 0x68:
 142                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 143                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
 144                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 145                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
 146                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
 147                 break;
 148         default:
 149                 nv_fatal(device, "unknown Curie chipset\n");
 150                 return -EINVAL;
 151         }
 152
 153         return 0;
 154 }