drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/device.h>
  26 #include <subdev/bios.h>
  27 #include <subdev/gpio.h>
  28 #include <subdev/i2c.h>
  29 #include <subdev/clock.h>
  30 #include <subdev/devinit.h>
  31
  32 int
  33 nvc0_identify(struct nouveau_device *device)
  34 {
  35         switch (device->chipset) {
  36         case 0xc0:
  37                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  38                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  39                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  40                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
  41                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  42                 break;
  43         case 0xc4:
  44                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  45                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  46                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  47                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
  48                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  49                 break;
  50         case 0xc3:
  51                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  52                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  53                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  54                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
  55                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  56                 break;
  57         case 0xce:
  58                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  59                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  60                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  61                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
  62                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  63                 break;
  64         case 0xcf:
  65                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  66                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  67                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  68                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
  69                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  70                 break;
  71         case 0xc1:
  72                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  73                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  74                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  75                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
  76                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  77                 break;
  78         case 0xc8:
  79                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  80                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  81                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  82                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
  83                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  84                 break;
  85         case 0xd9:
  86                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  87                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nvd0_gpio_oclass;
  88                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  89                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
  90                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  91                 break;
  92         default:
  93                 nv_fatal(device, "unknown Fermi chipset\n");
  94                 return -EINVAL;
  95         }
  96
  97         return 0;
  98 }