2 * Copyright (C) 2010 Francisco Jerez.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <subdev/vga.h>
32 struct nv04_devinit_priv {
33 struct nouveau_devinit base;
38 nv04_devinit_meminit(struct nouveau_devinit *devinit)
40 struct nv04_devinit_priv *priv = (void *)devinit;
41 u32 patt = 0xdeadbeef;
42 struct io_mapping *fb;
45 /* Map the framebuffer aperture */
46 fb = fbmem_init(nv_device(priv)->pdev);
48 nv_error(priv, "failed to map fb\n");
52 /* Sequencer and refresh off */
53 nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) | 0x20);
54 nv_mask(priv, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
56 nv_mask(priv, NV04_PFB_BOOT_0, ~0,
57 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
58 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
59 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
61 for (i = 0; i < 4; i++)
62 fbmem_poke(fb, 4 * i, patt);
64 fbmem_poke(fb, 0x400000, patt + 1);
66 if (fbmem_peek(fb, 0) == patt + 1) {
67 nv_mask(priv, NV04_PFB_BOOT_0,
68 NV04_PFB_BOOT_0_RAM_TYPE,
69 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
70 nv_mask(priv, NV04_PFB_DEBUG_0,
71 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
73 for (i = 0; i < 4; i++)
74 fbmem_poke(fb, 4 * i, patt);
76 if ((fbmem_peek(fb, 0xc) & 0xffff) != (patt & 0xffff))
77 nv_mask(priv, NV04_PFB_BOOT_0,
78 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
79 NV04_PFB_BOOT_0_RAM_AMOUNT,
80 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
82 if ((fbmem_peek(fb, 0xc) & 0xffff0000) != (patt & 0xffff0000)) {
83 nv_mask(priv, NV04_PFB_BOOT_0,
84 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
85 NV04_PFB_BOOT_0_RAM_AMOUNT,
86 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
88 if (fbmem_peek(fb, 0) != patt) {
89 if (fbmem_readback(fb, 0x800000, patt))
90 nv_mask(priv, NV04_PFB_BOOT_0,
91 NV04_PFB_BOOT_0_RAM_AMOUNT,
92 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
94 nv_mask(priv, NV04_PFB_BOOT_0,
95 NV04_PFB_BOOT_0_RAM_AMOUNT,
96 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
98 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
99 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
101 if (!fbmem_readback(fb, 0x800000, patt)) {
102 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
103 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
107 /* Refresh on, sequencer on */
108 nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
109 nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) & ~0x20);
114 powerctrl_1_shift(int chip_version, int reg)
118 if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)
133 * the shift for vpll regs is only used for nv3x chips with a single
136 if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||
137 chip_version == 0x36 || chip_version >= 0x40))
144 setPLL_single(struct nouveau_devinit *devinit, u32 reg,
145 struct nouveau_pll_vals *pv)
147 int chip_version = nouveau_bios(devinit)->version.chip;
148 uint32_t oldpll = nv_rd32(devinit, reg);
149 int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
150 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
151 uint32_t saved_powerctrl_1 = 0;
152 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);
155 return; /* already set */
157 if (shift_powerctrl_1 >= 0) {
158 saved_powerctrl_1 = nv_rd32(devinit, 0x001584);
159 nv_wr32(devinit, 0x001584,
160 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
161 1 << shift_powerctrl_1);
164 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
165 /* upclock -- write new post divider first */
166 nv_wr32(devinit, reg, pv->log2P << 16 | (oldpll & 0xffff));
168 /* downclock -- write new NM first */
169 nv_wr32(devinit, reg, (oldpll & 0xffff0000) | pv->NM1);
171 if (chip_version < 0x17 && chip_version != 0x11)
172 /* wait a bit on older chips */
174 nv_rd32(devinit, reg);
176 /* then write the other half as well */
177 nv_wr32(devinit, reg, pll);
179 if (shift_powerctrl_1 >= 0)
180 nv_wr32(devinit, 0x001584, saved_powerctrl_1);
184 new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
186 bool head_a = (reg1 == 0x680508);
188 if (ss) /* single stage pll mode */
189 ramdac580 |= head_a ? 0x00000100 : 0x10000000;
191 ramdac580 &= head_a ? 0xfffffeff : 0xefffffff;
197 setPLL_double_highregs(struct nouveau_devinit *devinit, u32 reg1,
198 struct nouveau_pll_vals *pv)
200 int chip_version = nouveau_bios(devinit)->version.chip;
201 bool nv3035 = chip_version == 0x30 || chip_version == 0x35;
202 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
203 uint32_t oldpll1 = nv_rd32(devinit, reg1);
204 uint32_t oldpll2 = !nv3035 ? nv_rd32(devinit, reg2) : 0;
205 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
206 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;
207 uint32_t oldramdac580 = 0, ramdac580 = 0;
208 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */
209 uint32_t saved_powerctrl_1 = 0, savedc040 = 0;
210 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
212 /* model specific additions to generic pll1 and pll2 set up above */
214 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
215 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
218 if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */
219 oldramdac580 = nv_rd32(devinit, 0x680580);
220 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
221 if (oldramdac580 != ramdac580)
222 oldpll1 = ~0; /* force mismatch */
224 /* magic value used by nvidia in single stage mode */
227 if (chip_version > 0x70)
228 /* magic bits set by the blob (but not the bios) on g71-73 */
229 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;
231 if (oldpll1 == pll1 && oldpll2 == pll2)
232 return; /* already set */
234 if (shift_powerctrl_1 >= 0) {
235 saved_powerctrl_1 = nv_rd32(devinit, 0x001584);
236 nv_wr32(devinit, 0x001584,
237 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
238 1 << shift_powerctrl_1);
241 if (chip_version >= 0x40) {
255 savedc040 = nv_rd32(devinit, 0xc040);
256 if (shift_c040 != 14)
257 nv_wr32(devinit, 0xc040, savedc040 & ~(3 << shift_c040));
260 if (oldramdac580 != ramdac580)
261 nv_wr32(devinit, 0x680580, ramdac580);
264 nv_wr32(devinit, reg2, pll2);
265 nv_wr32(devinit, reg1, pll1);
267 if (shift_powerctrl_1 >= 0)
268 nv_wr32(devinit, 0x001584, saved_powerctrl_1);
269 if (chip_version >= 0x40)
270 nv_wr32(devinit, 0xc040, savedc040);
274 setPLL_double_lowregs(struct nouveau_devinit *devinit, u32 NMNMreg,
275 struct nouveau_pll_vals *pv)
277 /* When setting PLLs, there is a merry game of disabling and enabling
278 * various bits of hardware during the process. This function is a
279 * synthesis of six nv4x traces, nearly each card doing a subtly
280 * different thing. With luck all the necessary bits for each card are
281 * combined herein. Without luck it deviates from each card's formula
282 * so as to not work on any :)
285 uint32_t Preg = NMNMreg - 4;
286 bool mpll = Preg == 0x4020;
287 uint32_t oldPval = nv_rd32(devinit, Preg);
288 uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
289 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |
290 0xc << 28 | pv->log2P << 16;
291 uint32_t saved4600 = 0;
292 /* some cards have different maskc040s */
293 uint32_t maskc040 = ~(3 << 14), savedc040;
294 bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
296 if (nv_rd32(devinit, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
302 maskc040 = ~(0xc << 24);
305 struct nvbios_pll info;
308 if (nvbios_pll_parse(nouveau_bios(devinit), Preg, &info))
311 Pval2 = pv->log2P + info.bias_p;
312 if (Pval2 > info.max_p)
314 Pval |= 1 << 28 | Pval2 << 20;
316 saved4600 = nv_rd32(devinit, 0x4600);
317 nv_wr32(devinit, 0x4600, saved4600 | 8 << 28);
320 Pval |= mpll ? 1 << 12 : 1 << 8;
322 nv_wr32(devinit, Preg, oldPval | 1 << 28);
323 nv_wr32(devinit, Preg, Pval & ~(4 << 28));
326 nv_wr32(devinit, 0x4020, Pval & ~(0xc << 28));
327 nv_wr32(devinit, 0x4038, Pval & ~(0xc << 28));
330 savedc040 = nv_rd32(devinit, 0xc040);
331 nv_wr32(devinit, 0xc040, savedc040 & maskc040);
333 nv_wr32(devinit, NMNMreg, NMNM);
334 if (NMNMreg == 0x4024)
335 nv_wr32(devinit, 0x403c, NMNM);
337 nv_wr32(devinit, Preg, Pval);
340 nv_wr32(devinit, 0x4020, Pval);
341 nv_wr32(devinit, 0x4038, Pval);
342 nv_wr32(devinit, 0x4600, saved4600);
345 nv_wr32(devinit, 0xc040, savedc040);
348 nv_wr32(devinit, 0x4020, Pval & ~(1 << 28));
349 nv_wr32(devinit, 0x4038, Pval & ~(1 << 28));
354 nv04_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
356 struct nouveau_bios *bios = nouveau_bios(devinit);
357 struct nouveau_pll_vals pv;
358 struct nvbios_pll info;
359 int cv = bios->version.chip;
360 int N1, M1, N2, M2, P;
363 ret = nvbios_pll_parse(bios, type > 0x405c ? type : type - 4, &info);
367 ret = nv04_pll_calc(nv_subdev(devinit), &info, freq,
368 &N1, &M1, &N2, &M2, &P);
372 pv.refclk = info.refclk;
379 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
382 setPLL_double_highregs(devinit, type, &pv);
384 setPLL_double_lowregs(devinit, type, &pv);
386 setPLL_single(devinit, type, &pv);
392 nv04_devinit_fini(struct nouveau_object *object, bool suspend)
394 struct nv04_devinit_priv *priv = (void *)object;
396 /* make i2c busses accessible */
397 nv_mask(priv, 0x000200, 0x00000001, 0x00000001);
399 /* unlock extended vga crtc regs, and unslave crtcs */
400 nv_lockvgac(priv, false);
402 priv->owner = nv_rdvgaowner(priv);
403 nv_wrvgaowner(priv, 0);
405 return nouveau_devinit_fini(&priv->base, suspend);
409 nv04_devinit_init(struct nouveau_object *object)
411 struct nv04_devinit_priv *priv = (void *)object;
413 if (!priv->base.post) {
414 u32 htotal = nv_rdvgac(priv, 0, 0x06);
415 htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x01) << 8;
416 htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x20) << 4;
417 htotal |= (nv_rdvgac(priv, 0, 0x25) & 0x01) << 10;
418 htotal |= (nv_rdvgac(priv, 0, 0x41) & 0x01) << 11;
420 nv_info(priv, "adaptor not initialised\n");
421 priv->base.post = true;
425 return nouveau_devinit_init(&priv->base);
429 nv04_devinit_dtor(struct nouveau_object *object)
431 struct nv04_devinit_priv *priv = (void *)object;
433 /* restore vga owner saved at first init, and lock crtc regs */
434 nv_wrvgaowner(priv, priv->owner);
435 nv_lockvgac(priv, true);
437 nouveau_devinit_destroy(&priv->base);
441 nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
442 struct nouveau_oclass *oclass, void *data, u32 size,
443 struct nouveau_object **pobject)
445 struct nv04_devinit_priv *priv;
448 ret = nouveau_devinit_create(parent, engine, oclass, &priv);
449 *pobject = nv_object(priv);
453 priv->base.meminit = nv04_devinit_meminit;
454 priv->base.pll_set = nv04_devinit_pll_set;
459 struct nouveau_oclass
460 nv04_devinit_oclass = {
461 .handle = NV_SUBDEV(DEVINIT, 0x04),
462 .ofuncs = &(struct nouveau_ofuncs) {
463 .ctor = nv04_devinit_ctor,
464 .dtor = nv04_devinit_dtor,
465 .init = nv04_devinit_init,
466 .fini = nv04_devinit_fini,