2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <subdev/gpio.h>
27 #include <subdev/bios.h>
28 #include <subdev/bios/pll.h>
29 #include <subdev/bios/init.h>
30 #include <subdev/bios/rammap.h>
31 #include <subdev/bios/timing.h>
33 #include <subdev/clock.h>
34 #include <subdev/clock/pll.h>
36 #include <subdev/timer.h>
38 #include <core/option.h>
44 /* binary driver only executes this path if the condition (a) is true
45 * for any configuration (combination of rammap+ramcfg+timing) that
46 * can be reached on a given card. for now, we will execute the branch
47 * unconditionally in the hope that a "false everywhere" in the bios
48 * tables doesn't actually mean "don't touch this".
55 struct nvbios_pll refpll;
56 struct nvbios_pll mempll;
58 struct ramfuc_reg r_gpioMV;
60 struct ramfuc_reg r_gpio2E;
62 struct ramfuc_reg r_gpiotrig;
64 struct ramfuc_reg r_0x132020;
65 struct ramfuc_reg r_0x132028;
66 struct ramfuc_reg r_0x132024;
67 struct ramfuc_reg r_0x132030;
68 struct ramfuc_reg r_0x132034;
69 struct ramfuc_reg r_0x132000;
70 struct ramfuc_reg r_0x132004;
71 struct ramfuc_reg r_0x132040;
73 struct ramfuc_reg r_0x10f248;
74 struct ramfuc_reg r_0x10f290;
75 struct ramfuc_reg r_0x10f294;
76 struct ramfuc_reg r_0x10f298;
77 struct ramfuc_reg r_0x10f29c;
78 struct ramfuc_reg r_0x10f2a0;
79 struct ramfuc_reg r_0x10f2a4;
80 struct ramfuc_reg r_0x10f2a8;
81 struct ramfuc_reg r_0x10f2ac;
82 struct ramfuc_reg r_0x10f2cc;
83 struct ramfuc_reg r_0x10f2e8;
84 struct ramfuc_reg r_0x10f250;
85 struct ramfuc_reg r_0x10f24c;
86 struct ramfuc_reg r_0x10fec4;
87 struct ramfuc_reg r_0x10fec8;
88 struct ramfuc_reg r_0x10f604;
89 struct ramfuc_reg r_0x10f614;
90 struct ramfuc_reg r_0x10f610;
91 struct ramfuc_reg r_0x100770;
92 struct ramfuc_reg r_0x100778;
93 struct ramfuc_reg r_0x10f224;
95 struct ramfuc_reg r_0x10f870;
96 struct ramfuc_reg r_0x10f698;
97 struct ramfuc_reg r_0x10f694;
98 struct ramfuc_reg r_0x10f6b8;
99 struct ramfuc_reg r_0x10f808;
100 struct ramfuc_reg r_0x10f670;
101 struct ramfuc_reg r_0x10f60c;
102 struct ramfuc_reg r_0x10f830;
103 struct ramfuc_reg r_0x1373ec;
104 struct ramfuc_reg r_0x10f800;
105 struct ramfuc_reg r_0x10f82c;
107 struct ramfuc_reg r_0x10f978;
108 struct ramfuc_reg r_0x10f910;
109 struct ramfuc_reg r_0x10f914;
111 struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */
113 struct ramfuc_reg r_0x62c000;
115 struct ramfuc_reg r_0x10f200;
117 struct ramfuc_reg r_0x10f210;
118 struct ramfuc_reg r_0x10f310;
119 struct ramfuc_reg r_0x10f314;
120 struct ramfuc_reg r_0x10f318;
121 struct ramfuc_reg r_0x10f090;
122 struct ramfuc_reg r_0x10f69c;
123 struct ramfuc_reg r_0x10f824;
124 struct ramfuc_reg r_0x1373f0;
125 struct ramfuc_reg r_0x1373f4;
126 struct ramfuc_reg r_0x137320;
127 struct ramfuc_reg r_0x10f65c;
128 struct ramfuc_reg r_0x10f6bc;
129 struct ramfuc_reg r_0x100710;
130 struct ramfuc_reg r_0x100750;
134 struct nouveau_ram base;
135 struct nve0_ramfuc fuc;
147 /*******************************************************************************
149 ******************************************************************************/
151 nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data)
153 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
154 u32 addr = 0x110974, i;
156 ram_mask(fuc, 0x10f910, mask, data);
157 ram_mask(fuc, 0x10f914, mask, data);
159 for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) {
160 if (ram->pmask & (1 << i))
162 ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
167 r1373f4_init(struct nve0_ramfuc *fuc)
169 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
170 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
171 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
172 const u32 runk0 = ram->fN1 << 16;
173 const u32 runk1 = ram->fN1;
175 if (ram->from == 2) {
176 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
177 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
179 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
182 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
183 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
185 /* (re)program refpll, if required */
186 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
187 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
188 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
189 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
190 ram_wr32(fuc, 0x137320, 0x00000000);
191 ram_mask(fuc, 0x132030, 0xffff0000, runk0);
192 ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
193 ram_wr32(fuc, 0x132024, rcoef);
194 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
195 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
196 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
197 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
200 /* (re)program mempll, if required */
201 if (ram->mode == 2) {
202 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
203 ram_mask(fuc, 0x132000, 0x80000000, 0x80000000);
204 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
205 ram_mask(fuc, 0x132004, 0x103fffff, mcoef);
206 ram_mask(fuc, 0x132000, 0x00000001, 0x00000001);
207 ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
208 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
210 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100);
213 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
217 r1373f4_fini(struct nve0_ramfuc *fuc)
219 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
220 struct nouveau_ram_data *next = ram->base.next;
221 u8 v0 = next->bios.ramcfg_11_03_c0;
222 u8 v1 = next->bios.ramcfg_11_03_30;
225 tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
226 ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16));
227 ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000);
228 if (ram->mode == 2) {
229 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000002);
230 ram_mask(fuc, 0x1373f4, 0x00001100, 0x000000000);
232 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000001);
233 ram_mask(fuc, 0x1373f4, 0x00010000, 0x000000000);
235 ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4);
239 nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg,
240 u32 _mask, u32 _data, u32 _copy)
242 struct nve0_fb_priv *priv = (void *)nouveau_fb(ram);
243 struct ramfuc *fuc = &ram->fuc.base;
244 u32 addr = 0x110000 + (reg->addr[0] & 0xfff);
245 u32 mask = _mask | _copy;
246 u32 data = (_data & _mask) | (reg->data & _copy);
249 for (i = 0; i < 16; i++, addr += 0x1000) {
250 if (ram->pnuts & (1 << i)) {
251 u32 prev = nv_rd32(priv, addr);
252 u32 next = (prev & ~mask) | data;
253 nouveau_memx_wr32(fuc->memx, addr, next);
257 #define ram_nuts(s,r,m,d,c) \
258 nve0_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c))
261 nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
263 struct nve0_ram *ram = (void *)pfb->ram;
264 struct nve0_ramfuc *fuc = &ram->fuc;
265 struct nouveau_ram_data *next = ram->base.next;
266 int vc = !next->bios.ramcfg_11_02_08;
267 int mv = !next->bios.ramcfg_11_02_04;
270 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
271 ram_wr32(fuc, 0x62c000, 0x0f0f0000);
273 /* MR1: turn termination on early, for some reason.. */
274 if ((ram->base.mr[1] & 0x03c) != 0x030) {
275 ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c);
276 ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000);
279 if (vc == 1 && ram_have(fuc, gpio2E)) {
280 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
281 if (temp != ram_rd32(fuc, gpio2E)) {
282 ram_wr32(fuc, gpiotrig, 1);
283 ram_nsec(fuc, 20000);
287 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
289 nve0_ram_train(fuc, 0x01020000, 0x000c0000);
291 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
293 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
296 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
297 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
298 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
299 ram_wr32(fuc, 0x10f090, 0x00000061);
300 ram_wr32(fuc, 0x10f090, 0xc000007f);
303 ram_wr32(fuc, 0x10f698, 0x00000000);
304 ram_wr32(fuc, 0x10f69c, 0x00000000);
306 /*XXX: there does appear to be some kind of condition here, simply
307 * modifying these bits in the vbios from the default pl0
308 * entries shows no change. however, the data does appear to
309 * be correct and may be required for the transition back
313 if (ram_rd32(fuc, 0x10f978) & 0x00800000)
318 switch (next->bios.ramcfg_11_03_c0) {
319 case 3: data &= ~0x00000040; break;
320 case 2: data &= ~0x00000100; break;
321 case 1: data &= ~0x80000000; break;
322 case 0: data &= ~0x00000400; break;
325 switch (next->bios.ramcfg_11_03_30) {
326 case 3: data &= ~0x00000020; break;
327 case 2: data &= ~0x00000080; break;
328 case 1: data &= ~0x00080000; break;
329 case 0: data &= ~0x00000200; break;
333 if (next->bios.ramcfg_11_02_80)
335 if (next->bios.ramcfg_11_02_40)
337 if (next->bios.ramcfg_11_07_10)
339 if (next->bios.ramcfg_11_07_08)
343 if (ram_rd32(fuc, 0x10f978) & 0x00800000)
346 ram_mask(fuc, 0x10f824, mask, data);
348 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
350 if (ram->from == 2 && ram->mode != 2) {
351 ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
352 ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000);
353 ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004);
354 ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010);
355 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
357 ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001);
359 ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001);
361 if (ram->from != 2 && ram->mode != 2) {
366 if (ram_have(fuc, gpioMV)) {
367 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
368 if (temp != ram_rd32(fuc, gpioMV)) {
369 ram_wr32(fuc, gpiotrig, 1);
370 ram_nsec(fuc, 64000);
374 if (next->bios.ramcfg_11_02_40 ||
375 next->bios.ramcfg_11_07_10) {
376 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
377 ram_nsec(fuc, 20000);
380 if (ram->from != 2 && ram->mode == 2) {
381 if (0 /*XXX: Titan */)
382 ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000);
383 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
384 ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002);
385 ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010);
388 ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000);
389 ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000);
391 if (ram->from == 2 && ram->mode == 2) {
392 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
397 if (ram->mode != 2) /*XXX*/ {
398 if (next->bios.ramcfg_11_07_40)
399 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
402 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
403 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
404 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
406 if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) {
407 ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04);
408 ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04);
410 if (!next->bios.ramcfg_11_07_08) {
411 ram_wr32(fuc, 0x10f698, 0x00000000);
412 ram_wr32(fuc, 0x10f69c, 0x00000000);
415 if (ram->mode != 2) {
416 u32 data = 0x01000100 * next->bios.ramcfg_11_04;
417 ram_nuke(fuc, 0x10f694);
418 ram_mask(fuc, 0x10f694, 0xff00ff00, data);
421 if (ram->mode == 2 && next->bios.ramcfg_11_08_10)
425 ram_mask(fuc, 0x10f60c, 0x00000080, data);
429 if (!next->bios.ramcfg_11_02_80)
431 if (!next->bios.ramcfg_11_02_40)
433 if (!next->bios.ramcfg_11_07_10)
435 if (!next->bios.ramcfg_11_07_08)
439 ram_mask(fuc, 0x10f824, mask, data);
441 if (next->bios.ramcfg_11_01_08)
445 ram_mask(fuc, 0x10f200, 0x00001000, data);
447 if (ram_rd32(fuc, 0x10f670) & 0x80000000) {
448 ram_nsec(fuc, 10000);
449 ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000);
452 if (next->bios.ramcfg_11_08_01)
456 ram_mask(fuc, 0x10f82c, 0x00100000, data);
459 if (next->bios.ramcfg_11_08_08)
461 if (next->bios.ramcfg_11_08_04)
463 if (next->bios.ramcfg_11_08_02)
465 ram_mask(fuc, 0x10f830, 0x00007000, data);
468 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
469 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
470 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
471 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
472 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
473 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
474 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
475 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
476 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
477 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
478 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
480 data = mask = 0x00000000;
481 if (NOTE00(ramcfg_08_20)) {
482 if (next->bios.ramcfg_11_08_20)
486 ram_mask(fuc, 0x10f200, mask, data);
488 data = mask = 0x00000000;
489 if (NOTE00(ramcfg_02_03 != 0)) {
490 data |= next->bios.ramcfg_11_02_03 << 8;
493 if (NOTE00(ramcfg_01_10)) {
494 if (next->bios.ramcfg_11_01_10)
498 ram_mask(fuc, 0x10f604, mask, data);
500 data = mask = 0x00000000;
501 if (NOTE00(timing_30_07 != 0)) {
502 data |= next->bios.timing_20_30_07 << 28;
505 if (NOTE00(ramcfg_01_01)) {
506 if (next->bios.ramcfg_11_01_01)
510 ram_mask(fuc, 0x10f614, mask, data);
512 data = mask = 0x00000000;
513 if (NOTE00(timing_30_07 != 0)) {
514 data |= next->bios.timing_20_30_07 << 28;
517 if (NOTE00(ramcfg_01_02)) {
518 if (next->bios.ramcfg_11_01_02)
522 ram_mask(fuc, 0x10f610, mask, data);
526 if (!next->bios.ramcfg_11_01_04)
528 if (!next->bios.ramcfg_11_07_80)
530 /*XXX: see note above about there probably being some condition
531 * for the 10f824 stuff that uses ramcfg 3...
533 if (next->bios.ramcfg_11_03_f0) {
534 if (next->bios.rammap_11_08_0c) {
535 if (!next->bios.ramcfg_11_07_80)
546 ram_mask(fuc, 0x10f808, mask, data);
548 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
550 data = mask = 0x00000000;
551 if (NOTE00(ramcfg_02_03 != 0)) {
552 data |= next->bios.ramcfg_11_02_03;
555 if (NOTE00(ramcfg_01_10)) {
556 if (next->bios.ramcfg_11_01_10)
561 if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) {
562 ram_mask(fuc, 0x100750, 0x00000008, 0x00000008);
563 ram_wr32(fuc, 0x100710, 0x00000000);
564 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000);
567 data = next->bios.timing_20_30_07 << 8;
568 if (next->bios.ramcfg_11_01_01)
570 ram_mask(fuc, 0x100778, 0x00000700, data);
572 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
573 data = (next->bios.timing[10] & 0x7f000000) >> 24;
574 if (data < next->bios.timing_20_2c_1fc0)
575 data = next->bios.timing_20_2c_1fc0;
576 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
577 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
579 ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 |
580 next->bios.timing_20_31_0780 << 17 |
581 next->bios.timing_20_31_0078 << 8 |
582 next->bios.timing_20_31_0007);
583 ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 |
584 next->bios.timing_20_31_7000);
586 ram_wr32(fuc, 0x10f090, 0x4000007e);
588 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
589 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
590 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
592 if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) {
593 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
594 nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
596 ram_wr32(fuc, 0x10f294, temp);
599 ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]);
600 ram_wr32(fuc, mr[0], ram->base.mr[0]);
601 ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]);
603 ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]);
604 ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */
605 ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]);
606 ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]);
608 if (vc == 0 && ram_have(fuc, gpio2E)) {
609 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
610 if (temp != ram_rd32(fuc, gpio2E)) {
611 ram_wr32(fuc, gpiotrig, 1);
612 ram_nsec(fuc, 20000);
616 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
617 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
618 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
620 ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800);
622 data = ram_rd32(fuc, 0x10f978);
625 if (!next->bios.ramcfg_11_07_08) {
626 if (!next->bios.ramcfg_11_07_04)
633 ram_wr32(fuc, 0x10f978, data);
635 if (ram->mode == 1) {
636 data = ram_rd32(fuc, 0x10f830) | 0x00000001;
637 ram_wr32(fuc, 0x10f830, data);
640 if (!next->bios.ramcfg_11_07_08) {
642 if ( next->bios.ramcfg_11_07_04)
644 if (!next->bios.rammap_11_08_10)
649 nve0_ram_train(fuc, 0xbc0f0000, data);
650 if (1) /* XXX: not always? */
653 if (ram->mode == 2) { /*XXX*/
654 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004);
658 if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5])
661 if (ram->mode != 2) {
662 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
663 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
666 if (next->bios.ramcfg_11_07_02)
667 nve0_ram_train(fuc, 0x80020000, 0x01000000);
669 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
671 if (next->bios.rammap_11_08_01)
675 ram_mask(fuc, 0x10f200, 0x00000800, data);
676 ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800);
680 /*******************************************************************************
682 ******************************************************************************/
685 nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
687 struct nve0_ram *ram = (void *)pfb->ram;
688 struct nve0_ramfuc *fuc = &ram->fuc;
689 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
690 const u32 runk0 = ram->fN1 << 16;
691 const u32 runk1 = ram->fN1;
692 struct nouveau_ram_data *next = ram->base.next;
693 int vc = !next->bios.ramcfg_11_02_08;
694 int mv = !next->bios.ramcfg_11_02_04;
697 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
698 ram_wr32(fuc, 0x62c000, 0x0f0f0000);
700 if (vc == 1 && ram_have(fuc, gpio2E)) {
701 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
702 if (temp != ram_rd32(fuc, gpio2E)) {
703 ram_wr32(fuc, gpiotrig, 1);
704 ram_nsec(fuc, 20000);
708 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
709 if (next->bios.ramcfg_11_03_f0)
710 ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000);
712 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
713 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
714 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
715 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
716 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
717 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
720 ram_wr32(fuc, 0x10f090, 0x00000060);
721 ram_wr32(fuc, 0x10f090, 0xc000007e);
723 /*XXX: there does appear to be some kind of condition here, simply
724 * modifying these bits in the vbios from the default pl0
725 * entries shows no change. however, the data does appear to
726 * be correct and may be required for the transition back
734 switch (next->bios.ramcfg_11_03_c0) {
735 case 3: data &= ~0x00000040; break;
736 case 2: data &= ~0x00000100; break;
737 case 1: data &= ~0x80000000; break;
738 case 0: data &= ~0x00000400; break;
741 switch (next->bios.ramcfg_11_03_30) {
742 case 3: data &= ~0x00000020; break;
743 case 2: data &= ~0x00000080; break;
744 case 1: data &= ~0x00080000; break;
745 case 0: data &= ~0x00000200; break;
749 if (next->bios.ramcfg_11_02_80)
751 if (next->bios.ramcfg_11_02_40)
753 if (next->bios.ramcfg_11_07_10)
755 if (next->bios.ramcfg_11_07_08)
759 ram_mask(fuc, 0x10f824, mask, data);
761 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
763 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
764 data = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
765 data |= next->bios.ramcfg_11_03_30 << 16;
766 ram_wr32(fuc, 0x1373ec, data);
767 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
768 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
770 /* (re)program refpll, if required */
771 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
772 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
773 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
774 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
775 ram_wr32(fuc, 0x137320, 0x00000000);
776 ram_mask(fuc, 0x132030, 0xffff0000, runk0);
777 ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
778 ram_wr32(fuc, 0x132024, rcoef);
779 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
780 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
781 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
782 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
785 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010);
786 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001);
787 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
789 if (ram_have(fuc, gpioMV)) {
790 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
791 if (temp != ram_rd32(fuc, gpioMV)) {
792 ram_wr32(fuc, gpiotrig, 1);
793 ram_nsec(fuc, 64000);
797 if (next->bios.ramcfg_11_02_40 ||
798 next->bios.ramcfg_11_07_10) {
799 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
800 ram_nsec(fuc, 20000);
803 if (ram->mode != 2) /*XXX*/ {
804 if (next->bios.ramcfg_11_07_40)
805 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
808 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
809 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
810 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
814 if (!next->bios.ramcfg_11_02_80)
816 if (!next->bios.ramcfg_11_02_40)
818 if (!next->bios.ramcfg_11_07_10)
820 if (!next->bios.ramcfg_11_07_08)
824 ram_mask(fuc, 0x10f824, mask, data);
827 if (next->bios.ramcfg_11_08_01)
831 ram_mask(fuc, 0x10f82c, 0x00100000, data);
834 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
835 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
836 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
837 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
838 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
839 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
840 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
841 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
842 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
843 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
844 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
848 if (!next->bios.ramcfg_11_01_04)
850 if (!next->bios.ramcfg_11_07_80)
852 /*XXX: see note above about there probably being some condition
853 * for the 10f824 stuff that uses ramcfg 3...
855 if (next->bios.ramcfg_11_03_f0) {
856 if (next->bios.rammap_11_08_0c) {
857 if (!next->bios.ramcfg_11_07_80)
869 ram_mask(fuc, 0x10f808, mask, data);
871 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
873 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
875 data = (next->bios.timing[10] & 0x7f000000) >> 24;
876 if (data < next->bios.timing_20_2c_1fc0)
877 data = next->bios.timing_20_2c_1fc0;
878 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
880 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
882 ram_wr32(fuc, 0x10f090, 0x4000007f);
885 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
886 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
887 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
890 ram_nuke(fuc, mr[0]);
891 ram_mask(fuc, mr[0], 0x100, 0x100);
892 ram_mask(fuc, mr[0], 0x100, 0x000);
894 ram_mask(fuc, mr[2], 0xfff, ram->base.mr[2]);
895 ram_wr32(fuc, mr[0], ram->base.mr[0]);
898 ram_nuke(fuc, mr[0]);
899 ram_mask(fuc, mr[0], 0x100, 0x100);
900 ram_mask(fuc, mr[0], 0x100, 0x000);
902 if (vc == 0 && ram_have(fuc, gpio2E)) {
903 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
904 if (temp != ram_rd32(fuc, gpio2E)) {
905 ram_wr32(fuc, gpiotrig, 1);
906 ram_nsec(fuc, 20000);
910 if (ram->mode != 2) {
911 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
912 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
915 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
916 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
917 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
920 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
922 if (next->bios.rammap_11_08_01)
926 ram_mask(fuc, 0x10f200, 0x00000800, data);
930 /*******************************************************************************
932 ******************************************************************************/
935 nve0_ram_calc_data(struct nouveau_fb *pfb, u32 freq,
936 struct nouveau_ram_data *data)
938 struct nouveau_bios *bios = nouveau_bios(pfb);
939 struct nve0_ram *ram = (void *)pfb->ram;
942 /* lookup memory config data relevant to the target frequency */
943 ram->base.rammap.data = nvbios_rammapEp(bios, freq / 1000,
944 &ram->base.rammap.version,
945 &ram->base.rammap.size,
946 &cnt, &len, &data->bios);
947 if (!ram->base.rammap.data || ram->base.rammap.version != 0x11 ||
948 ram->base.rammap.size < 0x09) {
949 nv_error(pfb, "invalid/missing rammap entry\n");
953 /* locate specific data set for the attached memory */
954 strap = nvbios_ramcfg_index(nv_subdev(pfb));
955 ram->base.ramcfg.data = nvbios_rammapSp(bios, ram->base.rammap.data,
956 ram->base.rammap.version,
957 ram->base.rammap.size,
959 &ram->base.ramcfg.version,
960 &ram->base.ramcfg.size,
962 if (!ram->base.ramcfg.data || ram->base.ramcfg.version != 0x11 ||
963 ram->base.ramcfg.size < 0x08) {
964 nv_error(pfb, "invalid/missing ramcfg entry\n");
968 /* lookup memory timings, if bios says they're present */
969 strap = nv_ro08(bios, ram->base.ramcfg.data + 0x00);
971 ram->base.timing.data =
972 nvbios_timingEp(bios, strap, &ram->base.timing.version,
973 &ram->base.timing.size, &cnt, &len,
975 if (!ram->base.timing.data ||
976 ram->base.timing.version != 0x20 ||
977 ram->base.timing.size < 0x33) {
978 nv_error(pfb, "invalid/missing timing entry\n");
982 ram->base.timing.data = 0;
990 nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next)
992 struct nve0_ram *ram = (void *)pfb->ram;
993 struct nve0_ramfuc *fuc = &ram->fuc;
997 ret = ram_init(fuc, pfb);
1001 ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1;
1002 ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f;
1004 /* XXX: this is *not* what nvidia do. on fermi nvidia generally
1005 * select, based on some unknown condition, one of the two possible
1006 * reference frequencies listed in the vbios table for mempll and
1007 * program refpll to that frequency.
1009 * so far, i've seen very weird values being chosen by nvidia on
1010 * kepler boards, no idea how/why they're chosen.
1012 refclk = next->freq;
1014 refclk = fuc->mempll.refclk;
1016 /* calculate refpll coefficients */
1017 ret = nva3_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1,
1018 &ram->fN1, &ram->M1, &ram->P1);
1019 fuc->mempll.refclk = ret;
1021 nv_error(pfb, "unable to calc refpll\n");
1025 /* calculate mempll coefficients, if we're using it */
1026 if (ram->mode == 2) {
1027 /* post-divider doesn't work... the reg takes the values but
1028 * appears to completely ignore it. there *is* a bit at
1029 * bit 28 that appears to divide the clock by 2 if set.
1031 fuc->mempll.min_p = 1;
1032 fuc->mempll.max_p = 2;
1034 ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq,
1035 &ram->N2, NULL, &ram->M2, &ram->P2);
1037 nv_error(pfb, "unable to calc mempll\n");
1042 for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) {
1043 if (ram_have(fuc, mr[i]))
1044 ram->base.mr[i] = ram_rd32(fuc, mr[i]);
1046 ram->base.freq = next->freq;
1048 switch (ram->base.type) {
1049 case NV_MEM_TYPE_DDR3:
1050 ret = nouveau_sddr3_calc(&ram->base);
1052 ret = nve0_ram_calc_sddr3(pfb, next->freq);
1054 case NV_MEM_TYPE_GDDR5:
1055 ret = nouveau_gddr5_calc(&ram->base, ram->pnuts != 0);
1057 ret = nve0_ram_calc_gddr5(pfb, next->freq);
1068 nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
1070 struct nouveau_clock *clk = nouveau_clock(pfb);
1071 struct nve0_ram *ram = (void *)pfb->ram;
1072 struct nouveau_ram_data *xits = &ram->base.xition;
1073 struct nouveau_ram_data *copy;
1076 if (ram->base.next == NULL) {
1077 ret = nve0_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem),
1082 ret = nve0_ram_calc_data(pfb, freq, &ram->base.target);
1086 if (ram->base.target.freq < ram->base.former.freq) {
1087 *xits = ram->base.target;
1088 copy = &ram->base.former;
1090 *xits = ram->base.former;
1091 copy = &ram->base.target;
1094 xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04;
1095 xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03;
1096 xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07;
1098 ram->base.next = &ram->base.target;
1099 if (memcmp(xits, &ram->base.former, sizeof(xits->bios)))
1100 ram->base.next = &ram->base.xition;
1102 BUG_ON(ram->base.next != &ram->base.xition);
1103 ram->base.next = &ram->base.target;
1106 return nve0_ram_calc_xits(pfb, ram->base.next);
1110 nve0_ram_prog(struct nouveau_fb *pfb)
1112 struct nouveau_device *device = nv_device(pfb);
1113 struct nve0_ram *ram = (void *)pfb->ram;
1114 struct nve0_ramfuc *fuc = &ram->fuc;
1115 ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", true));
1116 return (ram->base.next == &ram->base.xition);
1120 nve0_ram_tidy(struct nouveau_fb *pfb)
1122 struct nve0_ram *ram = (void *)pfb->ram;
1123 struct nve0_ramfuc *fuc = &ram->fuc;
1124 ram->base.next = NULL;
1125 ram_exec(fuc, false);
1129 nve0_ram_init(struct nouveau_object *object)
1131 struct nouveau_fb *pfb = (void *)object->parent;
1132 struct nve0_ram *ram = (void *)object;
1133 struct nouveau_bios *bios = nouveau_bios(pfb);
1134 static const u8 train0[] = {
1135 0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
1136 0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
1138 static const u32 train1[] = {
1139 0x00000000, 0xffffffff,
1140 0x55555555, 0xaaaaaaaa,
1141 0x33333333, 0xcccccccc,
1142 0xf0f0f0f0, 0x0f0f0f0f,
1143 0x00ff00ff, 0xff00ff00,
1144 0x0000ffff, 0xffff0000,
1146 u8 ver, hdr, cnt, len, snr, ssz;
1150 ret = nouveau_ram_init(&ram->base);
1154 /* run a bunch of tables from rammap table. there's actually
1155 * individual pointers for each rammap entry too, but, nvidia
1156 * seem to just run the last two entries' scripts early on in
1157 * their init, and never again.. we'll just run 'em all once
1160 * i strongly suspect that each script is for a separate mode
1161 * (likely selected by 0x10f65c's lower bits?), and the
1162 * binary driver skips the one that's already been setup by
1165 data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
1166 if (!data || hdr < 0x15)
1169 cnt = nv_ro08(bios, data + 0x14); /* guess at count */
1170 data = nv_ro32(bios, data + 0x10); /* guess u32... */
1171 save = nv_rd32(pfb, 0x10f65c);
1172 for (i = 0; i < cnt; i++) {
1173 nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4);
1174 nvbios_exec(&(struct nvbios_init) {
1175 .subdev = nv_subdev(pfb),
1177 .offset = nv_ro32(bios, data), /* guess u32 */
1182 nv_wr32(pfb, 0x10f65c, save);
1183 nv_mask(pfb, 0x10f584, 0x11000000, 0x00000000);
1185 switch (ram->base.type) {
1186 case NV_MEM_TYPE_GDDR5:
1187 for (i = 0; i < 0x30; i++) {
1188 nv_wr32(pfb, 0x10f968, 0x00000000 | (i << 8));
1189 nv_wr32(pfb, 0x10f920, 0x00000000 | train0[i % 12]);
1190 nv_wr32(pfb, 0x10f918, train1[i % 12]);
1191 nv_wr32(pfb, 0x10f920, 0x00000100 | train0[i % 12]);
1192 nv_wr32(pfb, 0x10f918, train1[i % 12]);
1194 nv_wr32(pfb, 0x10f96c, 0x00000000 | (i << 8));
1195 nv_wr32(pfb, 0x10f924, 0x00000000 | train0[i % 12]);
1196 nv_wr32(pfb, 0x10f91c, train1[i % 12]);
1197 nv_wr32(pfb, 0x10f924, 0x00000100 | train0[i % 12]);
1198 nv_wr32(pfb, 0x10f91c, train1[i % 12]);
1201 for (i = 0; i < 0x100; i++) {
1202 nv_wr32(pfb, 0x10f968, i);
1203 nv_wr32(pfb, 0x10f900, train1[2 + (i & 1)]);
1206 for (i = 0; i < 0x100; i++) {
1207 nv_wr32(pfb, 0x10f96c, i);
1208 nv_wr32(pfb, 0x10f900, train1[2 + (i & 1)]);
1219 nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
1220 struct nouveau_oclass *oclass, void *data, u32 size,
1221 struct nouveau_object **pobject)
1223 struct nouveau_fb *pfb = nouveau_fb(parent);
1224 struct nouveau_bios *bios = nouveau_bios(pfb);
1225 struct nouveau_gpio *gpio = nouveau_gpio(pfb);
1226 struct dcb_gpio_func func;
1227 struct nve0_ram *ram;
1231 ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram);
1232 *pobject = nv_object(ram);
1236 switch (ram->base.type) {
1237 case NV_MEM_TYPE_DDR3:
1238 case NV_MEM_TYPE_GDDR5:
1239 ram->base.calc = nve0_ram_calc;
1240 ram->base.prog = nve0_ram_prog;
1241 ram->base.tidy = nve0_ram_tidy;
1244 nv_warn(pfb, "reclocking of this RAM type is unsupported\n");
1248 /* calculate a mask of differently configured memory partitions,
1249 * because, of course reclocking wasn't complicated enough
1250 * already without having to treat some of them differently to
1253 ram->parts = nv_rd32(pfb, 0x022438);
1254 ram->pmask = nv_rd32(pfb, 0x022554);
1256 for (i = 0, tmp = 0; i < ram->parts; i++) {
1257 if (!(ram->pmask & (1 << i))) {
1258 u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000));
1259 if (tmp && tmp != cfg1) {
1260 ram->pnuts |= (1 << i);
1267 // parse bios data for both pll's
1268 ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll);
1270 nv_error(pfb, "mclk refpll data not found\n");
1274 ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll);
1276 nv_error(pfb, "mclk pll data not found\n");
1280 ret = gpio->find(gpio, 0, 0x18, DCB_GPIO_UNUSED, &func);
1282 ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (func.line * 0x04));
1283 ram->fuc.r_funcMV[0] = (func.log[0] ^ 2) << 12;
1284 ram->fuc.r_funcMV[1] = (func.log[1] ^ 2) << 12;
1287 ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
1289 ram->fuc.r_gpio2E = ramfuc_reg(0x00d610 + (func.line * 0x04));
1290 ram->fuc.r_func2E[0] = (func.log[0] ^ 2) << 12;
1291 ram->fuc.r_func2E[1] = (func.log[1] ^ 2) << 12;
1294 ram->fuc.r_gpiotrig = ramfuc_reg(0x00d604);
1296 ram->fuc.r_0x132020 = ramfuc_reg(0x132020);
1297 ram->fuc.r_0x132028 = ramfuc_reg(0x132028);
1298 ram->fuc.r_0x132024 = ramfuc_reg(0x132024);
1299 ram->fuc.r_0x132030 = ramfuc_reg(0x132030);
1300 ram->fuc.r_0x132034 = ramfuc_reg(0x132034);
1301 ram->fuc.r_0x132000 = ramfuc_reg(0x132000);
1302 ram->fuc.r_0x132004 = ramfuc_reg(0x132004);
1303 ram->fuc.r_0x132040 = ramfuc_reg(0x132040);
1305 ram->fuc.r_0x10f248 = ramfuc_reg(0x10f248);
1306 ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);
1307 ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);
1308 ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);
1309 ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);
1310 ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);
1311 ram->fuc.r_0x10f2a4 = ramfuc_reg(0x10f2a4);
1312 ram->fuc.r_0x10f2a8 = ramfuc_reg(0x10f2a8);
1313 ram->fuc.r_0x10f2ac = ramfuc_reg(0x10f2ac);
1314 ram->fuc.r_0x10f2cc = ramfuc_reg(0x10f2cc);
1315 ram->fuc.r_0x10f2e8 = ramfuc_reg(0x10f2e8);
1316 ram->fuc.r_0x10f250 = ramfuc_reg(0x10f250);
1317 ram->fuc.r_0x10f24c = ramfuc_reg(0x10f24c);
1318 ram->fuc.r_0x10fec4 = ramfuc_reg(0x10fec4);
1319 ram->fuc.r_0x10fec8 = ramfuc_reg(0x10fec8);
1320 ram->fuc.r_0x10f604 = ramfuc_reg(0x10f604);
1321 ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);
1322 ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);
1323 ram->fuc.r_0x100770 = ramfuc_reg(0x100770);
1324 ram->fuc.r_0x100778 = ramfuc_reg(0x100778);
1325 ram->fuc.r_0x10f224 = ramfuc_reg(0x10f224);
1327 ram->fuc.r_0x10f870 = ramfuc_reg(0x10f870);
1328 ram->fuc.r_0x10f698 = ramfuc_reg(0x10f698);
1329 ram->fuc.r_0x10f694 = ramfuc_reg(0x10f694);
1330 ram->fuc.r_0x10f6b8 = ramfuc_reg(0x10f6b8);
1331 ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);
1332 ram->fuc.r_0x10f670 = ramfuc_reg(0x10f670);
1333 ram->fuc.r_0x10f60c = ramfuc_reg(0x10f60c);
1334 ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);
1335 ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);
1336 ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);
1337 ram->fuc.r_0x10f82c = ramfuc_reg(0x10f82c);
1339 ram->fuc.r_0x10f978 = ramfuc_reg(0x10f978);
1340 ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);
1341 ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);
1343 switch (ram->base.type) {
1344 case NV_MEM_TYPE_GDDR5:
1345 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1346 ram->fuc.r_mr[1] = ramfuc_reg(0x10f330);
1347 ram->fuc.r_mr[2] = ramfuc_reg(0x10f334);
1348 ram->fuc.r_mr[3] = ramfuc_reg(0x10f338);
1349 ram->fuc.r_mr[4] = ramfuc_reg(0x10f33c);
1350 ram->fuc.r_mr[5] = ramfuc_reg(0x10f340);
1351 ram->fuc.r_mr[6] = ramfuc_reg(0x10f344);
1352 ram->fuc.r_mr[7] = ramfuc_reg(0x10f348);
1353 ram->fuc.r_mr[8] = ramfuc_reg(0x10f354);
1354 ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c);
1356 case NV_MEM_TYPE_DDR3:
1357 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1358 ram->fuc.r_mr[2] = ramfuc_reg(0x10f320);
1364 ram->fuc.r_0x62c000 = ramfuc_reg(0x62c000);
1365 ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);
1366 ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);
1367 ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);
1368 ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);
1369 ram->fuc.r_0x10f318 = ramfuc_reg(0x10f318);
1370 ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);
1371 ram->fuc.r_0x10f69c = ramfuc_reg(0x10f69c);
1372 ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);
1373 ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);
1374 ram->fuc.r_0x1373f4 = ramfuc_reg(0x1373f4);
1375 ram->fuc.r_0x137320 = ramfuc_reg(0x137320);
1376 ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c);
1377 ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc);
1378 ram->fuc.r_0x100710 = ramfuc_reg(0x100710);
1379 ram->fuc.r_0x100750 = ramfuc_reg(0x100750);
1383 struct nouveau_oclass
1386 .ofuncs = &(struct nouveau_ofuncs) {
1387 .ctor = nve0_ram_ctor,
1388 .dtor = _nouveau_ram_dtor,
1389 .init = nve0_ram_init,
1390 .fini = _nouveau_ram_fini,