2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <subdev/gpio.h>
27 #include <subdev/bios.h>
28 #include <subdev/bios/pll.h>
29 #include <subdev/bios/init.h>
30 #include <subdev/bios/rammap.h>
31 #include <subdev/bios/timing.h>
32 #include <subdev/bios/M0205.h>
33 #include <subdev/bios/M0209.h>
35 #include <subdev/clock.h>
36 #include <subdev/clock/pll.h>
38 #include <subdev/timer.h>
40 #include <core/option.h>
46 /* binary driver only executes this path if the condition (a) is true
47 * for any configuration (combination of rammap+ramcfg+timing) that
48 * can be reached on a given card. for now, we will execute the branch
49 * unconditionally in the hope that a "false everywhere" in the bios
50 * tables doesn't actually mean "don't touch this".
57 struct nvbios_pll refpll;
58 struct nvbios_pll mempll;
60 struct ramfuc_reg r_gpioMV;
62 struct ramfuc_reg r_gpio2E;
64 struct ramfuc_reg r_gpiotrig;
66 struct ramfuc_reg r_0x132020;
67 struct ramfuc_reg r_0x132028;
68 struct ramfuc_reg r_0x132024;
69 struct ramfuc_reg r_0x132030;
70 struct ramfuc_reg r_0x132034;
71 struct ramfuc_reg r_0x132000;
72 struct ramfuc_reg r_0x132004;
73 struct ramfuc_reg r_0x132040;
75 struct ramfuc_reg r_0x10f248;
76 struct ramfuc_reg r_0x10f290;
77 struct ramfuc_reg r_0x10f294;
78 struct ramfuc_reg r_0x10f298;
79 struct ramfuc_reg r_0x10f29c;
80 struct ramfuc_reg r_0x10f2a0;
81 struct ramfuc_reg r_0x10f2a4;
82 struct ramfuc_reg r_0x10f2a8;
83 struct ramfuc_reg r_0x10f2ac;
84 struct ramfuc_reg r_0x10f2cc;
85 struct ramfuc_reg r_0x10f2e8;
86 struct ramfuc_reg r_0x10f250;
87 struct ramfuc_reg r_0x10f24c;
88 struct ramfuc_reg r_0x10fec4;
89 struct ramfuc_reg r_0x10fec8;
90 struct ramfuc_reg r_0x10f604;
91 struct ramfuc_reg r_0x10f614;
92 struct ramfuc_reg r_0x10f610;
93 struct ramfuc_reg r_0x100770;
94 struct ramfuc_reg r_0x100778;
95 struct ramfuc_reg r_0x10f224;
97 struct ramfuc_reg r_0x10f870;
98 struct ramfuc_reg r_0x10f698;
99 struct ramfuc_reg r_0x10f694;
100 struct ramfuc_reg r_0x10f6b8;
101 struct ramfuc_reg r_0x10f808;
102 struct ramfuc_reg r_0x10f670;
103 struct ramfuc_reg r_0x10f60c;
104 struct ramfuc_reg r_0x10f830;
105 struct ramfuc_reg r_0x1373ec;
106 struct ramfuc_reg r_0x10f800;
107 struct ramfuc_reg r_0x10f82c;
109 struct ramfuc_reg r_0x10f978;
110 struct ramfuc_reg r_0x10f910;
111 struct ramfuc_reg r_0x10f914;
113 struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */
115 struct ramfuc_reg r_0x62c000;
117 struct ramfuc_reg r_0x10f200;
119 struct ramfuc_reg r_0x10f210;
120 struct ramfuc_reg r_0x10f310;
121 struct ramfuc_reg r_0x10f314;
122 struct ramfuc_reg r_0x10f318;
123 struct ramfuc_reg r_0x10f090;
124 struct ramfuc_reg r_0x10f69c;
125 struct ramfuc_reg r_0x10f824;
126 struct ramfuc_reg r_0x1373f0;
127 struct ramfuc_reg r_0x1373f4;
128 struct ramfuc_reg r_0x137320;
129 struct ramfuc_reg r_0x10f65c;
130 struct ramfuc_reg r_0x10f6bc;
131 struct ramfuc_reg r_0x100710;
132 struct ramfuc_reg r_0x100750;
136 struct nouveau_ram base;
137 struct nve0_ramfuc fuc;
149 /*******************************************************************************
151 ******************************************************************************/
153 nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data)
155 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
156 u32 addr = 0x110974, i;
158 ram_mask(fuc, 0x10f910, mask, data);
159 ram_mask(fuc, 0x10f914, mask, data);
161 for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) {
162 if (ram->pmask & (1 << i))
164 ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
169 r1373f4_init(struct nve0_ramfuc *fuc)
171 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
172 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
173 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
174 const u32 runk0 = ram->fN1 << 16;
175 const u32 runk1 = ram->fN1;
177 if (ram->from == 2) {
178 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
179 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
181 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
184 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
185 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
187 /* (re)program refpll, if required */
188 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
189 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
190 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
191 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
192 ram_wr32(fuc, 0x137320, 0x00000000);
193 ram_mask(fuc, 0x132030, 0xffff0000, runk0);
194 ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
195 ram_wr32(fuc, 0x132024, rcoef);
196 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
197 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
198 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
199 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
202 /* (re)program mempll, if required */
203 if (ram->mode == 2) {
204 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
205 ram_mask(fuc, 0x132000, 0x80000000, 0x80000000);
206 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
207 ram_mask(fuc, 0x132004, 0x103fffff, mcoef);
208 ram_mask(fuc, 0x132000, 0x00000001, 0x00000001);
209 ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
210 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
212 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100);
215 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
219 r1373f4_fini(struct nve0_ramfuc *fuc)
221 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
222 struct nouveau_ram_data *next = ram->base.next;
223 u8 v0 = next->bios.ramcfg_11_03_c0;
224 u8 v1 = next->bios.ramcfg_11_03_30;
227 tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
228 ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16));
229 ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000);
230 if (ram->mode == 2) {
231 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000002);
232 ram_mask(fuc, 0x1373f4, 0x00001100, 0x000000000);
234 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000001);
235 ram_mask(fuc, 0x1373f4, 0x00010000, 0x000000000);
237 ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4);
241 nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg,
242 u32 _mask, u32 _data, u32 _copy)
244 struct nve0_fb_priv *priv = (void *)nouveau_fb(ram);
245 struct ramfuc *fuc = &ram->fuc.base;
246 u32 addr = 0x110000 + (reg->addr[0] & 0xfff);
247 u32 mask = _mask | _copy;
248 u32 data = (_data & _mask) | (reg->data & _copy);
251 for (i = 0; i < 16; i++, addr += 0x1000) {
252 if (ram->pnuts & (1 << i)) {
253 u32 prev = nv_rd32(priv, addr);
254 u32 next = (prev & ~mask) | data;
255 nouveau_memx_wr32(fuc->memx, addr, next);
259 #define ram_nuts(s,r,m,d,c) \
260 nve0_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c))
263 nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
265 struct nve0_ram *ram = (void *)pfb->ram;
266 struct nve0_ramfuc *fuc = &ram->fuc;
267 struct nouveau_ram_data *next = ram->base.next;
268 int vc = !next->bios.ramcfg_11_02_08;
269 int mv = !next->bios.ramcfg_11_02_04;
272 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
273 ram_wr32(fuc, 0x62c000, 0x0f0f0000);
275 /* MR1: turn termination on early, for some reason.. */
276 if ((ram->base.mr[1] & 0x03c) != 0x030) {
277 ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c);
278 ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000);
281 if (vc == 1 && ram_have(fuc, gpio2E)) {
282 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
283 if (temp != ram_rd32(fuc, gpio2E)) {
284 ram_wr32(fuc, gpiotrig, 1);
285 ram_nsec(fuc, 20000);
289 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
291 nve0_ram_train(fuc, 0x01020000, 0x000c0000);
293 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
295 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
298 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
299 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
300 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
301 ram_wr32(fuc, 0x10f090, 0x00000061);
302 ram_wr32(fuc, 0x10f090, 0xc000007f);
305 ram_wr32(fuc, 0x10f698, 0x00000000);
306 ram_wr32(fuc, 0x10f69c, 0x00000000);
308 /*XXX: there does appear to be some kind of condition here, simply
309 * modifying these bits in the vbios from the default pl0
310 * entries shows no change. however, the data does appear to
311 * be correct and may be required for the transition back
315 if (ram_rd32(fuc, 0x10f978) & 0x00800000)
320 switch (next->bios.ramcfg_11_03_c0) {
321 case 3: data &= ~0x00000040; break;
322 case 2: data &= ~0x00000100; break;
323 case 1: data &= ~0x80000000; break;
324 case 0: data &= ~0x00000400; break;
327 switch (next->bios.ramcfg_11_03_30) {
328 case 3: data &= ~0x00000020; break;
329 case 2: data &= ~0x00000080; break;
330 case 1: data &= ~0x00080000; break;
331 case 0: data &= ~0x00000200; break;
335 if (next->bios.ramcfg_11_02_80)
337 if (next->bios.ramcfg_11_02_40)
339 if (next->bios.ramcfg_11_07_10)
341 if (next->bios.ramcfg_11_07_08)
345 if (ram_rd32(fuc, 0x10f978) & 0x00800000)
348 ram_mask(fuc, 0x10f824, mask, data);
350 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
352 if (ram->from == 2 && ram->mode != 2) {
353 ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
354 ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000);
355 ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004);
356 ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010);
357 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
359 ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001);
361 ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001);
363 if (ram->from != 2 && ram->mode != 2) {
368 if (ram_have(fuc, gpioMV)) {
369 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
370 if (temp != ram_rd32(fuc, gpioMV)) {
371 ram_wr32(fuc, gpiotrig, 1);
372 ram_nsec(fuc, 64000);
376 if (next->bios.ramcfg_11_02_40 ||
377 next->bios.ramcfg_11_07_10) {
378 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
379 ram_nsec(fuc, 20000);
382 if (ram->from != 2 && ram->mode == 2) {
383 if (0 /*XXX: Titan */)
384 ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000);
385 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
386 ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002);
387 ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010);
390 ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000);
391 ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000);
393 if (ram->from == 2 && ram->mode == 2) {
394 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
399 if (ram->mode != 2) /*XXX*/ {
400 if (next->bios.ramcfg_11_07_40)
401 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
404 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
405 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
406 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
408 if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) {
409 ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04);
410 ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04);
412 if (!next->bios.ramcfg_11_07_08) {
413 ram_wr32(fuc, 0x10f698, 0x00000000);
414 ram_wr32(fuc, 0x10f69c, 0x00000000);
417 if (ram->mode != 2) {
418 u32 data = 0x01000100 * next->bios.ramcfg_11_04;
419 ram_nuke(fuc, 0x10f694);
420 ram_mask(fuc, 0x10f694, 0xff00ff00, data);
423 if (ram->mode == 2 && next->bios.ramcfg_11_08_10)
427 ram_mask(fuc, 0x10f60c, 0x00000080, data);
431 if (!next->bios.ramcfg_11_02_80)
433 if (!next->bios.ramcfg_11_02_40)
435 if (!next->bios.ramcfg_11_07_10)
437 if (!next->bios.ramcfg_11_07_08)
441 ram_mask(fuc, 0x10f824, mask, data);
443 if (next->bios.ramcfg_11_01_08)
447 ram_mask(fuc, 0x10f200, 0x00001000, data);
449 if (ram_rd32(fuc, 0x10f670) & 0x80000000) {
450 ram_nsec(fuc, 10000);
451 ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000);
454 if (next->bios.ramcfg_11_08_01)
458 ram_mask(fuc, 0x10f82c, 0x00100000, data);
461 if (next->bios.ramcfg_11_08_08)
463 if (next->bios.ramcfg_11_08_04)
465 if (next->bios.ramcfg_11_08_02)
467 ram_mask(fuc, 0x10f830, 0x00007000, data);
470 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
471 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
472 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
473 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
474 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
475 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
476 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
477 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
478 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
479 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
480 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
482 data = mask = 0x00000000;
483 if (NOTE00(ramcfg_08_20)) {
484 if (next->bios.ramcfg_11_08_20)
488 ram_mask(fuc, 0x10f200, mask, data);
490 data = mask = 0x00000000;
491 if (NOTE00(ramcfg_02_03 != 0)) {
492 data |= next->bios.ramcfg_11_02_03 << 8;
495 if (NOTE00(ramcfg_01_10)) {
496 if (next->bios.ramcfg_11_01_10)
500 ram_mask(fuc, 0x10f604, mask, data);
502 data = mask = 0x00000000;
503 if (NOTE00(timing_30_07 != 0)) {
504 data |= next->bios.timing_20_30_07 << 28;
507 if (NOTE00(ramcfg_01_01)) {
508 if (next->bios.ramcfg_11_01_01)
512 ram_mask(fuc, 0x10f614, mask, data);
514 data = mask = 0x00000000;
515 if (NOTE00(timing_30_07 != 0)) {
516 data |= next->bios.timing_20_30_07 << 28;
519 if (NOTE00(ramcfg_01_02)) {
520 if (next->bios.ramcfg_11_01_02)
524 ram_mask(fuc, 0x10f610, mask, data);
528 if (!next->bios.ramcfg_11_01_04)
530 if (!next->bios.ramcfg_11_07_80)
532 /*XXX: see note above about there probably being some condition
533 * for the 10f824 stuff that uses ramcfg 3...
535 if (next->bios.ramcfg_11_03_f0) {
536 if (next->bios.rammap_11_08_0c) {
537 if (!next->bios.ramcfg_11_07_80)
548 ram_mask(fuc, 0x10f808, mask, data);
550 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
552 data = mask = 0x00000000;
553 if (NOTE00(ramcfg_02_03 != 0)) {
554 data |= next->bios.ramcfg_11_02_03;
557 if (NOTE00(ramcfg_01_10)) {
558 if (next->bios.ramcfg_11_01_10)
563 if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) {
564 ram_mask(fuc, 0x100750, 0x00000008, 0x00000008);
565 ram_wr32(fuc, 0x100710, 0x00000000);
566 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000);
569 data = next->bios.timing_20_30_07 << 8;
570 if (next->bios.ramcfg_11_01_01)
572 ram_mask(fuc, 0x100778, 0x00000700, data);
574 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
575 data = (next->bios.timing[10] & 0x7f000000) >> 24;
576 if (data < next->bios.timing_20_2c_1fc0)
577 data = next->bios.timing_20_2c_1fc0;
578 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
579 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
581 ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 |
582 next->bios.timing_20_31_0780 << 17 |
583 next->bios.timing_20_31_0078 << 8 |
584 next->bios.timing_20_31_0007);
585 ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 |
586 next->bios.timing_20_31_7000);
588 ram_wr32(fuc, 0x10f090, 0x4000007e);
590 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
591 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
592 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
594 if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) {
595 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
596 nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
598 ram_wr32(fuc, 0x10f294, temp);
601 ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]);
602 ram_wr32(fuc, mr[0], ram->base.mr[0]);
603 ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]);
605 ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]);
606 ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */
607 ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]);
608 ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]);
610 if (vc == 0 && ram_have(fuc, gpio2E)) {
611 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
612 if (temp != ram_rd32(fuc, gpio2E)) {
613 ram_wr32(fuc, gpiotrig, 1);
614 ram_nsec(fuc, 20000);
618 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
619 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
620 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
622 ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800);
624 data = ram_rd32(fuc, 0x10f978);
627 if (!next->bios.ramcfg_11_07_08) {
628 if (!next->bios.ramcfg_11_07_04)
635 ram_wr32(fuc, 0x10f978, data);
637 if (ram->mode == 1) {
638 data = ram_rd32(fuc, 0x10f830) | 0x00000001;
639 ram_wr32(fuc, 0x10f830, data);
642 if (!next->bios.ramcfg_11_07_08) {
644 if ( next->bios.ramcfg_11_07_04)
646 if (!next->bios.rammap_11_08_10)
651 nve0_ram_train(fuc, 0xbc0f0000, data);
652 if (1) /* XXX: not always? */
655 if (ram->mode == 2) { /*XXX*/
656 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004);
660 if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5])
663 if (ram->mode != 2) {
664 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
665 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
668 if (next->bios.ramcfg_11_07_02)
669 nve0_ram_train(fuc, 0x80020000, 0x01000000);
671 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
673 if (next->bios.rammap_11_08_01)
677 ram_mask(fuc, 0x10f200, 0x00000800, data);
678 ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800);
682 /*******************************************************************************
684 ******************************************************************************/
687 nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
689 struct nve0_ram *ram = (void *)pfb->ram;
690 struct nve0_ramfuc *fuc = &ram->fuc;
691 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
692 const u32 runk0 = ram->fN1 << 16;
693 const u32 runk1 = ram->fN1;
694 struct nouveau_ram_data *next = ram->base.next;
695 int vc = !next->bios.ramcfg_11_02_08;
696 int mv = !next->bios.ramcfg_11_02_04;
699 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
700 ram_wr32(fuc, 0x62c000, 0x0f0f0000);
702 if (vc == 1 && ram_have(fuc, gpio2E)) {
703 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
704 if (temp != ram_rd32(fuc, gpio2E)) {
705 ram_wr32(fuc, gpiotrig, 1);
706 ram_nsec(fuc, 20000);
710 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
711 if (next->bios.ramcfg_11_03_f0)
712 ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000);
714 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
715 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
716 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
717 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
718 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
719 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
722 ram_wr32(fuc, 0x10f090, 0x00000060);
723 ram_wr32(fuc, 0x10f090, 0xc000007e);
725 /*XXX: there does appear to be some kind of condition here, simply
726 * modifying these bits in the vbios from the default pl0
727 * entries shows no change. however, the data does appear to
728 * be correct and may be required for the transition back
736 switch (next->bios.ramcfg_11_03_c0) {
737 case 3: data &= ~0x00000040; break;
738 case 2: data &= ~0x00000100; break;
739 case 1: data &= ~0x80000000; break;
740 case 0: data &= ~0x00000400; break;
743 switch (next->bios.ramcfg_11_03_30) {
744 case 3: data &= ~0x00000020; break;
745 case 2: data &= ~0x00000080; break;
746 case 1: data &= ~0x00080000; break;
747 case 0: data &= ~0x00000200; break;
751 if (next->bios.ramcfg_11_02_80)
753 if (next->bios.ramcfg_11_02_40)
755 if (next->bios.ramcfg_11_07_10)
757 if (next->bios.ramcfg_11_07_08)
761 ram_mask(fuc, 0x10f824, mask, data);
763 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
765 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
766 data = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
767 data |= next->bios.ramcfg_11_03_30 << 16;
768 ram_wr32(fuc, 0x1373ec, data);
769 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
770 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
772 /* (re)program refpll, if required */
773 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
774 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
775 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
776 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
777 ram_wr32(fuc, 0x137320, 0x00000000);
778 ram_mask(fuc, 0x132030, 0xffff0000, runk0);
779 ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
780 ram_wr32(fuc, 0x132024, rcoef);
781 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
782 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
783 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
784 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
787 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010);
788 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001);
789 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
791 if (ram_have(fuc, gpioMV)) {
792 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
793 if (temp != ram_rd32(fuc, gpioMV)) {
794 ram_wr32(fuc, gpiotrig, 1);
795 ram_nsec(fuc, 64000);
799 if (next->bios.ramcfg_11_02_40 ||
800 next->bios.ramcfg_11_07_10) {
801 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
802 ram_nsec(fuc, 20000);
805 if (ram->mode != 2) /*XXX*/ {
806 if (next->bios.ramcfg_11_07_40)
807 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
810 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
811 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
812 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
816 if (!next->bios.ramcfg_11_02_80)
818 if (!next->bios.ramcfg_11_02_40)
820 if (!next->bios.ramcfg_11_07_10)
822 if (!next->bios.ramcfg_11_07_08)
826 ram_mask(fuc, 0x10f824, mask, data);
829 if (next->bios.ramcfg_11_08_01)
833 ram_mask(fuc, 0x10f82c, 0x00100000, data);
836 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
837 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
838 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
839 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
840 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
841 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
842 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
843 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
844 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
845 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
846 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
850 if (!next->bios.ramcfg_11_01_04)
852 if (!next->bios.ramcfg_11_07_80)
854 /*XXX: see note above about there probably being some condition
855 * for the 10f824 stuff that uses ramcfg 3...
857 if (next->bios.ramcfg_11_03_f0) {
858 if (next->bios.rammap_11_08_0c) {
859 if (!next->bios.ramcfg_11_07_80)
871 ram_mask(fuc, 0x10f808, mask, data);
873 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
875 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
877 data = (next->bios.timing[10] & 0x7f000000) >> 24;
878 if (data < next->bios.timing_20_2c_1fc0)
879 data = next->bios.timing_20_2c_1fc0;
880 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
882 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
884 ram_wr32(fuc, 0x10f090, 0x4000007f);
887 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
888 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
889 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
892 ram_nuke(fuc, mr[0]);
893 ram_mask(fuc, mr[0], 0x100, 0x100);
894 ram_mask(fuc, mr[0], 0x100, 0x000);
896 ram_mask(fuc, mr[2], 0xfff, ram->base.mr[2]);
897 ram_wr32(fuc, mr[0], ram->base.mr[0]);
900 ram_nuke(fuc, mr[0]);
901 ram_mask(fuc, mr[0], 0x100, 0x100);
902 ram_mask(fuc, mr[0], 0x100, 0x000);
904 if (vc == 0 && ram_have(fuc, gpio2E)) {
905 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
906 if (temp != ram_rd32(fuc, gpio2E)) {
907 ram_wr32(fuc, gpiotrig, 1);
908 ram_nsec(fuc, 20000);
912 if (ram->mode != 2) {
913 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
914 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
917 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
918 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
919 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
922 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
924 if (next->bios.rammap_11_08_01)
928 ram_mask(fuc, 0x10f200, 0x00000800, data);
932 /*******************************************************************************
934 ******************************************************************************/
937 nve0_ram_calc_data(struct nouveau_fb *pfb, u32 freq,
938 struct nouveau_ram_data *data)
940 struct nouveau_bios *bios = nouveau_bios(pfb);
941 struct nve0_ram *ram = (void *)pfb->ram;
944 /* lookup memory config data relevant to the target frequency */
945 ram->base.rammap.data = nvbios_rammapEp(bios, freq / 1000,
946 &ram->base.rammap.version,
947 &ram->base.rammap.size,
948 &cnt, &len, &data->bios);
949 if (!ram->base.rammap.data || ram->base.rammap.version != 0x11 ||
950 ram->base.rammap.size < 0x09) {
951 nv_error(pfb, "invalid/missing rammap entry\n");
955 /* locate specific data set for the attached memory */
956 strap = nvbios_ramcfg_index(nv_subdev(pfb));
957 ram->base.ramcfg.data = nvbios_rammapSp(bios, ram->base.rammap.data,
958 ram->base.rammap.version,
959 ram->base.rammap.size,
961 &ram->base.ramcfg.version,
962 &ram->base.ramcfg.size,
964 if (!ram->base.ramcfg.data || ram->base.ramcfg.version != 0x11 ||
965 ram->base.ramcfg.size < 0x08) {
966 nv_error(pfb, "invalid/missing ramcfg entry\n");
970 /* lookup memory timings, if bios says they're present */
971 strap = nv_ro08(bios, ram->base.ramcfg.data + 0x00);
973 ram->base.timing.data =
974 nvbios_timingEp(bios, strap, &ram->base.timing.version,
975 &ram->base.timing.size, &cnt, &len,
977 if (!ram->base.timing.data ||
978 ram->base.timing.version != 0x20 ||
979 ram->base.timing.size < 0x33) {
980 nv_error(pfb, "invalid/missing timing entry\n");
984 ram->base.timing.data = 0;
992 nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next)
994 struct nve0_ram *ram = (void *)pfb->ram;
995 struct nve0_ramfuc *fuc = &ram->fuc;
999 ret = ram_init(fuc, pfb);
1003 ram_fb_disable(fuc);
1005 ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1;
1006 ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f;
1008 /* XXX: this is *not* what nvidia do. on fermi nvidia generally
1009 * select, based on some unknown condition, one of the two possible
1010 * reference frequencies listed in the vbios table for mempll and
1011 * program refpll to that frequency.
1013 * so far, i've seen very weird values being chosen by nvidia on
1014 * kepler boards, no idea how/why they're chosen.
1016 refclk = next->freq;
1018 refclk = fuc->mempll.refclk;
1020 /* calculate refpll coefficients */
1021 ret = nva3_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1,
1022 &ram->fN1, &ram->M1, &ram->P1);
1023 fuc->mempll.refclk = ret;
1025 nv_error(pfb, "unable to calc refpll\n");
1029 /* calculate mempll coefficients, if we're using it */
1030 if (ram->mode == 2) {
1031 /* post-divider doesn't work... the reg takes the values but
1032 * appears to completely ignore it. there *is* a bit at
1033 * bit 28 that appears to divide the clock by 2 if set.
1035 fuc->mempll.min_p = 1;
1036 fuc->mempll.max_p = 2;
1038 ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq,
1039 &ram->N2, NULL, &ram->M2, &ram->P2);
1041 nv_error(pfb, "unable to calc mempll\n");
1046 for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) {
1047 if (ram_have(fuc, mr[i]))
1048 ram->base.mr[i] = ram_rd32(fuc, mr[i]);
1050 ram->base.freq = next->freq;
1052 switch (ram->base.type) {
1053 case NV_MEM_TYPE_DDR3:
1054 ret = nouveau_sddr3_calc(&ram->base);
1056 ret = nve0_ram_calc_sddr3(pfb, next->freq);
1058 case NV_MEM_TYPE_GDDR5:
1059 ret = nouveau_gddr5_calc(&ram->base, ram->pnuts != 0);
1061 ret = nve0_ram_calc_gddr5(pfb, next->freq);
1075 nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
1077 struct nouveau_clock *clk = nouveau_clock(pfb);
1078 struct nve0_ram *ram = (void *)pfb->ram;
1079 struct nouveau_ram_data *xits = &ram->base.xition;
1080 struct nouveau_ram_data *copy;
1083 if (ram->base.next == NULL) {
1084 ret = nve0_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem),
1089 ret = nve0_ram_calc_data(pfb, freq, &ram->base.target);
1093 if (ram->base.target.freq < ram->base.former.freq) {
1094 *xits = ram->base.target;
1095 copy = &ram->base.former;
1097 *xits = ram->base.former;
1098 copy = &ram->base.target;
1101 xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04;
1102 xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03;
1103 xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07;
1105 ram->base.next = &ram->base.target;
1106 if (memcmp(xits, &ram->base.former, sizeof(xits->bios)))
1107 ram->base.next = &ram->base.xition;
1109 BUG_ON(ram->base.next != &ram->base.xition);
1110 ram->base.next = &ram->base.target;
1113 return nve0_ram_calc_xits(pfb, ram->base.next);
1117 nve0_ram_prog(struct nouveau_fb *pfb)
1119 struct nouveau_device *device = nv_device(pfb);
1120 struct nve0_ram *ram = (void *)pfb->ram;
1121 struct nve0_ramfuc *fuc = &ram->fuc;
1122 ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", true));
1123 return (ram->base.next == &ram->base.xition);
1127 nve0_ram_tidy(struct nouveau_fb *pfb)
1129 struct nve0_ram *ram = (void *)pfb->ram;
1130 struct nve0_ramfuc *fuc = &ram->fuc;
1131 ram->base.next = NULL;
1132 ram_exec(fuc, false);
1135 struct nve0_ram_train {
1137 struct nvbios_M0209S remap;
1138 struct nvbios_M0209S type00;
1139 struct nvbios_M0209S type01;
1140 struct nvbios_M0209S type04;
1141 struct nvbios_M0209S type06;
1142 struct nvbios_M0209S type07;
1143 struct nvbios_M0209S type08;
1144 struct nvbios_M0209S type09;
1148 nve0_ram_train_type(struct nouveau_fb *pfb, int i, u8 ramcfg,
1149 struct nve0_ram_train *train)
1151 struct nouveau_bios *bios = nouveau_bios(pfb);
1152 struct nvbios_M0205E M0205E;
1153 struct nvbios_M0205S M0205S;
1154 struct nvbios_M0209E M0209E;
1155 struct nvbios_M0209S *remap = &train->remap;
1156 struct nvbios_M0209S *value;
1157 u8 ver, hdr, cnt, len;
1160 /* determine type of data for this index */
1161 if (!(data = nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E)))
1164 switch (M0205E.type) {
1165 case 0x00: value = &train->type00; break;
1166 case 0x01: value = &train->type01; break;
1167 case 0x04: value = &train->type04; break;
1168 case 0x06: value = &train->type06; break;
1169 case 0x07: value = &train->type07; break;
1170 case 0x08: value = &train->type08; break;
1171 case 0x09: value = &train->type09; break;
1176 /* training data index determined by ramcfg strap */
1177 if (!(data = nvbios_M0205Sp(bios, i, ramcfg, &ver, &hdr, &M0205S)))
1181 /* training data format information */
1182 if (!(data = nvbios_M0209Ep(bios, i, &ver, &hdr, &cnt, &len, &M0209E)))
1185 /* ... and the raw data */
1186 if (!(data = nvbios_M0209Sp(bios, i, 0, &ver, &hdr, value)))
1189 if (M0209E.v02_07 == 2) {
1190 /* of course! why wouldn't we have a pointer to another entry
1191 * in the same table, and use the first one as an array of
1194 if (!(data = nvbios_M0209Sp(bios, M0209E.v03, 0, &ver, &hdr,
1198 for (i = 0; i < ARRAY_SIZE(value->data); i++)
1199 value->data[i] = remap->data[value->data[i]];
1201 if (M0209E.v02_07 != 1)
1204 train->mask |= 1 << M0205E.type;
1209 nve0_ram_train_init_0(struct nouveau_fb *pfb, struct nve0_ram_train *train)
1213 if ((train->mask & 0x03d3) != 0x03d3) {
1214 nv_warn(pfb, "missing link training data\n");
1218 for (i = 0; i < 0x30; i++) {
1219 for (j = 0; j < 8; j += 4) {
1220 nv_wr32(pfb, 0x10f968 + j, 0x00000000 | (i << 8));
1221 nv_wr32(pfb, 0x10f920 + j, 0x00000000 |
1222 train->type08.data[i] << 4 |
1223 train->type06.data[i]);
1224 nv_wr32(pfb, 0x10f918 + j, train->type00.data[i]);
1225 nv_wr32(pfb, 0x10f920 + j, 0x00000100 |
1226 train->type09.data[i] << 4 |
1227 train->type07.data[i]);
1228 nv_wr32(pfb, 0x10f918 + j, train->type01.data[i]);
1232 for (j = 0; j < 8; j += 4) {
1233 for (i = 0; i < 0x100; i++) {
1234 nv_wr32(pfb, 0x10f968 + j, i);
1235 nv_wr32(pfb, 0x10f900 + j, train->type04.data[i]);
1243 nve0_ram_train_init(struct nouveau_fb *pfb)
1245 u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb));
1246 struct nve0_ram_train *train;
1247 int ret = -ENOMEM, i;
1249 if ((train = kzalloc(sizeof(*train), GFP_KERNEL))) {
1250 for (i = 0; i < 0x100; i++) {
1251 ret = nve0_ram_train_type(pfb, i, ramcfg, train);
1252 if (ret && ret != -ENOENT)
1257 switch (pfb->ram->type) {
1258 case NV_MEM_TYPE_GDDR5:
1259 ret = nve0_ram_train_init_0(pfb, train);
1271 nve0_ram_init(struct nouveau_object *object)
1273 struct nouveau_fb *pfb = (void *)object->parent;
1274 struct nve0_ram *ram = (void *)object;
1275 struct nouveau_bios *bios = nouveau_bios(pfb);
1276 u8 ver, hdr, cnt, len, snr, ssz;
1280 ret = nouveau_ram_init(&ram->base);
1284 /* run a bunch of tables from rammap table. there's actually
1285 * individual pointers for each rammap entry too, but, nvidia
1286 * seem to just run the last two entries' scripts early on in
1287 * their init, and never again.. we'll just run 'em all once
1290 * i strongly suspect that each script is for a separate mode
1291 * (likely selected by 0x10f65c's lower bits?), and the
1292 * binary driver skips the one that's already been setup by
1295 data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
1296 if (!data || hdr < 0x15)
1299 cnt = nv_ro08(bios, data + 0x14); /* guess at count */
1300 data = nv_ro32(bios, data + 0x10); /* guess u32... */
1301 save = nv_rd32(pfb, 0x10f65c) & 0x000000f0;
1302 for (i = 0; i < cnt; i++, data += 4) {
1303 if (i != save >> 4) {
1304 nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4);
1305 nvbios_exec(&(struct nvbios_init) {
1306 .subdev = nv_subdev(pfb),
1308 .offset = nv_ro32(bios, data),
1313 nv_mask(pfb, 0x10f65c, 0x000000f0, save);
1314 nv_mask(pfb, 0x10f584, 0x11000000, 0x00000000);
1315 nv_wr32(pfb, 0x10ecc0, 0xffffffff);
1316 nv_mask(pfb, 0x10f160, 0x00000010, 0x00000010);
1318 return nve0_ram_train_init(pfb);
1322 nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
1323 struct nouveau_oclass *oclass, void *data, u32 size,
1324 struct nouveau_object **pobject)
1326 struct nouveau_fb *pfb = nouveau_fb(parent);
1327 struct nouveau_bios *bios = nouveau_bios(pfb);
1328 struct nouveau_gpio *gpio = nouveau_gpio(pfb);
1329 struct dcb_gpio_func func;
1330 struct nve0_ram *ram;
1334 ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram);
1335 *pobject = nv_object(ram);
1339 switch (ram->base.type) {
1340 case NV_MEM_TYPE_DDR3:
1341 case NV_MEM_TYPE_GDDR5:
1342 ram->base.calc = nve0_ram_calc;
1343 ram->base.prog = nve0_ram_prog;
1344 ram->base.tidy = nve0_ram_tidy;
1347 nv_warn(pfb, "reclocking of this RAM type is unsupported\n");
1351 /* calculate a mask of differently configured memory partitions,
1352 * because, of course reclocking wasn't complicated enough
1353 * already without having to treat some of them differently to
1356 ram->parts = nv_rd32(pfb, 0x022438);
1357 ram->pmask = nv_rd32(pfb, 0x022554);
1359 for (i = 0, tmp = 0; i < ram->parts; i++) {
1360 if (!(ram->pmask & (1 << i))) {
1361 u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000));
1362 if (tmp && tmp != cfg1) {
1363 ram->pnuts |= (1 << i);
1370 // parse bios data for both pll's
1371 ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll);
1373 nv_error(pfb, "mclk refpll data not found\n");
1377 ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll);
1379 nv_error(pfb, "mclk pll data not found\n");
1383 ret = gpio->find(gpio, 0, 0x18, DCB_GPIO_UNUSED, &func);
1385 ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (func.line * 0x04));
1386 ram->fuc.r_funcMV[0] = (func.log[0] ^ 2) << 12;
1387 ram->fuc.r_funcMV[1] = (func.log[1] ^ 2) << 12;
1390 ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
1392 ram->fuc.r_gpio2E = ramfuc_reg(0x00d610 + (func.line * 0x04));
1393 ram->fuc.r_func2E[0] = (func.log[0] ^ 2) << 12;
1394 ram->fuc.r_func2E[1] = (func.log[1] ^ 2) << 12;
1397 ram->fuc.r_gpiotrig = ramfuc_reg(0x00d604);
1399 ram->fuc.r_0x132020 = ramfuc_reg(0x132020);
1400 ram->fuc.r_0x132028 = ramfuc_reg(0x132028);
1401 ram->fuc.r_0x132024 = ramfuc_reg(0x132024);
1402 ram->fuc.r_0x132030 = ramfuc_reg(0x132030);
1403 ram->fuc.r_0x132034 = ramfuc_reg(0x132034);
1404 ram->fuc.r_0x132000 = ramfuc_reg(0x132000);
1405 ram->fuc.r_0x132004 = ramfuc_reg(0x132004);
1406 ram->fuc.r_0x132040 = ramfuc_reg(0x132040);
1408 ram->fuc.r_0x10f248 = ramfuc_reg(0x10f248);
1409 ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);
1410 ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);
1411 ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);
1412 ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);
1413 ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);
1414 ram->fuc.r_0x10f2a4 = ramfuc_reg(0x10f2a4);
1415 ram->fuc.r_0x10f2a8 = ramfuc_reg(0x10f2a8);
1416 ram->fuc.r_0x10f2ac = ramfuc_reg(0x10f2ac);
1417 ram->fuc.r_0x10f2cc = ramfuc_reg(0x10f2cc);
1418 ram->fuc.r_0x10f2e8 = ramfuc_reg(0x10f2e8);
1419 ram->fuc.r_0x10f250 = ramfuc_reg(0x10f250);
1420 ram->fuc.r_0x10f24c = ramfuc_reg(0x10f24c);
1421 ram->fuc.r_0x10fec4 = ramfuc_reg(0x10fec4);
1422 ram->fuc.r_0x10fec8 = ramfuc_reg(0x10fec8);
1423 ram->fuc.r_0x10f604 = ramfuc_reg(0x10f604);
1424 ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);
1425 ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);
1426 ram->fuc.r_0x100770 = ramfuc_reg(0x100770);
1427 ram->fuc.r_0x100778 = ramfuc_reg(0x100778);
1428 ram->fuc.r_0x10f224 = ramfuc_reg(0x10f224);
1430 ram->fuc.r_0x10f870 = ramfuc_reg(0x10f870);
1431 ram->fuc.r_0x10f698 = ramfuc_reg(0x10f698);
1432 ram->fuc.r_0x10f694 = ramfuc_reg(0x10f694);
1433 ram->fuc.r_0x10f6b8 = ramfuc_reg(0x10f6b8);
1434 ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);
1435 ram->fuc.r_0x10f670 = ramfuc_reg(0x10f670);
1436 ram->fuc.r_0x10f60c = ramfuc_reg(0x10f60c);
1437 ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);
1438 ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);
1439 ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);
1440 ram->fuc.r_0x10f82c = ramfuc_reg(0x10f82c);
1442 ram->fuc.r_0x10f978 = ramfuc_reg(0x10f978);
1443 ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);
1444 ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);
1446 switch (ram->base.type) {
1447 case NV_MEM_TYPE_GDDR5:
1448 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1449 ram->fuc.r_mr[1] = ramfuc_reg(0x10f330);
1450 ram->fuc.r_mr[2] = ramfuc_reg(0x10f334);
1451 ram->fuc.r_mr[3] = ramfuc_reg(0x10f338);
1452 ram->fuc.r_mr[4] = ramfuc_reg(0x10f33c);
1453 ram->fuc.r_mr[5] = ramfuc_reg(0x10f340);
1454 ram->fuc.r_mr[6] = ramfuc_reg(0x10f344);
1455 ram->fuc.r_mr[7] = ramfuc_reg(0x10f348);
1456 ram->fuc.r_mr[8] = ramfuc_reg(0x10f354);
1457 ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c);
1459 case NV_MEM_TYPE_DDR3:
1460 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1461 ram->fuc.r_mr[2] = ramfuc_reg(0x10f320);
1467 ram->fuc.r_0x62c000 = ramfuc_reg(0x62c000);
1468 ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);
1469 ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);
1470 ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);
1471 ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);
1472 ram->fuc.r_0x10f318 = ramfuc_reg(0x10f318);
1473 ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);
1474 ram->fuc.r_0x10f69c = ramfuc_reg(0x10f69c);
1475 ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);
1476 ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);
1477 ram->fuc.r_0x1373f4 = ramfuc_reg(0x1373f4);
1478 ram->fuc.r_0x137320 = ramfuc_reg(0x137320);
1479 ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c);
1480 ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc);
1481 ram->fuc.r_0x100710 = ramfuc_reg(0x100710);
1482 ram->fuc.r_0x100750 = ramfuc_reg(0x100750);
1486 struct nouveau_oclass
1489 .ofuncs = &(struct nouveau_ofuncs) {
1490 .ctor = nve0_ram_ctor,
1491 .dtor = _nouveau_ram_dtor,
1492 .init = nve0_ram_init,
1493 .fini = _nouveau_ram_fini,