2 * Copyright 2014 Roy Spliet
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Roy Spliet <rspliet@eclipso.eu>
26 #include <subdev/bios.h>
35 ramxlat(const struct ramxlat *xlat, int id)
37 while (xlat->id >= 0) {
45 static const struct ramxlat
47 { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 },
48 /* The following are available in some, but not all DDR2 docs */
53 static const struct ramxlat
55 { 2, 1 }, { 3, 2 }, { 4, 3 }, { 5, 4 }, { 6, 5 },
56 /* The following are available in some, but not all DDR2 docs */
62 nouveau_sddr2_calc(struct nouveau_ram *ram)
64 struct nouveau_bios *bios = nouveau_bios(ram);
65 int CL, WR, DLL = 0, ODT = 0;
67 switch (!!ram->timing.data * ram->timing.version) {
69 CL = nv_ro08(bios, ram->timing.data + 0x02);
70 WR = nv_ro08(bios, ram->timing.data + 0x00);
71 DLL = !(nv_ro08(bios, ram->ramcfg.data + 0x02) & 0x40);
72 ODT = nv_ro08(bios, ram->timing.data + 0x0e) & 0x03;
75 CL = nv_ro08(bios, ram->timing.data + 0x04) & 0x1f;
76 WR = nv_ro08(bios, ram->timing.data + 0x0a) & 0x7f;
82 CL = ramxlat(ramddr2_cl, CL);
83 WR = ramxlat(ramddr2_wr, WR);
88 ram->mr[0] |= (WR & 0x07) << 9;
89 ram->mr[0] |= (CL & 0x07) << 4;
92 ram->mr[1] |= (ODT & 0x1) << 2;
93 ram->mr[1] |= (ODT & 0x2) << 5;