drivers/gpu/drm/nouveau/core/subdev/therm/nv40.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *          Martin Peres
  24  */
  25
  26 #include "priv.h"
  27
  28 struct nv40_therm_priv {
  29         struct nouveau_therm_priv base;
  30 };
  31
  32 enum nv40_sensor_style { INVALID_STYLE = -1, OLD_STYLE = 0, NEW_STYLE = 1 };
  33
  34 static enum nv40_sensor_style
  35 nv40_sensor_style(struct nouveau_therm *therm)
  36 {
  37         struct nouveau_device *device = nv_device(therm);
  38
  39         switch (device->chipset) {
  40         case 0x43:
  41         case 0x44:
  42         case 0x4a:
  43         case 0x47:
  44                 return OLD_STYLE;
  45
  46         case 0x46:
  47         case 0x49:
  48         case 0x4b:
  49         case 0x4e:
  50         case 0x4c:
  51         case 0x67:
  52         case 0x68:
  53         case 0x63:
  54                 return NEW_STYLE;
  55         default:
  56                 return INVALID_STYLE;
  57         }
  58 }
  59
  60 static int
  61 nv40_sensor_setup(struct nouveau_therm *therm)
  62 {
  63         enum nv40_sensor_style style = nv40_sensor_style(therm);
  64
  65         /* enable ADC readout and disable the ALARM threshold */
  66         if (style == NEW_STYLE) {
  67                 nv_mask(therm, 0x15b8, 0x80000000, 0);
  68                 nv_wr32(therm, 0x15b0, 0x80003fff);
  69                 mdelay(20); /* wait for the temperature to stabilize */
  70                 return nv_rd32(therm, 0x15b4) & 0x3fff;
  71         } else if (style == OLD_STYLE) {
  72                 nv_wr32(therm, 0x15b0, 0xff);
  73                 mdelay(20); /* wait for the temperature to stabilize */
  74                 return nv_rd32(therm, 0x15b4) & 0xff;
  75         } else
  76                 return -ENODEV;
  77 }
  78
  79 static int
  80 nv40_temp_get(struct nouveau_therm *therm)
  81 {
  82         struct nouveau_therm_priv *priv = (void *)therm;
  83         struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
  84         enum nv40_sensor_style style = nv40_sensor_style(therm);
  85         int core_temp;
  86
  87         if (style == NEW_STYLE) {
  88                 nv_wr32(therm, 0x15b0, 0x80003fff);
  89                 core_temp = nv_rd32(therm, 0x15b4) & 0x3fff;
  90         } else if (style == OLD_STYLE) {
  91                 nv_wr32(therm, 0x15b0, 0xff);
  92                 core_temp = nv_rd32(therm, 0x15b4) & 0xff;
  93         } else
  94                 return -ENODEV;
  95
  96         /* if the slope or the offset is unset, do no use the sensor */
  97         if (!sensor->slope_div || !sensor->slope_mult ||
  98             !sensor->offset_num || !sensor->offset_den)
  99             return -ENODEV;
 100
 101         core_temp = core_temp * sensor->slope_mult / sensor->slope_div;
 102         core_temp = core_temp + sensor->offset_num / sensor->offset_den;
 103         core_temp = core_temp + sensor->offset_constant - 8;
 104
 105         /* reserve negative temperatures for errors */
 106         if (core_temp < 0)
 107                 core_temp = 0;
 108
 109         return core_temp;
 110 }
 111
 112 static int
 113 nv40_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
 114 {
 115         u32 mask = enable ? 0x80000000 : 0x0000000;
 116         if      (line == 2) nv_mask(therm, 0x0010f0, 0x80000000, mask);
 117         else if (line == 9) nv_mask(therm, 0x0015f4, 0x80000000, mask);
 118         else {
 119                 nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);
 120                 return -ENODEV;
 121         }
 122         return 0;
 123 }
 124
 125 static int
 126 nv40_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
 127 {
 128         if (line == 2) {
 129                 u32 reg = nv_rd32(therm, 0x0010f0);
 130                 if (reg & 0x80000000) {
 131                         *duty = (reg & 0x7fff0000) >> 16;
 132                         *divs = (reg & 0x00007fff);
 133                         return 0;
 134                 }
 135         } else
 136         if (line == 9) {
 137                 u32 reg = nv_rd32(therm, 0x0015f4);
 138                 if (reg & 0x80000000) {
 139                         *divs = nv_rd32(therm, 0x0015f8);
 140                         *duty = (reg & 0x7fffffff);
 141                         return 0;
 142                 }
 143         } else {
 144                 nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);
 145                 return -ENODEV;
 146         }
 147
 148         return -EINVAL;
 149 }
 150
 151 static int
 152 nv40_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
 153 {
 154         if (line == 2) {
 155                 nv_mask(therm, 0x0010f0, 0x7fff7fff, (duty << 16) | divs);
 156         } else
 157         if (line == 9) {
 158                 nv_wr32(therm, 0x0015f8, divs);
 159                 nv_mask(therm, 0x0015f4, 0x7fffffff, duty);
 160         } else {
 161                 nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);
 162                 return -ENODEV;
 163         }
 164
 165         return 0;
 166 }
 167
 168 void
 169 nv40_therm_intr(struct nouveau_subdev *subdev)
 170 {
 171         struct nouveau_therm *therm = nouveau_therm(subdev);
 172         uint32_t stat = nv_rd32(therm, 0x1100);
 173
 174         /* traitement */
 175
 176         /* ack all IRQs */
 177         nv_wr32(therm, 0x1100, 0x70000);
 178
 179         nv_error(therm, "THERM received an IRQ: stat = %x\n", stat);
 180 }
 181
 182 static int
 183 nv40_therm_ctor(struct nouveau_object *parent,
 184                 struct nouveau_object *engine,
 185                 struct nouveau_oclass *oclass, void *data, u32 size,
 186                 struct nouveau_object **pobject)
 187 {
 188         struct nv40_therm_priv *priv;
 189         int ret;
 190
 191         ret = nouveau_therm_create(parent, engine, oclass, &priv);
 192         *pobject = nv_object(priv);
 193         if (ret)
 194                 return ret;
 195
 196         priv->base.base.pwm_ctrl = nv40_fan_pwm_ctrl;
 197         priv->base.base.pwm_get = nv40_fan_pwm_get;
 198         priv->base.base.pwm_set = nv40_fan_pwm_set;
 199         priv->base.base.temp_get = nv40_temp_get;
 200         priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
 201         nv_subdev(priv)->intr = nv40_therm_intr;
 202         return nouveau_therm_preinit(&priv->base.base);
 203 }
 204
 205 static int
 206 nv40_therm_init(struct nouveau_object *object)
 207 {
 208         struct nouveau_therm *therm = (void *)object;
 209
 210         nv40_sensor_setup(therm);
 211
 212         return _nouveau_therm_init(object);
 213 }
 214
 215 struct nouveau_oclass
 216 nv40_therm_oclass = {
 217         .handle = NV_SUBDEV(THERM, 0x40),
 218         .ofuncs = &(struct nouveau_ofuncs) {
 219                 .ctor = nv40_therm_ctor,
 220                 .dtor = _nouveau_therm_dtor,
 221                 .init = nv40_therm_init,
 222                 .fini = _nouveau_therm_fini,
 223         },
 224 };