drivers/gpu/drm/nouveau/nouveau_bo.c

   1 /*
   2  * Copyright 2007 Dave Airlied
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * Authors: Dave Airlied <airlied@linux.ie>
  26  *          Ben Skeggs   <darktama@iinet.net.au>
  27  *          Jeremy Kolb  <jkolb@brandeis.edu>
  28  */
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/swiotlb.h>
  32
  33 #include "nouveau_drm.h"
  34 #include "nouveau_dma.h"
  35 #include "nouveau_fence.h"
  36
  37 #include "nouveau_bo.h"
  38 #include "nouveau_ttm.h"
  39 #include "nouveau_gem.h"
  40
  41 /*
  42  * NV10-NV40 tiling helpers
  43  */
  44
  45 static void
  46 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
  47                            u32 addr, u32 size, u32 pitch, u32 flags)
  48 {
  49         struct nouveau_drm *drm = nouveau_drm(dev);
  50         int i = reg - drm->tile.reg;
  51         struct nvkm_device *device = nvxx_device(&drm->device);
  52         struct nvkm_fb *fb = device->fb;
  53         struct nvkm_fb_tile *tile = &fb->tile.region[i];
  54
  55         nouveau_fence_unref(&reg->fence);
  56
  57         if (tile->pitch)
  58                 nvkm_fb_tile_fini(fb, i, tile);
  59
  60         if (pitch)
  61                 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
  62
  63         nvkm_fb_tile_prog(fb, i, tile);
  64 }
  65
  66 static struct nouveau_drm_tile *
  67 nv10_bo_get_tile_region(struct drm_device *dev, int i)
  68 {
  69         struct nouveau_drm *drm = nouveau_drm(dev);
  70         struct nouveau_drm_tile *tile = &drm->tile.reg[i];
  71
  72         spin_lock(&drm->tile.lock);
  73
  74         if (!tile->used &&
  75             (!tile->fence || nouveau_fence_done(tile->fence)))
  76                 tile->used = true;
  77         else
  78                 tile = NULL;
  79
  80         spin_unlock(&drm->tile.lock);
  81         return tile;
  82 }
  83
  84 static void
  85 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
  86                         struct fence *fence)
  87 {
  88         struct nouveau_drm *drm = nouveau_drm(dev);
  89
  90         if (tile) {
  91                 spin_lock(&drm->tile.lock);
  92                 tile->fence = (struct nouveau_fence *)fence_get(fence);
  93                 tile->used = false;
  94                 spin_unlock(&drm->tile.lock);
  95         }
  96 }
  97
  98 static struct nouveau_drm_tile *
  99 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
 100                    u32 size, u32 pitch, u32 flags)
 101 {
 102         struct nouveau_drm *drm = nouveau_drm(dev);
 103         struct nvkm_fb *fb = nvxx_fb(&drm->device);
 104         struct nouveau_drm_tile *tile, *found = NULL;
 105         int i;
 106
 107         for (i = 0; i < fb->tile.regions; i++) {
 108                 tile = nv10_bo_get_tile_region(dev, i);
 109
 110                 if (pitch && !found) {
 111                         found = tile;
 112                         continue;
 113
 114                 } else if (tile && fb->tile.region[i].pitch) {
 115                         /* Kill an unused tile region. */
 116                         nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
 117                 }
 118
 119                 nv10_bo_put_tile_region(dev, tile, NULL);
 120         }
 121
 122         if (found)
 123                 nv10_bo_update_tile_region(dev, found, addr, size,
 124                                             pitch, flags);
 125         return found;
 126 }
 127
 128 static void
 129 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
 130 {
 131         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 132         struct drm_device *dev = drm->dev;
 133         struct nouveau_bo *nvbo = nouveau_bo(bo);
 134
 135         if (unlikely(nvbo->gem.filp))
 136                 DRM_ERROR("bo %p still attached to GEM object\n", bo);
 137         WARN_ON(nvbo->pin_refcnt > 0);
 138         nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
 139         kfree(nvbo);
 140 }
 141
 142 static void
 143 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
 144                        int *align, int *size)
 145 {
 146         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 147         struct nvif_device *device = &drm->device;
 148
 149         if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
 150                 if (nvbo->tile_mode) {
 151                         if (device->info.chipset >= 0x40) {
 152                                 *align = 65536;
 153                                 *size = roundup(*size, 64 * nvbo->tile_mode);
 154
 155                         } else if (device->info.chipset >= 0x30) {
 156                                 *align = 32768;
 157                                 *size = roundup(*size, 64 * nvbo->tile_mode);
 158
 159                         } else if (device->info.chipset >= 0x20) {
 160                                 *align = 16384;
 161                                 *size = roundup(*size, 64 * nvbo->tile_mode);
 162
 163                         } else if (device->info.chipset >= 0x10) {
 164                                 *align = 16384;
 165                                 *size = roundup(*size, 32 * nvbo->tile_mode);
 166                         }
 167                 }
 168         } else {
 169                 *size = roundup(*size, (1 << nvbo->page_shift));
 170                 *align = max((1 <<  nvbo->page_shift), *align);
 171         }
 172
 173         *size = roundup(*size, PAGE_SIZE);
 174 }
 175
 176 int
 177 nouveau_bo_new(struct drm_device *dev, int size, int align,
 178                uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
 179                struct sg_table *sg, struct reservation_object *robj,
 180                struct nouveau_bo **pnvbo)
 181 {
 182         struct nouveau_drm *drm = nouveau_drm(dev);
 183         struct nouveau_bo *nvbo;
 184         size_t acc_size;
 185         int ret;
 186         int type = ttm_bo_type_device;
 187         int lpg_shift = 12;
 188         int max_size;
 189
 190         if (drm->client.vm)
 191                 lpg_shift = drm->client.vm->mmu->lpg_shift;
 192         max_size = INT_MAX & ~((1 << lpg_shift) - 1);
 193
 194         if (size <= 0 || size > max_size) {
 195                 NV_WARN(drm, "skipped size %x\n", (u32)size);
 196                 return -EINVAL;
 197         }
 198
 199         if (sg)
 200                 type = ttm_bo_type_sg;
 201
 202         nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
 203         if (!nvbo)
 204                 return -ENOMEM;
 205         INIT_LIST_HEAD(&nvbo->head);
 206         INIT_LIST_HEAD(&nvbo->entry);
 207         INIT_LIST_HEAD(&nvbo->vma_list);
 208         nvbo->tile_mode = tile_mode;
 209         nvbo->tile_flags = tile_flags;
 210         nvbo->bo.bdev = &drm->ttm.bdev;
 211
 212         if (!nvxx_device(&drm->device)->func->cpu_coherent)
 213                 nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED;
 214
 215         nvbo->page_shift = 12;
 216         if (drm->client.vm) {
 217                 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
 218                         nvbo->page_shift = drm->client.vm->mmu->lpg_shift;
 219         }
 220
 221         nouveau_bo_fixup_align(nvbo, flags, &align, &size);
 222         nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
 223         nouveau_bo_placement_set(nvbo, flags, 0);
 224
 225         acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
 226                                        sizeof(struct nouveau_bo));
 227
 228         ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
 229                           type, &nvbo->placement,
 230                           align >> PAGE_SHIFT, false, NULL, acc_size, sg,
 231                           robj, nouveau_bo_del_ttm);
 232         if (ret) {
 233                 /* ttm will call nouveau_bo_del_ttm if it fails.. */
 234                 return ret;
 235         }
 236
 237         *pnvbo = nvbo;
 238         return 0;
 239 }
 240
 241 static void
 242 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags)
 243 {
 244         *n = 0;
 245
 246         if (type & TTM_PL_FLAG_VRAM)
 247                 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;
 248         if (type & TTM_PL_FLAG_TT)
 249                 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags;
 250         if (type & TTM_PL_FLAG_SYSTEM)
 251                 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags;
 252 }
 253
 254 static void
 255 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
 256 {
 257         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 258         u32 vram_pages = drm->device.info.ram_size >> PAGE_SHIFT;
 259         unsigned i, fpfn, lpfn;
 260
 261         if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
 262             nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
 263             nvbo->bo.mem.num_pages < vram_pages / 4) {
 264                 /*
 265                  * Make sure that the color and depth buffers are handled
 266                  * by independent memory controller units. Up to a 9x
 267                  * speed up when alpha-blending and depth-test are enabled
 268                  * at the same time.
 269                  */
 270                 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
 271                         fpfn = vram_pages / 2;
 272                         lpfn = ~0;
 273                 } else {
 274                         fpfn = 0;
 275                         lpfn = vram_pages / 2;
 276                 }
 277                 for (i = 0; i < nvbo->placement.num_placement; ++i) {
 278                         nvbo->placements[i].fpfn = fpfn;
 279                         nvbo->placements[i].lpfn = lpfn;
 280                 }
 281                 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
 282                         nvbo->busy_placements[i].fpfn = fpfn;
 283                         nvbo->busy_placements[i].lpfn = lpfn;
 284                 }
 285         }
 286 }
 287
 288 void
 289 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
 290 {
 291         struct ttm_placement *pl = &nvbo->placement;
 292         uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
 293                                                  TTM_PL_MASK_CACHING) |
 294                          (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
 295
 296         pl->placement = nvbo->placements;
 297         set_placement_list(nvbo->placements, &pl->num_placement,
 298                            type, flags);
 299
 300         pl->busy_placement = nvbo->busy_placements;
 301         set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
 302                            type | busy, flags);
 303
 304         set_placement_range(nvbo, type);
 305 }
 306
 307 int
 308 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig)
 309 {
 310         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 311         struct ttm_buffer_object *bo = &nvbo->bo;
 312         bool force = false, evict = false;
 313         int ret;
 314
 315         ret = ttm_bo_reserve(bo, false, false, false, NULL);
 316         if (ret)
 317                 return ret;
 318
 319         if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
 320             memtype == TTM_PL_FLAG_VRAM && contig) {
 321                 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) {
 322                         if (bo->mem.mem_type == TTM_PL_VRAM) {
 323                                 struct nvkm_mem *mem = bo->mem.mm_node;
 324                                 if (!list_is_singular(&mem->regions))
 325                                         evict = true;
 326                         }
 327                         nvbo->tile_flags &= ~NOUVEAU_GEM_TILE_NONCONTIG;
 328                         force = true;
 329                 }
 330         }
 331
 332         if (nvbo->pin_refcnt) {
 333                 if (!(memtype & (1 << bo->mem.mem_type)) || evict) {
 334                         NV_ERROR(drm, "bo %p pinned elsewhere: "
 335                                       "0x%08x vs 0x%08x\n", bo,
 336                                  1 << bo->mem.mem_type, memtype);
 337                         ret = -EBUSY;
 338                 }
 339                 nvbo->pin_refcnt++;
 340                 goto out;
 341         }
 342
 343         if (evict) {
 344                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0);
 345                 ret = nouveau_bo_validate(nvbo, false, false);
 346                 if (ret)
 347                         goto out;
 348         }
 349
 350         nvbo->pin_refcnt++;
 351         nouveau_bo_placement_set(nvbo, memtype, 0);
 352
 353         /* drop pin_refcnt temporarily, so we don't trip the assertion
 354          * in nouveau_bo_move() that makes sure we're not trying to
 355          * move a pinned buffer
 356          */
 357         nvbo->pin_refcnt--;
 358         ret = nouveau_bo_validate(nvbo, false, false);
 359         if (ret)
 360                 goto out;
 361         nvbo->pin_refcnt++;
 362
 363         switch (bo->mem.mem_type) {
 364         case TTM_PL_VRAM:
 365                 drm->gem.vram_available -= bo->mem.size;
 366                 break;
 367         case TTM_PL_TT:
 368                 drm->gem.gart_available -= bo->mem.size;
 369                 break;
 370         default:
 371                 break;
 372         }
 373
 374 out:
 375         if (force && ret)
 376                 nvbo->tile_flags |= NOUVEAU_GEM_TILE_NONCONTIG;
 377         ttm_bo_unreserve(bo);
 378         return ret;
 379 }
 380
 381 int
 382 nouveau_bo_unpin(struct nouveau_bo *nvbo)
 383 {
 384         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 385         struct ttm_buffer_object *bo = &nvbo->bo;
 386         int ret, ref;
 387
 388         ret = ttm_bo_reserve(bo, false, false, false, NULL);
 389         if (ret)
 390                 return ret;
 391
 392         ref = --nvbo->pin_refcnt;
 393         WARN_ON_ONCE(ref < 0);
 394         if (ref)
 395                 goto out;
 396
 397         nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
 398
 399         ret = nouveau_bo_validate(nvbo, false, false);
 400         if (ret == 0) {
 401                 switch (bo->mem.mem_type) {
 402                 case TTM_PL_VRAM:
 403                         drm->gem.vram_available += bo->mem.size;
 404                         break;
 405                 case TTM_PL_TT:
 406                         drm->gem.gart_available += bo->mem.size;
 407                         break;
 408                 default:
 409                         break;
 410                 }
 411         }
 412
 413 out:
 414         ttm_bo_unreserve(bo);
 415         return ret;
 416 }
 417
 418 int
 419 nouveau_bo_map(struct nouveau_bo *nvbo)
 420 {
 421         int ret;
 422
 423         ret = ttm_bo_reserve(&nvbo->bo, false, false, false, NULL);
 424         if (ret)
 425                 return ret;
 426
 427         /*
 428          * TTM buffers allocated using the DMA API already have a mapping, let's
 429          * use it instead.
 430          */
 431         if (!nvbo->force_coherent)
 432                 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages,
 433                                   &nvbo->kmap);
 434
 435         ttm_bo_unreserve(&nvbo->bo);
 436         return ret;
 437 }
 438
 439 void
 440 nouveau_bo_unmap(struct nouveau_bo *nvbo)
 441 {
 442         if (!nvbo)
 443                 return;
 444
 445         /*
 446          * TTM buffers allocated using the DMA API already had a coherent
 447          * mapping which we used, no need to unmap.
 448          */
 449         if (!nvbo->force_coherent)
 450                 ttm_bo_kunmap(&nvbo->kmap);
 451 }
 452
 453 void
 454 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
 455 {
 456         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 457         struct nvkm_device *device = nvxx_device(&drm->device);
 458         struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
 459         int i;
 460
 461         if (!ttm_dma)
 462                 return;
 463
 464         /* Don't waste time looping if the object is coherent */
 465         if (nvbo->force_coherent)
 466                 return;
 467
 468         for (i = 0; i < ttm_dma->ttm.num_pages; i++)
 469                 dma_sync_single_for_device(device->dev, ttm_dma->dma_address[i],
 470                                            PAGE_SIZE, DMA_TO_DEVICE);
 471 }
 472
 473 void
 474 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
 475 {
 476         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 477         struct nvkm_device *device = nvxx_device(&drm->device);
 478         struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
 479         int i;
 480
 481         if (!ttm_dma)
 482                 return;
 483
 484         /* Don't waste time looping if the object is coherent */
 485         if (nvbo->force_coherent)
 486                 return;
 487
 488         for (i = 0; i < ttm_dma->ttm.num_pages; i++)
 489                 dma_sync_single_for_cpu(device->dev, ttm_dma->dma_address[i],
 490                                         PAGE_SIZE, DMA_FROM_DEVICE);
 491 }
 492
 493 int
 494 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
 495                     bool no_wait_gpu)
 496 {
 497         int ret;
 498
 499         ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
 500                               interruptible, no_wait_gpu);
 501         if (ret)
 502                 return ret;
 503
 504         nouveau_bo_sync_for_device(nvbo);
 505
 506         return 0;
 507 }
 508
 509 static inline void *
 510 _nouveau_bo_mem_index(struct nouveau_bo *nvbo, unsigned index, void *mem, u8 sz)
 511 {
 512         struct ttm_dma_tt *dma_tt;
 513         u8 *m = mem;
 514
 515         index *= sz;
 516
 517         if (m) {
 518                 /* kmap'd address, return the corresponding offset */
 519                 m += index;
 520         } else {
 521                 /* DMA-API mapping, lookup the right address */
 522                 dma_tt = (struct ttm_dma_tt *)nvbo->bo.ttm;
 523                 m = dma_tt->cpu_address[index / PAGE_SIZE];
 524                 m += index % PAGE_SIZE;
 525         }
 526
 527         return m;
 528 }
 529 #define nouveau_bo_mem_index(o, i, m) _nouveau_bo_mem_index(o, i, m, sizeof(*m))
 530
 531 void
 532 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
 533 {
 534         bool is_iomem;
 535         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 536
 537         mem = nouveau_bo_mem_index(nvbo, index, mem);
 538
 539         if (is_iomem)
 540                 iowrite16_native(val, (void __force __iomem *)mem);
 541         else
 542                 *mem = val;
 543 }
 544
 545 u32
 546 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
 547 {
 548         bool is_iomem;
 549         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 550
 551         mem = nouveau_bo_mem_index(nvbo, index, mem);
 552
 553         if (is_iomem)
 554                 return ioread32_native((void __force __iomem *)mem);
 555         else
 556                 return *mem;
 557 }
 558
 559 void
 560 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
 561 {
 562         bool is_iomem;
 563         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 564
 565         mem = nouveau_bo_mem_index(nvbo, index, mem);
 566
 567         if (is_iomem)
 568                 iowrite32_native(val, (void __force __iomem *)mem);
 569         else
 570                 *mem = val;
 571 }
 572
 573 static struct ttm_tt *
 574 nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
 575                       uint32_t page_flags, struct page *dummy_read)
 576 {
 577 #if __OS_HAS_AGP
 578         struct nouveau_drm *drm = nouveau_bdev(bdev);
 579         struct drm_device *dev = drm->dev;
 580
 581         if (drm->agp.stat == ENABLED) {
 582                 return ttm_agp_tt_create(bdev, dev->agp->bridge, size,
 583                                          page_flags, dummy_read);
 584         }
 585 #endif
 586
 587         return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
 588 }
 589
 590 static int
 591 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 592 {
 593         /* We'll do this from user space. */
 594         return 0;
 595 }
 596
 597 static int
 598 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 599                          struct ttm_mem_type_manager *man)
 600 {
 601         struct nouveau_drm *drm = nouveau_bdev(bdev);
 602
 603         switch (type) {
 604         case TTM_PL_SYSTEM:
 605                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 606                 man->available_caching = TTM_PL_MASK_CACHING;
 607                 man->default_caching = TTM_PL_FLAG_CACHED;
 608                 break;
 609         case TTM_PL_VRAM:
 610                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 611                              TTM_MEMTYPE_FLAG_MAPPABLE;
 612                 man->available_caching = TTM_PL_FLAG_UNCACHED |
 613                                          TTM_PL_FLAG_WC;
 614                 man->default_caching = TTM_PL_FLAG_WC;
 615
 616                 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
 617                         /* Some BARs do not support being ioremapped WC */
 618                         if (nvxx_bar(&drm->device)->iomap_uncached) {
 619                                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 620                                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 621                         }
 622
 623                         man->func = &nouveau_vram_manager;
 624                         man->io_reserve_fastpath = false;
 625                         man->use_io_reserve_lru = true;
 626                 } else {
 627                         man->func = &ttm_bo_manager_func;
 628                 }
 629                 break;
 630         case TTM_PL_TT:
 631                 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA)
 632                         man->func = &nouveau_gart_manager;
 633                 else
 634                 if (drm->agp.stat != ENABLED)
 635                         man->func = &nv04_gart_manager;
 636                 else
 637                         man->func = &ttm_bo_manager_func;
 638
 639                 if (drm->agp.stat == ENABLED) {
 640                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 641                         man->available_caching = TTM_PL_FLAG_UNCACHED |
 642                                 TTM_PL_FLAG_WC;
 643                         man->default_caching = TTM_PL_FLAG_WC;
 644                 } else {
 645                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
 646                                      TTM_MEMTYPE_FLAG_CMA;
 647                         man->available_caching = TTM_PL_MASK_CACHING;
 648                         man->default_caching = TTM_PL_FLAG_CACHED;
 649                 }
 650
 651                 break;
 652         default:
 653                 return -EINVAL;
 654         }
 655         return 0;
 656 }
 657
 658 static void
 659 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
 660 {
 661         struct nouveau_bo *nvbo = nouveau_bo(bo);
 662
 663         switch (bo->mem.mem_type) {
 664         case TTM_PL_VRAM:
 665                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
 666                                          TTM_PL_FLAG_SYSTEM);
 667                 break;
 668         default:
 669                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
 670                 break;
 671         }
 672
 673         *pl = nvbo->placement;
 674 }
 675
 676
 677 static int
 678 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
 679 {
 680         int ret = RING_SPACE(chan, 2);
 681         if (ret == 0) {
 682                 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
 683                 OUT_RING  (chan, handle & 0x0000ffff);
 684                 FIRE_RING (chan);
 685         }
 686         return ret;
 687 }
 688
 689 static int
 690 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 691                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 692 {
 693         struct nvkm_mem *node = old_mem->mm_node;
 694         int ret = RING_SPACE(chan, 10);
 695         if (ret == 0) {
 696                 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
 697                 OUT_RING  (chan, upper_32_bits(node->vma[0].offset));
 698                 OUT_RING  (chan, lower_32_bits(node->vma[0].offset));
 699                 OUT_RING  (chan, upper_32_bits(node->vma[1].offset));
 700                 OUT_RING  (chan, lower_32_bits(node->vma[1].offset));
 701                 OUT_RING  (chan, PAGE_SIZE);
 702                 OUT_RING  (chan, PAGE_SIZE);
 703                 OUT_RING  (chan, PAGE_SIZE);
 704                 OUT_RING  (chan, new_mem->num_pages);
 705                 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
 706         }
 707         return ret;
 708 }
 709
 710 static int
 711 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
 712 {
 713         int ret = RING_SPACE(chan, 2);
 714         if (ret == 0) {
 715                 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
 716                 OUT_RING  (chan, handle);
 717         }
 718         return ret;
 719 }
 720
 721 static int
 722 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 723                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 724 {
 725         struct nvkm_mem *node = old_mem->mm_node;
 726         u64 src_offset = node->vma[0].offset;
 727         u64 dst_offset = node->vma[1].offset;
 728         u32 page_count = new_mem->num_pages;
 729         int ret;
 730
 731         page_count = new_mem->num_pages;
 732         while (page_count) {
 733                 int line_count = (page_count > 8191) ? 8191 : page_count;
 734
 735                 ret = RING_SPACE(chan, 11);
 736                 if (ret)
 737                         return ret;
 738
 739                 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
 740                 OUT_RING  (chan, upper_32_bits(src_offset));
 741                 OUT_RING  (chan, lower_32_bits(src_offset));
 742                 OUT_RING  (chan, upper_32_bits(dst_offset));
 743                 OUT_RING  (chan, lower_32_bits(dst_offset));
 744                 OUT_RING  (chan, PAGE_SIZE);
 745                 OUT_RING  (chan, PAGE_SIZE);
 746                 OUT_RING  (chan, PAGE_SIZE);
 747                 OUT_RING  (chan, line_count);
 748                 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
 749                 OUT_RING  (chan, 0x00000110);
 750
 751                 page_count -= line_count;
 752                 src_offset += (PAGE_SIZE * line_count);
 753                 dst_offset += (PAGE_SIZE * line_count);
 754         }
 755
 756         return 0;
 757 }
 758
 759 static int
 760 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 761                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 762 {
 763         struct nvkm_mem *node = old_mem->mm_node;
 764         u64 src_offset = node->vma[0].offset;
 765         u64 dst_offset = node->vma[1].offset;
 766         u32 page_count = new_mem->num_pages;
 767         int ret;
 768
 769         page_count = new_mem->num_pages;
 770         while (page_count) {
 771                 int line_count = (page_count > 2047) ? 2047 : page_count;
 772
 773                 ret = RING_SPACE(chan, 12);
 774                 if (ret)
 775                         return ret;
 776
 777                 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
 778                 OUT_RING  (chan, upper_32_bits(dst_offset));
 779                 OUT_RING  (chan, lower_32_bits(dst_offset));
 780                 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
 781                 OUT_RING  (chan, upper_32_bits(src_offset));
 782                 OUT_RING  (chan, lower_32_bits(src_offset));
 783                 OUT_RING  (chan, PAGE_SIZE); /* src_pitch */
 784                 OUT_RING  (chan, PAGE_SIZE); /* dst_pitch */
 785                 OUT_RING  (chan, PAGE_SIZE); /* line_length */
 786                 OUT_RING  (chan, line_count);
 787                 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
 788                 OUT_RING  (chan, 0x00100110);
 789
 790                 page_count -= line_count;
 791                 src_offset += (PAGE_SIZE * line_count);
 792                 dst_offset += (PAGE_SIZE * line_count);
 793         }
 794
 795         return 0;
 796 }
 797
 798 static int
 799 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 800                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 801 {
 802         struct nvkm_mem *node = old_mem->mm_node;
 803         u64 src_offset = node->vma[0].offset;
 804         u64 dst_offset = node->vma[1].offset;
 805         u32 page_count = new_mem->num_pages;
 806         int ret;
 807
 808         page_count = new_mem->num_pages;
 809         while (page_count) {
 810                 int line_count = (page_count > 8191) ? 8191 : page_count;
 811
 812                 ret = RING_SPACE(chan, 11);
 813                 if (ret)
 814                         return ret;
 815
 816                 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
 817                 OUT_RING  (chan, upper_32_bits(src_offset));
 818                 OUT_RING  (chan, lower_32_bits(src_offset));
 819                 OUT_RING  (chan, upper_32_bits(dst_offset));
 820                 OUT_RING  (chan, lower_32_bits(dst_offset));
 821                 OUT_RING  (chan, PAGE_SIZE);
 822                 OUT_RING  (chan, PAGE_SIZE);
 823                 OUT_RING  (chan, PAGE_SIZE);
 824                 OUT_RING  (chan, line_count);
 825                 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
 826                 OUT_RING  (chan, 0x00000110);
 827
 828                 page_count -= line_count;
 829                 src_offset += (PAGE_SIZE * line_count);
 830                 dst_offset += (PAGE_SIZE * line_count);
 831         }
 832
 833         return 0;
 834 }
 835
 836 static int
 837 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 838                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 839 {
 840         struct nvkm_mem *node = old_mem->mm_node;
 841         int ret = RING_SPACE(chan, 7);
 842         if (ret == 0) {
 843                 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
 844                 OUT_RING  (chan, upper_32_bits(node->vma[0].offset));
 845                 OUT_RING  (chan, lower_32_bits(node->vma[0].offset));
 846                 OUT_RING  (chan, upper_32_bits(node->vma[1].offset));
 847                 OUT_RING  (chan, lower_32_bits(node->vma[1].offset));
 848                 OUT_RING  (chan, 0x00000000 /* COPY */);
 849                 OUT_RING  (chan, new_mem->num_pages << PAGE_SHIFT);
 850         }
 851         return ret;
 852 }
 853
 854 static int
 855 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 856                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 857 {
 858         struct nvkm_mem *node = old_mem->mm_node;
 859         int ret = RING_SPACE(chan, 7);
 860         if (ret == 0) {
 861                 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
 862                 OUT_RING  (chan, new_mem->num_pages << PAGE_SHIFT);
 863                 OUT_RING  (chan, upper_32_bits(node->vma[0].offset));
 864                 OUT_RING  (chan, lower_32_bits(node->vma[0].offset));
 865                 OUT_RING  (chan, upper_32_bits(node->vma[1].offset));
 866                 OUT_RING  (chan, lower_32_bits(node->vma[1].offset));
 867                 OUT_RING  (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
 868         }
 869         return ret;
 870 }
 871
 872 static int
 873 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
 874 {
 875         int ret = RING_SPACE(chan, 6);
 876         if (ret == 0) {
 877                 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
 878                 OUT_RING  (chan, handle);
 879                 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
 880                 OUT_RING  (chan, chan->drm->ntfy.handle);
 881                 OUT_RING  (chan, chan->vram.handle);
 882                 OUT_RING  (chan, chan->vram.handle);
 883         }
 884
 885         return ret;
 886 }
 887
 888 static int
 889 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 890                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 891 {
 892         struct nvkm_mem *node = old_mem->mm_node;
 893         u64 length = (new_mem->num_pages << PAGE_SHIFT);
 894         u64 src_offset = node->vma[0].offset;
 895         u64 dst_offset = node->vma[1].offset;
 896         int src_tiled = !!node->memtype;
 897         int dst_tiled = !!((struct nvkm_mem *)new_mem->mm_node)->memtype;
 898         int ret;
 899
 900         while (length) {
 901                 u32 amount, stride, height;
 902
 903                 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
 904                 if (ret)
 905                         return ret;
 906
 907                 amount  = min(length, (u64)(4 * 1024 * 1024));
 908                 stride  = 16 * 4;
 909                 height  = amount / stride;
 910
 911                 if (src_tiled) {
 912                         BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
 913                         OUT_RING  (chan, 0);
 914                         OUT_RING  (chan, 0);
 915                         OUT_RING  (chan, stride);
 916                         OUT_RING  (chan, height);
 917                         OUT_RING  (chan, 1);
 918                         OUT_RING  (chan, 0);
 919                         OUT_RING  (chan, 0);
 920                 } else {
 921                         BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
 922                         OUT_RING  (chan, 1);
 923                 }
 924                 if (dst_tiled) {
 925                         BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
 926                         OUT_RING  (chan, 0);
 927                         OUT_RING  (chan, 0);
 928                         OUT_RING  (chan, stride);
 929                         OUT_RING  (chan, height);
 930                         OUT_RING  (chan, 1);
 931                         OUT_RING  (chan, 0);
 932                         OUT_RING  (chan, 0);
 933                 } else {
 934                         BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
 935                         OUT_RING  (chan, 1);
 936                 }
 937
 938                 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
 939                 OUT_RING  (chan, upper_32_bits(src_offset));
 940                 OUT_RING  (chan, upper_32_bits(dst_offset));
 941                 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
 942                 OUT_RING  (chan, lower_32_bits(src_offset));
 943                 OUT_RING  (chan, lower_32_bits(dst_offset));
 944                 OUT_RING  (chan, stride);
 945                 OUT_RING  (chan, stride);
 946                 OUT_RING  (chan, stride);
 947                 OUT_RING  (chan, height);
 948                 OUT_RING  (chan, 0x00000101);
 949                 OUT_RING  (chan, 0x00000000);
 950                 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
 951                 OUT_RING  (chan, 0);
 952
 953                 length -= amount;
 954                 src_offset += amount;
 955                 dst_offset += amount;
 956         }
 957
 958         return 0;
 959 }
 960
 961 static int
 962 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
 963 {
 964         int ret = RING_SPACE(chan, 4);
 965         if (ret == 0) {
 966                 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
 967                 OUT_RING  (chan, handle);
 968                 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
 969                 OUT_RING  (chan, chan->drm->ntfy.handle);
 970         }
 971
 972         return ret;
 973 }
 974
 975 static inline uint32_t
 976 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
 977                       struct nouveau_channel *chan, struct ttm_mem_reg *mem)
 978 {
 979         if (mem->mem_type == TTM_PL_TT)
 980                 return NvDmaTT;
 981         return chan->vram.handle;
 982 }
 983
 984 static int
 985 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 986                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 987 {
 988         u32 src_offset = old_mem->start << PAGE_SHIFT;
 989         u32 dst_offset = new_mem->start << PAGE_SHIFT;
 990         u32 page_count = new_mem->num_pages;
 991         int ret;
 992
 993         ret = RING_SPACE(chan, 3);
 994         if (ret)
 995                 return ret;
 996
 997         BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
 998         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
 999         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
1000
1001         page_count = new_mem->num_pages;
1002         while (page_count) {
1003                 int line_count = (page_count > 2047) ? 2047 : page_count;
1004
1005                 ret = RING_SPACE(chan, 11);
1006                 if (ret)
1007                         return ret;
1008
1009                 BEGIN_NV04(chan, NvSubCopy,
1010                                  NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
1011                 OUT_RING  (chan, src_offset);
1012                 OUT_RING  (chan, dst_offset);
1013                 OUT_RING  (chan, PAGE_SIZE); /* src_pitch */
1014                 OUT_RING  (chan, PAGE_SIZE); /* dst_pitch */
1015                 OUT_RING  (chan, PAGE_SIZE); /* line_length */
1016                 OUT_RING  (chan, line_count);
1017                 OUT_RING  (chan, 0x00000101);
1018                 OUT_RING  (chan, 0x00000000);
1019                 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
1020                 OUT_RING  (chan, 0);
1021
1022                 page_count -= line_count;
1023                 src_offset += (PAGE_SIZE * line_count);
1024                 dst_offset += (PAGE_SIZE * line_count);
1025         }
1026
1027         return 0;
1028 }
1029
1030 static int
1031 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
1032                      struct ttm_mem_reg *mem)
1033 {
1034         struct nvkm_mem *old_node = bo->mem.mm_node;
1035         struct nvkm_mem *new_node = mem->mm_node;
1036         u64 size = (u64)mem->num_pages << PAGE_SHIFT;
1037         int ret;
1038
1039         ret = nvkm_vm_get(drm->client.vm, size, old_node->page_shift,
1040                           NV_MEM_ACCESS_RW, &old_node->vma[0]);
1041         if (ret)
1042                 return ret;
1043
1044         ret = nvkm_vm_get(drm->client.vm, size, new_node->page_shift,
1045                           NV_MEM_ACCESS_RW, &old_node->vma[1]);
1046         if (ret) {
1047                 nvkm_vm_put(&old_node->vma[0]);
1048                 return ret;
1049         }
1050
1051         nvkm_vm_map(&old_node->vma[0], old_node);
1052         nvkm_vm_map(&old_node->vma[1], new_node);
1053         return 0;
1054 }
1055
1056 static int
1057 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
1058                      bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1059 {
1060         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1061         struct nouveau_channel *chan = drm->ttm.chan;
1062         struct nouveau_cli *cli = (void *)chan->user.client;
1063         struct nouveau_fence *fence;
1064         int ret;
1065
1066         /* create temporary vmas for the transfer and attach them to the
1067          * old nvkm_mem node, these will get cleaned up after ttm has
1068          * destroyed the ttm_mem_reg
1069          */
1070         if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1071                 ret = nouveau_bo_move_prep(drm, bo, new_mem);
1072                 if (ret)
1073                         return ret;
1074         }
1075
1076         mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
1077         ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
1078         if (ret == 0) {
1079                 ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
1080                 if (ret == 0) {
1081                         ret = nouveau_fence_new(chan, false, &fence);
1082                         if (ret == 0) {
1083                                 ret = ttm_bo_move_accel_cleanup(bo,
1084                                                                 &fence->base,
1085                                                                 evict,
1086                                                                 no_wait_gpu,
1087                                                                 new_mem);
1088                                 nouveau_fence_unref(&fence);
1089                         }
1090                 }
1091         }
1092         mutex_unlock(&cli->mutex);
1093         return ret;
1094 }
1095
1096 void
1097 nouveau_bo_move_init(struct nouveau_drm *drm)
1098 {
1099         static const struct {
1100                 const char *name;
1101                 int engine;
1102                 s32 oclass;
1103                 int (*exec)(struct nouveau_channel *,
1104                             struct ttm_buffer_object *,
1105                             struct ttm_mem_reg *, struct ttm_mem_reg *);
1106                 int (*init)(struct nouveau_channel *, u32 handle);
1107         } _methods[] = {
1108                 {  "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
1109                 {  "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1110                 {  "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1111                 {  "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1112                 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1113                 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1114                 {  "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1115                 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1116                 {  "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1117                 {  "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1118                 {  "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1119                 {},
1120                 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1121         }, *mthd = _methods;
1122         const char *name = "CPU";
1123         int ret;
1124
1125         do {
1126                 struct nouveau_channel *chan;
1127
1128                 if (mthd->engine)
1129                         chan = drm->cechan;
1130                 else
1131                         chan = drm->channel;
1132                 if (chan == NULL)
1133                         continue;
1134
1135                 ret = nvif_object_init(&chan->user,
1136                                        mthd->oclass | (mthd->engine << 16),
1137                                        mthd->oclass, NULL, 0,
1138                                        &drm->ttm.copy);
1139                 if (ret == 0) {
1140                         ret = mthd->init(chan, drm->ttm.copy.handle);
1141                         if (ret) {
1142                                 nvif_object_fini(&drm->ttm.copy);
1143                                 continue;
1144                         }
1145
1146                         drm->ttm.move = mthd->exec;
1147                         drm->ttm.chan = chan;
1148                         name = mthd->name;
1149                         break;
1150                 }
1151         } while ((++mthd)->exec);
1152
1153         NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1154 }
1155
1156 static int
1157 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1158                       bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1159 {
1160         struct ttm_place placement_memtype = {
1161                 .fpfn = 0,
1162                 .lpfn = 0,
1163                 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1164         };
1165         struct ttm_placement placement;
1166         struct ttm_mem_reg tmp_mem;
1167         int ret;
1168
1169         placement.num_placement = placement.num_busy_placement = 1;
1170         placement.placement = placement.busy_placement = &placement_memtype;
1171
1172         tmp_mem = *new_mem;
1173         tmp_mem.mm_node = NULL;
1174         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1175         if (ret)
1176                 return ret;
1177
1178         ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1179         if (ret)
1180                 goto out;
1181
1182         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem);
1183         if (ret)
1184                 goto out;
1185
1186         ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
1187 out:
1188         ttm_bo_mem_put(bo, &tmp_mem);
1189         return ret;
1190 }
1191
1192 static int
1193 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1194                       bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1195 {
1196         struct ttm_place placement_memtype = {
1197                 .fpfn = 0,
1198                 .lpfn = 0,
1199                 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1200         };
1201         struct ttm_placement placement;
1202         struct ttm_mem_reg tmp_mem;
1203         int ret;
1204
1205         placement.num_placement = placement.num_busy_placement = 1;
1206         placement.placement = placement.busy_placement = &placement_memtype;
1207
1208         tmp_mem = *new_mem;
1209         tmp_mem.mm_node = NULL;
1210         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1211         if (ret)
1212                 return ret;
1213
1214         ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
1215         if (ret)
1216                 goto out;
1217
1218         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem);
1219         if (ret)
1220                 goto out;
1221
1222 out:
1223         ttm_bo_mem_put(bo, &tmp_mem);
1224         return ret;
1225 }
1226
1227 static void
1228 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1229 {
1230         struct nouveau_bo *nvbo = nouveau_bo(bo);
1231         struct nvkm_vma *vma;
1232
1233         /* ttm can now (stupidly) pass the driver bos it didn't create... */
1234         if (bo->destroy != nouveau_bo_del_ttm)
1235                 return;
1236
1237         list_for_each_entry(vma, &nvbo->vma_list, head) {
1238                 if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM &&
1239                               (new_mem->mem_type == TTM_PL_VRAM ||
1240                                nvbo->page_shift != vma->vm->mmu->lpg_shift)) {
1241                         nvkm_vm_map(vma, new_mem->mm_node);
1242                 } else {
1243                         nvkm_vm_unmap(vma);
1244                 }
1245         }
1246 }
1247
1248 static int
1249 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1250                    struct nouveau_drm_tile **new_tile)
1251 {
1252         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1253         struct drm_device *dev = drm->dev;
1254         struct nouveau_bo *nvbo = nouveau_bo(bo);
1255         u64 offset = new_mem->start << PAGE_SHIFT;
1256
1257         *new_tile = NULL;
1258         if (new_mem->mem_type != TTM_PL_VRAM)
1259                 return 0;
1260
1261         if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1262                 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1263                                                 nvbo->tile_mode,
1264                                                 nvbo->tile_flags);
1265         }
1266
1267         return 0;
1268 }
1269
1270 static void
1271 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1272                       struct nouveau_drm_tile *new_tile,
1273                       struct nouveau_drm_tile **old_tile)
1274 {
1275         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1276         struct drm_device *dev = drm->dev;
1277         struct fence *fence = reservation_object_get_excl(bo->resv);
1278
1279         nv10_bo_put_tile_region(dev, *old_tile, fence);
1280         *old_tile = new_tile;
1281 }
1282
1283 static int
1284 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1285                 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1286 {
1287         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1288         struct nouveau_bo *nvbo = nouveau_bo(bo);
1289         struct ttm_mem_reg *old_mem = &bo->mem;
1290         struct nouveau_drm_tile *new_tile = NULL;
1291         int ret = 0;
1292
1293         if (nvbo->pin_refcnt)
1294                 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1295
1296         if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1297                 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1298                 if (ret)
1299                         return ret;
1300         }
1301
1302         /* Fake bo copy. */
1303         if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1304                 BUG_ON(bo->mem.mm_node != NULL);
1305                 bo->mem = *new_mem;
1306                 new_mem->mm_node = NULL;
1307                 goto out;
1308         }
1309
1310         /* Hardware assisted copy. */
1311         if (drm->ttm.move) {
1312                 if (new_mem->mem_type == TTM_PL_SYSTEM)
1313                         ret = nouveau_bo_move_flipd(bo, evict, intr,
1314                                                     no_wait_gpu, new_mem);
1315                 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1316                         ret = nouveau_bo_move_flips(bo, evict, intr,
1317                                                     no_wait_gpu, new_mem);
1318                 else
1319                         ret = nouveau_bo_move_m2mf(bo, evict, intr,
1320                                                    no_wait_gpu, new_mem);
1321                 if (!ret)
1322                         goto out;
1323         }
1324
1325         /* Fallback to software copy. */
1326         ret = ttm_bo_wait(bo, true, intr, no_wait_gpu);
1327         if (ret == 0)
1328                 ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1329
1330 out:
1331         if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1332                 if (ret)
1333                         nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1334                 else
1335                         nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1336         }
1337
1338         return ret;
1339 }
1340
1341 static int
1342 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1343 {
1344         struct nouveau_bo *nvbo = nouveau_bo(bo);
1345
1346         return drm_vma_node_verify_access(&nvbo->gem.vma_node, filp);
1347 }
1348
1349 static int
1350 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1351 {
1352         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1353         struct nouveau_drm *drm = nouveau_bdev(bdev);
1354         struct nvkm_device *device = nvxx_device(&drm->device);
1355         struct nvkm_mem *node = mem->mm_node;
1356         int ret;
1357
1358         mem->bus.addr = NULL;
1359         mem->bus.offset = 0;
1360         mem->bus.size = mem->num_pages << PAGE_SHIFT;
1361         mem->bus.base = 0;
1362         mem->bus.is_iomem = false;
1363         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1364                 return -EINVAL;
1365         switch (mem->mem_type) {
1366         case TTM_PL_SYSTEM:
1367                 /* System memory */
1368                 return 0;
1369         case TTM_PL_TT:
1370 #if __OS_HAS_AGP
1371                 if (drm->agp.stat == ENABLED) {
1372                         mem->bus.offset = mem->start << PAGE_SHIFT;
1373                         mem->bus.base = drm->agp.base;
1374                         mem->bus.is_iomem = !drm->dev->agp->cant_use_aperture;
1375                 }
1376 #endif
1377                 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || !node->memtype)
1378                         /* untiled */
1379                         break;
1380                 /* fallthrough, tiled memory */
1381         case TTM_PL_VRAM:
1382                 mem->bus.offset = mem->start << PAGE_SHIFT;
1383                 mem->bus.base = device->func->resource_addr(device, 1);
1384                 mem->bus.is_iomem = true;
1385                 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1386                         struct nvkm_bar *bar = nvxx_bar(&drm->device);
1387                         int page_shift = 12;
1388                         if (drm->device.info.family >= NV_DEVICE_INFO_V0_FERMI)
1389                                 page_shift = node->page_shift;
1390
1391                         ret = nvkm_bar_umap(bar, node->size << 12, page_shift,
1392                                             &node->bar_vma);
1393                         if (ret)
1394                                 return ret;
1395
1396                         nvkm_vm_map(&node->bar_vma, node);
1397                         mem->bus.offset = node->bar_vma.offset;
1398                 }
1399                 break;
1400         default:
1401                 return -EINVAL;
1402         }
1403         return 0;
1404 }
1405
1406 static void
1407 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1408 {
1409         struct nvkm_mem *node = mem->mm_node;
1410
1411         if (!node->bar_vma.node)
1412                 return;
1413
1414         nvkm_vm_unmap(&node->bar_vma);
1415         nvkm_vm_put(&node->bar_vma);
1416 }
1417
1418 static int
1419 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1420 {
1421         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1422         struct nouveau_bo *nvbo = nouveau_bo(bo);
1423         struct nvkm_device *device = nvxx_device(&drm->device);
1424         u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1425         int i, ret;
1426
1427         /* as long as the bo isn't in vram, and isn't tiled, we've got
1428          * nothing to do here.
1429          */
1430         if (bo->mem.mem_type != TTM_PL_VRAM) {
1431                 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1432                     !nouveau_bo_tile_layout(nvbo))
1433                         return 0;
1434
1435                 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1436                         nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
1437
1438                         ret = nouveau_bo_validate(nvbo, false, false);
1439                         if (ret)
1440                                 return ret;
1441                 }
1442                 return 0;
1443         }
1444
1445         /* make sure bo is in mappable vram */
1446         if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1447             bo->mem.start + bo->mem.num_pages < mappable)
1448                 return 0;
1449
1450         for (i = 0; i < nvbo->placement.num_placement; ++i) {
1451                 nvbo->placements[i].fpfn = 0;
1452                 nvbo->placements[i].lpfn = mappable;
1453         }
1454
1455         for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1456                 nvbo->busy_placements[i].fpfn = 0;
1457                 nvbo->busy_placements[i].lpfn = mappable;
1458         }
1459
1460         nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1461         return nouveau_bo_validate(nvbo, false, false);
1462 }
1463
1464 static int
1465 nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1466 {
1467         struct ttm_dma_tt *ttm_dma = (void *)ttm;
1468         struct nouveau_drm *drm;
1469         struct nvkm_device *device;
1470         struct drm_device *dev;
1471         struct device *pdev;
1472         unsigned i;
1473         int r;
1474         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1475
1476         if (ttm->state != tt_unpopulated)
1477                 return 0;
1478
1479         if (slave && ttm->sg) {
1480                 /* make userspace faulting work */
1481                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1482                                                  ttm_dma->dma_address, ttm->num_pages);
1483                 ttm->state = tt_unbound;
1484                 return 0;
1485         }
1486
1487         drm = nouveau_bdev(ttm->bdev);
1488         device = nvxx_device(&drm->device);
1489         dev = drm->dev;
1490         pdev = device->dev;
1491
1492         /*
1493          * Objects matching this condition have been marked as force_coherent,
1494          * so use the DMA API for them.
1495          */
1496         if (!nvxx_device(&drm->device)->func->cpu_coherent &&
1497             ttm->caching_state == tt_uncached)
1498                 return ttm_dma_populate(ttm_dma, dev->dev);
1499
1500 #if __OS_HAS_AGP
1501         if (drm->agp.stat == ENABLED) {
1502                 return ttm_agp_tt_populate(ttm);
1503         }
1504 #endif
1505
1506 #ifdef CONFIG_SWIOTLB
1507         if (swiotlb_nr_tbl()) {
1508                 return ttm_dma_populate((void *)ttm, dev->dev);
1509         }
1510 #endif
1511
1512         r = ttm_pool_populate(ttm);
1513         if (r) {
1514                 return r;
1515         }
1516
1517         for (i = 0; i < ttm->num_pages; i++) {
1518                 dma_addr_t addr;
1519
1520                 addr = dma_map_page(pdev, ttm->pages[i], 0, PAGE_SIZE,
1521                                     DMA_BIDIRECTIONAL);
1522
1523                 if (dma_mapping_error(pdev, addr)) {
1524                         while (--i) {
1525                                 dma_unmap_page(pdev, ttm_dma->dma_address[i],
1526                                                PAGE_SIZE, DMA_BIDIRECTIONAL);
1527                                 ttm_dma->dma_address[i] = 0;
1528                         }
1529                         ttm_pool_unpopulate(ttm);
1530                         return -EFAULT;
1531                 }
1532
1533                 ttm_dma->dma_address[i] = addr;
1534         }
1535         return 0;
1536 }
1537
1538 static void
1539 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1540 {
1541         struct ttm_dma_tt *ttm_dma = (void *)ttm;
1542         struct nouveau_drm *drm;
1543         struct nvkm_device *device;
1544         struct drm_device *dev;
1545         struct device *pdev;
1546         unsigned i;
1547         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1548
1549         if (slave)
1550                 return;
1551
1552         drm = nouveau_bdev(ttm->bdev);
1553         device = nvxx_device(&drm->device);
1554         dev = drm->dev;
1555         pdev = device->dev;
1556
1557         /*
1558          * Objects matching this condition have been marked as force_coherent,
1559          * so use the DMA API for them.
1560          */
1561         if (!nvxx_device(&drm->device)->func->cpu_coherent &&
1562             ttm->caching_state == tt_uncached) {
1563                 ttm_dma_unpopulate(ttm_dma, dev->dev);
1564                 return;
1565         }
1566
1567 #if __OS_HAS_AGP
1568         if (drm->agp.stat == ENABLED) {
1569                 ttm_agp_tt_unpopulate(ttm);
1570                 return;
1571         }
1572 #endif
1573
1574 #ifdef CONFIG_SWIOTLB
1575         if (swiotlb_nr_tbl()) {
1576                 ttm_dma_unpopulate((void *)ttm, dev->dev);
1577                 return;
1578         }
1579 #endif
1580
1581         for (i = 0; i < ttm->num_pages; i++) {
1582                 if (ttm_dma->dma_address[i]) {
1583                         dma_unmap_page(pdev, ttm_dma->dma_address[i], PAGE_SIZE,
1584                                        DMA_BIDIRECTIONAL);
1585                 }
1586         }
1587
1588         ttm_pool_unpopulate(ttm);
1589 }
1590
1591 void
1592 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1593 {
1594         struct reservation_object *resv = nvbo->bo.resv;
1595
1596         if (exclusive)
1597                 reservation_object_add_excl_fence(resv, &fence->base);
1598         else if (fence)
1599                 reservation_object_add_shared_fence(resv, &fence->base);
1600 }
1601
1602 struct ttm_bo_driver nouveau_bo_driver = {
1603         .ttm_tt_create = &nouveau_ttm_tt_create,
1604         .ttm_tt_populate = &nouveau_ttm_tt_populate,
1605         .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1606         .invalidate_caches = nouveau_bo_invalidate_caches,
1607         .init_mem_type = nouveau_bo_init_mem_type,
1608         .evict_flags = nouveau_bo_evict_flags,
1609         .move_notify = nouveau_bo_move_ntfy,
1610         .move = nouveau_bo_move,
1611         .verify_access = nouveau_bo_verify_access,
1612         .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1613         .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1614         .io_mem_free = &nouveau_ttm_io_mem_free,
1615 };
1616
1617 struct nvkm_vma *
1618 nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nvkm_vm *vm)
1619 {
1620         struct nvkm_vma *vma;
1621         list_for_each_entry(vma, &nvbo->vma_list, head) {
1622                 if (vma->vm == vm)
1623                         return vma;
1624         }
1625
1626         return NULL;
1627 }
1628
1629 int
1630 nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nvkm_vm *vm,
1631                    struct nvkm_vma *vma)
1632 {
1633         const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1634         int ret;
1635
1636         ret = nvkm_vm_get(vm, size, nvbo->page_shift,
1637                              NV_MEM_ACCESS_RW, vma);
1638         if (ret)
1639                 return ret;
1640
1641         if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM &&
1642             (nvbo->bo.mem.mem_type == TTM_PL_VRAM ||
1643              nvbo->page_shift != vma->vm->mmu->lpg_shift))
1644                 nvkm_vm_map(vma, nvbo->bo.mem.mm_node);
1645
1646         list_add_tail(&vma->head, &nvbo->vma_list);
1647         vma->refcount = 1;
1648         return 0;
1649 }
1650
1651 void
1652 nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nvkm_vma *vma)
1653 {
1654         if (vma->node) {
1655                 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM)
1656                         nvkm_vm_unmap(vma);
1657                 nvkm_vm_put(vma);
1658                 list_del(&vma->head);
1659         }
1660 }