2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <nvif/class.h>
29 #include <core/client.h>
31 #include "nouveau_drm.h"
32 #include "nouveau_dma.h"
33 #include "nouveau_bo.h"
34 #include "nouveau_chan.h"
35 #include "nouveau_fence.h"
36 #include "nouveau_abi16.h"
38 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
39 int nouveau_vram_pushbuf;
40 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
43 nouveau_channel_idle(struct nouveau_channel *chan)
45 struct nouveau_cli *cli = (void *)chan->user.client;
46 struct nouveau_fence *fence = NULL;
49 ret = nouveau_fence_new(chan, false, &fence);
51 ret = nouveau_fence_wait(fence, false, false);
52 nouveau_fence_unref(&fence);
56 NV_PRINTK(err, cli, "failed to idle channel 0x%08x [%s]\n",
57 chan->user.handle, nvxx_client(&cli->base)->name);
62 nouveau_channel_del(struct nouveau_channel **pchan)
64 struct nouveau_channel *chan = *pchan;
67 nouveau_channel_idle(chan);
68 nouveau_fence(chan->drm)->context_del(chan);
70 nvif_object_fini(&chan->nvsw);
71 nvif_object_fini(&chan->gart);
72 nvif_object_fini(&chan->vram);
73 nvif_object_fini(&chan->user);
74 nvif_object_fini(&chan->push.ctxdma);
75 nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma);
76 nouveau_bo_unmap(chan->push.buffer);
77 if (chan->push.buffer && chan->push.buffer->pin_refcnt)
78 nouveau_bo_unpin(chan->push.buffer);
79 nouveau_bo_ref(NULL, &chan->push.buffer);
86 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
87 u32 handle, u32 size, struct nouveau_channel **pchan)
89 struct nouveau_cli *cli = (void *)device->object.client;
90 struct nvkm_mmu *mmu = nvxx_mmu(device);
91 struct nv_dma_v0 args = {};
92 struct nouveau_channel *chan;
96 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
100 chan->device = device;
103 /* allocate memory for dma push buffer */
104 target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
105 if (nouveau_vram_pushbuf)
106 target = TTM_PL_FLAG_VRAM;
108 ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, NULL,
111 ret = nouveau_bo_pin(chan->push.buffer, target, false);
113 ret = nouveau_bo_map(chan->push.buffer);
117 nouveau_channel_del(pchan);
121 /* create dma object covering the *entire* memory space that the
122 * pushbuf lives in, this is because the GEM code requires that
123 * we be able to call out to other (indirect) push buffers
125 chan->push.vma.offset = chan->push.buffer->bo.offset;
127 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
128 ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm,
131 nouveau_channel_del(pchan);
135 args.target = NV_DMA_V0_TARGET_VM;
136 args.access = NV_DMA_V0_ACCESS_VM;
138 args.limit = cli->vm->mmu->limit - 1;
140 if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
141 if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
142 /* nv04 vram pushbuf hack, retarget to its location in
143 * the framebuffer bar rather than direct vram access..
144 * nfi why this exists, it came from the -nv ddx.
146 args.target = NV_DMA_V0_TARGET_PCI;
147 args.access = NV_DMA_V0_ACCESS_RDWR;
148 args.start = nv_device_resource_start(nvxx_device(device), 1);
149 args.limit = args.start + device->info.ram_user - 1;
151 args.target = NV_DMA_V0_TARGET_VRAM;
152 args.access = NV_DMA_V0_ACCESS_RDWR;
154 args.limit = device->info.ram_user - 1;
157 if (chan->drm->agp.stat == ENABLED) {
158 args.target = NV_DMA_V0_TARGET_AGP;
159 args.access = NV_DMA_V0_ACCESS_RDWR;
160 args.start = chan->drm->agp.base;
161 args.limit = chan->drm->agp.base +
162 chan->drm->agp.size - 1;
164 args.target = NV_DMA_V0_TARGET_VM;
165 args.access = NV_DMA_V0_ACCESS_RDWR;
167 args.limit = mmu->limit - 1;
171 ret = nvif_object_init(&device->object, NVDRM_PUSH |
172 (handle & 0xffff), NV_DMA_FROM_MEMORY,
173 &args, sizeof(args), &chan->push.ctxdma);
175 nouveau_channel_del(pchan);
183 nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
184 u32 handle, u32 engine, struct nouveau_channel **pchan)
186 static const u16 oclasses[] = { MAXWELL_CHANNEL_GPFIFO_A,
187 KEPLER_CHANNEL_GPFIFO_A,
188 FERMI_CHANNEL_GPFIFO,
192 const u16 *oclass = oclasses;
194 struct nv50_channel_gpfifo_v0 nv50;
195 struct kepler_channel_gpfifo_a_v0 kepler;
197 struct nouveau_channel *chan;
201 /* allocate dma push buffer */
202 ret = nouveau_channel_prep(drm, device, handle, 0x12000, &chan);
207 /* create channel object */
209 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) {
210 args.kepler.version = 0;
211 args.kepler.engine = engine;
212 args.kepler.pushbuf = chan->push.ctxdma.handle;
213 args.kepler.ilength = 0x02000;
214 args.kepler.ioffset = 0x10000 + chan->push.vma.offset;
215 size = sizeof(args.kepler);
217 args.nv50.version = 0;
218 args.nv50.pushbuf = chan->push.ctxdma.handle;
219 args.nv50.ilength = 0x02000;
220 args.nv50.ioffset = 0x10000 + chan->push.vma.offset;
221 size = sizeof(args.nv50);
224 ret = nvif_object_init(&device->object, handle, *oclass++,
225 &args, size, &chan->user);
227 if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A)
228 chan->chid = args.kepler.chid;
230 chan->chid = args.nv50.chid;
235 nouveau_channel_del(pchan);
240 nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device,
241 u32 handle, struct nouveau_channel **pchan)
243 static const u16 oclasses[] = { NV40_CHANNEL_DMA,
248 const u16 *oclass = oclasses;
249 struct nv03_channel_dma_v0 args;
250 struct nouveau_channel *chan;
253 /* allocate dma push buffer */
254 ret = nouveau_channel_prep(drm, device, handle, 0x10000, &chan);
259 /* create channel object */
261 args.pushbuf = chan->push.ctxdma.handle;
262 args.offset = chan->push.vma.offset;
265 ret = nvif_object_init(&device->object, handle, *oclass++,
266 &args, sizeof(args), &chan->user);
268 chan->chid = args.chid;
271 } while (ret && *oclass);
273 nouveau_channel_del(pchan);
278 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
280 struct nvif_device *device = chan->device;
281 struct nouveau_cli *cli = (void *)chan->user.client;
282 struct nvkm_mmu *mmu = nvxx_mmu(device);
283 struct nvkm_sw_chan *swch;
284 struct nv_dma_v0 args = {};
287 nvif_object_map(&chan->user);
289 /* allocate dma objects to cover all allowed vram, and gart */
290 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
291 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
292 args.target = NV_DMA_V0_TARGET_VM;
293 args.access = NV_DMA_V0_ACCESS_VM;
295 args.limit = cli->vm->mmu->limit - 1;
297 args.target = NV_DMA_V0_TARGET_VRAM;
298 args.access = NV_DMA_V0_ACCESS_RDWR;
300 args.limit = device->info.ram_user - 1;
303 ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY,
304 &args, sizeof(args), &chan->vram);
308 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
309 args.target = NV_DMA_V0_TARGET_VM;
310 args.access = NV_DMA_V0_ACCESS_VM;
312 args.limit = cli->vm->mmu->limit - 1;
314 if (chan->drm->agp.stat == ENABLED) {
315 args.target = NV_DMA_V0_TARGET_AGP;
316 args.access = NV_DMA_V0_ACCESS_RDWR;
317 args.start = chan->drm->agp.base;
318 args.limit = chan->drm->agp.base +
319 chan->drm->agp.size - 1;
321 args.target = NV_DMA_V0_TARGET_VM;
322 args.access = NV_DMA_V0_ACCESS_RDWR;
324 args.limit = mmu->limit - 1;
327 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY,
328 &args, sizeof(args), &chan->gart);
333 /* initialise dma tracking parameters */
334 switch (chan->user.oclass & 0x00ff) {
337 chan->user_put = 0x40;
338 chan->user_get = 0x44;
339 chan->dma.max = (0x10000 / 4) - 2;
342 chan->user_put = 0x40;
343 chan->user_get = 0x44;
344 chan->user_get_hi = 0x60;
345 chan->dma.ib_base = 0x10000 / 4;
346 chan->dma.ib_max = (0x02000 / 8) - 1;
347 chan->dma.ib_put = 0;
348 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
349 chan->dma.max = chan->dma.ib_base;
354 chan->dma.cur = chan->dma.put;
355 chan->dma.free = chan->dma.max - chan->dma.cur;
357 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
361 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
362 OUT_RING(chan, 0x00000000);
364 /* allocate software object class (used for fences on <= nv05) */
365 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
366 ret = nvif_object_init(&chan->user, 0x006e, 0x006e,
367 NULL, 0, &chan->nvsw);
371 swch = (void *)nvxx_object(&chan->nvsw)->parent;
372 swch->flip = nouveau_flip_complete;
373 swch->flip_data = chan;
375 ret = RING_SPACE(chan, 2);
379 BEGIN_NV04(chan, NvSubSw, 0x0000, 1);
380 OUT_RING (chan, chan->nvsw.handle);
384 /* initialise synchronisation */
385 return nouveau_fence(chan->drm)->context_new(chan);
389 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device,
390 u32 handle, u32 arg0, u32 arg1,
391 struct nouveau_channel **pchan)
393 struct nouveau_cli *cli = (void *)device->object.client;
397 /* hack until fencenv50 is fixed, and agp access relaxed */
398 super = cli->base.super;
399 cli->base.super = true;
401 ret = nouveau_channel_ind(drm, device, handle, arg0, pchan);
403 NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret);
404 ret = nouveau_channel_dma(drm, device, handle, pchan);
406 NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret);
411 ret = nouveau_channel_init(*pchan, arg0, arg1);
413 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
414 nouveau_channel_del(pchan);
418 cli->base.super = super;