drivers/gpu/drm/nouveau/nouveau_chan.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <nvif/os.h>
  26 #include <nvif/class.h>
  27 #include <nvif/ioctl.h>
  28
  29 /*XXX*/
  30 #include <core/client.h>
  31
  32 #include "nouveau_drm.h"
  33 #include "nouveau_dma.h"
  34 #include "nouveau_bo.h"
  35 #include "nouveau_chan.h"
  36 #include "nouveau_fence.h"
  37 #include "nouveau_abi16.h"
  38
  39 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
  40 int nouveau_vram_pushbuf;
  41 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
  42
  43 int
  44 nouveau_channel_idle(struct nouveau_channel *chan)
  45 {
  46         if (likely(chan && chan->fence)) {
  47                 struct nouveau_cli *cli = (void *)chan->user.client;
  48                 struct nouveau_fence *fence = NULL;
  49                 int ret;
  50
  51                 ret = nouveau_fence_new(chan, false, &fence);
  52                 if (!ret) {
  53                         ret = nouveau_fence_wait(fence, false, false);
  54                         nouveau_fence_unref(&fence);
  55                 }
  56
  57                 if (ret) {
  58                         NV_PRINTK(err, cli, "failed to idle channel "
  59                                             "0x%08x [%s]\n",
  60                                   chan->user.handle,
  61                                   nvxx_client(&cli->base)->name);
  62                         return ret;
  63                 }
  64         }
  65         return 0;
  66 }
  67
  68 void
  69 nouveau_channel_del(struct nouveau_channel **pchan)
  70 {
  71         struct nouveau_channel *chan = *pchan;
  72         if (chan) {
  73                 if (chan->fence)
  74                         nouveau_fence(chan->drm)->context_del(chan);
  75                 nvif_object_fini(&chan->nvsw);
  76                 nvif_object_fini(&chan->gart);
  77                 nvif_object_fini(&chan->vram);
  78                 nvif_object_fini(&chan->user);
  79                 nvif_object_fini(&chan->push.ctxdma);
  80                 nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma);
  81                 nouveau_bo_unmap(chan->push.buffer);
  82                 if (chan->push.buffer && chan->push.buffer->pin_refcnt)
  83                         nouveau_bo_unpin(chan->push.buffer);
  84                 nouveau_bo_ref(NULL, &chan->push.buffer);
  85                 kfree(chan);
  86         }
  87         *pchan = NULL;
  88 }
  89
  90 static int
  91 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
  92                      u32 handle, u32 size, struct nouveau_channel **pchan)
  93 {
  94         struct nouveau_cli *cli = (void *)device->object.client;
  95         struct nvkm_mmu *mmu = nvxx_mmu(device);
  96         struct nv_dma_v0 args = {};
  97         struct nouveau_channel *chan;
  98         u32 target;
  99         int ret;
 100
 101         chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
 102         if (!chan)
 103                 return -ENOMEM;
 104
 105         chan->device = device;
 106         chan->drm = drm;
 107
 108         /* allocate memory for dma push buffer */
 109         target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
 110         if (nouveau_vram_pushbuf)
 111                 target = TTM_PL_FLAG_VRAM;
 112
 113         ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, NULL,
 114                             &chan->push.buffer);
 115         if (ret == 0) {
 116                 ret = nouveau_bo_pin(chan->push.buffer, target, false);
 117                 if (ret == 0)
 118                         ret = nouveau_bo_map(chan->push.buffer);
 119         }
 120
 121         if (ret) {
 122                 nouveau_channel_del(pchan);
 123                 return ret;
 124         }
 125
 126         /* create dma object covering the *entire* memory space that the
 127          * pushbuf lives in, this is because the GEM code requires that
 128          * we be able to call out to other (indirect) push buffers
 129          */
 130         chan->push.vma.offset = chan->push.buffer->bo.offset;
 131
 132         if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
 133                 ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm,
 134                                         &chan->push.vma);
 135                 if (ret) {
 136                         nouveau_channel_del(pchan);
 137                         return ret;
 138                 }
 139
 140                 args.target = NV_DMA_V0_TARGET_VM;
 141                 args.access = NV_DMA_V0_ACCESS_VM;
 142                 args.start = 0;
 143                 args.limit = cli->vm->mmu->limit - 1;
 144         } else
 145         if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
 146                 if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
 147                         /* nv04 vram pushbuf hack, retarget to its location in
 148                          * the framebuffer bar rather than direct vram access..
 149                          * nfi why this exists, it came from the -nv ddx.
 150                          */
 151                         args.target = NV_DMA_V0_TARGET_PCI;
 152                         args.access = NV_DMA_V0_ACCESS_RDWR;
 153                         args.start = nv_device_resource_start(nvxx_device(device), 1);
 154                         args.limit = args.start + device->info.ram_user - 1;
 155                 } else {
 156                         args.target = NV_DMA_V0_TARGET_VRAM;
 157                         args.access = NV_DMA_V0_ACCESS_RDWR;
 158                         args.start = 0;
 159                         args.limit = device->info.ram_user - 1;
 160                 }
 161         } else {
 162                 if (chan->drm->agp.stat == ENABLED) {
 163                         args.target = NV_DMA_V0_TARGET_AGP;
 164                         args.access = NV_DMA_V0_ACCESS_RDWR;
 165                         args.start = chan->drm->agp.base;
 166                         args.limit = chan->drm->agp.base +
 167                                      chan->drm->agp.size - 1;
 168                 } else {
 169                         args.target = NV_DMA_V0_TARGET_VM;
 170                         args.access = NV_DMA_V0_ACCESS_RDWR;
 171                         args.start = 0;
 172                         args.limit = mmu->limit - 1;
 173                 }
 174         }
 175
 176         ret = nvif_object_init(&device->object, NVDRM_PUSH |
 177                                (handle & 0xffff), NV_DMA_FROM_MEMORY,
 178                                &args, sizeof(args), &chan->push.ctxdma);
 179         if (ret) {
 180                 nouveau_channel_del(pchan);
 181                 return ret;
 182         }
 183
 184         return 0;
 185 }
 186
 187 static int
 188 nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
 189                     u32 handle, u32 engine, struct nouveau_channel **pchan)
 190 {
 191         static const u16 oclasses[] = { MAXWELL_CHANNEL_GPFIFO_A,
 192                                         KEPLER_CHANNEL_GPFIFO_A,
 193                                         FERMI_CHANNEL_GPFIFO,
 194                                         G82_CHANNEL_GPFIFO,
 195                                         NV50_CHANNEL_GPFIFO,
 196                                         0 };
 197         const u16 *oclass = oclasses;
 198         union {
 199                 struct nv50_channel_gpfifo_v0 nv50;
 200                 struct fermi_channel_gpfifo_v0 fermi;
 201                 struct kepler_channel_gpfifo_a_v0 kepler;
 202         } args;
 203         struct nouveau_channel *chan;
 204         u32 size;
 205         int ret;
 206
 207         /* allocate dma push buffer */
 208         ret = nouveau_channel_prep(drm, device, handle, 0x12000, &chan);
 209         *pchan = chan;
 210         if (ret)
 211                 return ret;
 212
 213         /* create channel object */
 214         do {
 215                 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) {
 216                         args.kepler.version = 0;
 217                         args.kepler.engine  = engine;
 218                         args.kepler.ilength = 0x02000;
 219                         args.kepler.ioffset = 0x10000 + chan->push.vma.offset;
 220                         args.kepler.vm = 0;
 221                         size = sizeof(args.kepler);
 222                 } else
 223                 if (oclass[0] >= FERMI_CHANNEL_GPFIFO) {
 224                         args.fermi.version = 0;
 225                         args.fermi.ilength = 0x02000;
 226                         args.fermi.ioffset = 0x10000 + chan->push.vma.offset;
 227                         args.fermi.vm = 0;
 228                         size = sizeof(args.fermi);
 229                 } else {
 230                         args.nv50.version = 0;
 231                         args.nv50.ilength = 0x02000;
 232                         args.nv50.ioffset = 0x10000 + chan->push.vma.offset;
 233                         args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma);
 234                         args.nv50.vm = 0;
 235                         size = sizeof(args.nv50);
 236                 }
 237
 238                 ret = nvif_object_init(&device->object, handle, *oclass++,
 239                                        &args, size, &chan->user);
 240                 if (ret == 0) {
 241                         if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A)
 242                                 chan->chid = args.kepler.chid;
 243                         else
 244                         if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO)
 245                                 chan->chid = args.fermi.chid;
 246                         else
 247                                 chan->chid = args.nv50.chid;
 248                         return ret;
 249                 }
 250         } while (*oclass);
 251
 252         nouveau_channel_del(pchan);
 253         return ret;
 254 }
 255
 256 static int
 257 nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device,
 258                     u32 handle, struct nouveau_channel **pchan)
 259 {
 260         static const u16 oclasses[] = { NV40_CHANNEL_DMA,
 261                                         NV17_CHANNEL_DMA,
 262                                         NV10_CHANNEL_DMA,
 263                                         NV03_CHANNEL_DMA,
 264                                         0 };
 265         const u16 *oclass = oclasses;
 266         struct nv03_channel_dma_v0 args;
 267         struct nouveau_channel *chan;
 268         int ret;
 269
 270         /* allocate dma push buffer */
 271         ret = nouveau_channel_prep(drm, device, handle, 0x10000, &chan);
 272         *pchan = chan;
 273         if (ret)
 274                 return ret;
 275
 276         /* create channel object */
 277         args.version = 0;
 278         args.pushbuf = nvif_handle(&chan->push.ctxdma);
 279         args.offset = chan->push.vma.offset;
 280
 281         do {
 282                 ret = nvif_object_init(&device->object, handle, *oclass++,
 283                                        &args, sizeof(args), &chan->user);
 284                 if (ret == 0) {
 285                         chan->chid = args.chid;
 286                         return ret;
 287                 }
 288         } while (ret && *oclass);
 289
 290         nouveau_channel_del(pchan);
 291         return ret;
 292 }
 293
 294 static int
 295 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
 296 {
 297         struct nvif_device *device = chan->device;
 298         struct nouveau_cli *cli = (void *)chan->user.client;
 299         struct nvkm_mmu *mmu = nvxx_mmu(device);
 300         struct nv_dma_v0 args = {};
 301         int ret, i;
 302
 303         nvif_object_map(&chan->user);
 304
 305         /* allocate dma objects to cover all allowed vram, and gart */
 306         if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
 307                 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
 308                         args.target = NV_DMA_V0_TARGET_VM;
 309                         args.access = NV_DMA_V0_ACCESS_VM;
 310                         args.start = 0;
 311                         args.limit = cli->vm->mmu->limit - 1;
 312                 } else {
 313                         args.target = NV_DMA_V0_TARGET_VRAM;
 314                         args.access = NV_DMA_V0_ACCESS_RDWR;
 315                         args.start = 0;
 316                         args.limit = device->info.ram_user - 1;
 317                 }
 318
 319                 ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY,
 320                                        &args, sizeof(args), &chan->vram);
 321                 if (ret)
 322                         return ret;
 323
 324                 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
 325                         args.target = NV_DMA_V0_TARGET_VM;
 326                         args.access = NV_DMA_V0_ACCESS_VM;
 327                         args.start = 0;
 328                         args.limit = cli->vm->mmu->limit - 1;
 329                 } else
 330                 if (chan->drm->agp.stat == ENABLED) {
 331                         args.target = NV_DMA_V0_TARGET_AGP;
 332                         args.access = NV_DMA_V0_ACCESS_RDWR;
 333                         args.start = chan->drm->agp.base;
 334                         args.limit = chan->drm->agp.base +
 335                                      chan->drm->agp.size - 1;
 336                 } else {
 337                         args.target = NV_DMA_V0_TARGET_VM;
 338                         args.access = NV_DMA_V0_ACCESS_RDWR;
 339                         args.start = 0;
 340                         args.limit = mmu->limit - 1;
 341                 }
 342
 343                 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY,
 344                                        &args, sizeof(args), &chan->gart);
 345                 if (ret)
 346                         return ret;
 347         }
 348
 349         /* initialise dma tracking parameters */
 350         switch (chan->user.oclass & 0x00ff) {
 351         case 0x006b:
 352         case 0x006e:
 353                 chan->user_put = 0x40;
 354                 chan->user_get = 0x44;
 355                 chan->dma.max = (0x10000 / 4) - 2;
 356                 break;
 357         default:
 358                 chan->user_put = 0x40;
 359                 chan->user_get = 0x44;
 360                 chan->user_get_hi = 0x60;
 361                 chan->dma.ib_base =  0x10000 / 4;
 362                 chan->dma.ib_max  = (0x02000 / 8) - 1;
 363                 chan->dma.ib_put  = 0;
 364                 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
 365                 chan->dma.max = chan->dma.ib_base;
 366                 break;
 367         }
 368
 369         chan->dma.put = 0;
 370         chan->dma.cur = chan->dma.put;
 371         chan->dma.free = chan->dma.max - chan->dma.cur;
 372
 373         ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
 374         if (ret)
 375                 return ret;
 376
 377         for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
 378                 OUT_RING(chan, 0x00000000);
 379
 380         /* allocate software object class (used for fences on <= nv05) */
 381         if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
 382                 ret = nvif_object_init(&chan->user, 0x006e,
 383                                        NVIF_IOCTL_NEW_V0_SW_NV04,
 384                                        NULL, 0, &chan->nvsw);
 385                 if (ret)
 386                         return ret;
 387
 388                 ret = RING_SPACE(chan, 2);
 389                 if (ret)
 390                         return ret;
 391
 392                 BEGIN_NV04(chan, NvSubSw, 0x0000, 1);
 393                 OUT_RING  (chan, chan->nvsw.handle);
 394                 FIRE_RING (chan);
 395         }
 396
 397         /* initialise synchronisation */
 398         return nouveau_fence(chan->drm)->context_new(chan);
 399 }
 400
 401 int
 402 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device,
 403                     u32 handle, u32 arg0, u32 arg1,
 404                     struct nouveau_channel **pchan)
 405 {
 406         struct nouveau_cli *cli = (void *)device->object.client;
 407         bool super;
 408         int ret;
 409
 410         /* hack until fencenv50 is fixed, and agp access relaxed */
 411         super = cli->base.super;
 412         cli->base.super = true;
 413
 414         ret = nouveau_channel_ind(drm, device, handle, arg0, pchan);
 415         if (ret) {
 416                 NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret);
 417                 ret = nouveau_channel_dma(drm, device, handle, pchan);
 418                 if (ret) {
 419                         NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret);
 420                         goto done;
 421                 }
 422         }
 423
 424         ret = nouveau_channel_init(*pchan, arg0, arg1);
 425         if (ret) {
 426                 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
 427                 nouveau_channel_del(pchan);
 428         }
 429
 430 done:
 431         cli->base.super = super;
 432         return ret;
 433 }