2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "nouveau@lists.freedesktop.org"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20120316"
35 #define DRIVER_MAJOR 1
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 0
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
50 struct list_head channels;
51 struct nouveau_vm *vm;
54 static inline struct nouveau_fpriv *
55 nouveau_fpriv(struct drm_file *file_priv)
57 return file_priv ? file_priv->driver_priv : NULL;
60 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
62 #include "nouveau_drm.h"
63 #include "nouveau_reg.h"
64 #include "nouveau_bios.h"
65 #include "nouveau_util.h"
69 #include "nouveau_vm.h"
71 #define MAX_NUM_DCB_ENTRIES 16
73 #define NOUVEAU_MAX_CHANNEL_NR 4096
74 #define NOUVEAU_MAX_TILE_NR 15
77 struct drm_device *dev;
79 struct nouveau_vma bar_vma;
80 struct nouveau_vma vma[2];
83 struct drm_mm_node *tag;
84 struct list_head regions;
92 struct nouveau_tile_reg {
98 struct drm_mm_node *tag_mem;
99 struct nouveau_fence *fence;
103 struct ttm_buffer_object bo;
104 struct ttm_placement placement;
107 u32 busy_placements[3];
108 struct ttm_bo_kmap_obj kmap;
109 struct list_head head;
111 /* protected by ttm_bo_reserve() */
112 struct drm_file *reserved_by;
113 struct list_head entry;
115 bool validate_mapped;
117 struct list_head vma_list;
122 struct nouveau_tile_reg *tile;
124 struct drm_gem_object *gem;
127 struct ttm_bo_kmap_obj dma_buf_vmap;
131 #define nouveau_bo_tile_layout(nvbo) \
132 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
134 static inline struct nouveau_bo *
135 nouveau_bo(struct ttm_buffer_object *bo)
137 return container_of(bo, struct nouveau_bo, bo);
140 static inline struct nouveau_bo *
141 nouveau_gem_object(struct drm_gem_object *gem)
143 return gem ? gem->driver_private : NULL;
146 /* TODO: submit equivalent to TTM generic API upstream? */
147 static inline void __iomem *
148 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
151 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
152 &nvbo->kmap, &is_iomem);
153 WARN_ON_ONCE(ioptr && !is_iomem);
158 NV_NFORCE = 0x10000000,
159 NV_NFORCE2 = 0x20000000
162 #define NVOBJ_ENGINE_SW 0
163 #define NVOBJ_ENGINE_GR 1
164 #define NVOBJ_ENGINE_CRYPT 2
165 #define NVOBJ_ENGINE_COPY0 3
166 #define NVOBJ_ENGINE_COPY1 4
167 #define NVOBJ_ENGINE_MPEG 5
168 #define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG
169 #define NVOBJ_ENGINE_BSP 6
170 #define NVOBJ_ENGINE_VP 7
171 #define NVOBJ_ENGINE_FIFO 14
172 #define NVOBJ_ENGINE_FENCE 15
173 #define NVOBJ_ENGINE_NR 16
174 #define NVOBJ_ENGINE_DISPLAY (NVOBJ_ENGINE_NR + 0) /*XXX*/
176 #define NVOBJ_FLAG_DONT_MAP (1 << 0)
177 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
178 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
179 #define NVOBJ_FLAG_VM (1 << 3)
180 #define NVOBJ_FLAG_VM_USER (1 << 4)
182 #define NVOBJ_CINST_GLOBAL 0xdeadbeef
184 struct nouveau_gpuobj {
185 struct drm_device *dev;
186 struct kref refcount;
187 struct list_head list;
195 u32 pinst; /* PRAMIN BAR offset */
196 u32 cinst; /* Channel offset */
197 u64 vinst; /* VRAM address */
198 u64 linst; /* VM address */
203 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
207 struct nouveau_page_flip_state {
208 struct list_head head;
209 struct drm_pending_vblank_event *event;
210 int crtc, bpp, pitch, x, y;
214 enum nouveau_channel_mutex_class {
215 NOUVEAU_UCHANNEL_MUTEX,
216 NOUVEAU_KCHANNEL_MUTEX
219 struct nouveau_channel {
220 struct drm_device *dev;
221 struct list_head list;
224 /* references to the channel data structure */
226 /* users of the hardware channel resources, the hardware
227 * context will be kicked off when it reaches zero. */
231 /* owner of this fifo */
232 struct drm_file *file_priv;
233 /* mapping of the fifo itself */
234 struct drm_local_map *map;
236 /* mapping of the regs controlling the fifo */
239 uint32_t user_get_hi;
242 /* DMA push buffer */
243 struct nouveau_gpuobj *pushbuf;
244 struct nouveau_bo *pushbuf_bo;
245 struct nouveau_vma pushbuf_vma;
246 uint64_t pushbuf_base;
248 /* Notifier memory */
249 struct nouveau_bo *notifier_bo;
250 struct nouveau_vma notifier_vma;
251 struct drm_mm notifier_heap;
254 struct nouveau_gpuobj *ramfc;
256 /* Execution engine contexts */
257 void *engctx[NVOBJ_ENGINE_NR];
260 struct nouveau_vm *vm;
261 struct nouveau_gpuobj *vm_pd;
264 struct nouveau_gpuobj *ramin; /* Private instmem */
265 struct drm_mm ramin_heap; /* Private PRAMIN heap */
266 struct nouveau_ramht *ramht; /* Hash table */
268 /* GPU object info for stuff used in-kernel (mm_enabled) */
270 uint32_t vram_handle;
271 uint32_t gart_handle;
274 /* Push buffer state (only for drm's channel on !mm_enabled) */
280 /* access via pushbuf_bo */
291 struct drm_info_list info;
295 struct nouveau_exec_engine {
296 void (*destroy)(struct drm_device *, int engine);
297 int (*init)(struct drm_device *, int engine);
298 int (*fini)(struct drm_device *, int engine, bool suspend);
299 int (*context_new)(struct nouveau_channel *, int engine);
300 void (*context_del)(struct nouveau_channel *, int engine);
301 int (*object_new)(struct nouveau_channel *, int engine,
302 u32 handle, u16 class);
303 void (*set_tile_region)(struct drm_device *dev, int i);
304 void (*tlb_flush)(struct drm_device *, int engine);
307 struct nouveau_instmem_engine {
310 int (*init)(struct drm_device *dev);
311 void (*takedown)(struct drm_device *dev);
312 int (*suspend)(struct drm_device *dev);
313 void (*resume)(struct drm_device *dev);
315 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *,
316 u32 size, u32 align);
317 void (*put)(struct nouveau_gpuobj *);
318 int (*map)(struct nouveau_gpuobj *);
319 void (*unmap)(struct nouveau_gpuobj *);
321 void (*flush)(struct drm_device *);
324 struct nouveau_mc_engine {
325 int (*init)(struct drm_device *dev);
326 void (*takedown)(struct drm_device *dev);
329 struct nouveau_timer_engine {
330 int (*init)(struct drm_device *dev);
331 void (*takedown)(struct drm_device *dev);
332 uint64_t (*read)(struct drm_device *dev);
335 struct nouveau_fb_engine {
337 struct drm_mm tag_heap;
340 int (*init)(struct drm_device *dev);
341 void (*takedown)(struct drm_device *dev);
343 void (*init_tile_region)(struct drm_device *dev, int i,
344 uint32_t addr, uint32_t size,
345 uint32_t pitch, uint32_t flags);
346 void (*set_tile_region)(struct drm_device *dev, int i);
347 void (*free_tile_region)(struct drm_device *dev, int i);
350 struct nouveau_display_engine {
352 int (*early_init)(struct drm_device *);
353 void (*late_takedown)(struct drm_device *);
354 int (*create)(struct drm_device *);
355 void (*destroy)(struct drm_device *);
356 int (*init)(struct drm_device *);
357 void (*fini)(struct drm_device *);
359 struct drm_property *dithering_mode;
360 struct drm_property *dithering_depth;
361 struct drm_property *underscan_property;
362 struct drm_property *underscan_hborder_property;
363 struct drm_property *underscan_vborder_property;
364 /* not really hue and saturation: */
365 struct drm_property *vibrant_hue_property;
366 struct drm_property *color_vibrance_property;
369 struct nouveau_gpio_engine {
371 struct list_head isr;
372 int (*init)(struct drm_device *);
373 void (*fini)(struct drm_device *);
374 int (*drive)(struct drm_device *, int line, int dir, int out);
375 int (*sense)(struct drm_device *, int line);
376 void (*irq_enable)(struct drm_device *, int line, bool);
379 struct nouveau_pm_voltage_level {
380 u32 voltage; /* microvolts */
384 struct nouveau_pm_voltage {
389 struct nouveau_pm_voltage_level *level;
393 /* Exclusive upper limits */
394 #define NV_MEM_CL_DDR2_MAX 8
395 #define NV_MEM_WR_DDR2_MAX 9
396 #define NV_MEM_CL_DDR3_MAX 17
397 #define NV_MEM_WR_DDR3_MAX 17
398 #define NV_MEM_CL_GDDR3_MAX 16
399 #define NV_MEM_WR_GDDR3_MAX 18
400 #define NV_MEM_CL_GDDR5_MAX 21
401 #define NV_MEM_WR_GDDR5_MAX 20
403 struct nouveau_pm_memtiming {
415 struct nouveau_pm_tbl_header {
422 struct nouveau_pm_tbl_entry {
428 u8 tRFC; /* Byte 5 */
430 u8 tRAS; /* Byte 7 */
437 u8 RAM_FT1; /* 14, a bitmask of random RAM features */
446 struct nouveau_pm_profile;
447 struct nouveau_pm_profile_func {
448 void (*destroy)(struct nouveau_pm_profile *);
449 void (*init)(struct nouveau_pm_profile *);
450 void (*fini)(struct nouveau_pm_profile *);
451 struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
454 struct nouveau_pm_profile {
455 const struct nouveau_pm_profile_func *func;
456 struct list_head head;
460 #define NOUVEAU_PM_MAX_LEVEL 8
461 struct nouveau_pm_level {
462 struct nouveau_pm_profile profile;
463 struct device_attribute dev_attr;
467 struct nouveau_pm_memtiming timing;
478 u32 unka0; /* nva3:nvc0 */
479 u32 hub01; /* nvc0- */
480 u32 hub06; /* nvc0- */
481 u32 hub07; /* nvc0- */
483 u32 volt_min; /* microvolts */
488 struct nouveau_pm_temp_sensor_constants {
496 struct nouveau_pm_threshold_temp {
502 struct nouveau_pm_fan {
510 struct nouveau_pm_engine {
511 struct nouveau_pm_voltage voltage;
512 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
514 struct nouveau_pm_temp_sensor_constants sensor_constants;
515 struct nouveau_pm_threshold_temp threshold_temp;
516 struct nouveau_pm_fan fan;
518 struct nouveau_pm_profile *profile_ac;
519 struct nouveau_pm_profile *profile_dc;
520 struct nouveau_pm_profile *profile;
521 struct list_head profiles;
523 struct nouveau_pm_level boot;
524 struct nouveau_pm_level *cur;
526 struct device *hwmon;
527 struct notifier_block acpi_nb;
529 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
530 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
531 int (*clocks_set)(struct drm_device *, void *);
533 int (*voltage_get)(struct drm_device *);
534 int (*voltage_set)(struct drm_device *, int voltage);
535 int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
536 int (*pwm_set)(struct drm_device *, int line, u32, u32);
537 int (*temp_get)(struct drm_device *);
540 struct nouveau_vram_engine {
541 struct nouveau_mm mm;
543 int (*init)(struct drm_device *);
544 void (*takedown)(struct drm_device *dev);
545 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
546 u32 type, struct nouveau_mem **);
547 void (*put)(struct drm_device *, struct nouveau_mem **);
549 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
552 struct nouveau_engine {
553 struct nouveau_instmem_engine instmem;
554 struct nouveau_mc_engine mc;
555 struct nouveau_timer_engine timer;
556 struct nouveau_fb_engine fb;
557 struct nouveau_display_engine display;
558 struct nouveau_gpio_engine gpio;
559 struct nouveau_pm_engine pm;
560 struct nouveau_vram_engine vram;
563 struct nouveau_pll_vals {
567 uint8_t N1, M1, N2, M2;
569 uint8_t M1, N1, M2, N2;
574 } __attribute__((packed));
581 enum nv04_fp_display_regs {
591 struct nv04_crtc_reg {
592 unsigned char MiscOutReg;
595 uint8_t Sequencer[5];
597 uint8_t Attribute[21];
598 unsigned char DAC[768];
608 uint32_t crtc_eng_ctrl;
611 uint32_t nv10_cursync;
612 struct nouveau_pll_vals pllvals;
613 uint32_t ramdac_gen_ctrl;
619 uint32_t tv_vsync_delay;
622 uint32_t tv_hsync_delay;
623 uint32_t tv_hsync_delay2;
624 uint32_t fp_horiz_regs[7];
625 uint32_t fp_vert_regs[7];
628 uint32_t dither_regs[6];
632 uint32_t fp_margin_color;
637 uint32_t ctv_regs[38];
640 struct nv04_output_reg {
645 struct nv04_mode_state {
646 struct nv04_crtc_reg crtc_reg[2];
651 enum nouveau_card_type {
663 struct drm_nouveau_private {
664 struct drm_device *dev;
667 /* the card type, takes NV_* as values */
668 enum nouveau_card_type card_type;
669 /* exact chipset, derived from NV_PMC_BOOT_0 */
676 spinlock_t ramin_lock;
680 bool ramin_available;
681 struct drm_mm ramin_heap;
682 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR];
683 struct list_head gpuobj_list;
684 struct list_head classes;
686 struct nouveau_bo *vga_ram;
688 /* interrupt handling */
689 void (*irq_handler[32])(struct drm_device *);
692 struct list_head vbl_waiting;
695 struct drm_global_reference mem_global_ref;
696 struct ttm_bo_global_ref bo_global_ref;
697 struct ttm_bo_device bdev;
698 atomic_t validate_sequence;
699 int (*move)(struct nouveau_channel *,
700 struct ttm_buffer_object *,
701 struct ttm_mem_reg *, struct ttm_mem_reg *);
707 struct nouveau_bo *bo;
712 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
715 struct nouveau_engine engine;
716 struct nouveau_channel *channel;
718 /* For PFIFO and PGRAPH. */
719 spinlock_t context_switch_lock;
721 /* VM/PRAMIN flush, legacy PRAMIN aperture */
724 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
725 struct nouveau_ramht *ramht;
726 struct nouveau_gpuobj *ramfc;
727 struct nouveau_gpuobj *ramro;
729 uint32_t ramin_rsvd_vram;
733 NOUVEAU_GART_NONE = 0,
734 NOUVEAU_GART_AGP, /* AGP */
735 NOUVEAU_GART_PDMA, /* paged dma object */
736 NOUVEAU_GART_HW /* on-chip gart/vm */
742 struct ttm_backend_func *func;
749 struct nouveau_gpuobj *sg_ctxdma;
752 /* nv10-nv40 tiling regions */
754 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
758 /* VRAM/fb configuration */
760 NV_MEM_TYPE_UNKNOWN = 0,
773 uint64_t vram_sys_base;
776 uint64_t fb_available_size;
777 uint64_t fb_mappable_pages;
778 uint64_t fb_aper_free;
781 /* BAR control (NV50-) */
782 struct nouveau_vm *bar1_vm;
783 struct nouveau_vm *bar3_vm;
785 /* G8x/G9x virtual address space */
786 struct nouveau_vm *chan_vm;
790 struct list_head i2c_ports;
792 struct nv04_mode_state mode_reg;
793 struct nv04_mode_state saved_reg;
794 uint32_t saved_vga_font[4][16384];
796 uint32_t dac_users[4];
798 struct backlight_device *backlight;
801 struct dentry *channel_root;
804 struct nouveau_fbdev *nfbdev;
805 struct apertures_struct *apertures;
808 static inline struct drm_nouveau_private *
809 nouveau_private(struct drm_device *dev)
811 return dev->dev_private;
814 static inline struct drm_nouveau_private *
815 nouveau_bdev(struct ttm_bo_device *bd)
817 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
821 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
823 struct nouveau_bo *prev;
829 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
831 struct ttm_buffer_object *bo = &prev->bo;
840 extern int nouveau_modeset;
841 extern int nouveau_agpmode;
842 extern int nouveau_duallink;
843 extern int nouveau_uscript_lvds;
844 extern int nouveau_uscript_tmds;
845 extern int nouveau_vram_pushbuf;
846 extern int nouveau_vram_notify;
847 extern char *nouveau_vram_type;
848 extern int nouveau_fbpercrtc;
849 extern int nouveau_tv_disable;
850 extern char *nouveau_tv_norm;
851 extern int nouveau_reg_debug;
852 extern char *nouveau_vbios;
853 extern int nouveau_ignorelid;
854 extern int nouveau_nofbaccel;
855 extern int nouveau_noaccel;
856 extern int nouveau_force_post;
857 extern int nouveau_override_conntype;
858 extern char *nouveau_perflvl;
859 extern int nouveau_perflvl_wr;
860 extern int nouveau_msi;
861 extern int nouveau_ctxfw;
862 extern int nouveau_mxmdcb;
864 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
865 extern int nouveau_pci_resume(struct pci_dev *pdev);
867 /* nouveau_state.c */
868 extern int nouveau_open(struct drm_device *, struct drm_file *);
869 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
870 extern void nouveau_postclose(struct drm_device *, struct drm_file *);
871 extern int nouveau_load(struct drm_device *, unsigned long flags);
872 extern int nouveau_firstopen(struct drm_device *);
873 extern void nouveau_lastclose(struct drm_device *);
874 extern int nouveau_unload(struct drm_device *);
875 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
876 uint32_t reg, uint32_t mask, uint32_t val);
877 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
878 uint32_t reg, uint32_t mask, uint32_t val);
879 extern bool nouveau_wait_cb(struct drm_device *, u64 timeout,
880 bool (*cond)(void *), void *);
881 extern bool nouveau_wait_for_idle(struct drm_device *);
882 extern int nouveau_card_init(struct drm_device *);
885 extern int nouveau_mem_vram_init(struct drm_device *);
886 extern void nouveau_mem_vram_fini(struct drm_device *);
887 extern int nouveau_mem_gart_init(struct drm_device *);
888 extern void nouveau_mem_gart_fini(struct drm_device *);
889 extern int nouveau_mem_init_agp(struct drm_device *);
890 extern int nouveau_mem_reset_agp(struct drm_device *);
891 extern void nouveau_mem_close(struct drm_device *);
892 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
893 extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
894 struct nouveau_pm_memtiming *);
895 extern void nouveau_mem_timing_read(struct drm_device *,
896 struct nouveau_pm_memtiming *);
897 extern int nouveau_mem_vbios_type(struct drm_device *);
898 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
899 struct drm_device *dev, uint32_t addr, uint32_t size,
900 uint32_t pitch, uint32_t flags);
901 extern void nv10_mem_put_tile_region(struct drm_device *dev,
902 struct nouveau_tile_reg *tile,
903 struct nouveau_fence *fence);
904 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
905 extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
907 /* nouveau_notifier.c */
908 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
909 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
910 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
911 int cout, uint32_t start, uint32_t end,
914 /* nouveau_channel.c */
915 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
916 extern int nouveau_channel_alloc(struct drm_device *dev,
917 struct nouveau_channel **chan,
918 struct drm_file *file_priv,
919 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
920 extern struct nouveau_channel *
921 nouveau_channel_get_unlocked(struct nouveau_channel *);
922 extern struct nouveau_channel *
923 nouveau_channel_get(struct drm_file *, int id);
924 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
925 extern void nouveau_channel_put(struct nouveau_channel **);
926 extern void nouveau_channel_ref(struct nouveau_channel *chan,
927 struct nouveau_channel **pchan);
928 extern int nouveau_channel_idle(struct nouveau_channel *chan);
930 /* nouveau_gpuobj.c */
931 #define NVOBJ_ENGINE_ADD(d, e, p) do { \
932 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
933 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
936 #define NVOBJ_ENGINE_DEL(d, e) do { \
937 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
938 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \
941 #define NVOBJ_CLASS(d, c, e) do { \
942 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
947 #define NVOBJ_MTHD(d, c, m, e) do { \
948 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
953 extern int nouveau_gpuobj_early_init(struct drm_device *);
954 extern int nouveau_gpuobj_init(struct drm_device *);
955 extern void nouveau_gpuobj_takedown(struct drm_device *);
956 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
957 extern void nouveau_gpuobj_resume(struct drm_device *dev);
958 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
959 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
960 int (*exec)(struct nouveau_channel *,
961 u32 class, u32 mthd, u32 data));
962 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
963 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
964 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
965 uint32_t vram_h, uint32_t tt_h);
966 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
967 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
968 uint32_t size, int align, uint32_t flags,
969 struct nouveau_gpuobj **);
970 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
971 struct nouveau_gpuobj **);
972 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
974 struct nouveau_gpuobj **);
975 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
976 uint64_t offset, uint64_t size, int access,
977 int target, struct nouveau_gpuobj **);
978 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
979 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
980 u64 size, int target, int access, u32 type,
981 u32 comp, struct nouveau_gpuobj **pobj);
982 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
983 int class, u64 base, u64 size, int target,
984 int access, u32 type, u32 comp);
987 extern int nouveau_irq_init(struct drm_device *);
988 extern void nouveau_irq_fini(struct drm_device *);
989 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
990 extern void nouveau_irq_register(struct drm_device *, int status_bit,
991 void (*)(struct drm_device *));
992 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
993 extern void nouveau_irq_preinstall(struct drm_device *);
994 extern int nouveau_irq_postinstall(struct drm_device *);
995 extern void nouveau_irq_uninstall(struct drm_device *);
997 /* nouveau_sgdma.c */
998 extern int nouveau_sgdma_init(struct drm_device *);
999 extern void nouveau_sgdma_takedown(struct drm_device *);
1000 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
1002 extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev,
1004 uint32_t page_flags,
1005 struct page *dummy_read_page);
1007 /* nouveau_debugfs.c */
1008 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
1009 extern int nouveau_debugfs_init(struct drm_minor *);
1010 extern void nouveau_debugfs_takedown(struct drm_minor *);
1011 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
1012 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
1015 nouveau_debugfs_init(struct drm_minor *minor)
1020 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
1025 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
1031 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
1037 extern void nouveau_dma_init(struct nouveau_channel *);
1038 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
1040 /* nouveau_acpi.c */
1041 #define ROM_BIOS_PAGE 4096
1042 #if defined(CONFIG_ACPI)
1043 void nouveau_register_dsm_handler(void);
1044 void nouveau_unregister_dsm_handler(void);
1045 void nouveau_switcheroo_optimus_dsm(void);
1046 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
1047 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
1048 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
1050 static inline void nouveau_register_dsm_handler(void) {}
1051 static inline void nouveau_unregister_dsm_handler(void) {}
1052 static inline void nouveau_switcheroo_optimus_dsm(void) {}
1053 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
1054 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
1055 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
1058 /* nouveau_backlight.c */
1059 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1060 extern int nouveau_backlight_init(struct drm_device *);
1061 extern void nouveau_backlight_exit(struct drm_device *);
1063 static inline int nouveau_backlight_init(struct drm_device *dev)
1068 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
1071 /* nouveau_bios.c */
1072 extern int nouveau_bios_init(struct drm_device *);
1073 extern void nouveau_bios_takedown(struct drm_device *dev);
1074 extern int nouveau_run_vbios_init(struct drm_device *);
1075 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1076 struct dcb_entry *, int crtc);
1077 extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table);
1078 extern struct dcb_connector_table_entry *
1079 nouveau_bios_connector_entry(struct drm_device *, int index);
1080 extern u32 get_pll_register(struct drm_device *, enum pll_types);
1081 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1083 extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
1084 struct dcb_entry *, int crtc);
1085 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1086 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1087 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1088 bool *dl, bool *if_is_24bit);
1089 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1090 int head, int pxclk);
1091 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1092 enum LVDS_script, int pxclk);
1093 bool bios_encoder_match(struct dcb_entry *, u32 hash);
1096 int nouveau_mxm_init(struct drm_device *dev);
1097 void nouveau_mxm_fini(struct drm_device *dev);
1100 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1101 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1102 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1104 /* nouveau_hdmi.c */
1105 void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
1108 extern int nv04_fb_vram_init(struct drm_device *);
1109 extern int nv04_fb_init(struct drm_device *);
1110 extern void nv04_fb_takedown(struct drm_device *);
1113 extern int nv10_fb_vram_init(struct drm_device *dev);
1114 extern int nv1a_fb_vram_init(struct drm_device *dev);
1115 extern int nv10_fb_init(struct drm_device *);
1116 extern void nv10_fb_takedown(struct drm_device *);
1117 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1118 uint32_t addr, uint32_t size,
1119 uint32_t pitch, uint32_t flags);
1120 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1121 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1124 extern int nv20_fb_vram_init(struct drm_device *dev);
1125 extern int nv20_fb_init(struct drm_device *);
1126 extern void nv20_fb_takedown(struct drm_device *);
1127 extern void nv20_fb_init_tile_region(struct drm_device *dev, int i,
1128 uint32_t addr, uint32_t size,
1129 uint32_t pitch, uint32_t flags);
1130 extern void nv20_fb_set_tile_region(struct drm_device *dev, int i);
1131 extern void nv20_fb_free_tile_region(struct drm_device *dev, int i);
1134 extern int nv30_fb_init(struct drm_device *);
1135 extern void nv30_fb_takedown(struct drm_device *);
1136 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1137 uint32_t addr, uint32_t size,
1138 uint32_t pitch, uint32_t flags);
1139 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1142 extern int nv40_fb_vram_init(struct drm_device *dev);
1143 extern int nv40_fb_init(struct drm_device *);
1144 extern void nv40_fb_takedown(struct drm_device *);
1145 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1148 extern int nv50_fb_init(struct drm_device *);
1149 extern void nv50_fb_takedown(struct drm_device *);
1150 extern void nv50_fb_vm_trap(struct drm_device *, int display);
1153 extern int nvc0_fb_init(struct drm_device *);
1154 extern void nvc0_fb_takedown(struct drm_device *);
1157 extern int nv04_graph_create(struct drm_device *);
1158 extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
1159 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1160 u32 class, u32 mthd, u32 data);
1161 extern struct nouveau_bitfield nv04_graph_nsource[];
1164 extern int nv10_graph_create(struct drm_device *);
1165 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1166 extern struct nouveau_bitfield nv10_graph_intr[];
1167 extern struct nouveau_bitfield nv10_graph_nstatus[];
1170 extern int nv20_graph_create(struct drm_device *);
1173 extern int nv40_graph_create(struct drm_device *);
1174 extern void nv40_grctx_init(struct drm_device *, u32 *size);
1175 extern void nv40_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);
1178 extern int nv50_graph_create(struct drm_device *);
1179 extern struct nouveau_enum nv50_data_error_names[];
1180 extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
1181 extern int nv50_grctx_init(struct drm_device *, u32 *, u32, u32 *, u32 *);
1182 extern void nv50_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);
1185 extern int nvc0_graph_create(struct drm_device *);
1186 extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst);
1189 extern int nve0_graph_create(struct drm_device *);
1192 extern int nv84_crypt_create(struct drm_device *);
1195 extern int nv98_crypt_create(struct drm_device *dev);
1198 extern int nva3_copy_create(struct drm_device *dev);
1201 extern int nvc0_copy_create(struct drm_device *dev, int engine);
1204 extern int nv31_mpeg_create(struct drm_device *dev);
1207 extern int nv50_mpeg_create(struct drm_device *dev);
1211 extern int nv84_bsp_create(struct drm_device *dev);
1215 extern int nv84_vp_create(struct drm_device *dev);
1218 extern int nv98_ppp_create(struct drm_device *dev);
1220 /* nv04_instmem.c */
1221 extern int nv04_instmem_init(struct drm_device *);
1222 extern void nv04_instmem_takedown(struct drm_device *);
1223 extern int nv04_instmem_suspend(struct drm_device *);
1224 extern void nv04_instmem_resume(struct drm_device *);
1225 extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1226 u32 size, u32 align);
1227 extern void nv04_instmem_put(struct nouveau_gpuobj *);
1228 extern int nv04_instmem_map(struct nouveau_gpuobj *);
1229 extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
1230 extern void nv04_instmem_flush(struct drm_device *);
1232 /* nv50_instmem.c */
1233 extern int nv50_instmem_init(struct drm_device *);
1234 extern void nv50_instmem_takedown(struct drm_device *);
1235 extern int nv50_instmem_suspend(struct drm_device *);
1236 extern void nv50_instmem_resume(struct drm_device *);
1237 extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1238 u32 size, u32 align);
1239 extern void nv50_instmem_put(struct nouveau_gpuobj *);
1240 extern int nv50_instmem_map(struct nouveau_gpuobj *);
1241 extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
1242 extern void nv50_instmem_flush(struct drm_device *);
1243 extern void nv84_instmem_flush(struct drm_device *);
1245 /* nvc0_instmem.c */
1246 extern int nvc0_instmem_init(struct drm_device *);
1247 extern void nvc0_instmem_takedown(struct drm_device *);
1248 extern int nvc0_instmem_suspend(struct drm_device *);
1249 extern void nvc0_instmem_resume(struct drm_device *);
1252 extern int nv04_mc_init(struct drm_device *);
1253 extern void nv04_mc_takedown(struct drm_device *);
1256 extern int nv40_mc_init(struct drm_device *);
1257 extern void nv40_mc_takedown(struct drm_device *);
1260 extern int nv50_mc_init(struct drm_device *);
1261 extern void nv50_mc_takedown(struct drm_device *);
1264 extern int nv04_timer_init(struct drm_device *);
1265 extern uint64_t nv04_timer_read(struct drm_device *);
1266 extern void nv04_timer_takedown(struct drm_device *);
1268 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1272 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1273 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1274 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1275 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1276 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1279 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1280 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1281 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1283 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1284 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1287 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1288 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1291 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1293 /* nv04_display.c */
1294 extern int nv04_display_early_init(struct drm_device *);
1295 extern void nv04_display_late_takedown(struct drm_device *);
1296 extern int nv04_display_create(struct drm_device *);
1297 extern void nv04_display_destroy(struct drm_device *);
1298 extern int nv04_display_init(struct drm_device *);
1299 extern void nv04_display_fini(struct drm_device *);
1301 /* nvd0_display.c */
1302 extern int nvd0_display_create(struct drm_device *);
1303 extern void nvd0_display_destroy(struct drm_device *);
1304 extern int nvd0_display_init(struct drm_device *);
1305 extern void nvd0_display_fini(struct drm_device *);
1306 struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc);
1307 void nvd0_display_flip_stop(struct drm_crtc *);
1308 int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
1309 struct nouveau_channel *, u32 swap_interval);
1312 extern int nv04_crtc_create(struct drm_device *, int index);
1315 extern struct ttm_bo_driver nouveau_bo_driver;
1316 extern void nouveau_bo_move_init(struct nouveau_channel *);
1317 extern int nouveau_bo_new(struct drm_device *, int size, int align,
1318 uint32_t flags, uint32_t tile_mode,
1319 uint32_t tile_flags,
1320 struct sg_table *sg,
1321 struct nouveau_bo **);
1322 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1323 extern int nouveau_bo_unpin(struct nouveau_bo *);
1324 extern int nouveau_bo_map(struct nouveau_bo *);
1325 extern void nouveau_bo_unmap(struct nouveau_bo *);
1326 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1328 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1329 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1330 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1331 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1332 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1333 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1334 bool no_wait_reserve, bool no_wait_gpu);
1336 extern struct nouveau_vma *
1337 nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *);
1338 extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *,
1339 struct nouveau_vma *);
1340 extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *);
1343 extern int nouveau_gem_new(struct drm_device *, int size, int align,
1344 uint32_t domain, uint32_t tile_mode,
1345 uint32_t tile_flags, struct nouveau_bo **);
1346 extern int nouveau_gem_object_new(struct drm_gem_object *);
1347 extern void nouveau_gem_object_del(struct drm_gem_object *);
1348 extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *);
1349 extern void nouveau_gem_object_close(struct drm_gem_object *,
1351 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1353 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1355 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1357 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1359 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1362 extern struct dma_buf *nouveau_gem_prime_export(struct drm_device *dev,
1363 struct drm_gem_object *obj, int flags);
1364 extern struct drm_gem_object *nouveau_gem_prime_import(struct drm_device *dev,
1365 struct dma_buf *dma_buf);
1367 /* nouveau_display.c */
1368 int nouveau_display_create(struct drm_device *dev);
1369 void nouveau_display_destroy(struct drm_device *dev);
1370 int nouveau_display_init(struct drm_device *dev);
1371 void nouveau_display_fini(struct drm_device *dev);
1372 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1373 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1374 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1375 struct drm_pending_vblank_event *event);
1376 int nouveau_finish_page_flip(struct nouveau_channel *,
1377 struct nouveau_page_flip_state *);
1378 int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
1379 struct drm_mode_create_dumb *args);
1380 int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
1381 uint32_t handle, uint64_t *offset);
1382 int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
1386 int nv10_gpio_init(struct drm_device *dev);
1387 void nv10_gpio_fini(struct drm_device *dev);
1388 int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1389 int nv10_gpio_sense(struct drm_device *dev, int line);
1390 void nv10_gpio_irq_enable(struct drm_device *, int line, bool on);
1393 int nv50_gpio_init(struct drm_device *dev);
1394 void nv50_gpio_fini(struct drm_device *dev);
1395 int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1396 int nv50_gpio_sense(struct drm_device *dev, int line);
1397 void nv50_gpio_irq_enable(struct drm_device *, int line, bool on);
1398 int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1399 int nvd0_gpio_sense(struct drm_device *dev, int line);
1402 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1403 int *N1, int *M1, int *N2, int *M2, int *P);
1404 int nva3_calc_pll(struct drm_device *, struct pll_lims *,
1405 int clk, int *N, int *fN, int *M, int *P);
1407 #ifndef ioread32_native
1409 #define ioread16_native ioread16be
1410 #define iowrite16_native iowrite16be
1411 #define ioread32_native ioread32be
1412 #define iowrite32_native iowrite32be
1413 #else /* def __BIG_ENDIAN */
1414 #define ioread16_native ioread16
1415 #define iowrite16_native iowrite16
1416 #define ioread32_native ioread32
1417 #define iowrite32_native iowrite32
1418 #endif /* def __BIG_ENDIAN else */
1419 #endif /* !ioread32_native */
1421 /* channel control reg access */
1422 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1424 return ioread32_native(chan->user + reg);
1427 static inline void nvchan_wr32(struct nouveau_channel *chan,
1428 unsigned reg, u32 val)
1430 iowrite32_native(val, chan->user + reg);
1433 /* register access */
1434 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1436 struct drm_nouveau_private *dev_priv = dev->dev_private;
1437 return ioread32_native(dev_priv->mmio + reg);
1440 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1442 struct drm_nouveau_private *dev_priv = dev->dev_private;
1443 iowrite32_native(val, dev_priv->mmio + reg);
1446 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1448 u32 tmp = nv_rd32(dev, reg);
1449 nv_wr32(dev, reg, (tmp & ~mask) | val);
1453 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1455 struct drm_nouveau_private *dev_priv = dev->dev_private;
1456 return ioread8(dev_priv->mmio + reg);
1459 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1461 struct drm_nouveau_private *dev_priv = dev->dev_private;
1462 iowrite8(val, dev_priv->mmio + reg);
1465 #define nv_wait(dev, reg, mask, val) \
1466 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1467 #define nv_wait_ne(dev, reg, mask, val) \
1468 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
1469 #define nv_wait_cb(dev, func, data) \
1470 nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
1473 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1475 struct drm_nouveau_private *dev_priv = dev->dev_private;
1476 return ioread32_native(dev_priv->ramin + offset);
1479 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1481 struct drm_nouveau_private *dev_priv = dev->dev_private;
1482 iowrite32_native(val, dev_priv->ramin + offset);
1486 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1487 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1491 * Argument d is (struct drm_device *).
1493 #define NV_PRINTK(level, d, fmt, arg...) \
1494 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1495 pci_name(d->pdev), ##arg)
1496 #ifndef NV_DEBUG_NOTRACE
1497 #define NV_DEBUG(d, fmt, arg...) do { \
1498 if (drm_debug & DRM_UT_DRIVER) { \
1499 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1503 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1504 if (drm_debug & DRM_UT_KMS) { \
1505 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1510 #define NV_DEBUG(d, fmt, arg...) do { \
1511 if (drm_debug & DRM_UT_DRIVER) \
1512 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1514 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1515 if (drm_debug & DRM_UT_KMS) \
1516 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1519 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1520 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1521 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1522 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1523 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1524 #define NV_WARNONCE(d, fmt, arg...) do { \
1525 static int _warned = 0; \
1527 NV_WARN(d, fmt, ##arg); \
1532 /* nouveau_reg_debug bitmask */
1534 NOUVEAU_REG_DEBUG_MC = 0x1,
1535 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1536 NOUVEAU_REG_DEBUG_FB = 0x4,
1537 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1538 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1539 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1540 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1541 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1542 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1543 NOUVEAU_REG_DEBUG_EVO = 0x200,
1544 NOUVEAU_REG_DEBUG_AUXCH = 0x400
1547 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1548 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1549 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1553 nv_two_heads(struct drm_device *dev)
1555 struct drm_nouveau_private *dev_priv = dev->dev_private;
1556 const int impl = dev->pci_device & 0x0ff0;
1558 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1559 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1566 nv_gf4_disp_arch(struct drm_device *dev)
1568 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1572 nv_two_reg_pll(struct drm_device *dev)
1574 struct drm_nouveau_private *dev_priv = dev->dev_private;
1575 const int impl = dev->pci_device & 0x0ff0;
1577 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1583 nv_match_device(struct drm_device *dev, unsigned device,
1584 unsigned sub_vendor, unsigned sub_device)
1586 return dev->pdev->device == device &&
1587 dev->pdev->subsystem_vendor == sub_vendor &&
1588 dev->pdev->subsystem_device == sub_device;
1591 static inline void *
1592 nv_engine(struct drm_device *dev, int engine)
1594 struct drm_nouveau_private *dev_priv = dev->dev_private;
1595 return (void *)dev_priv->eng[engine];
1598 /* returns 1 if device is one of the nv4x using the 0x4497 object class,
1599 * helpful to determine a number of other hardware features
1602 nv44_graph_class(struct drm_device *dev)
1604 struct drm_nouveau_private *dev_priv = dev->dev_private;
1606 if ((dev_priv->chipset & 0xf0) == 0x60)
1609 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1612 /* memory type/access flags, do not match hardware values */
1613 #define NV_MEM_ACCESS_RO 1
1614 #define NV_MEM_ACCESS_WO 2
1615 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1616 #define NV_MEM_ACCESS_SYS 4
1617 #define NV_MEM_ACCESS_VM 8
1618 #define NV_MEM_ACCESS_NOSNOOP 16
1620 #define NV_MEM_TARGET_VRAM 0
1621 #define NV_MEM_TARGET_PCI 1
1622 #define NV_MEM_TARGET_PCI_NOSNOOP 2
1623 #define NV_MEM_TARGET_VM 3
1624 #define NV_MEM_TARGET_GART 4
1626 #define NV_MEM_TYPE_VM 0x7f
1627 #define NV_MEM_COMP_VM 0x03
1630 #define NV01_SUBCHAN_OBJECT 0x00000000
1631 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
1632 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
1633 #define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
1634 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c
1635 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001
1636 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
1637 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
1638 #define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000
1639 #define NV84_SUBCHAN_NOTIFY_INTR 0x00000020
1640 #define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
1641 #define NV10_SUBCHAN_REF_CNT 0x00000050
1642 #define NVSW_SUBCHAN_PAGE_FLIP 0x00000054
1643 #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
1644 #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
1645 #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
1646 #define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
1647 #define NV40_SUBCHAN_YIELD 0x00000080
1649 /* NV_SW object class */
1650 #define NV_SW 0x0000506e
1651 #define NV_SW_DMA_VBLSEM 0x0000018c
1652 #define NV_SW_VBLSEM_OFFSET 0x00000400
1653 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1654 #define NV_SW_VBLSEM_RELEASE 0x00000408
1655 #define NV_SW_PAGE_FLIP 0x00000500
1657 #endif /* __NOUVEAU_DRV_H__ */