2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
59 #define MAX_NUM_DCB_ENTRIES 16
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68 struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
79 u32 busy_placements[3];
80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
89 struct nouveau_channel *channel;
96 struct nouveau_tile_reg *tile;
98 struct drm_gem_object *gem;
102 #define nouveau_bo_tile_layout(nvbo) \
103 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
105 static inline struct nouveau_bo *
106 nouveau_bo(struct ttm_buffer_object *bo)
108 return container_of(bo, struct nouveau_bo, bo);
111 static inline struct nouveau_bo *
112 nouveau_gem_object(struct drm_gem_object *gem)
114 return gem ? gem->driver_private : NULL;
117 /* TODO: submit equivalent to TTM generic API upstream? */
118 static inline void __iomem *
119 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
122 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
123 &nvbo->kmap, &is_iomem);
124 WARN_ON_ONCE(ioptr && !is_iomem);
129 NV_NFORCE = 0x10000000,
130 NV_NFORCE2 = 0x20000000
133 #define NVOBJ_ENGINE_SW 0
134 #define NVOBJ_ENGINE_GR 1
135 #define NVOBJ_ENGINE_PPP 2
136 #define NVOBJ_ENGINE_COPY 3
137 #define NVOBJ_ENGINE_VP 4
138 #define NVOBJ_ENGINE_CRYPT 5
139 #define NVOBJ_ENGINE_BSP 6
140 #define NVOBJ_ENGINE_DISPLAY 0xcafe0001
141 #define NVOBJ_ENGINE_INT 0xdeadbeef
143 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
144 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
145 struct nouveau_gpuobj {
146 struct drm_device *dev;
147 struct kref refcount;
148 struct list_head list;
150 struct drm_mm_node *im_pramin;
151 struct nouveau_bo *im_backing;
152 uint32_t *im_backing_suspend;
165 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
169 struct nouveau_channel {
170 struct drm_device *dev;
173 /* references to the channel data structure */
175 /* users of the hardware channel resources, the hardware
176 * context will be kicked off when it reaches zero. */
180 /* owner of this fifo */
181 struct drm_file *file_priv;
182 /* mapping of the fifo itself */
183 struct drm_local_map *map;
185 /* mapping of the regs controling the fifo */
192 /* lock protects the pending list only */
194 struct list_head pending;
196 uint32_t sequence_ack;
197 atomic_t last_sequence_irq;
200 /* DMA push buffer */
201 struct nouveau_gpuobj *pushbuf;
202 struct nouveau_bo *pushbuf_bo;
203 uint32_t pushbuf_base;
205 /* Notifier memory */
206 struct nouveau_bo *notifier_bo;
207 struct drm_mm notifier_heap;
210 struct nouveau_gpuobj *ramfc;
211 struct nouveau_gpuobj *cache;
214 /* XXX may be merge 2 pointers as private data ??? */
215 struct nouveau_gpuobj *ramin_grctx;
216 struct nouveau_gpuobj *crypt_ctx;
220 struct nouveau_gpuobj *vm_pd;
221 struct nouveau_gpuobj *vm_gart_pt;
222 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
225 struct nouveau_gpuobj *ramin; /* Private instmem */
226 struct drm_mm ramin_heap; /* Private PRAMIN heap */
227 struct nouveau_ramht *ramht; /* Hash table */
229 /* GPU object info for stuff used in-kernel (mm_enabled) */
231 uint32_t vram_handle;
232 uint32_t gart_handle;
235 /* Push buffer state (only for drm's channel on !mm_enabled) */
241 /* access via pushbuf_bo */
249 uint32_t sw_subchannel[8];
252 struct nouveau_gpuobj *vblsem;
253 uint32_t vblsem_offset;
254 uint32_t vblsem_rval;
255 struct list_head vbl_wait;
261 struct drm_info_list info;
265 struct nouveau_instmem_engine {
268 int (*init)(struct drm_device *dev);
269 void (*takedown)(struct drm_device *dev);
270 int (*suspend)(struct drm_device *dev);
271 void (*resume)(struct drm_device *dev);
273 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
274 u32 *size, u32 align);
275 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
276 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
277 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
278 void (*flush)(struct drm_device *);
281 struct nouveau_mc_engine {
282 int (*init)(struct drm_device *dev);
283 void (*takedown)(struct drm_device *dev);
286 struct nouveau_timer_engine {
287 int (*init)(struct drm_device *dev);
288 void (*takedown)(struct drm_device *dev);
289 uint64_t (*read)(struct drm_device *dev);
292 struct nouveau_fb_engine {
295 int (*init)(struct drm_device *dev);
296 void (*takedown)(struct drm_device *dev);
298 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
299 uint32_t size, uint32_t pitch);
302 struct nouveau_fifo_engine {
305 struct nouveau_gpuobj *playlist[2];
308 int (*init)(struct drm_device *);
309 void (*takedown)(struct drm_device *);
311 void (*disable)(struct drm_device *);
312 void (*enable)(struct drm_device *);
313 bool (*reassign)(struct drm_device *, bool enable);
314 bool (*cache_pull)(struct drm_device *dev, bool enable);
316 int (*channel_id)(struct drm_device *);
318 int (*create_context)(struct nouveau_channel *);
319 void (*destroy_context)(struct nouveau_channel *);
320 int (*load_context)(struct nouveau_channel *);
321 int (*unload_context)(struct drm_device *);
322 void (*tlb_flush)(struct drm_device *dev);
325 struct nouveau_pgraph_engine {
330 /* NV2x/NV3x context table (0x400780) */
331 struct nouveau_gpuobj *ctx_table;
333 int (*init)(struct drm_device *);
334 void (*takedown)(struct drm_device *);
336 void (*fifo_access)(struct drm_device *, bool);
338 struct nouveau_channel *(*channel)(struct drm_device *);
339 int (*create_context)(struct nouveau_channel *);
340 void (*destroy_context)(struct nouveau_channel *);
341 int (*load_context)(struct nouveau_channel *);
342 int (*unload_context)(struct drm_device *);
343 void (*tlb_flush)(struct drm_device *dev);
345 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
346 uint32_t size, uint32_t pitch);
349 struct nouveau_display_engine {
350 int (*early_init)(struct drm_device *);
351 void (*late_takedown)(struct drm_device *);
352 int (*create)(struct drm_device *);
353 int (*init)(struct drm_device *);
354 void (*destroy)(struct drm_device *);
357 struct nouveau_gpio_engine {
358 int (*init)(struct drm_device *);
359 void (*takedown)(struct drm_device *);
361 int (*get)(struct drm_device *, enum dcb_gpio_tag);
362 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
364 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
367 struct nouveau_pm_voltage_level {
372 struct nouveau_pm_voltage {
376 struct nouveau_pm_voltage_level *level;
380 #define NOUVEAU_PM_MAX_LEVEL 8
381 struct nouveau_pm_level {
382 struct device_attribute dev_attr;
397 struct nouveau_pm_temp_sensor_constants {
405 struct nouveau_pm_threshold_temp {
411 struct nouveau_pm_memtiming {
422 struct nouveau_pm_memtimings {
424 struct nouveau_pm_memtiming *timing;
428 struct nouveau_pm_engine {
429 struct nouveau_pm_voltage voltage;
430 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
432 struct nouveau_pm_memtimings memtimings;
433 struct nouveau_pm_temp_sensor_constants sensor_constants;
434 struct nouveau_pm_threshold_temp threshold_temp;
436 struct nouveau_pm_level boot;
437 struct nouveau_pm_level *cur;
439 struct device *hwmon;
440 struct notifier_block acpi_nb;
442 int (*clock_get)(struct drm_device *, u32 id);
443 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
445 void (*clock_set)(struct drm_device *, void *);
446 int (*voltage_get)(struct drm_device *);
447 int (*voltage_set)(struct drm_device *, int voltage);
448 int (*fanspeed_get)(struct drm_device *);
449 int (*fanspeed_set)(struct drm_device *, int fanspeed);
450 int (*temp_get)(struct drm_device *);
453 struct nouveau_crypt_engine {
456 int (*init)(struct drm_device *);
457 void (*takedown)(struct drm_device *);
458 int (*create_context)(struct nouveau_channel *);
459 void (*destroy_context)(struct nouveau_channel *);
460 void (*tlb_flush)(struct drm_device *dev);
463 struct nouveau_engine {
464 struct nouveau_instmem_engine instmem;
465 struct nouveau_mc_engine mc;
466 struct nouveau_timer_engine timer;
467 struct nouveau_fb_engine fb;
468 struct nouveau_pgraph_engine graph;
469 struct nouveau_fifo_engine fifo;
470 struct nouveau_display_engine display;
471 struct nouveau_gpio_engine gpio;
472 struct nouveau_pm_engine pm;
473 struct nouveau_crypt_engine crypt;
476 struct nouveau_pll_vals {
480 uint8_t N1, M1, N2, M2;
482 uint8_t M1, N1, M2, N2;
487 } __attribute__((packed));
494 enum nv04_fp_display_regs {
504 struct nv04_crtc_reg {
505 unsigned char MiscOutReg;
508 uint8_t Sequencer[5];
510 uint8_t Attribute[21];
511 unsigned char DAC[768];
521 uint32_t crtc_eng_ctrl;
524 uint32_t nv10_cursync;
525 struct nouveau_pll_vals pllvals;
526 uint32_t ramdac_gen_ctrl;
532 uint32_t tv_vsync_delay;
535 uint32_t tv_hsync_delay;
536 uint32_t tv_hsync_delay2;
537 uint32_t fp_horiz_regs[7];
538 uint32_t fp_vert_regs[7];
541 uint32_t dither_regs[6];
545 uint32_t fp_margin_color;
550 uint32_t ctv_regs[38];
553 struct nv04_output_reg {
558 struct nv04_mode_state {
559 struct nv04_crtc_reg crtc_reg[2];
564 enum nouveau_card_type {
574 struct drm_nouveau_private {
575 struct drm_device *dev;
577 /* the card type, takes NV_* as values */
578 enum nouveau_card_type card_type;
579 /* exact chipset, derived from NV_PMC_BOOT_0 */
585 spinlock_t ramin_lock;
589 bool ramin_available;
590 struct drm_mm ramin_heap;
591 struct list_head gpuobj_list;
592 struct list_head classes;
594 struct nouveau_bo *vga_ram;
596 /* interrupt handling */
598 struct workqueue_struct *wq;
599 struct work_struct irq_work;
600 struct work_struct hpd_work;
608 struct list_head vbl_waiting;
611 struct drm_global_reference mem_global_ref;
612 struct ttm_bo_global_ref bo_global_ref;
613 struct ttm_bo_device bdev;
614 atomic_t validate_sequence;
620 struct nouveau_bo *bo;
625 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
628 struct nouveau_engine engine;
629 struct nouveau_channel *channel;
631 /* For PFIFO and PGRAPH. */
632 spinlock_t context_switch_lock;
634 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
635 struct nouveau_ramht *ramht;
636 struct nouveau_gpuobj *ramfc;
637 struct nouveau_gpuobj *ramro;
639 uint32_t ramin_rsvd_vram;
643 NOUVEAU_GART_NONE = 0,
651 struct nouveau_gpuobj *sg_ctxdma;
652 struct page *sg_dummy_page;
653 dma_addr_t sg_dummy_bus;
656 /* nv10-nv40 tiling regions */
657 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR];
659 /* VRAM/fb configuration */
661 uint64_t vram_sys_base;
662 u32 vram_rblock_size;
665 uint64_t fb_available_size;
666 uint64_t fb_mappable_pages;
667 uint64_t fb_aper_free;
670 /* G8x/G9x virtual address space */
671 uint64_t vm_gart_base;
672 uint64_t vm_gart_size;
673 uint64_t vm_vram_base;
674 uint64_t vm_vram_size;
676 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
681 struct nv04_mode_state mode_reg;
682 struct nv04_mode_state saved_reg;
683 uint32_t saved_vga_font[4][16384];
685 uint32_t dac_users[4];
687 struct nouveau_suspend_resume {
688 uint32_t *ramin_copy;
691 struct backlight_device *backlight;
693 struct nouveau_channel *evo;
696 struct dcb_entry *dcb;
702 struct dentry *channel_root;
705 struct nouveau_fbdev *nfbdev;
706 struct apertures_struct *apertures;
709 static inline struct drm_nouveau_private *
710 nouveau_private(struct drm_device *dev)
712 return dev->dev_private;
715 static inline struct drm_nouveau_private *
716 nouveau_bdev(struct ttm_bo_device *bd)
718 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
722 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
724 struct nouveau_bo *prev;
730 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
732 struct ttm_buffer_object *bo = &prev->bo;
741 extern int nouveau_agpmode;
742 extern int nouveau_duallink;
743 extern int nouveau_uscript_lvds;
744 extern int nouveau_uscript_tmds;
745 extern int nouveau_vram_pushbuf;
746 extern int nouveau_vram_notify;
747 extern int nouveau_fbpercrtc;
748 extern int nouveau_tv_disable;
749 extern char *nouveau_tv_norm;
750 extern int nouveau_reg_debug;
751 extern char *nouveau_vbios;
752 extern int nouveau_ignorelid;
753 extern int nouveau_nofbaccel;
754 extern int nouveau_noaccel;
755 extern int nouveau_force_post;
756 extern int nouveau_override_conntype;
757 extern char *nouveau_perflvl;
758 extern int nouveau_perflvl_wr;
759 extern int nouveau_msi;
761 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
762 extern int nouveau_pci_resume(struct pci_dev *pdev);
764 /* nouveau_state.c */
765 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
766 extern int nouveau_load(struct drm_device *, unsigned long flags);
767 extern int nouveau_firstopen(struct drm_device *);
768 extern void nouveau_lastclose(struct drm_device *);
769 extern int nouveau_unload(struct drm_device *);
770 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
772 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
774 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
775 uint32_t reg, uint32_t mask, uint32_t val);
776 extern bool nouveau_wait_for_idle(struct drm_device *);
777 extern int nouveau_card_init(struct drm_device *);
780 extern int nouveau_mem_vram_init(struct drm_device *);
781 extern void nouveau_mem_vram_fini(struct drm_device *);
782 extern int nouveau_mem_gart_init(struct drm_device *);
783 extern void nouveau_mem_gart_fini(struct drm_device *);
784 extern int nouveau_mem_init_agp(struct drm_device *);
785 extern int nouveau_mem_reset_agp(struct drm_device *);
786 extern void nouveau_mem_close(struct drm_device *);
787 extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
791 extern void nv10_mem_expire_tiling(struct drm_device *dev,
792 struct nouveau_tile_reg *tile,
793 struct nouveau_fence *fence);
794 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
795 uint32_t size, uint32_t flags,
797 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
800 /* nouveau_notifier.c */
801 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
802 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
803 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
804 int cout, uint32_t *offset);
805 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
806 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
808 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
811 /* nouveau_channel.c */
812 extern struct drm_ioctl_desc nouveau_ioctls[];
813 extern int nouveau_max_ioctl;
814 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
815 extern int nouveau_channel_alloc(struct drm_device *dev,
816 struct nouveau_channel **chan,
817 struct drm_file *file_priv,
818 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
819 extern struct nouveau_channel *
820 nouveau_channel_get_unlocked(struct nouveau_channel *);
821 extern struct nouveau_channel *
822 nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
823 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
824 extern void nouveau_channel_put(struct nouveau_channel **);
825 extern void nouveau_channel_ref(struct nouveau_channel *chan,
826 struct nouveau_channel **pchan);
828 /* nouveau_object.c */
829 #define NVOBJ_CLASS(d,c,e) do { \
830 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
835 #define NVOBJ_MTHD(d,c,m,e) do { \
836 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
841 extern int nouveau_gpuobj_early_init(struct drm_device *);
842 extern int nouveau_gpuobj_init(struct drm_device *);
843 extern void nouveau_gpuobj_takedown(struct drm_device *);
844 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
845 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
846 extern void nouveau_gpuobj_resume(struct drm_device *dev);
847 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
848 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
849 int (*exec)(struct nouveau_channel *,
850 u32 class, u32 mthd, u32 data));
851 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
852 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
853 uint32_t vram_h, uint32_t tt_h);
854 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
855 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
856 uint32_t size, int align, uint32_t flags,
857 struct nouveau_gpuobj **);
858 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
859 struct nouveau_gpuobj **);
860 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
862 struct nouveau_gpuobj **);
863 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
864 uint64_t offset, uint64_t size, int access,
865 int target, struct nouveau_gpuobj **);
866 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
867 uint64_t offset, uint64_t size,
868 int access, struct nouveau_gpuobj **,
870 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
871 struct nouveau_gpuobj **);
872 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
874 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
878 extern int nouveau_irq_init(struct drm_device *);
879 extern void nouveau_irq_fini(struct drm_device *);
880 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
881 extern void nouveau_irq_preinstall(struct drm_device *);
882 extern int nouveau_irq_postinstall(struct drm_device *);
883 extern void nouveau_irq_uninstall(struct drm_device *);
885 /* nouveau_sgdma.c */
886 extern int nouveau_sgdma_init(struct drm_device *);
887 extern void nouveau_sgdma_takedown(struct drm_device *);
888 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
890 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
892 /* nouveau_debugfs.c */
893 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
894 extern int nouveau_debugfs_init(struct drm_minor *);
895 extern void nouveau_debugfs_takedown(struct drm_minor *);
896 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
897 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
900 nouveau_debugfs_init(struct drm_minor *minor)
905 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
910 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
916 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
922 extern void nouveau_dma_pre_init(struct nouveau_channel *);
923 extern int nouveau_dma_init(struct nouveau_channel *);
924 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
927 #define ROM_BIOS_PAGE 4096
928 #if defined(CONFIG_ACPI)
929 void nouveau_register_dsm_handler(void);
930 void nouveau_unregister_dsm_handler(void);
931 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
932 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
933 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
935 static inline void nouveau_register_dsm_handler(void) {}
936 static inline void nouveau_unregister_dsm_handler(void) {}
937 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
938 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
939 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
942 /* nouveau_backlight.c */
943 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
944 extern int nouveau_backlight_init(struct drm_device *);
945 extern void nouveau_backlight_exit(struct drm_device *);
947 static inline int nouveau_backlight_init(struct drm_device *dev)
952 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
956 extern int nouveau_bios_init(struct drm_device *);
957 extern void nouveau_bios_takedown(struct drm_device *dev);
958 extern int nouveau_run_vbios_init(struct drm_device *);
959 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
961 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
963 extern struct dcb_connector_table_entry *
964 nouveau_bios_connector_entry(struct drm_device *, int index);
965 extern u32 get_pll_register(struct drm_device *, enum pll_types);
966 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
968 extern int nouveau_bios_run_display_table(struct drm_device *,
970 uint32_t script, int pxclk);
971 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
973 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
974 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
975 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
976 bool *dl, bool *if_is_24bit);
977 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
978 int head, int pxclk);
979 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
980 enum LVDS_script, int pxclk);
983 int nouveau_ttm_global_init(struct drm_nouveau_private *);
984 void nouveau_ttm_global_release(struct drm_nouveau_private *);
985 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
988 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
989 uint8_t *data, int data_nr);
990 bool nouveau_dp_detect(struct drm_encoder *);
991 bool nouveau_dp_link_train(struct drm_encoder *);
994 extern int nv04_fb_init(struct drm_device *);
995 extern void nv04_fb_takedown(struct drm_device *);
998 extern int nv10_fb_init(struct drm_device *);
999 extern void nv10_fb_takedown(struct drm_device *);
1000 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
1001 uint32_t, uint32_t);
1004 extern int nv30_fb_init(struct drm_device *);
1005 extern void nv30_fb_takedown(struct drm_device *);
1008 extern int nv40_fb_init(struct drm_device *);
1009 extern void nv40_fb_takedown(struct drm_device *);
1010 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
1011 uint32_t, uint32_t);
1013 extern int nv50_fb_init(struct drm_device *);
1014 extern void nv50_fb_takedown(struct drm_device *);
1015 extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
1018 extern int nvc0_fb_init(struct drm_device *);
1019 extern void nvc0_fb_takedown(struct drm_device *);
1022 extern int nv04_fifo_init(struct drm_device *);
1023 extern void nv04_fifo_disable(struct drm_device *);
1024 extern void nv04_fifo_enable(struct drm_device *);
1025 extern bool nv04_fifo_reassign(struct drm_device *, bool);
1026 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1027 extern int nv04_fifo_channel_id(struct drm_device *);
1028 extern int nv04_fifo_create_context(struct nouveau_channel *);
1029 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1030 extern int nv04_fifo_load_context(struct nouveau_channel *);
1031 extern int nv04_fifo_unload_context(struct drm_device *);
1034 extern int nv10_fifo_init(struct drm_device *);
1035 extern int nv10_fifo_channel_id(struct drm_device *);
1036 extern int nv10_fifo_create_context(struct nouveau_channel *);
1037 extern int nv10_fifo_load_context(struct nouveau_channel *);
1038 extern int nv10_fifo_unload_context(struct drm_device *);
1041 extern int nv40_fifo_init(struct drm_device *);
1042 extern int nv40_fifo_create_context(struct nouveau_channel *);
1043 extern int nv40_fifo_load_context(struct nouveau_channel *);
1044 extern int nv40_fifo_unload_context(struct drm_device *);
1047 extern int nv50_fifo_init(struct drm_device *);
1048 extern void nv50_fifo_takedown(struct drm_device *);
1049 extern int nv50_fifo_channel_id(struct drm_device *);
1050 extern int nv50_fifo_create_context(struct nouveau_channel *);
1051 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1052 extern int nv50_fifo_load_context(struct nouveau_channel *);
1053 extern int nv50_fifo_unload_context(struct drm_device *);
1054 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1057 extern int nvc0_fifo_init(struct drm_device *);
1058 extern void nvc0_fifo_takedown(struct drm_device *);
1059 extern void nvc0_fifo_disable(struct drm_device *);
1060 extern void nvc0_fifo_enable(struct drm_device *);
1061 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1062 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1063 extern int nvc0_fifo_channel_id(struct drm_device *);
1064 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1065 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1066 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1067 extern int nvc0_fifo_unload_context(struct drm_device *);
1070 extern int nv04_graph_init(struct drm_device *);
1071 extern void nv04_graph_takedown(struct drm_device *);
1072 extern void nv04_graph_fifo_access(struct drm_device *, bool);
1073 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1074 extern int nv04_graph_create_context(struct nouveau_channel *);
1075 extern void nv04_graph_destroy_context(struct nouveau_channel *);
1076 extern int nv04_graph_load_context(struct nouveau_channel *);
1077 extern int nv04_graph_unload_context(struct drm_device *);
1078 extern void nv04_graph_context_switch(struct drm_device *);
1081 extern int nv10_graph_init(struct drm_device *);
1082 extern void nv10_graph_takedown(struct drm_device *);
1083 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1084 extern int nv10_graph_create_context(struct nouveau_channel *);
1085 extern void nv10_graph_destroy_context(struct nouveau_channel *);
1086 extern int nv10_graph_load_context(struct nouveau_channel *);
1087 extern int nv10_graph_unload_context(struct drm_device *);
1088 extern void nv10_graph_context_switch(struct drm_device *);
1089 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1090 uint32_t, uint32_t);
1093 extern int nv20_graph_create_context(struct nouveau_channel *);
1094 extern void nv20_graph_destroy_context(struct nouveau_channel *);
1095 extern int nv20_graph_load_context(struct nouveau_channel *);
1096 extern int nv20_graph_unload_context(struct drm_device *);
1097 extern int nv20_graph_init(struct drm_device *);
1098 extern void nv20_graph_takedown(struct drm_device *);
1099 extern int nv30_graph_init(struct drm_device *);
1100 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1101 uint32_t, uint32_t);
1104 extern int nv40_graph_init(struct drm_device *);
1105 extern void nv40_graph_takedown(struct drm_device *);
1106 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1107 extern int nv40_graph_create_context(struct nouveau_channel *);
1108 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1109 extern int nv40_graph_load_context(struct nouveau_channel *);
1110 extern int nv40_graph_unload_context(struct drm_device *);
1111 extern void nv40_grctx_init(struct nouveau_grctx *);
1112 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1113 uint32_t, uint32_t);
1116 extern int nv50_graph_init(struct drm_device *);
1117 extern void nv50_graph_takedown(struct drm_device *);
1118 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1119 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1120 extern int nv50_graph_create_context(struct nouveau_channel *);
1121 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1122 extern int nv50_graph_load_context(struct nouveau_channel *);
1123 extern int nv50_graph_unload_context(struct drm_device *);
1124 extern void nv50_graph_context_switch(struct drm_device *);
1125 extern int nv50_grctx_init(struct nouveau_grctx *);
1126 extern void nv50_graph_tlb_flush(struct drm_device *dev);
1127 extern void nv86_graph_tlb_flush(struct drm_device *dev);
1130 extern int nvc0_graph_init(struct drm_device *);
1131 extern void nvc0_graph_takedown(struct drm_device *);
1132 extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1133 extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1134 extern int nvc0_graph_create_context(struct nouveau_channel *);
1135 extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1136 extern int nvc0_graph_load_context(struct nouveau_channel *);
1137 extern int nvc0_graph_unload_context(struct drm_device *);
1140 extern int nv84_crypt_init(struct drm_device *dev);
1141 extern void nv84_crypt_fini(struct drm_device *dev);
1142 extern int nv84_crypt_create_context(struct nouveau_channel *);
1143 extern void nv84_crypt_destroy_context(struct nouveau_channel *);
1144 extern void nv84_crypt_tlb_flush(struct drm_device *dev);
1146 /* nv04_instmem.c */
1147 extern int nv04_instmem_init(struct drm_device *);
1148 extern void nv04_instmem_takedown(struct drm_device *);
1149 extern int nv04_instmem_suspend(struct drm_device *);
1150 extern void nv04_instmem_resume(struct drm_device *);
1151 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1152 u32 *size, u32 align);
1153 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1154 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1155 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1156 extern void nv04_instmem_flush(struct drm_device *);
1158 /* nv50_instmem.c */
1159 extern int nv50_instmem_init(struct drm_device *);
1160 extern void nv50_instmem_takedown(struct drm_device *);
1161 extern int nv50_instmem_suspend(struct drm_device *);
1162 extern void nv50_instmem_resume(struct drm_device *);
1163 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1164 u32 *size, u32 align);
1165 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1166 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1167 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1168 extern void nv50_instmem_flush(struct drm_device *);
1169 extern void nv84_instmem_flush(struct drm_device *);
1170 extern void nv50_vm_flush(struct drm_device *, int engine);
1172 /* nvc0_instmem.c */
1173 extern int nvc0_instmem_init(struct drm_device *);
1174 extern void nvc0_instmem_takedown(struct drm_device *);
1175 extern int nvc0_instmem_suspend(struct drm_device *);
1176 extern void nvc0_instmem_resume(struct drm_device *);
1177 extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1178 u32 *size, u32 align);
1179 extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1180 extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1181 extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1182 extern void nvc0_instmem_flush(struct drm_device *);
1185 extern int nv04_mc_init(struct drm_device *);
1186 extern void nv04_mc_takedown(struct drm_device *);
1189 extern int nv40_mc_init(struct drm_device *);
1190 extern void nv40_mc_takedown(struct drm_device *);
1193 extern int nv50_mc_init(struct drm_device *);
1194 extern void nv50_mc_takedown(struct drm_device *);
1197 extern int nv04_timer_init(struct drm_device *);
1198 extern uint64_t nv04_timer_read(struct drm_device *);
1199 extern void nv04_timer_takedown(struct drm_device *);
1201 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1205 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1206 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1207 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1208 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1209 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1212 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1213 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1214 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1216 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1217 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1220 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1221 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1224 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1226 /* nv04_display.c */
1227 extern int nv04_display_early_init(struct drm_device *);
1228 extern void nv04_display_late_takedown(struct drm_device *);
1229 extern int nv04_display_create(struct drm_device *);
1230 extern int nv04_display_init(struct drm_device *);
1231 extern void nv04_display_destroy(struct drm_device *);
1234 extern int nv04_crtc_create(struct drm_device *, int index);
1237 extern struct ttm_bo_driver nouveau_bo_driver;
1238 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1239 int size, int align, uint32_t flags,
1240 uint32_t tile_mode, uint32_t tile_flags,
1241 bool no_vm, bool mappable, struct nouveau_bo **);
1242 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1243 extern int nouveau_bo_unpin(struct nouveau_bo *);
1244 extern int nouveau_bo_map(struct nouveau_bo *);
1245 extern void nouveau_bo_unmap(struct nouveau_bo *);
1246 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1248 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1249 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1250 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1251 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1253 /* nouveau_fence.c */
1254 struct nouveau_fence;
1255 extern int nouveau_fence_init(struct drm_device *);
1256 extern void nouveau_fence_fini(struct drm_device *);
1257 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1258 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1259 extern void nouveau_fence_update(struct nouveau_channel *);
1260 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1262 extern int nouveau_fence_emit(struct nouveau_fence *);
1263 extern void nouveau_fence_work(struct nouveau_fence *fence,
1264 void (*work)(void *priv, bool signalled),
1266 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1268 extern bool __nouveau_fence_signalled(void *obj, void *arg);
1269 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1270 extern int __nouveau_fence_flush(void *obj, void *arg);
1271 extern void __nouveau_fence_unref(void **obj);
1272 extern void *__nouveau_fence_ref(void *obj);
1274 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1276 return __nouveau_fence_signalled(obj, NULL);
1279 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1281 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1283 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1284 static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1286 return __nouveau_fence_flush(obj, NULL);
1288 static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1290 __nouveau_fence_unref((void **)obj);
1292 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1294 return __nouveau_fence_ref(obj);
1298 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1299 int size, int align, uint32_t flags,
1300 uint32_t tile_mode, uint32_t tile_flags,
1301 bool no_vm, bool mappable, struct nouveau_bo **);
1302 extern int nouveau_gem_object_new(struct drm_gem_object *);
1303 extern void nouveau_gem_object_del(struct drm_gem_object *);
1304 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1306 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1308 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1310 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1312 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1315 /* nouveau_display.c */
1316 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1317 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1320 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1321 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1324 int nv50_gpio_init(struct drm_device *dev);
1325 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1326 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1327 void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1330 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1331 int *N1, int *M1, int *N2, int *M2, int *P);
1332 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1333 int clk, int *N, int *fN, int *M, int *P);
1335 #ifndef ioread32_native
1337 #define ioread16_native ioread16be
1338 #define iowrite16_native iowrite16be
1339 #define ioread32_native ioread32be
1340 #define iowrite32_native iowrite32be
1341 #else /* def __BIG_ENDIAN */
1342 #define ioread16_native ioread16
1343 #define iowrite16_native iowrite16
1344 #define ioread32_native ioread32
1345 #define iowrite32_native iowrite32
1346 #endif /* def __BIG_ENDIAN else */
1347 #endif /* !ioread32_native */
1349 /* channel control reg access */
1350 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1352 return ioread32_native(chan->user + reg);
1355 static inline void nvchan_wr32(struct nouveau_channel *chan,
1356 unsigned reg, u32 val)
1358 iowrite32_native(val, chan->user + reg);
1361 /* register access */
1362 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1364 struct drm_nouveau_private *dev_priv = dev->dev_private;
1365 return ioread32_native(dev_priv->mmio + reg);
1368 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1370 struct drm_nouveau_private *dev_priv = dev->dev_private;
1371 iowrite32_native(val, dev_priv->mmio + reg);
1374 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1376 u32 tmp = nv_rd32(dev, reg);
1377 nv_wr32(dev, reg, (tmp & ~mask) | val);
1381 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1383 struct drm_nouveau_private *dev_priv = dev->dev_private;
1384 return ioread8(dev_priv->mmio + reg);
1387 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1389 struct drm_nouveau_private *dev_priv = dev->dev_private;
1390 iowrite8(val, dev_priv->mmio + reg);
1393 #define nv_wait(dev, reg, mask, val) \
1394 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1397 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1399 struct drm_nouveau_private *dev_priv = dev->dev_private;
1400 return ioread32_native(dev_priv->ramin + offset);
1403 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1405 struct drm_nouveau_private *dev_priv = dev->dev_private;
1406 iowrite32_native(val, dev_priv->ramin + offset);
1410 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1411 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1415 * Argument d is (struct drm_device *).
1417 #define NV_PRINTK(level, d, fmt, arg...) \
1418 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1419 pci_name(d->pdev), ##arg)
1420 #ifndef NV_DEBUG_NOTRACE
1421 #define NV_DEBUG(d, fmt, arg...) do { \
1422 if (drm_debug & DRM_UT_DRIVER) { \
1423 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1427 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1428 if (drm_debug & DRM_UT_KMS) { \
1429 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1434 #define NV_DEBUG(d, fmt, arg...) do { \
1435 if (drm_debug & DRM_UT_DRIVER) \
1436 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1438 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1439 if (drm_debug & DRM_UT_KMS) \
1440 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1443 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1444 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1445 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1446 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1447 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1449 /* nouveau_reg_debug bitmask */
1451 NOUVEAU_REG_DEBUG_MC = 0x1,
1452 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1453 NOUVEAU_REG_DEBUG_FB = 0x4,
1454 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1455 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1456 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1457 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1458 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1459 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1460 NOUVEAU_REG_DEBUG_EVO = 0x200,
1463 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1464 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1465 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1469 nv_two_heads(struct drm_device *dev)
1471 struct drm_nouveau_private *dev_priv = dev->dev_private;
1472 const int impl = dev->pci_device & 0x0ff0;
1474 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1475 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1482 nv_gf4_disp_arch(struct drm_device *dev)
1484 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1488 nv_two_reg_pll(struct drm_device *dev)
1490 struct drm_nouveau_private *dev_priv = dev->dev_private;
1491 const int impl = dev->pci_device & 0x0ff0;
1493 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1499 nv_match_device(struct drm_device *dev, unsigned device,
1500 unsigned sub_vendor, unsigned sub_device)
1502 return dev->pdev->device == device &&
1503 dev->pdev->subsystem_vendor == sub_vendor &&
1504 dev->pdev->subsystem_device == sub_device;
1507 #define NV_SW 0x0000506e
1508 #define NV_SW_DMA_SEMAPHORE 0x00000060
1509 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1510 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1511 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1512 #define NV_SW_YIELD 0x00000080
1513 #define NV_SW_DMA_VBLSEM 0x0000018c
1514 #define NV_SW_VBLSEM_OFFSET 0x00000400
1515 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1516 #define NV_SW_VBLSEM_RELEASE 0x00000408
1518 #endif /* __NOUVEAU_DRV_H__ */