2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
50 struct list_head channels;
51 struct nouveau_vm *vm;
54 static inline struct nouveau_fpriv *
55 nouveau_fpriv(struct drm_file *file_priv)
57 return file_priv ? file_priv->driver_priv : NULL;
60 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
62 #include "nouveau_drm.h"
63 #include "nouveau_reg.h"
64 #include "nouveau_bios.h"
65 #include "nouveau_util.h"
69 #include "nouveau_vm.h"
71 #define MAX_NUM_DCB_ENTRIES 16
73 #define NOUVEAU_MAX_CHANNEL_NR 128
74 #define NOUVEAU_MAX_TILE_NR 15
77 struct drm_device *dev;
79 struct nouveau_vma bar_vma;
80 struct nouveau_vma vma[2];
83 struct drm_mm_node *tag;
84 struct list_head regions;
91 struct nouveau_tile_reg {
97 struct drm_mm_node *tag_mem;
98 struct nouveau_fence *fence;
102 struct ttm_buffer_object bo;
103 struct ttm_placement placement;
106 u32 busy_placements[3];
107 struct ttm_bo_kmap_obj kmap;
108 struct list_head head;
110 /* protected by ttm_bo_reserve() */
111 struct drm_file *reserved_by;
112 struct list_head entry;
114 bool validate_mapped;
116 struct nouveau_channel *channel;
118 struct list_head vma_list;
123 struct nouveau_tile_reg *tile;
125 struct drm_gem_object *gem;
129 #define nouveau_bo_tile_layout(nvbo) \
130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
132 static inline struct nouveau_bo *
133 nouveau_bo(struct ttm_buffer_object *bo)
135 return container_of(bo, struct nouveau_bo, bo);
138 static inline struct nouveau_bo *
139 nouveau_gem_object(struct drm_gem_object *gem)
141 return gem ? gem->driver_private : NULL;
144 /* TODO: submit equivalent to TTM generic API upstream? */
145 static inline void __iomem *
146 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
150 &nvbo->kmap, &is_iomem);
151 WARN_ON_ONCE(ioptr && !is_iomem);
156 NV_NFORCE = 0x10000000,
157 NV_NFORCE2 = 0x20000000
160 #define NVOBJ_ENGINE_SW 0
161 #define NVOBJ_ENGINE_GR 1
162 #define NVOBJ_ENGINE_CRYPT 2
163 #define NVOBJ_ENGINE_COPY0 3
164 #define NVOBJ_ENGINE_COPY1 4
165 #define NVOBJ_ENGINE_MPEG 5
166 #define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG
167 #define NVOBJ_ENGINE_BSP 6
168 #define NVOBJ_ENGINE_VP 7
169 #define NVOBJ_ENGINE_DISPLAY 15
170 #define NVOBJ_ENGINE_NR 16
172 #define NVOBJ_FLAG_DONT_MAP (1 << 0)
173 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
174 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
175 #define NVOBJ_FLAG_VM (1 << 3)
176 #define NVOBJ_FLAG_VM_USER (1 << 4)
178 #define NVOBJ_CINST_GLOBAL 0xdeadbeef
180 struct nouveau_gpuobj {
181 struct drm_device *dev;
182 struct kref refcount;
183 struct list_head list;
191 u32 pinst; /* PRAMIN BAR offset */
192 u32 cinst; /* Channel offset */
193 u64 vinst; /* VRAM address */
194 u64 linst; /* VM address */
199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
203 struct nouveau_page_flip_state {
204 struct list_head head;
205 struct drm_pending_vblank_event *event;
206 int crtc, bpp, pitch, x, y;
210 enum nouveau_channel_mutex_class {
211 NOUVEAU_UCHANNEL_MUTEX,
212 NOUVEAU_KCHANNEL_MUTEX
215 struct nouveau_channel {
216 struct drm_device *dev;
217 struct list_head list;
220 /* references to the channel data structure */
222 /* users of the hardware channel resources, the hardware
223 * context will be kicked off when it reaches zero. */
227 /* owner of this fifo */
228 struct drm_file *file_priv;
229 /* mapping of the fifo itself */
230 struct drm_local_map *map;
232 /* mapping of the regs controlling the fifo */
239 /* lock protects the pending list only */
241 struct list_head pending;
243 uint32_t sequence_ack;
244 atomic_t last_sequence_irq;
245 struct nouveau_vma vma;
248 /* DMA push buffer */
249 struct nouveau_gpuobj *pushbuf;
250 struct nouveau_bo *pushbuf_bo;
251 struct nouveau_vma pushbuf_vma;
252 uint32_t pushbuf_base;
254 /* Notifier memory */
255 struct nouveau_bo *notifier_bo;
256 struct nouveau_vma notifier_vma;
257 struct drm_mm notifier_heap;
260 struct nouveau_gpuobj *ramfc;
261 struct nouveau_gpuobj *cache;
264 /* Execution engine contexts */
265 void *engctx[NVOBJ_ENGINE_NR];
268 struct nouveau_vm *vm;
269 struct nouveau_gpuobj *vm_pd;
272 struct nouveau_gpuobj *ramin; /* Private instmem */
273 struct drm_mm ramin_heap; /* Private PRAMIN heap */
274 struct nouveau_ramht *ramht; /* Hash table */
276 /* GPU object info for stuff used in-kernel (mm_enabled) */
278 uint32_t vram_handle;
279 uint32_t gart_handle;
282 /* Push buffer state (only for drm's channel on !mm_enabled) */
288 /* access via pushbuf_bo */
296 uint32_t sw_subchannel[8];
298 struct nouveau_vma dispc_vma[2];
300 struct nouveau_gpuobj *vblsem;
301 uint32_t vblsem_head;
302 uint32_t vblsem_offset;
303 uint32_t vblsem_rval;
304 struct list_head vbl_wait;
305 struct list_head flip;
311 struct drm_info_list info;
315 struct nouveau_exec_engine {
316 void (*destroy)(struct drm_device *, int engine);
317 int (*init)(struct drm_device *, int engine);
318 int (*fini)(struct drm_device *, int engine, bool suspend);
319 int (*context_new)(struct nouveau_channel *, int engine);
320 void (*context_del)(struct nouveau_channel *, int engine);
321 int (*object_new)(struct nouveau_channel *, int engine,
322 u32 handle, u16 class);
323 void (*set_tile_region)(struct drm_device *dev, int i);
324 void (*tlb_flush)(struct drm_device *, int engine);
327 struct nouveau_instmem_engine {
330 int (*init)(struct drm_device *dev);
331 void (*takedown)(struct drm_device *dev);
332 int (*suspend)(struct drm_device *dev);
333 void (*resume)(struct drm_device *dev);
335 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *,
336 u32 size, u32 align);
337 void (*put)(struct nouveau_gpuobj *);
338 int (*map)(struct nouveau_gpuobj *);
339 void (*unmap)(struct nouveau_gpuobj *);
341 void (*flush)(struct drm_device *);
344 struct nouveau_mc_engine {
345 int (*init)(struct drm_device *dev);
346 void (*takedown)(struct drm_device *dev);
349 struct nouveau_timer_engine {
350 int (*init)(struct drm_device *dev);
351 void (*takedown)(struct drm_device *dev);
352 uint64_t (*read)(struct drm_device *dev);
355 struct nouveau_fb_engine {
357 struct drm_mm tag_heap;
360 int (*init)(struct drm_device *dev);
361 void (*takedown)(struct drm_device *dev);
363 void (*init_tile_region)(struct drm_device *dev, int i,
364 uint32_t addr, uint32_t size,
365 uint32_t pitch, uint32_t flags);
366 void (*set_tile_region)(struct drm_device *dev, int i);
367 void (*free_tile_region)(struct drm_device *dev, int i);
370 struct nouveau_fifo_engine {
374 struct nouveau_gpuobj *playlist[2];
377 int (*init)(struct drm_device *);
378 void (*takedown)(struct drm_device *);
380 void (*disable)(struct drm_device *);
381 void (*enable)(struct drm_device *);
382 bool (*reassign)(struct drm_device *, bool enable);
383 bool (*cache_pull)(struct drm_device *dev, bool enable);
385 int (*channel_id)(struct drm_device *);
387 int (*create_context)(struct nouveau_channel *);
388 void (*destroy_context)(struct nouveau_channel *);
389 int (*load_context)(struct nouveau_channel *);
390 int (*unload_context)(struct drm_device *);
391 void (*tlb_flush)(struct drm_device *dev);
394 struct nouveau_display_engine {
396 int (*early_init)(struct drm_device *);
397 void (*late_takedown)(struct drm_device *);
398 int (*create)(struct drm_device *);
399 void (*destroy)(struct drm_device *);
400 int (*init)(struct drm_device *);
401 void (*fini)(struct drm_device *);
403 struct drm_property *dithering_mode;
404 struct drm_property *dithering_depth;
405 struct drm_property *underscan_property;
406 struct drm_property *underscan_hborder_property;
407 struct drm_property *underscan_vborder_property;
410 struct nouveau_gpio_engine {
413 int (*init)(struct drm_device *);
414 void (*takedown)(struct drm_device *);
416 int (*get)(struct drm_device *, enum dcb_gpio_tag);
417 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
419 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag,
420 void (*)(void *, int), void *);
421 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag,
422 void (*)(void *, int), void *);
423 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
426 struct nouveau_pm_voltage_level {
427 u32 voltage; /* microvolts */
431 struct nouveau_pm_voltage {
436 struct nouveau_pm_voltage_level *level;
440 struct nouveau_pm_memtiming {
442 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */
451 /* To be written to 0x1002c0 */
456 struct nouveau_pm_tbl_header{
463 struct nouveau_pm_tbl_entry{
469 u8 tRAS; /* Byte 5 */
471 u8 tRFC; /* Byte 7 */
474 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
475 u8 empty_15,empty_16,empty_17;
476 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
480 void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
481 struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
482 struct nouveau_pm_memtiming *timing);
484 #define NOUVEAU_PM_MAX_LEVEL 8
485 struct nouveau_pm_level {
486 struct device_attribute dev_attr;
498 u32 unka0; /* nva3:nvc0 */
499 u32 hub01; /* nvc0- */
500 u32 hub06; /* nvc0- */
501 u32 hub07; /* nvc0- */
503 u32 volt_min; /* microvolts */
508 struct nouveau_pm_memtiming *timing;
511 struct nouveau_pm_temp_sensor_constants {
519 struct nouveau_pm_threshold_temp {
525 struct nouveau_pm_memtimings {
527 struct nouveau_pm_memtiming *timing;
531 struct nouveau_pm_fan {
537 struct nouveau_pm_engine {
538 struct nouveau_pm_voltage voltage;
539 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
541 struct nouveau_pm_memtimings memtimings;
542 struct nouveau_pm_temp_sensor_constants sensor_constants;
543 struct nouveau_pm_threshold_temp threshold_temp;
544 struct nouveau_pm_fan fan;
547 struct nouveau_pm_level boot;
548 struct nouveau_pm_level *cur;
550 struct device *hwmon;
551 struct notifier_block acpi_nb;
553 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
554 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
555 int (*clocks_set)(struct drm_device *, void *);
557 int (*voltage_get)(struct drm_device *);
558 int (*voltage_set)(struct drm_device *, int voltage);
559 int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
560 int (*pwm_set)(struct drm_device *, int line, u32, u32);
561 int (*temp_get)(struct drm_device *);
564 struct nouveau_vram_engine {
565 struct nouveau_mm mm;
567 int (*init)(struct drm_device *);
568 void (*takedown)(struct drm_device *dev);
569 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
570 u32 type, struct nouveau_mem **);
571 void (*put)(struct drm_device *, struct nouveau_mem **);
573 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
576 struct nouveau_engine {
577 struct nouveau_instmem_engine instmem;
578 struct nouveau_mc_engine mc;
579 struct nouveau_timer_engine timer;
580 struct nouveau_fb_engine fb;
581 struct nouveau_fifo_engine fifo;
582 struct nouveau_display_engine display;
583 struct nouveau_gpio_engine gpio;
584 struct nouveau_pm_engine pm;
585 struct nouveau_vram_engine vram;
588 struct nouveau_pll_vals {
592 uint8_t N1, M1, N2, M2;
594 uint8_t M1, N1, M2, N2;
599 } __attribute__((packed));
606 enum nv04_fp_display_regs {
616 struct nv04_crtc_reg {
617 unsigned char MiscOutReg;
620 uint8_t Sequencer[5];
622 uint8_t Attribute[21];
623 unsigned char DAC[768];
633 uint32_t crtc_eng_ctrl;
636 uint32_t nv10_cursync;
637 struct nouveau_pll_vals pllvals;
638 uint32_t ramdac_gen_ctrl;
644 uint32_t tv_vsync_delay;
647 uint32_t tv_hsync_delay;
648 uint32_t tv_hsync_delay2;
649 uint32_t fp_horiz_regs[7];
650 uint32_t fp_vert_regs[7];
653 uint32_t dither_regs[6];
657 uint32_t fp_margin_color;
662 uint32_t ctv_regs[38];
665 struct nv04_output_reg {
670 struct nv04_mode_state {
671 struct nv04_crtc_reg crtc_reg[2];
676 enum nouveau_card_type {
687 struct drm_nouveau_private {
688 struct drm_device *dev;
691 /* the card type, takes NV_* as values */
692 enum nouveau_card_type card_type;
693 /* exact chipset, derived from NV_PMC_BOOT_0 */
700 spinlock_t ramin_lock;
704 bool ramin_available;
705 struct drm_mm ramin_heap;
706 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR];
707 struct list_head gpuobj_list;
708 struct list_head classes;
710 struct nouveau_bo *vga_ram;
712 /* interrupt handling */
713 void (*irq_handler[32])(struct drm_device *);
716 struct list_head vbl_waiting;
719 struct drm_global_reference mem_global_ref;
720 struct ttm_bo_global_ref bo_global_ref;
721 struct ttm_bo_device bdev;
722 atomic_t validate_sequence;
728 struct nouveau_bo *bo;
733 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
736 struct nouveau_engine engine;
737 struct nouveau_channel *channel;
739 /* For PFIFO and PGRAPH. */
740 spinlock_t context_switch_lock;
742 /* VM/PRAMIN flush, legacy PRAMIN aperture */
745 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
746 struct nouveau_ramht *ramht;
747 struct nouveau_gpuobj *ramfc;
748 struct nouveau_gpuobj *ramro;
750 uint32_t ramin_rsvd_vram;
754 NOUVEAU_GART_NONE = 0,
755 NOUVEAU_GART_AGP, /* AGP */
756 NOUVEAU_GART_PDMA, /* paged dma object */
757 NOUVEAU_GART_HW /* on-chip gart/vm */
763 struct ttm_backend_func *func;
770 struct nouveau_gpuobj *sg_ctxdma;
773 /* nv10-nv40 tiling regions */
775 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
779 /* VRAM/fb configuration */
781 uint64_t vram_sys_base;
783 uint64_t fb_available_size;
784 uint64_t fb_mappable_pages;
785 uint64_t fb_aper_free;
788 /* BAR control (NV50-) */
789 struct nouveau_vm *bar1_vm;
790 struct nouveau_vm *bar3_vm;
792 /* G8x/G9x virtual address space */
793 struct nouveau_vm *chan_vm;
797 struct list_head i2c_ports;
799 struct nv04_mode_state mode_reg;
800 struct nv04_mode_state saved_reg;
801 uint32_t saved_vga_font[4][16384];
803 uint32_t dac_users[4];
805 struct backlight_device *backlight;
808 struct dentry *channel_root;
811 struct nouveau_fbdev *nfbdev;
812 struct apertures_struct *apertures;
815 static inline struct drm_nouveau_private *
816 nouveau_private(struct drm_device *dev)
818 return dev->dev_private;
821 static inline struct drm_nouveau_private *
822 nouveau_bdev(struct ttm_bo_device *bd)
824 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
828 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
830 struct nouveau_bo *prev;
836 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
838 struct ttm_buffer_object *bo = &prev->bo;
847 extern int nouveau_modeset;
848 extern int nouveau_agpmode;
849 extern int nouveau_duallink;
850 extern int nouveau_uscript_lvds;
851 extern int nouveau_uscript_tmds;
852 extern int nouveau_vram_pushbuf;
853 extern int nouveau_vram_notify;
854 extern int nouveau_fbpercrtc;
855 extern int nouveau_tv_disable;
856 extern char *nouveau_tv_norm;
857 extern int nouveau_reg_debug;
858 extern char *nouveau_vbios;
859 extern int nouveau_ignorelid;
860 extern int nouveau_nofbaccel;
861 extern int nouveau_noaccel;
862 extern int nouveau_force_post;
863 extern int nouveau_override_conntype;
864 extern char *nouveau_perflvl;
865 extern int nouveau_perflvl_wr;
866 extern int nouveau_msi;
867 extern int nouveau_ctxfw;
868 extern int nouveau_mxmdcb;
870 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
871 extern int nouveau_pci_resume(struct pci_dev *pdev);
873 /* nouveau_state.c */
874 extern int nouveau_open(struct drm_device *, struct drm_file *);
875 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
876 extern void nouveau_postclose(struct drm_device *, struct drm_file *);
877 extern int nouveau_load(struct drm_device *, unsigned long flags);
878 extern int nouveau_firstopen(struct drm_device *);
879 extern void nouveau_lastclose(struct drm_device *);
880 extern int nouveau_unload(struct drm_device *);
881 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
883 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
885 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
886 uint32_t reg, uint32_t mask, uint32_t val);
887 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
888 uint32_t reg, uint32_t mask, uint32_t val);
889 extern bool nouveau_wait_cb(struct drm_device *, u64 timeout,
890 bool (*cond)(void *), void *);
891 extern bool nouveau_wait_for_idle(struct drm_device *);
892 extern int nouveau_card_init(struct drm_device *);
895 extern int nouveau_mem_vram_init(struct drm_device *);
896 extern void nouveau_mem_vram_fini(struct drm_device *);
897 extern int nouveau_mem_gart_init(struct drm_device *);
898 extern void nouveau_mem_gart_fini(struct drm_device *);
899 extern int nouveau_mem_init_agp(struct drm_device *);
900 extern int nouveau_mem_reset_agp(struct drm_device *);
901 extern void nouveau_mem_close(struct drm_device *);
902 extern int nouveau_mem_detect(struct drm_device *);
903 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
904 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
905 struct drm_device *dev, uint32_t addr, uint32_t size,
906 uint32_t pitch, uint32_t flags);
907 extern void nv10_mem_put_tile_region(struct drm_device *dev,
908 struct nouveau_tile_reg *tile,
909 struct nouveau_fence *fence);
910 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
911 extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
913 /* nouveau_notifier.c */
914 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
915 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
916 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
917 int cout, uint32_t start, uint32_t end,
919 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
920 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
922 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
925 /* nouveau_channel.c */
926 extern struct drm_ioctl_desc nouveau_ioctls[];
927 extern int nouveau_max_ioctl;
928 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
929 extern int nouveau_channel_alloc(struct drm_device *dev,
930 struct nouveau_channel **chan,
931 struct drm_file *file_priv,
932 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
933 extern struct nouveau_channel *
934 nouveau_channel_get_unlocked(struct nouveau_channel *);
935 extern struct nouveau_channel *
936 nouveau_channel_get(struct drm_file *, int id);
937 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
938 extern void nouveau_channel_put(struct nouveau_channel **);
939 extern void nouveau_channel_ref(struct nouveau_channel *chan,
940 struct nouveau_channel **pchan);
941 extern void nouveau_channel_idle(struct nouveau_channel *chan);
943 /* nouveau_object.c */
944 #define NVOBJ_ENGINE_ADD(d, e, p) do { \
945 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
946 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
949 #define NVOBJ_ENGINE_DEL(d, e) do { \
950 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
951 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \
954 #define NVOBJ_CLASS(d, c, e) do { \
955 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
960 #define NVOBJ_MTHD(d, c, m, e) do { \
961 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
966 extern int nouveau_gpuobj_early_init(struct drm_device *);
967 extern int nouveau_gpuobj_init(struct drm_device *);
968 extern void nouveau_gpuobj_takedown(struct drm_device *);
969 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
970 extern void nouveau_gpuobj_resume(struct drm_device *dev);
971 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
972 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
973 int (*exec)(struct nouveau_channel *,
974 u32 class, u32 mthd, u32 data));
975 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
976 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
977 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
978 uint32_t vram_h, uint32_t tt_h);
979 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
980 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
981 uint32_t size, int align, uint32_t flags,
982 struct nouveau_gpuobj **);
983 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
984 struct nouveau_gpuobj **);
985 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
987 struct nouveau_gpuobj **);
988 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
989 uint64_t offset, uint64_t size, int access,
990 int target, struct nouveau_gpuobj **);
991 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
992 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
993 u64 size, int target, int access, u32 type,
994 u32 comp, struct nouveau_gpuobj **pobj);
995 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
996 int class, u64 base, u64 size, int target,
997 int access, u32 type, u32 comp);
998 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
1000 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
1004 extern int nouveau_irq_init(struct drm_device *);
1005 extern void nouveau_irq_fini(struct drm_device *);
1006 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
1007 extern void nouveau_irq_register(struct drm_device *, int status_bit,
1008 void (*)(struct drm_device *));
1009 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
1010 extern void nouveau_irq_preinstall(struct drm_device *);
1011 extern int nouveau_irq_postinstall(struct drm_device *);
1012 extern void nouveau_irq_uninstall(struct drm_device *);
1014 /* nouveau_sgdma.c */
1015 extern int nouveau_sgdma_init(struct drm_device *);
1016 extern void nouveau_sgdma_takedown(struct drm_device *);
1017 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
1019 extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev,
1021 uint32_t page_flags,
1022 struct page *dummy_read_page);
1024 /* nouveau_debugfs.c */
1025 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
1026 extern int nouveau_debugfs_init(struct drm_minor *);
1027 extern void nouveau_debugfs_takedown(struct drm_minor *);
1028 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
1029 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
1032 nouveau_debugfs_init(struct drm_minor *minor)
1037 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
1042 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
1048 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
1054 extern void nouveau_dma_pre_init(struct nouveau_channel *);
1055 extern int nouveau_dma_init(struct nouveau_channel *);
1056 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
1058 /* nouveau_acpi.c */
1059 #define ROM_BIOS_PAGE 4096
1060 #if defined(CONFIG_ACPI)
1061 void nouveau_register_dsm_handler(void);
1062 void nouveau_unregister_dsm_handler(void);
1063 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
1064 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
1065 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
1067 static inline void nouveau_register_dsm_handler(void) {}
1068 static inline void nouveau_unregister_dsm_handler(void) {}
1069 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
1070 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
1071 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
1074 /* nouveau_backlight.c */
1075 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1076 extern int nouveau_backlight_init(struct drm_device *);
1077 extern void nouveau_backlight_exit(struct drm_device *);
1079 static inline int nouveau_backlight_init(struct drm_device *dev)
1084 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
1087 /* nouveau_bios.c */
1088 extern int nouveau_bios_init(struct drm_device *);
1089 extern void nouveau_bios_takedown(struct drm_device *dev);
1090 extern int nouveau_run_vbios_init(struct drm_device *);
1091 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1092 struct dcb_entry *, int crtc);
1093 extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table);
1094 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
1096 extern struct dcb_connector_table_entry *
1097 nouveau_bios_connector_entry(struct drm_device *, int index);
1098 extern u32 get_pll_register(struct drm_device *, enum pll_types);
1099 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1101 extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
1102 struct dcb_entry *, int crtc);
1103 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1104 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1105 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1106 bool *dl, bool *if_is_24bit);
1107 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1108 int head, int pxclk);
1109 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1110 enum LVDS_script, int pxclk);
1111 bool bios_encoder_match(struct dcb_entry *, u32 hash);
1114 int nouveau_mxm_init(struct drm_device *dev);
1115 void nouveau_mxm_fini(struct drm_device *dev);
1118 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1119 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1120 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1122 /* nouveau_hdmi.c */
1123 void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
1126 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1127 uint8_t *data, int data_nr);
1128 bool nouveau_dp_detect(struct drm_encoder *);
1129 bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate);
1130 void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32);
1131 u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **);
1134 extern int nv04_fb_init(struct drm_device *);
1135 extern void nv04_fb_takedown(struct drm_device *);
1138 extern int nv10_fb_init(struct drm_device *);
1139 extern void nv10_fb_takedown(struct drm_device *);
1140 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1141 uint32_t addr, uint32_t size,
1142 uint32_t pitch, uint32_t flags);
1143 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1144 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1147 extern int nv30_fb_init(struct drm_device *);
1148 extern void nv30_fb_takedown(struct drm_device *);
1149 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1150 uint32_t addr, uint32_t size,
1151 uint32_t pitch, uint32_t flags);
1152 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1155 extern int nv40_fb_init(struct drm_device *);
1156 extern void nv40_fb_takedown(struct drm_device *);
1157 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1160 extern int nv50_fb_init(struct drm_device *);
1161 extern void nv50_fb_takedown(struct drm_device *);
1162 extern void nv50_fb_vm_trap(struct drm_device *, int display);
1165 extern int nvc0_fb_init(struct drm_device *);
1166 extern void nvc0_fb_takedown(struct drm_device *);
1169 extern int nv04_fifo_init(struct drm_device *);
1170 extern void nv04_fifo_fini(struct drm_device *);
1171 extern void nv04_fifo_disable(struct drm_device *);
1172 extern void nv04_fifo_enable(struct drm_device *);
1173 extern bool nv04_fifo_reassign(struct drm_device *, bool);
1174 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1175 extern int nv04_fifo_channel_id(struct drm_device *);
1176 extern int nv04_fifo_create_context(struct nouveau_channel *);
1177 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1178 extern int nv04_fifo_load_context(struct nouveau_channel *);
1179 extern int nv04_fifo_unload_context(struct drm_device *);
1180 extern void nv04_fifo_isr(struct drm_device *);
1183 extern int nv10_fifo_init(struct drm_device *);
1184 extern int nv10_fifo_channel_id(struct drm_device *);
1185 extern int nv10_fifo_create_context(struct nouveau_channel *);
1186 extern int nv10_fifo_load_context(struct nouveau_channel *);
1187 extern int nv10_fifo_unload_context(struct drm_device *);
1190 extern int nv40_fifo_init(struct drm_device *);
1191 extern int nv40_fifo_create_context(struct nouveau_channel *);
1192 extern int nv40_fifo_load_context(struct nouveau_channel *);
1193 extern int nv40_fifo_unload_context(struct drm_device *);
1196 extern int nv50_fifo_init(struct drm_device *);
1197 extern void nv50_fifo_takedown(struct drm_device *);
1198 extern int nv50_fifo_channel_id(struct drm_device *);
1199 extern int nv50_fifo_create_context(struct nouveau_channel *);
1200 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1201 extern int nv50_fifo_load_context(struct nouveau_channel *);
1202 extern int nv50_fifo_unload_context(struct drm_device *);
1203 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1206 extern int nvc0_fifo_init(struct drm_device *);
1207 extern void nvc0_fifo_takedown(struct drm_device *);
1208 extern void nvc0_fifo_disable(struct drm_device *);
1209 extern void nvc0_fifo_enable(struct drm_device *);
1210 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1211 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1212 extern int nvc0_fifo_channel_id(struct drm_device *);
1213 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1214 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1215 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1216 extern int nvc0_fifo_unload_context(struct drm_device *);
1219 extern int nv04_graph_create(struct drm_device *);
1220 extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
1221 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1222 u32 class, u32 mthd, u32 data);
1223 extern struct nouveau_bitfield nv04_graph_nsource[];
1226 extern int nv10_graph_create(struct drm_device *);
1227 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1228 extern struct nouveau_bitfield nv10_graph_intr[];
1229 extern struct nouveau_bitfield nv10_graph_nstatus[];
1232 extern int nv20_graph_create(struct drm_device *);
1235 extern int nv40_graph_create(struct drm_device *);
1236 extern void nv40_grctx_init(struct nouveau_grctx *);
1239 extern int nv50_graph_create(struct drm_device *);
1240 extern int nv50_grctx_init(struct nouveau_grctx *);
1241 extern struct nouveau_enum nv50_data_error_names[];
1242 extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
1245 extern int nvc0_graph_create(struct drm_device *);
1246 extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst);
1249 extern int nv84_crypt_create(struct drm_device *);
1252 extern int nv98_crypt_create(struct drm_device *dev);
1255 extern int nva3_copy_create(struct drm_device *dev);
1258 extern int nvc0_copy_create(struct drm_device *dev, int engine);
1261 extern int nv31_mpeg_create(struct drm_device *dev);
1264 extern int nv50_mpeg_create(struct drm_device *dev);
1268 extern int nv84_bsp_create(struct drm_device *dev);
1272 extern int nv84_vp_create(struct drm_device *dev);
1275 extern int nv98_ppp_create(struct drm_device *dev);
1277 /* nv04_instmem.c */
1278 extern int nv04_instmem_init(struct drm_device *);
1279 extern void nv04_instmem_takedown(struct drm_device *);
1280 extern int nv04_instmem_suspend(struct drm_device *);
1281 extern void nv04_instmem_resume(struct drm_device *);
1282 extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1283 u32 size, u32 align);
1284 extern void nv04_instmem_put(struct nouveau_gpuobj *);
1285 extern int nv04_instmem_map(struct nouveau_gpuobj *);
1286 extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
1287 extern void nv04_instmem_flush(struct drm_device *);
1289 /* nv50_instmem.c */
1290 extern int nv50_instmem_init(struct drm_device *);
1291 extern void nv50_instmem_takedown(struct drm_device *);
1292 extern int nv50_instmem_suspend(struct drm_device *);
1293 extern void nv50_instmem_resume(struct drm_device *);
1294 extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1295 u32 size, u32 align);
1296 extern void nv50_instmem_put(struct nouveau_gpuobj *);
1297 extern int nv50_instmem_map(struct nouveau_gpuobj *);
1298 extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
1299 extern void nv50_instmem_flush(struct drm_device *);
1300 extern void nv84_instmem_flush(struct drm_device *);
1302 /* nvc0_instmem.c */
1303 extern int nvc0_instmem_init(struct drm_device *);
1304 extern void nvc0_instmem_takedown(struct drm_device *);
1305 extern int nvc0_instmem_suspend(struct drm_device *);
1306 extern void nvc0_instmem_resume(struct drm_device *);
1309 extern int nv04_mc_init(struct drm_device *);
1310 extern void nv04_mc_takedown(struct drm_device *);
1313 extern int nv40_mc_init(struct drm_device *);
1314 extern void nv40_mc_takedown(struct drm_device *);
1317 extern int nv50_mc_init(struct drm_device *);
1318 extern void nv50_mc_takedown(struct drm_device *);
1321 extern int nv04_timer_init(struct drm_device *);
1322 extern uint64_t nv04_timer_read(struct drm_device *);
1323 extern void nv04_timer_takedown(struct drm_device *);
1325 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1329 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1330 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1331 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1332 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1333 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1336 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1337 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1338 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1340 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1341 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1344 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1345 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1348 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1350 /* nv04_display.c */
1351 extern int nv04_display_early_init(struct drm_device *);
1352 extern void nv04_display_late_takedown(struct drm_device *);
1353 extern int nv04_display_create(struct drm_device *);
1354 extern void nv04_display_destroy(struct drm_device *);
1355 extern int nv04_display_init(struct drm_device *);
1356 extern void nv04_display_fini(struct drm_device *);
1358 /* nvd0_display.c */
1359 extern int nvd0_display_create(struct drm_device *);
1360 extern void nvd0_display_destroy(struct drm_device *);
1361 extern int nvd0_display_init(struct drm_device *);
1362 extern void nvd0_display_fini(struct drm_device *);
1363 struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc);
1364 void nvd0_display_flip_stop(struct drm_crtc *);
1365 int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
1366 struct nouveau_channel *, u32 swap_interval);
1369 extern int nv04_crtc_create(struct drm_device *, int index);
1372 extern struct ttm_bo_driver nouveau_bo_driver;
1373 extern int nouveau_bo_new(struct drm_device *, int size, int align,
1374 uint32_t flags, uint32_t tile_mode,
1375 uint32_t tile_flags, struct nouveau_bo **);
1376 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1377 extern int nouveau_bo_unpin(struct nouveau_bo *);
1378 extern int nouveau_bo_map(struct nouveau_bo *);
1379 extern void nouveau_bo_unmap(struct nouveau_bo *);
1380 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1382 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1383 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1384 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1385 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1386 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1387 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1388 bool no_wait_reserve, bool no_wait_gpu);
1390 extern struct nouveau_vma *
1391 nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *);
1392 extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *,
1393 struct nouveau_vma *);
1394 extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *);
1396 /* nouveau_fence.c */
1397 struct nouveau_fence;
1398 extern int nouveau_fence_init(struct drm_device *);
1399 extern void nouveau_fence_fini(struct drm_device *);
1400 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1401 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1402 extern void nouveau_fence_update(struct nouveau_channel *);
1403 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1405 extern int nouveau_fence_emit(struct nouveau_fence *);
1406 extern void nouveau_fence_work(struct nouveau_fence *fence,
1407 void (*work)(void *priv, bool signalled),
1409 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1411 extern bool __nouveau_fence_signalled(void *obj, void *arg);
1412 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1413 extern int __nouveau_fence_flush(void *obj, void *arg);
1414 extern void __nouveau_fence_unref(void **obj);
1415 extern void *__nouveau_fence_ref(void *obj);
1417 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1419 return __nouveau_fence_signalled(obj, NULL);
1422 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1424 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1426 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1427 static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1429 return __nouveau_fence_flush(obj, NULL);
1431 static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1433 __nouveau_fence_unref((void **)obj);
1435 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1437 return __nouveau_fence_ref(obj);
1441 extern int nouveau_gem_new(struct drm_device *, int size, int align,
1442 uint32_t domain, uint32_t tile_mode,
1443 uint32_t tile_flags, struct nouveau_bo **);
1444 extern int nouveau_gem_object_new(struct drm_gem_object *);
1445 extern void nouveau_gem_object_del(struct drm_gem_object *);
1446 extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *);
1447 extern void nouveau_gem_object_close(struct drm_gem_object *,
1449 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1451 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1453 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1455 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1457 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1460 /* nouveau_display.c */
1461 int nouveau_display_create(struct drm_device *dev);
1462 void nouveau_display_destroy(struct drm_device *dev);
1463 int nouveau_display_init(struct drm_device *dev);
1464 void nouveau_display_fini(struct drm_device *dev);
1465 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1466 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1467 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1468 struct drm_pending_vblank_event *event);
1469 int nouveau_finish_page_flip(struct nouveau_channel *,
1470 struct nouveau_page_flip_state *);
1471 int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
1472 struct drm_mode_create_dumb *args);
1473 int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
1474 uint32_t handle, uint64_t *offset);
1475 int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
1479 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1480 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1483 int nv50_gpio_init(struct drm_device *dev);
1484 void nv50_gpio_fini(struct drm_device *dev);
1485 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1486 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1487 int nvd0_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1488 int nvd0_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1489 int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag,
1490 void (*)(void *, int), void *);
1491 void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag,
1492 void (*)(void *, int), void *);
1493 bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1496 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1497 int *N1, int *M1, int *N2, int *M2, int *P);
1498 int nva3_calc_pll(struct drm_device *, struct pll_lims *,
1499 int clk, int *N, int *fN, int *M, int *P);
1501 #ifndef ioread32_native
1503 #define ioread16_native ioread16be
1504 #define iowrite16_native iowrite16be
1505 #define ioread32_native ioread32be
1506 #define iowrite32_native iowrite32be
1507 #else /* def __BIG_ENDIAN */
1508 #define ioread16_native ioread16
1509 #define iowrite16_native iowrite16
1510 #define ioread32_native ioread32
1511 #define iowrite32_native iowrite32
1512 #endif /* def __BIG_ENDIAN else */
1513 #endif /* !ioread32_native */
1515 /* channel control reg access */
1516 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1518 return ioread32_native(chan->user + reg);
1521 static inline void nvchan_wr32(struct nouveau_channel *chan,
1522 unsigned reg, u32 val)
1524 iowrite32_native(val, chan->user + reg);
1527 /* register access */
1528 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1530 struct drm_nouveau_private *dev_priv = dev->dev_private;
1531 return ioread32_native(dev_priv->mmio + reg);
1534 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1536 struct drm_nouveau_private *dev_priv = dev->dev_private;
1537 iowrite32_native(val, dev_priv->mmio + reg);
1540 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1542 u32 tmp = nv_rd32(dev, reg);
1543 nv_wr32(dev, reg, (tmp & ~mask) | val);
1547 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1549 struct drm_nouveau_private *dev_priv = dev->dev_private;
1550 return ioread8(dev_priv->mmio + reg);
1553 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1555 struct drm_nouveau_private *dev_priv = dev->dev_private;
1556 iowrite8(val, dev_priv->mmio + reg);
1559 #define nv_wait(dev, reg, mask, val) \
1560 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1561 #define nv_wait_ne(dev, reg, mask, val) \
1562 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
1563 #define nv_wait_cb(dev, func, data) \
1564 nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
1567 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1569 struct drm_nouveau_private *dev_priv = dev->dev_private;
1570 return ioread32_native(dev_priv->ramin + offset);
1573 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1575 struct drm_nouveau_private *dev_priv = dev->dev_private;
1576 iowrite32_native(val, dev_priv->ramin + offset);
1580 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1581 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1585 * Argument d is (struct drm_device *).
1587 #define NV_PRINTK(level, d, fmt, arg...) \
1588 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1589 pci_name(d->pdev), ##arg)
1590 #ifndef NV_DEBUG_NOTRACE
1591 #define NV_DEBUG(d, fmt, arg...) do { \
1592 if (drm_debug & DRM_UT_DRIVER) { \
1593 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1597 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1598 if (drm_debug & DRM_UT_KMS) { \
1599 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1604 #define NV_DEBUG(d, fmt, arg...) do { \
1605 if (drm_debug & DRM_UT_DRIVER) \
1606 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1608 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1609 if (drm_debug & DRM_UT_KMS) \
1610 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1613 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1614 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1615 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1616 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1617 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1618 #define NV_WARNONCE(d, fmt, arg...) do { \
1619 static int _warned = 0; \
1621 NV_WARN(d, fmt, ##arg); \
1626 /* nouveau_reg_debug bitmask */
1628 NOUVEAU_REG_DEBUG_MC = 0x1,
1629 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1630 NOUVEAU_REG_DEBUG_FB = 0x4,
1631 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1632 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1633 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1634 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1635 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1636 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1637 NOUVEAU_REG_DEBUG_EVO = 0x200,
1638 NOUVEAU_REG_DEBUG_AUXCH = 0x400
1641 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1642 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1643 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1647 nv_two_heads(struct drm_device *dev)
1649 struct drm_nouveau_private *dev_priv = dev->dev_private;
1650 const int impl = dev->pci_device & 0x0ff0;
1652 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1653 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1660 nv_gf4_disp_arch(struct drm_device *dev)
1662 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1666 nv_two_reg_pll(struct drm_device *dev)
1668 struct drm_nouveau_private *dev_priv = dev->dev_private;
1669 const int impl = dev->pci_device & 0x0ff0;
1671 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1677 nv_match_device(struct drm_device *dev, unsigned device,
1678 unsigned sub_vendor, unsigned sub_device)
1680 return dev->pdev->device == device &&
1681 dev->pdev->subsystem_vendor == sub_vendor &&
1682 dev->pdev->subsystem_device == sub_device;
1685 static inline void *
1686 nv_engine(struct drm_device *dev, int engine)
1688 struct drm_nouveau_private *dev_priv = dev->dev_private;
1689 return (void *)dev_priv->eng[engine];
1692 /* returns 1 if device is one of the nv4x using the 0x4497 object class,
1693 * helpful to determine a number of other hardware features
1696 nv44_graph_class(struct drm_device *dev)
1698 struct drm_nouveau_private *dev_priv = dev->dev_private;
1700 if ((dev_priv->chipset & 0xf0) == 0x60)
1703 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1706 /* memory type/access flags, do not match hardware values */
1707 #define NV_MEM_ACCESS_RO 1
1708 #define NV_MEM_ACCESS_WO 2
1709 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1710 #define NV_MEM_ACCESS_SYS 4
1711 #define NV_MEM_ACCESS_VM 8
1713 #define NV_MEM_TARGET_VRAM 0
1714 #define NV_MEM_TARGET_PCI 1
1715 #define NV_MEM_TARGET_PCI_NOSNOOP 2
1716 #define NV_MEM_TARGET_VM 3
1717 #define NV_MEM_TARGET_GART 4
1719 #define NV_MEM_TYPE_VM 0x7f
1720 #define NV_MEM_COMP_VM 0x03
1722 /* NV_SW object class */
1723 #define NV_SW 0x0000506e
1724 #define NV_SW_DMA_SEMAPHORE 0x00000060
1725 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1726 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1727 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1728 #define NV_SW_YIELD 0x00000080
1729 #define NV_SW_DMA_VBLSEM 0x0000018c
1730 #define NV_SW_VBLSEM_OFFSET 0x00000400
1731 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1732 #define NV_SW_VBLSEM_RELEASE 0x00000408
1733 #define NV_SW_PAGE_FLIP 0x00000500
1735 #endif /* __NOUVEAU_DRV_H__ */