2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "nouveau@lists.freedesktop.org"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20120316"
35 #define DRIVER_MAJOR 1
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 0
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
50 struct list_head channels;
51 struct nouveau_vm *vm;
54 static inline struct nouveau_fpriv *
55 nouveau_fpriv(struct drm_file *file_priv)
57 return file_priv ? file_priv->driver_priv : NULL;
60 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
62 #include "nouveau_drm.h"
63 #include "nouveau_reg.h"
64 #include "nouveau_bios.h"
65 #include "nouveau_util.h"
69 #include "nouveau_vm.h"
71 #define MAX_NUM_DCB_ENTRIES 16
73 #define NOUVEAU_MAX_CHANNEL_NR 4096
74 #define NOUVEAU_MAX_TILE_NR 15
77 struct drm_device *dev;
79 struct nouveau_vma bar_vma;
80 struct nouveau_vma vma[2];
83 struct drm_mm_node *tag;
84 struct list_head regions;
92 struct nouveau_tile_reg {
98 struct drm_mm_node *tag_mem;
99 struct nouveau_fence *fence;
103 struct ttm_buffer_object bo;
104 struct ttm_placement placement;
107 u32 busy_placements[3];
108 struct ttm_bo_kmap_obj kmap;
109 struct list_head head;
111 /* protected by ttm_bo_reserve() */
112 struct drm_file *reserved_by;
113 struct list_head entry;
115 bool validate_mapped;
117 struct list_head vma_list;
122 struct nouveau_tile_reg *tile;
124 struct drm_gem_object *gem;
128 #define nouveau_bo_tile_layout(nvbo) \
129 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
131 static inline struct nouveau_bo *
132 nouveau_bo(struct ttm_buffer_object *bo)
134 return container_of(bo, struct nouveau_bo, bo);
137 static inline struct nouveau_bo *
138 nouveau_gem_object(struct drm_gem_object *gem)
140 return gem ? gem->driver_private : NULL;
143 /* TODO: submit equivalent to TTM generic API upstream? */
144 static inline void __iomem *
145 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
148 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
149 &nvbo->kmap, &is_iomem);
150 WARN_ON_ONCE(ioptr && !is_iomem);
155 NV_NFORCE = 0x10000000,
156 NV_NFORCE2 = 0x20000000
159 #define NVOBJ_ENGINE_SW 0
160 #define NVOBJ_ENGINE_GR 1
161 #define NVOBJ_ENGINE_CRYPT 2
162 #define NVOBJ_ENGINE_COPY0 3
163 #define NVOBJ_ENGINE_COPY1 4
164 #define NVOBJ_ENGINE_MPEG 5
165 #define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG
166 #define NVOBJ_ENGINE_BSP 6
167 #define NVOBJ_ENGINE_VP 7
168 #define NVOBJ_ENGINE_FIFO 14
169 #define NVOBJ_ENGINE_FENCE 15
170 #define NVOBJ_ENGINE_NR 16
171 #define NVOBJ_ENGINE_DISPLAY (NVOBJ_ENGINE_NR + 0) /*XXX*/
173 #define NVOBJ_FLAG_DONT_MAP (1 << 0)
174 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
175 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
176 #define NVOBJ_FLAG_VM (1 << 3)
177 #define NVOBJ_FLAG_VM_USER (1 << 4)
179 #define NVOBJ_CINST_GLOBAL 0xdeadbeef
181 struct nouveau_gpuobj {
182 struct drm_device *dev;
183 struct kref refcount;
184 struct list_head list;
192 u32 pinst; /* PRAMIN BAR offset */
193 u32 cinst; /* Channel offset */
194 u64 vinst; /* VRAM address */
195 u64 linst; /* VM address */
200 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
204 struct nouveau_page_flip_state {
205 struct list_head head;
206 struct drm_pending_vblank_event *event;
207 int crtc, bpp, pitch, x, y;
211 enum nouveau_channel_mutex_class {
212 NOUVEAU_UCHANNEL_MUTEX,
213 NOUVEAU_KCHANNEL_MUTEX
216 struct nouveau_channel {
217 struct drm_device *dev;
218 struct list_head list;
221 /* references to the channel data structure */
223 /* users of the hardware channel resources, the hardware
224 * context will be kicked off when it reaches zero. */
228 /* owner of this fifo */
229 struct drm_file *file_priv;
230 /* mapping of the fifo itself */
231 struct drm_local_map *map;
233 /* mapping of the regs controlling the fifo */
236 uint32_t user_get_hi;
239 /* DMA push buffer */
240 struct nouveau_gpuobj *pushbuf;
241 struct nouveau_bo *pushbuf_bo;
242 struct nouveau_vma pushbuf_vma;
243 uint64_t pushbuf_base;
245 /* Notifier memory */
246 struct nouveau_bo *notifier_bo;
247 struct nouveau_vma notifier_vma;
248 struct drm_mm notifier_heap;
251 struct nouveau_gpuobj *ramfc;
253 /* Execution engine contexts */
254 void *engctx[NVOBJ_ENGINE_NR];
257 struct nouveau_vm *vm;
258 struct nouveau_gpuobj *vm_pd;
261 struct nouveau_gpuobj *ramin; /* Private instmem */
262 struct drm_mm ramin_heap; /* Private PRAMIN heap */
263 struct nouveau_ramht *ramht; /* Hash table */
265 /* GPU object info for stuff used in-kernel (mm_enabled) */
267 uint32_t vram_handle;
268 uint32_t gart_handle;
271 /* Push buffer state (only for drm's channel on !mm_enabled) */
277 /* access via pushbuf_bo */
288 struct drm_info_list info;
292 struct nouveau_exec_engine {
293 void (*destroy)(struct drm_device *, int engine);
294 int (*init)(struct drm_device *, int engine);
295 int (*fini)(struct drm_device *, int engine, bool suspend);
296 int (*context_new)(struct nouveau_channel *, int engine);
297 void (*context_del)(struct nouveau_channel *, int engine);
298 int (*object_new)(struct nouveau_channel *, int engine,
299 u32 handle, u16 class);
300 void (*set_tile_region)(struct drm_device *dev, int i);
301 void (*tlb_flush)(struct drm_device *, int engine);
304 struct nouveau_instmem_engine {
307 int (*init)(struct drm_device *dev);
308 void (*takedown)(struct drm_device *dev);
309 int (*suspend)(struct drm_device *dev);
310 void (*resume)(struct drm_device *dev);
312 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *,
313 u32 size, u32 align);
314 void (*put)(struct nouveau_gpuobj *);
315 int (*map)(struct nouveau_gpuobj *);
316 void (*unmap)(struct nouveau_gpuobj *);
318 void (*flush)(struct drm_device *);
321 struct nouveau_mc_engine {
322 int (*init)(struct drm_device *dev);
323 void (*takedown)(struct drm_device *dev);
326 struct nouveau_timer_engine {
327 int (*init)(struct drm_device *dev);
328 void (*takedown)(struct drm_device *dev);
329 uint64_t (*read)(struct drm_device *dev);
332 struct nouveau_fb_engine {
334 struct drm_mm tag_heap;
337 int (*init)(struct drm_device *dev);
338 void (*takedown)(struct drm_device *dev);
340 void (*init_tile_region)(struct drm_device *dev, int i,
341 uint32_t addr, uint32_t size,
342 uint32_t pitch, uint32_t flags);
343 void (*set_tile_region)(struct drm_device *dev, int i);
344 void (*free_tile_region)(struct drm_device *dev, int i);
347 struct nouveau_display_engine {
349 int (*early_init)(struct drm_device *);
350 void (*late_takedown)(struct drm_device *);
351 int (*create)(struct drm_device *);
352 void (*destroy)(struct drm_device *);
353 int (*init)(struct drm_device *);
354 void (*fini)(struct drm_device *);
356 struct drm_property *dithering_mode;
357 struct drm_property *dithering_depth;
358 struct drm_property *underscan_property;
359 struct drm_property *underscan_hborder_property;
360 struct drm_property *underscan_vborder_property;
361 /* not really hue and saturation: */
362 struct drm_property *vibrant_hue_property;
363 struct drm_property *color_vibrance_property;
366 struct nouveau_gpio_engine {
368 struct list_head isr;
369 int (*init)(struct drm_device *);
370 void (*fini)(struct drm_device *);
371 int (*drive)(struct drm_device *, int line, int dir, int out);
372 int (*sense)(struct drm_device *, int line);
373 void (*irq_enable)(struct drm_device *, int line, bool);
376 struct nouveau_pm_voltage_level {
377 u32 voltage; /* microvolts */
381 struct nouveau_pm_voltage {
386 struct nouveau_pm_voltage_level *level;
390 /* Exclusive upper limits */
391 #define NV_MEM_CL_DDR2_MAX 8
392 #define NV_MEM_WR_DDR2_MAX 9
393 #define NV_MEM_CL_DDR3_MAX 17
394 #define NV_MEM_WR_DDR3_MAX 17
395 #define NV_MEM_CL_GDDR3_MAX 16
396 #define NV_MEM_WR_GDDR3_MAX 18
397 #define NV_MEM_CL_GDDR5_MAX 21
398 #define NV_MEM_WR_GDDR5_MAX 20
400 struct nouveau_pm_memtiming {
412 struct nouveau_pm_tbl_header {
419 struct nouveau_pm_tbl_entry {
425 u8 tRFC; /* Byte 5 */
427 u8 tRAS; /* Byte 7 */
434 u8 RAM_FT1; /* 14, a bitmask of random RAM features */
443 struct nouveau_pm_profile;
444 struct nouveau_pm_profile_func {
445 void (*destroy)(struct nouveau_pm_profile *);
446 void (*init)(struct nouveau_pm_profile *);
447 void (*fini)(struct nouveau_pm_profile *);
448 struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
451 struct nouveau_pm_profile {
452 const struct nouveau_pm_profile_func *func;
453 struct list_head head;
457 #define NOUVEAU_PM_MAX_LEVEL 8
458 struct nouveau_pm_level {
459 struct nouveau_pm_profile profile;
460 struct device_attribute dev_attr;
464 struct nouveau_pm_memtiming timing;
475 u32 unka0; /* nva3:nvc0 */
476 u32 hub01; /* nvc0- */
477 u32 hub06; /* nvc0- */
478 u32 hub07; /* nvc0- */
480 u32 volt_min; /* microvolts */
485 struct nouveau_pm_temp_sensor_constants {
493 struct nouveau_pm_threshold_temp {
499 struct nouveau_pm_fan {
507 struct nouveau_pm_engine {
508 struct nouveau_pm_voltage voltage;
509 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
511 struct nouveau_pm_temp_sensor_constants sensor_constants;
512 struct nouveau_pm_threshold_temp threshold_temp;
513 struct nouveau_pm_fan fan;
515 struct nouveau_pm_profile *profile_ac;
516 struct nouveau_pm_profile *profile_dc;
517 struct nouveau_pm_profile *profile;
518 struct list_head profiles;
520 struct nouveau_pm_level boot;
521 struct nouveau_pm_level *cur;
523 struct device *hwmon;
524 struct notifier_block acpi_nb;
526 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
527 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
528 int (*clocks_set)(struct drm_device *, void *);
530 int (*voltage_get)(struct drm_device *);
531 int (*voltage_set)(struct drm_device *, int voltage);
532 int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
533 int (*pwm_set)(struct drm_device *, int line, u32, u32);
534 int (*temp_get)(struct drm_device *);
537 struct nouveau_vram_engine {
538 struct nouveau_mm mm;
540 int (*init)(struct drm_device *);
541 void (*takedown)(struct drm_device *dev);
542 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
543 u32 type, struct nouveau_mem **);
544 void (*put)(struct drm_device *, struct nouveau_mem **);
546 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
549 struct nouveau_engine {
550 struct nouveau_instmem_engine instmem;
551 struct nouveau_mc_engine mc;
552 struct nouveau_timer_engine timer;
553 struct nouveau_fb_engine fb;
554 struct nouveau_display_engine display;
555 struct nouveau_gpio_engine gpio;
556 struct nouveau_pm_engine pm;
557 struct nouveau_vram_engine vram;
560 struct nouveau_pll_vals {
564 uint8_t N1, M1, N2, M2;
566 uint8_t M1, N1, M2, N2;
571 } __attribute__((packed));
578 enum nv04_fp_display_regs {
588 struct nv04_crtc_reg {
589 unsigned char MiscOutReg;
592 uint8_t Sequencer[5];
594 uint8_t Attribute[21];
595 unsigned char DAC[768];
605 uint32_t crtc_eng_ctrl;
608 uint32_t nv10_cursync;
609 struct nouveau_pll_vals pllvals;
610 uint32_t ramdac_gen_ctrl;
616 uint32_t tv_vsync_delay;
619 uint32_t tv_hsync_delay;
620 uint32_t tv_hsync_delay2;
621 uint32_t fp_horiz_regs[7];
622 uint32_t fp_vert_regs[7];
625 uint32_t dither_regs[6];
629 uint32_t fp_margin_color;
634 uint32_t ctv_regs[38];
637 struct nv04_output_reg {
642 struct nv04_mode_state {
643 struct nv04_crtc_reg crtc_reg[2];
648 enum nouveau_card_type {
660 struct drm_nouveau_private {
661 struct drm_device *dev;
664 /* the card type, takes NV_* as values */
665 enum nouveau_card_type card_type;
666 /* exact chipset, derived from NV_PMC_BOOT_0 */
673 spinlock_t ramin_lock;
677 bool ramin_available;
678 struct drm_mm ramin_heap;
679 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR];
680 struct list_head gpuobj_list;
681 struct list_head classes;
683 struct nouveau_bo *vga_ram;
685 /* interrupt handling */
686 void (*irq_handler[32])(struct drm_device *);
689 struct list_head vbl_waiting;
692 struct drm_global_reference mem_global_ref;
693 struct ttm_bo_global_ref bo_global_ref;
694 struct ttm_bo_device bdev;
695 atomic_t validate_sequence;
696 int (*move)(struct nouveau_channel *,
697 struct ttm_buffer_object *,
698 struct ttm_mem_reg *, struct ttm_mem_reg *);
704 struct nouveau_bo *bo;
709 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
712 struct nouveau_engine engine;
713 struct nouveau_channel *channel;
715 /* For PFIFO and PGRAPH. */
716 spinlock_t context_switch_lock;
718 /* VM/PRAMIN flush, legacy PRAMIN aperture */
721 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
722 struct nouveau_ramht *ramht;
723 struct nouveau_gpuobj *ramfc;
724 struct nouveau_gpuobj *ramro;
726 uint32_t ramin_rsvd_vram;
730 NOUVEAU_GART_NONE = 0,
731 NOUVEAU_GART_AGP, /* AGP */
732 NOUVEAU_GART_PDMA, /* paged dma object */
733 NOUVEAU_GART_HW /* on-chip gart/vm */
739 struct ttm_backend_func *func;
746 struct nouveau_gpuobj *sg_ctxdma;
749 /* nv10-nv40 tiling regions */
751 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
755 /* VRAM/fb configuration */
757 NV_MEM_TYPE_UNKNOWN = 0,
770 uint64_t vram_sys_base;
773 uint64_t fb_available_size;
774 uint64_t fb_mappable_pages;
775 uint64_t fb_aper_free;
778 /* BAR control (NV50-) */
779 struct nouveau_vm *bar1_vm;
780 struct nouveau_vm *bar3_vm;
782 /* G8x/G9x virtual address space */
783 struct nouveau_vm *chan_vm;
787 struct list_head i2c_ports;
789 struct nv04_mode_state mode_reg;
790 struct nv04_mode_state saved_reg;
791 uint32_t saved_vga_font[4][16384];
793 uint32_t dac_users[4];
795 struct backlight_device *backlight;
798 struct dentry *channel_root;
801 struct nouveau_fbdev *nfbdev;
802 struct apertures_struct *apertures;
805 static inline struct drm_nouveau_private *
806 nouveau_private(struct drm_device *dev)
808 return dev->dev_private;
811 static inline struct drm_nouveau_private *
812 nouveau_bdev(struct ttm_bo_device *bd)
814 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
818 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
820 struct nouveau_bo *prev;
826 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
828 struct ttm_buffer_object *bo = &prev->bo;
837 extern int nouveau_modeset;
838 extern int nouveau_agpmode;
839 extern int nouveau_duallink;
840 extern int nouveau_uscript_lvds;
841 extern int nouveau_uscript_tmds;
842 extern int nouveau_vram_pushbuf;
843 extern int nouveau_vram_notify;
844 extern char *nouveau_vram_type;
845 extern int nouveau_fbpercrtc;
846 extern int nouveau_tv_disable;
847 extern char *nouveau_tv_norm;
848 extern int nouveau_reg_debug;
849 extern char *nouveau_vbios;
850 extern int nouveau_ignorelid;
851 extern int nouveau_nofbaccel;
852 extern int nouveau_noaccel;
853 extern int nouveau_force_post;
854 extern int nouveau_override_conntype;
855 extern char *nouveau_perflvl;
856 extern int nouveau_perflvl_wr;
857 extern int nouveau_msi;
858 extern int nouveau_ctxfw;
859 extern int nouveau_mxmdcb;
861 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
862 extern int nouveau_pci_resume(struct pci_dev *pdev);
864 /* nouveau_state.c */
865 extern int nouveau_open(struct drm_device *, struct drm_file *);
866 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
867 extern void nouveau_postclose(struct drm_device *, struct drm_file *);
868 extern int nouveau_load(struct drm_device *, unsigned long flags);
869 extern int nouveau_firstopen(struct drm_device *);
870 extern void nouveau_lastclose(struct drm_device *);
871 extern int nouveau_unload(struct drm_device *);
872 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
874 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
876 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
877 uint32_t reg, uint32_t mask, uint32_t val);
878 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
879 uint32_t reg, uint32_t mask, uint32_t val);
880 extern bool nouveau_wait_cb(struct drm_device *, u64 timeout,
881 bool (*cond)(void *), void *);
882 extern bool nouveau_wait_for_idle(struct drm_device *);
883 extern int nouveau_card_init(struct drm_device *);
886 extern int nouveau_mem_vram_init(struct drm_device *);
887 extern void nouveau_mem_vram_fini(struct drm_device *);
888 extern int nouveau_mem_gart_init(struct drm_device *);
889 extern void nouveau_mem_gart_fini(struct drm_device *);
890 extern int nouveau_mem_init_agp(struct drm_device *);
891 extern int nouveau_mem_reset_agp(struct drm_device *);
892 extern void nouveau_mem_close(struct drm_device *);
893 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
894 extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
895 struct nouveau_pm_memtiming *);
896 extern void nouveau_mem_timing_read(struct drm_device *,
897 struct nouveau_pm_memtiming *);
898 extern int nouveau_mem_vbios_type(struct drm_device *);
899 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
900 struct drm_device *dev, uint32_t addr, uint32_t size,
901 uint32_t pitch, uint32_t flags);
902 extern void nv10_mem_put_tile_region(struct drm_device *dev,
903 struct nouveau_tile_reg *tile,
904 struct nouveau_fence *fence);
905 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
906 extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
908 /* nouveau_notifier.c */
909 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
910 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
911 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
912 int cout, uint32_t start, uint32_t end,
914 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
915 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
917 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
920 /* nouveau_channel.c */
921 extern struct drm_ioctl_desc nouveau_ioctls[];
922 extern int nouveau_max_ioctl;
923 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
924 extern int nouveau_channel_alloc(struct drm_device *dev,
925 struct nouveau_channel **chan,
926 struct drm_file *file_priv,
927 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
928 extern struct nouveau_channel *
929 nouveau_channel_get_unlocked(struct nouveau_channel *);
930 extern struct nouveau_channel *
931 nouveau_channel_get(struct drm_file *, int id);
932 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
933 extern void nouveau_channel_put(struct nouveau_channel **);
934 extern void nouveau_channel_ref(struct nouveau_channel *chan,
935 struct nouveau_channel **pchan);
936 extern int nouveau_channel_idle(struct nouveau_channel *chan);
938 /* nouveau_object.c */
939 #define NVOBJ_ENGINE_ADD(d, e, p) do { \
940 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
941 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
944 #define NVOBJ_ENGINE_DEL(d, e) do { \
945 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
946 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \
949 #define NVOBJ_CLASS(d, c, e) do { \
950 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
955 #define NVOBJ_MTHD(d, c, m, e) do { \
956 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
961 extern int nouveau_gpuobj_early_init(struct drm_device *);
962 extern int nouveau_gpuobj_init(struct drm_device *);
963 extern void nouveau_gpuobj_takedown(struct drm_device *);
964 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
965 extern void nouveau_gpuobj_resume(struct drm_device *dev);
966 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
967 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
968 int (*exec)(struct nouveau_channel *,
969 u32 class, u32 mthd, u32 data));
970 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
971 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
972 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
973 uint32_t vram_h, uint32_t tt_h);
974 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
975 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
976 uint32_t size, int align, uint32_t flags,
977 struct nouveau_gpuobj **);
978 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
979 struct nouveau_gpuobj **);
980 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
982 struct nouveau_gpuobj **);
983 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
984 uint64_t offset, uint64_t size, int access,
985 int target, struct nouveau_gpuobj **);
986 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
987 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
988 u64 size, int target, int access, u32 type,
989 u32 comp, struct nouveau_gpuobj **pobj);
990 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
991 int class, u64 base, u64 size, int target,
992 int access, u32 type, u32 comp);
993 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
995 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
999 extern int nouveau_irq_init(struct drm_device *);
1000 extern void nouveau_irq_fini(struct drm_device *);
1001 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
1002 extern void nouveau_irq_register(struct drm_device *, int status_bit,
1003 void (*)(struct drm_device *));
1004 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
1005 extern void nouveau_irq_preinstall(struct drm_device *);
1006 extern int nouveau_irq_postinstall(struct drm_device *);
1007 extern void nouveau_irq_uninstall(struct drm_device *);
1009 /* nouveau_sgdma.c */
1010 extern int nouveau_sgdma_init(struct drm_device *);
1011 extern void nouveau_sgdma_takedown(struct drm_device *);
1012 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
1014 extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev,
1016 uint32_t page_flags,
1017 struct page *dummy_read_page);
1019 /* nouveau_debugfs.c */
1020 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
1021 extern int nouveau_debugfs_init(struct drm_minor *);
1022 extern void nouveau_debugfs_takedown(struct drm_minor *);
1023 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
1024 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
1027 nouveau_debugfs_init(struct drm_minor *minor)
1032 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
1037 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
1043 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
1049 extern void nouveau_dma_init(struct nouveau_channel *);
1050 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
1052 /* nouveau_acpi.c */
1053 #define ROM_BIOS_PAGE 4096
1054 #if defined(CONFIG_ACPI)
1055 void nouveau_register_dsm_handler(void);
1056 void nouveau_unregister_dsm_handler(void);
1057 void nouveau_switcheroo_optimus_dsm(void);
1058 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
1059 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
1060 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
1062 static inline void nouveau_register_dsm_handler(void) {}
1063 static inline void nouveau_unregister_dsm_handler(void) {}
1064 static inline void nouveau_switcheroo_optimus_dsm(void) {}
1065 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
1066 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
1067 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
1070 /* nouveau_backlight.c */
1071 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1072 extern int nouveau_backlight_init(struct drm_device *);
1073 extern void nouveau_backlight_exit(struct drm_device *);
1075 static inline int nouveau_backlight_init(struct drm_device *dev)
1080 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
1083 /* nouveau_bios.c */
1084 extern int nouveau_bios_init(struct drm_device *);
1085 extern void nouveau_bios_takedown(struct drm_device *dev);
1086 extern int nouveau_run_vbios_init(struct drm_device *);
1087 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1088 struct dcb_entry *, int crtc);
1089 extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table);
1090 extern struct dcb_connector_table_entry *
1091 nouveau_bios_connector_entry(struct drm_device *, int index);
1092 extern u32 get_pll_register(struct drm_device *, enum pll_types);
1093 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1095 extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
1096 struct dcb_entry *, int crtc);
1097 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1098 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1099 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1100 bool *dl, bool *if_is_24bit);
1101 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1102 int head, int pxclk);
1103 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1104 enum LVDS_script, int pxclk);
1105 bool bios_encoder_match(struct dcb_entry *, u32 hash);
1108 int nouveau_mxm_init(struct drm_device *dev);
1109 void nouveau_mxm_fini(struct drm_device *dev);
1112 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1113 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1114 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1116 /* nouveau_hdmi.c */
1117 void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
1120 extern int nv04_fb_vram_init(struct drm_device *);
1121 extern int nv04_fb_init(struct drm_device *);
1122 extern void nv04_fb_takedown(struct drm_device *);
1125 extern int nv10_fb_vram_init(struct drm_device *dev);
1126 extern int nv1a_fb_vram_init(struct drm_device *dev);
1127 extern int nv10_fb_init(struct drm_device *);
1128 extern void nv10_fb_takedown(struct drm_device *);
1129 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1130 uint32_t addr, uint32_t size,
1131 uint32_t pitch, uint32_t flags);
1132 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1133 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1136 extern int nv20_fb_vram_init(struct drm_device *dev);
1137 extern int nv20_fb_init(struct drm_device *);
1138 extern void nv20_fb_takedown(struct drm_device *);
1139 extern void nv20_fb_init_tile_region(struct drm_device *dev, int i,
1140 uint32_t addr, uint32_t size,
1141 uint32_t pitch, uint32_t flags);
1142 extern void nv20_fb_set_tile_region(struct drm_device *dev, int i);
1143 extern void nv20_fb_free_tile_region(struct drm_device *dev, int i);
1146 extern int nv30_fb_init(struct drm_device *);
1147 extern void nv30_fb_takedown(struct drm_device *);
1148 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1149 uint32_t addr, uint32_t size,
1150 uint32_t pitch, uint32_t flags);
1151 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1154 extern int nv40_fb_vram_init(struct drm_device *dev);
1155 extern int nv40_fb_init(struct drm_device *);
1156 extern void nv40_fb_takedown(struct drm_device *);
1157 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1160 extern int nv50_fb_init(struct drm_device *);
1161 extern void nv50_fb_takedown(struct drm_device *);
1162 extern void nv50_fb_vm_trap(struct drm_device *, int display);
1165 extern int nvc0_fb_init(struct drm_device *);
1166 extern void nvc0_fb_takedown(struct drm_device *);
1169 extern int nv04_graph_create(struct drm_device *);
1170 extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
1171 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1172 u32 class, u32 mthd, u32 data);
1173 extern struct nouveau_bitfield nv04_graph_nsource[];
1176 extern int nv10_graph_create(struct drm_device *);
1177 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1178 extern struct nouveau_bitfield nv10_graph_intr[];
1179 extern struct nouveau_bitfield nv10_graph_nstatus[];
1182 extern int nv20_graph_create(struct drm_device *);
1185 extern int nv40_graph_create(struct drm_device *);
1186 extern void nv40_grctx_init(struct drm_device *, u32 *size);
1187 extern void nv40_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);
1190 extern int nv50_graph_create(struct drm_device *);
1191 extern struct nouveau_enum nv50_data_error_names[];
1192 extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
1193 extern int nv50_grctx_init(struct drm_device *, u32 *, u32, u32 *, u32 *);
1194 extern void nv50_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);
1197 extern int nvc0_graph_create(struct drm_device *);
1198 extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst);
1201 extern int nve0_graph_create(struct drm_device *);
1204 extern int nv84_crypt_create(struct drm_device *);
1207 extern int nv98_crypt_create(struct drm_device *dev);
1210 extern int nva3_copy_create(struct drm_device *dev);
1213 extern int nvc0_copy_create(struct drm_device *dev, int engine);
1216 extern int nv31_mpeg_create(struct drm_device *dev);
1219 extern int nv50_mpeg_create(struct drm_device *dev);
1223 extern int nv84_bsp_create(struct drm_device *dev);
1227 extern int nv84_vp_create(struct drm_device *dev);
1230 extern int nv98_ppp_create(struct drm_device *dev);
1232 /* nv04_instmem.c */
1233 extern int nv04_instmem_init(struct drm_device *);
1234 extern void nv04_instmem_takedown(struct drm_device *);
1235 extern int nv04_instmem_suspend(struct drm_device *);
1236 extern void nv04_instmem_resume(struct drm_device *);
1237 extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1238 u32 size, u32 align);
1239 extern void nv04_instmem_put(struct nouveau_gpuobj *);
1240 extern int nv04_instmem_map(struct nouveau_gpuobj *);
1241 extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
1242 extern void nv04_instmem_flush(struct drm_device *);
1244 /* nv50_instmem.c */
1245 extern int nv50_instmem_init(struct drm_device *);
1246 extern void nv50_instmem_takedown(struct drm_device *);
1247 extern int nv50_instmem_suspend(struct drm_device *);
1248 extern void nv50_instmem_resume(struct drm_device *);
1249 extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1250 u32 size, u32 align);
1251 extern void nv50_instmem_put(struct nouveau_gpuobj *);
1252 extern int nv50_instmem_map(struct nouveau_gpuobj *);
1253 extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
1254 extern void nv50_instmem_flush(struct drm_device *);
1255 extern void nv84_instmem_flush(struct drm_device *);
1257 /* nvc0_instmem.c */
1258 extern int nvc0_instmem_init(struct drm_device *);
1259 extern void nvc0_instmem_takedown(struct drm_device *);
1260 extern int nvc0_instmem_suspend(struct drm_device *);
1261 extern void nvc0_instmem_resume(struct drm_device *);
1264 extern int nv04_mc_init(struct drm_device *);
1265 extern void nv04_mc_takedown(struct drm_device *);
1268 extern int nv40_mc_init(struct drm_device *);
1269 extern void nv40_mc_takedown(struct drm_device *);
1272 extern int nv50_mc_init(struct drm_device *);
1273 extern void nv50_mc_takedown(struct drm_device *);
1276 extern int nv04_timer_init(struct drm_device *);
1277 extern uint64_t nv04_timer_read(struct drm_device *);
1278 extern void nv04_timer_takedown(struct drm_device *);
1280 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1284 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1285 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1286 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1287 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1288 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1291 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1292 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1293 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1295 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1296 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1299 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1300 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1303 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1305 /* nv04_display.c */
1306 extern int nv04_display_early_init(struct drm_device *);
1307 extern void nv04_display_late_takedown(struct drm_device *);
1308 extern int nv04_display_create(struct drm_device *);
1309 extern void nv04_display_destroy(struct drm_device *);
1310 extern int nv04_display_init(struct drm_device *);
1311 extern void nv04_display_fini(struct drm_device *);
1313 /* nvd0_display.c */
1314 extern int nvd0_display_create(struct drm_device *);
1315 extern void nvd0_display_destroy(struct drm_device *);
1316 extern int nvd0_display_init(struct drm_device *);
1317 extern void nvd0_display_fini(struct drm_device *);
1318 struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc);
1319 void nvd0_display_flip_stop(struct drm_crtc *);
1320 int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
1321 struct nouveau_channel *, u32 swap_interval);
1324 extern int nv04_crtc_create(struct drm_device *, int index);
1327 extern struct ttm_bo_driver nouveau_bo_driver;
1328 extern void nouveau_bo_move_init(struct nouveau_channel *);
1329 extern int nouveau_bo_new(struct drm_device *, int size, int align,
1330 uint32_t flags, uint32_t tile_mode,
1331 uint32_t tile_flags,
1332 struct sg_table *sg,
1333 struct nouveau_bo **);
1334 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1335 extern int nouveau_bo_unpin(struct nouveau_bo *);
1336 extern int nouveau_bo_map(struct nouveau_bo *);
1337 extern void nouveau_bo_unmap(struct nouveau_bo *);
1338 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1340 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1341 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1342 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1343 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1344 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1345 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1346 bool no_wait_reserve, bool no_wait_gpu);
1348 extern struct nouveau_vma *
1349 nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *);
1350 extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *,
1351 struct nouveau_vma *);
1352 extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *);
1355 extern int nouveau_gem_new(struct drm_device *, int size, int align,
1356 uint32_t domain, uint32_t tile_mode,
1357 uint32_t tile_flags, struct nouveau_bo **);
1358 extern int nouveau_gem_object_new(struct drm_gem_object *);
1359 extern void nouveau_gem_object_del(struct drm_gem_object *);
1360 extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *);
1361 extern void nouveau_gem_object_close(struct drm_gem_object *,
1363 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1365 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1367 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1369 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1371 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1374 extern struct dma_buf *nouveau_gem_prime_export(struct drm_device *dev,
1375 struct drm_gem_object *obj, int flags);
1376 extern struct drm_gem_object *nouveau_gem_prime_import(struct drm_device *dev,
1377 struct dma_buf *dma_buf);
1379 /* nouveau_display.c */
1380 int nouveau_display_create(struct drm_device *dev);
1381 void nouveau_display_destroy(struct drm_device *dev);
1382 int nouveau_display_init(struct drm_device *dev);
1383 void nouveau_display_fini(struct drm_device *dev);
1384 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1385 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1386 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1387 struct drm_pending_vblank_event *event);
1388 int nouveau_finish_page_flip(struct nouveau_channel *,
1389 struct nouveau_page_flip_state *);
1390 int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
1391 struct drm_mode_create_dumb *args);
1392 int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
1393 uint32_t handle, uint64_t *offset);
1394 int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
1398 int nv10_gpio_init(struct drm_device *dev);
1399 void nv10_gpio_fini(struct drm_device *dev);
1400 int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1401 int nv10_gpio_sense(struct drm_device *dev, int line);
1402 void nv10_gpio_irq_enable(struct drm_device *, int line, bool on);
1405 int nv50_gpio_init(struct drm_device *dev);
1406 void nv50_gpio_fini(struct drm_device *dev);
1407 int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1408 int nv50_gpio_sense(struct drm_device *dev, int line);
1409 void nv50_gpio_irq_enable(struct drm_device *, int line, bool on);
1410 int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1411 int nvd0_gpio_sense(struct drm_device *dev, int line);
1414 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1415 int *N1, int *M1, int *N2, int *M2, int *P);
1416 int nva3_calc_pll(struct drm_device *, struct pll_lims *,
1417 int clk, int *N, int *fN, int *M, int *P);
1419 #ifndef ioread32_native
1421 #define ioread16_native ioread16be
1422 #define iowrite16_native iowrite16be
1423 #define ioread32_native ioread32be
1424 #define iowrite32_native iowrite32be
1425 #else /* def __BIG_ENDIAN */
1426 #define ioread16_native ioread16
1427 #define iowrite16_native iowrite16
1428 #define ioread32_native ioread32
1429 #define iowrite32_native iowrite32
1430 #endif /* def __BIG_ENDIAN else */
1431 #endif /* !ioread32_native */
1433 /* channel control reg access */
1434 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1436 return ioread32_native(chan->user + reg);
1439 static inline void nvchan_wr32(struct nouveau_channel *chan,
1440 unsigned reg, u32 val)
1442 iowrite32_native(val, chan->user + reg);
1445 /* register access */
1446 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1448 struct drm_nouveau_private *dev_priv = dev->dev_private;
1449 return ioread32_native(dev_priv->mmio + reg);
1452 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1454 struct drm_nouveau_private *dev_priv = dev->dev_private;
1455 iowrite32_native(val, dev_priv->mmio + reg);
1458 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1460 u32 tmp = nv_rd32(dev, reg);
1461 nv_wr32(dev, reg, (tmp & ~mask) | val);
1465 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1467 struct drm_nouveau_private *dev_priv = dev->dev_private;
1468 return ioread8(dev_priv->mmio + reg);
1471 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1473 struct drm_nouveau_private *dev_priv = dev->dev_private;
1474 iowrite8(val, dev_priv->mmio + reg);
1477 #define nv_wait(dev, reg, mask, val) \
1478 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1479 #define nv_wait_ne(dev, reg, mask, val) \
1480 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
1481 #define nv_wait_cb(dev, func, data) \
1482 nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
1485 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1487 struct drm_nouveau_private *dev_priv = dev->dev_private;
1488 return ioread32_native(dev_priv->ramin + offset);
1491 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1493 struct drm_nouveau_private *dev_priv = dev->dev_private;
1494 iowrite32_native(val, dev_priv->ramin + offset);
1498 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1499 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1503 * Argument d is (struct drm_device *).
1505 #define NV_PRINTK(level, d, fmt, arg...) \
1506 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1507 pci_name(d->pdev), ##arg)
1508 #ifndef NV_DEBUG_NOTRACE
1509 #define NV_DEBUG(d, fmt, arg...) do { \
1510 if (drm_debug & DRM_UT_DRIVER) { \
1511 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1515 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1516 if (drm_debug & DRM_UT_KMS) { \
1517 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1522 #define NV_DEBUG(d, fmt, arg...) do { \
1523 if (drm_debug & DRM_UT_DRIVER) \
1524 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1526 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1527 if (drm_debug & DRM_UT_KMS) \
1528 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1531 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1532 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1533 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1534 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1535 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1536 #define NV_WARNONCE(d, fmt, arg...) do { \
1537 static int _warned = 0; \
1539 NV_WARN(d, fmt, ##arg); \
1544 /* nouveau_reg_debug bitmask */
1546 NOUVEAU_REG_DEBUG_MC = 0x1,
1547 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1548 NOUVEAU_REG_DEBUG_FB = 0x4,
1549 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1550 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1551 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1552 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1553 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1554 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1555 NOUVEAU_REG_DEBUG_EVO = 0x200,
1556 NOUVEAU_REG_DEBUG_AUXCH = 0x400
1559 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1560 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1561 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1565 nv_two_heads(struct drm_device *dev)
1567 struct drm_nouveau_private *dev_priv = dev->dev_private;
1568 const int impl = dev->pci_device & 0x0ff0;
1570 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1571 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1578 nv_gf4_disp_arch(struct drm_device *dev)
1580 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1584 nv_two_reg_pll(struct drm_device *dev)
1586 struct drm_nouveau_private *dev_priv = dev->dev_private;
1587 const int impl = dev->pci_device & 0x0ff0;
1589 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1595 nv_match_device(struct drm_device *dev, unsigned device,
1596 unsigned sub_vendor, unsigned sub_device)
1598 return dev->pdev->device == device &&
1599 dev->pdev->subsystem_vendor == sub_vendor &&
1600 dev->pdev->subsystem_device == sub_device;
1603 static inline void *
1604 nv_engine(struct drm_device *dev, int engine)
1606 struct drm_nouveau_private *dev_priv = dev->dev_private;
1607 return (void *)dev_priv->eng[engine];
1610 /* returns 1 if device is one of the nv4x using the 0x4497 object class,
1611 * helpful to determine a number of other hardware features
1614 nv44_graph_class(struct drm_device *dev)
1616 struct drm_nouveau_private *dev_priv = dev->dev_private;
1618 if ((dev_priv->chipset & 0xf0) == 0x60)
1621 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1624 /* memory type/access flags, do not match hardware values */
1625 #define NV_MEM_ACCESS_RO 1
1626 #define NV_MEM_ACCESS_WO 2
1627 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1628 #define NV_MEM_ACCESS_SYS 4
1629 #define NV_MEM_ACCESS_VM 8
1630 #define NV_MEM_ACCESS_NOSNOOP 16
1632 #define NV_MEM_TARGET_VRAM 0
1633 #define NV_MEM_TARGET_PCI 1
1634 #define NV_MEM_TARGET_PCI_NOSNOOP 2
1635 #define NV_MEM_TARGET_VM 3
1636 #define NV_MEM_TARGET_GART 4
1638 #define NV_MEM_TYPE_VM 0x7f
1639 #define NV_MEM_COMP_VM 0x03
1642 #define NV01_SUBCHAN_OBJECT 0x00000000
1643 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
1644 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
1645 #define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
1646 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c
1647 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001
1648 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
1649 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
1650 #define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000
1651 #define NV84_SUBCHAN_NOTIFY_INTR 0x00000020
1652 #define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
1653 #define NV10_SUBCHAN_REF_CNT 0x00000050
1654 #define NVSW_SUBCHAN_PAGE_FLIP 0x00000054
1655 #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
1656 #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
1657 #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
1658 #define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
1659 #define NV40_SUBCHAN_YIELD 0x00000080
1661 /* NV_SW object class */
1662 #define NV_SW 0x0000506e
1663 #define NV_SW_DMA_VBLSEM 0x0000018c
1664 #define NV_SW_VBLSEM_OFFSET 0x00000400
1665 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1666 #define NV_SW_VBLSEM_RELEASE 0x00000408
1667 #define NV_SW_PAGE_FLIP 0x00000500
1669 #endif /* __NOUVEAU_DRV_H__ */